3,5c3,5
< sim_seconds 2.802882 # Number of seconds simulated
< sim_ticks 2802882496500 # Number of ticks simulated
< final_tick 2802882496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.802883 # Number of seconds simulated
> sim_ticks 2802882713500 # Number of ticks simulated
> final_tick 2802882713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1330236 # Simulator instruction rate (inst/s)
< host_op_rate 1620871 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 25395755903 # Simulator tick rate (ticks/s)
< host_mem_usage 564312 # Number of bytes of host memory used
< host_seconds 110.37 # Real time elapsed on the host
< sim_insts 146815698 # Number of instructions simulated
< sim_ops 178892459 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1349319 # Simulator instruction rate (inst/s)
> host_op_rate 1644123 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 25757810314 # Simulator tick rate (ticks/s)
> host_mem_usage 564420 # Number of bytes of host memory used
> host_seconds 108.82 # Real time elapsed on the host
> sim_insts 146828498 # Number of instructions simulated
> sim_ops 178908222 # Number of ops (including micro ops) simulated
16,33d15
< system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::cpu1.inst 19 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu1.inst 19 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu1.inst 19 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s)
35c17
< system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
37,38c19,20
< system.physmem.bytes_read::cpu0.inst 1117476 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 9458684 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 1116900 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 9456508 # Number of bytes read from this memory
40,46c22,28
< system.physmem.bytes_read::cpu1.inst 149780 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 1082912 # Number of bytes read from this memory
< system.physmem.bytes_read::total 11810580 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 1117476 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 149780 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1267256 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6081216 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 1081824 # Number of bytes read from this memory
> system.physmem.bytes_read::total 11808788 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 1116900 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1268792 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6072384 # Number of bytes written to this memory
50c32
< system.physmem.bytes_written::total 8417296 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8408464 # Number of bytes written to this memory
52c34
< system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
54,55c36,37
< system.physmem.num_reads::cpu0.inst 25914 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 148317 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 25905 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 148283 # Number of read requests responded to by this memory
57,60c39,42
< system.physmem.num_reads::cpu1.inst 2495 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 16944 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 193697 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 95019 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 16927 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 193669 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 94881 # Number of write requests responded to by this memory
64c46
< system.physmem.num_writes::total 135679 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 135541 # Number of write requests responded to by this memory
66c48
< system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
68,69c50,51
< system.physmem.bw_read::cpu0.inst 398688 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 3374627 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 398483 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 3373851 # Total read bandwidth from this memory (bytes/s)
71,77c53,59
< system.physmem.bw_read::cpu1.inst 53438 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 386357 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 4213726 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 398688 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 53438 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 452126 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2169629 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 54191 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 385968 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 4213087 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 398483 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 54191 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 452674 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2166478 # Write bandwidth from this memory (bytes/s)
81,82c63,64
< system.physmem.bw_write::total 3003086 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2169629 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2999934 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2166478 # Total bandwidth to/from this memory (bytes/s)
84c66
< system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
86,87c68,69
< system.physmem.bw_total::cpu0.inst 398688 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 3380944 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 398483 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 3380167 # Total bandwidth to/from this memory (bytes/s)
89,96c71,96
< system.physmem.bw_total::cpu1.inst 53438 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 386371 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 7216812 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 75963 # Transaction distribution
< system.membus.trans_dist::ReadResp 75963 # Transaction distribution
< system.membus.trans_dist::WriteReq 30903 # Transaction distribution
< system.membus.trans_dist::WriteResp 30903 # Transaction distribution
< system.membus.trans_dist::Writeback 95019 # Transaction distribution
---
> system.physmem.bw_total::cpu1.inst 54191 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 385983 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 7213021 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
> system.membus.trans_dist::ReadReq 75957 # Transaction distribution
> system.membus.trans_dist::ReadResp 75957 # Transaction distribution
> system.membus.trans_dist::WriteReq 30905 # Transaction distribution
> system.membus.trans_dist::WriteResp 30905 # Transaction distribution
> system.membus.trans_dist::Writeback 94881 # Transaction distribution
99,103c99,103
< system.membus.trans_dist::UpgradeReq 60332 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 40886 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 15607 # Transaction distribution
< system.membus.trans_dist::ReadExReq 196321 # Transaction distribution
< system.membus.trans_dist::ReadExResp 152216 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 60384 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 40930 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 15620 # Transaction distribution
> system.membus.trans_dist::ReadExReq 196326 # Transaction distribution
> system.membus.trans_dist::ReadExResp 152193 # Transaction distribution
105,108c105,108
< system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652185 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 773609 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652128 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 773554 # Packet count per connected master and slave (bytes)
111c111
< system.membus.pkt_count::total 846561 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 846506 # Packet count per connected master and slave (bytes)
113,116c113,116
< system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17908580 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 18098400 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897956 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 18087780 # Cumulative packet size per connected master and slave (bytes)
119c119
< system.membus.pkt_size::total 20432864 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 20422244 # Cumulative packet size per connected master and slave (bytes)
121c121
< system.membus.snoop_fanout::samples 460731 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 460689 # Request fanout histogram
126c126
< system.membus.snoop_fanout::1 460731 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 460689 100.00% 100.00% # Request fanout histogram
131c131
< system.membus.snoop_fanout::total 460731 # Request fanout histogram
---
> system.membus.snoop_fanout::total 460689 # Request fanout histogram
133,137c133,137
< system.l2c.tags.replacements 107723 # number of replacements
< system.l2c.tags.tagsinuse 62123.921751 # Cycle average of tags in use
< system.l2c.tags.total_refs 208051 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 168144 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 1.237338 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 107632 # number of replacements
> system.l2c.tags.tagsinuse 62143.934871 # Cycle average of tags in use
> system.l2c.tags.total_refs 207938 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 168025 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 1.237542 # Average number of references to valid blocks.
139,140c139,140
< system.l2c.tags.occ_blocks::writebacks 48622.171138 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.975943 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::writebacks 48688.027343 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor
142,147c142,147
< system.l2c.tags.occ_blocks::cpu0.inst 7348.709599 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 3778.182164 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823425 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 1628.255131 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 741.773959 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.741915 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_blocks::cpu0.inst 7324.741121 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 3758.950125 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 1656.363289 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 711.020717 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.742920 # Average percentage of cache occupancy
150,151c150,151
< system.l2c.tags.occ_percent::cpu0.inst 0.112132 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.057650 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.057357 # Average percentage of cache occupancy
153,159c153,160
< system.l2c.tags.occ_percent::cpu1.inst 0.024845 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.011319 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.947936 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 60415 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
---
> system.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 60384 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
161,179c162,180
< system.l2c.tags.age_task_id_blocks_1024::2 1884 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 13069 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.921860 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 4905185 # Number of tag accesses
< system.l2c.tags.data_accesses 4905185 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.dtb.walker 79 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 74 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 28057 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 75985 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 42 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 11512 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 11347 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 127129 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 225966 # number of Writeback hits
< system.l2c.Writeback_hits::total 225966 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 512 # number of UpgradeReq hits
---
> system.l2c.tags.age_task_id_blocks_1024::2 1906 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 12994 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 45387 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.921387 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 4903910 # Number of tag accesses
> system.l2c.tags.data_accesses 4903910 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.dtb.walker 69 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 59 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 28044 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 76113 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 38 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 35 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 11456 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 11379 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 127193 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 225882 # number of Writeback hits
> system.l2c.Writeback_hits::total 225882 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 506 # number of UpgradeReq hits
181,206c182,207
< system.l2c.UpgradeReq_hits::total 577 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 56 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 11 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 13971 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 3083 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 17054 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 79 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 74 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 28057 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 89956 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 11512 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 14430 # number of demand (read+write) hits
< system.l2c.demand_hits::total 144183 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 79 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 74 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 28057 # number of overall hits
< system.l2c.overall_hits::cpu0.data 89956 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 11512 # number of overall hits
< system.l2c.overall_hits::cpu1.data 14430 # number of overall hits
< system.l2c.overall_hits::total 144183 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses
---
> system.l2c.UpgradeReq_hits::total 571 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 71 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 13825 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 3137 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 16962 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 69 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 59 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 28044 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 89938 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 11456 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 14516 # number of demand (read+write) hits
> system.l2c.demand_hits::total 144155 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 69 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 59 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 28044 # number of overall hits
> system.l2c.overall_hits::cpu0.data 89938 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 11456 # number of overall hits
> system.l2c.overall_hits::cpu1.data 14516 # number of overall hits
> system.l2c.overall_hits::total 144155 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses
208,209c209,210
< system.l2c.ReadReq_misses::cpu0.inst 16897 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 11316 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu0.inst 16888 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 11308 # number of ReadReq misses
211,223c212,224
< system.l2c.ReadReq_misses::cpu1.inst 2330 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 1142 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 31697 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 9967 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 3302 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 13269 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 763 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1181 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1944 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 15814 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 152610 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses
---
> system.l2c.ReadReq_misses::cpu1.inst 2363 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 1122 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 31692 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 9982 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 3290 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 13272 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 756 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1185 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1941 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 136781 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 15819 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 152600 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
225,226c226,227
< system.l2c.demand_misses::cpu0.inst 16897 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 148112 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.inst 16888 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 148089 # number of demand (read+write) misses
228,231c229,232
< system.l2c.demand_misses::cpu1.inst 2330 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 16956 # number of demand (read+write) misses
< system.l2c.demand_misses::total 184307 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses
---
> system.l2c.demand_misses::cpu1.inst 2363 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 16941 # number of demand (read+write) misses
> system.l2c.demand_misses::total 184292 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
233,234c234,235
< system.l2c.overall_misses::cpu0.inst 16897 # number of overall misses
< system.l2c.overall_misses::cpu0.data 148112 # number of overall misses
---
> system.l2c.overall_misses::cpu0.inst 16888 # number of overall misses
> system.l2c.overall_misses::cpu0.data 148089 # number of overall misses
236,309c237,310
< system.l2c.overall_misses::cpu1.inst 2330 # number of overall misses
< system.l2c.overall_misses::cpu1.data 16956 # number of overall misses
< system.l2c.overall_misses::total 184307 # number of overall misses
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 87 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 76 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 44954 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 87301 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 44 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 33 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 13842 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 12489 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 158826 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 225966 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 225966 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 10479 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 3367 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 13846 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 2011 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 150767 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 18897 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 169664 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 76 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 44954 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 238068 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 44 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 13842 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 31386 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 328490 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 76 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 44954 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 238068 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 44 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 13842 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 31386 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 328490 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.026316 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.375873 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.129621 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.168328 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.091440 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.199571 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951140 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980695 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.958327 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.931624 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.990772 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.966683 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.907334 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.836852 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.899484 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.026316 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.375873 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.622142 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.168328 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.540241 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.561073 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.026316 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.375873 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.622142 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.168328 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.540241 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.561073 # miss rate for overall accesses
---
> system.l2c.overall_misses::cpu1.inst 2363 # number of overall misses
> system.l2c.overall_misses::cpu1.data 16941 # number of overall misses
> system.l2c.overall_misses::total 184292 # number of overall misses
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 76 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 61 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 44932 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 87421 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 40 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 13819 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 12501 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 158885 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 225882 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 225882 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 10488 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 3355 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 13843 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 1191 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 150606 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 18956 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 169562 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 76 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 61 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 44932 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 238027 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 40 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 13819 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 31457 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 328447 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 76 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 61 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 44932 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 238027 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 40 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 13819 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 31457 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 328447 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.032787 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.375857 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.129351 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.170996 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.089753 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.199465 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951754 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980626 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.958752 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920828 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994962 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.964712 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.908204 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.834512 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.899966 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.032787 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.375857 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.622152 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.170996 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.538545 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.561101 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.032787 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.375857 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.622152 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.170996 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.538545 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.561101 # miss rate for overall accesses
318,319c319,320
< system.l2c.writebacks::writebacks 95019 # number of writebacks
< system.l2c.writebacks::total 95019 # number of writebacks
---
> system.l2c.writebacks::writebacks 94881 # number of writebacks
> system.l2c.writebacks::total 94881 # number of writebacks
358,373c359,374
< system.toL2Bus.trans_dist::ReadReq 305028 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 305028 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 30903 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 30903 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 225966 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 60515 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 40953 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 101468 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 213769 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 213769 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117772 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410530 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 1528302 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34667382 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10427306 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 45094688 # Cumulative packet size per connected master and slave (bytes)
---
> system.toL2Bus.trans_dist::ReadReq 305223 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 305223 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 225882 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 41001 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 101549 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 213695 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 213695 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117774 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410852 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 1528626 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664498 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432626 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 45097124 # Cumulative packet size per connected master and slave (bytes)
375,377c376,378
< system.toL2Bus.snoop_fanout::samples 838693 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.043491 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.203961 # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::samples 838812 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.203947 # Request fanout histogram
380c381
< system.toL2Bus.snoop_fanout::1 802217 95.65% 95.65% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::1 802336 95.65% 95.65% # Request fanout histogram
385c386
< system.toL2Bus.snoop_fanout::total 838693 # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::total 838812 # Request fanout histogram
464c465
< system.cpu0.dtb.read_hits 20338466 # DTB read hits
---
> system.cpu0.dtb.read_hits 20339791 # DTB read hits
466c467
< system.cpu0.dtb.write_hits 16389914 # DTB write hits
---
> system.cpu0.dtb.write_hits 16391007 # DTB write hits
477,478c478,479
< system.cpu0.dtb.read_accesses 20345337 # DTB read accesses
< system.cpu0.dtb.write_accesses 16391007 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 20346662 # DTB read accesses
> system.cpu0.dtb.write_accesses 16392100 # DTB write accesses
480c481
< system.cpu0.dtb.hits 36728380 # DTB hits
---
> system.cpu0.dtb.hits 36730798 # DTB hits
482c483
< system.cpu0.dtb.accesses 36736344 # DTB accesses
---
> system.cpu0.dtb.accesses 36738762 # DTB accesses
504c505
< system.cpu0.itb.inst_hits 97433991 # ITB inst hits
---
> system.cpu0.itb.inst_hits 97439560 # ITB inst hits
521,522c522,523
< system.cpu0.itb.inst_accesses 97437349 # ITB inst accesses
< system.cpu0.itb.hits 97433991 # DTB hits
---
> system.cpu0.itb.inst_accesses 97442918 # ITB inst accesses
> system.cpu0.itb.hits 97439560 # DTB hits
524,525c525,526
< system.cpu0.itb.accesses 97437349 # DTB accesses
< system.cpu0.numCycles 5605766965 # number of cpu cycles simulated
---
> system.cpu0.itb.accesses 97442918 # DTB accesses
> system.cpu0.numCycles 5605767393 # number of cpu cycles simulated
528,530c529,531
< system.cpu0.committedInsts 95421538 # Number of instructions committed
< system.cpu0.committedOps 115553717 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 100756647 # Number of integer alu accesses
---
> system.cpu0.committedInsts 95427097 # Number of instructions committed
> system.cpu0.committedOps 115560530 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 100762762 # Number of integer alu accesses
532,534c533,535
< system.cpu0.num_func_calls 7999979 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 13203645 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 100756647 # number of integer instructions
---
> system.cpu0.num_func_calls 8000275 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 13204265 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 100762762 # number of integer instructions
536,537c537,538
< system.cpu0.num_int_register_reads 182446507 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 69131058 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 182457576 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 69135597 # number of times the integer registers were written
540,549c541,550
< system.cpu0.num_cc_register_reads 349951369 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 44905035 # number of times the CC registers were written
< system.cpu0.num_mem_refs 37871263 # number of memory refs
< system.cpu0.num_load_insts 20596038 # Number of load instructions
< system.cpu0.num_store_insts 17275225 # Number of store instructions
< system.cpu0.num_idle_cycles 5488189135.402444 # Number of idle cycles
< system.cpu0.num_busy_cycles 117577829.597556 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles
< system.cpu0.Branches 21940727 # Number of branches fetched
---
> system.cpu0.num_cc_register_reads 349971872 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 44907557 # number of times the CC registers were written
> system.cpu0.num_mem_refs 37873781 # number of memory refs
> system.cpu0.num_load_insts 20597370 # Number of load instructions
> system.cpu0.num_store_insts 17276411 # Number of store instructions
> system.cpu0.num_idle_cycles 5488182740.223901 # Number of idle cycles
> system.cpu0.num_busy_cycles 117584652.776099 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles
> system.cpu0.Branches 21941666 # Number of branches fetched
551,552c552,553
< system.cpu0.op_class::IntAlu 78883166 67.49% 67.50% # Class of executed instruction
< system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 78887449 67.49% 67.50% # Class of executed instruction
> system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction
580,581c581,582
< system.cpu0.op_class::MemRead 20596038 17.62% 85.22% # Class of executed instruction
< system.cpu0.op_class::MemWrite 17275225 14.78% 100.00% # Class of executed instruction
---
> system.cpu0.op_class::MemRead 20597370 17.62% 85.22% # Class of executed instruction
> system.cpu0.op_class::MemWrite 17276411 14.78% 100.00% # Class of executed instruction
584c585
< system.cpu0.op_class::total 116875407 # Class of executed instruction
---
> system.cpu0.op_class::total 116882229 # Class of executed instruction
586,587c587,588
< system.cpu0.kern.inst.quiesce 1971 # number of quiesce instructions executed
< system.cpu0.icache.tags.replacements 1109428 # number of replacements
---
> system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed
> system.cpu0.icache.tags.replacements 1109631 # number of replacements
589,592c590,593
< system.cpu0.icache.tags.total_refs 96326384 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1109940 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 86.785217 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 6345717500 # Cycle when the warmup percentage was hit.
---
> system.cpu0.icache.tags.total_refs 96331750 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1110143 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 86.774181 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit.
601,626c602,627
< system.cpu0.icache.tags.tag_accesses 195982615 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 195982615 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 96326384 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 96326384 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 96326384 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 96326384 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 96326384 # number of overall hits
< system.cpu0.icache.overall_hits::total 96326384 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1109949 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1109949 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1109949 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1109949 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1109949 # number of overall misses
< system.cpu0.icache.overall_misses::total 1109949 # number of overall misses
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 97436333 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 97436333 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 97436333 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 97436333 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 97436333 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 97436333 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011392 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.011392 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011392 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.011392 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011392 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.011392 # miss rate for overall accesses
---
> system.cpu0.icache.tags.tag_accesses 195993956 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 195993956 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 96331750 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 96331750 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 96331750 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 96331750 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 96331750 # number of overall hits
> system.cpu0.icache.overall_hits::total 96331750 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1110152 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1110152 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1110152 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1110152 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1110152 # number of overall misses
> system.cpu0.icache.overall_misses::total 1110152 # number of overall misses
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441902 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 97441902 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 97441902 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 97441902 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 97441902 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 97441902 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses
645,670c646,671
< system.cpu0.l2cache.tags.replacements 252470 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16140.899010 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 1809063 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 268660 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 6.733652 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 1814551000 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 8130.897895 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.403919 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.095149 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4678.277611 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3330.224436 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.496271 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000086 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285539 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.203261 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.985162 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5558 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7600 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.replacements 252387 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16137.494570 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 1809761 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 268581 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 6.738232 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 8061.802195 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.197687 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081095 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.849314 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.564278 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.492053 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.291373 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201328 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.984955 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16188 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5625 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7524 # Occupied blocks per task id
672,682c673,683
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 39435786 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 39435786 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7516 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3210 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1064995 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.data 352145 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 1427866 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 511188 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 511188 # number of Writeback hits
---
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988037 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 39447588 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 39447588 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7603 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3246 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065220 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.data 351970 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 1428039 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 511617 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 511617 # number of Writeback hits
685,745c686,746
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94088 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 94088 # number of ReadExReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7516 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3210 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1064995 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 446233 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1521954 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7516 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3210 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1064995 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 446233 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1521954 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 135 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44954 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.data 128031 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 173336 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26217 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 26217 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18426 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 18426 # number of SCUpgradeReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175429 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 175429 # number of ReadExReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 135 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 44954 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 303460 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 135 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 44954 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 303460 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 348765 # number of overall misses
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7732 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3345 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1109949 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480176 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 1601202 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 511188 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 511188 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26234 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 26234 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18426 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 18426 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7732 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3345 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1109949 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 749693 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 1870719 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7732 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3345 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1109949 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 749693 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 1870719 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040359 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040501 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266633 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.108254 # miss rate for ReadReq accesses
---
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94214 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 94214 # number of ReadExReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7603 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3246 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1065220 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 446184 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1522253 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7603 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3246 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1065220 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 446184 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1522253 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 205 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 119 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44932 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.data 128186 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 173442 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26232 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 26232 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175300 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 175300 # number of ReadExReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 205 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 119 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 44932 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 303486 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 348742 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 205 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 119 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 44932 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 303486 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 348742 # number of overall misses
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7808 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3365 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110152 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480156 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 1601481 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 511617 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 511617 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26249 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 26249 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269514 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 269514 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7808 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3365 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1110152 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 749670 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 1870995 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7808 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3365 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1110152 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 749670 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 1870995 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035364 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040474 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266967 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.108301 # miss rate for ReadReq accesses
750,761c751,762
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650901 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650901 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040359 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040501 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404779 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.186434 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040359 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040501 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404779 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.186434 # miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650430 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650430 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035364 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040474 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404826 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.186394 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035364 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040474 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404826 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.186394 # miss rate for overall accesses
770,771c771,772
< system.cpu0.l2cache.writebacks::writebacks 192932 # number of writebacks
< system.cpu0.l2cache.writebacks::total 192932 # number of writebacks
---
> system.cpu0.l2cache.writebacks::writebacks 192916 # number of writebacks
> system.cpu0.l2cache.writebacks::total 192916 # number of writebacks
773,781c774,782
< system.cpu0.dcache.tags.replacements 693475 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 494.745909 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 35929913 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 51.773179 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 23662000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.745909 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966301 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.966301 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.replacements 693468 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 494.853462 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 35932354 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 51.777218 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853462 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy
787,844c788,845
< system.cpu0.dcache.tags.tag_accesses 74108905 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 74108905 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 19107323 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 19107323 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 15689235 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 15689235 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346054 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 346054 # number of SoftPFReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379605 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 379605 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363036 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 363036 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 34796558 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 34796558 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 35142612 # number of overall hits
< system.cpu0.dcache.overall_hits::total 35142612 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 373110 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 373110 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 295751 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 295751 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100324 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 100324 # number of SoftPFReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18426 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 18426 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 668861 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 668861 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 769185 # number of overall misses
< system.cpu0.dcache.overall_misses::total 769185 # number of overall misses
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480433 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 19480433 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984986 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 15984986 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446378 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 446378 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386347 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 386347 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381462 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 381462 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 35465419 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 35465419 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 35911797 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 35911797 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019153 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.019153 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224751 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224751 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017451 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017451 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048304 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048304 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018860 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.018860 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021419 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.021419 # miss rate for overall accesses
---
> system.cpu0.dcache.tags.tag_accesses 74113718 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 74113718 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 19108629 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 19108629 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 15690304 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 15690304 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 34798933 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 34798933 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 35145013 # number of overall hits
> system.cpu0.dcache.overall_hits::total 35145013 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 295763 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 295763 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 668857 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 668857 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 769179 # number of overall misses
> system.cpu0.dcache.overall_misses::total 769179 # number of overall misses
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481723 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 19481723 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986067 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 15986067 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 35467790 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 35467790 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses
853,854c854,855
< system.cpu0.dcache.writebacks::writebacks 511188 # number of writebacks
< system.cpu0.dcache.writebacks::total 511188 # number of writebacks
---
> system.cpu0.dcache.writebacks::writebacks 511617 # number of writebacks
> system.cpu0.dcache.writebacks::total 511617 # number of writebacks
856,867c857,868
< system.cpu0.toL2Bus.trans_dist::ReadReq 1651550 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1651550 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 28399 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 28399 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 511188 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 26234 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18426 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 44660 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2237944 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2219872 # Packet count per connected master and slave (bytes)
---
> system.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 511617 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 26249 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 44693 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220321 # Packet count per connected master and slave (bytes)
870,872c871,873
< system.cpu0.toL2Bus.pkt_count::total 4499440 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71072828 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887162 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu0.toL2Bus.pkt_count::total 4500293 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80913146 # Cumulative packet size per connected master and slave (bytes)
875,879c876,880
< system.cpu0.toL2Bus.pkt_size::total 152043238 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 321922 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 2655621 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 5.082587 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.275257 # Request fanout histogram
---
> system.cpu0.toL2Bus.pkt_size::total 152082210 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 322119 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 2656456 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 5.082633 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.275327 # Request fanout histogram
886,887c887,888
< system.cpu0.toL2Bus.snoop_fanout::5 2436302 91.74% 91.74% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::6 219319 8.26% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::5 2436944 91.74% 91.74% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::6 219512 8.26% 100.00% # Request fanout histogram
891c892
< system.cpu0.toL2Bus.snoop_fanout::total 2655621 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::total 2656456 # Request fanout histogram
915c916
< system.cpu1.dtb.read_hits 12172110 # DTB read hits
---
> system.cpu1.dtb.read_hits 12173926 # DTB read hits
917c918
< system.cpu1.dtb.write_hits 7585805 # DTB write hits
---
> system.cpu1.dtb.write_hits 7587211 # DTB write hits
928,929c929,930
< system.cpu1.dtb.read_accesses 12174963 # DTB read accesses
< system.cpu1.dtb.write_accesses 7586311 # DTB write accesses
---
> system.cpu1.dtb.read_accesses 12176779 # DTB read accesses
> system.cpu1.dtb.write_accesses 7587717 # DTB write accesses
931c932
< system.cpu1.dtb.hits 19757915 # DTB hits
---
> system.cpu1.dtb.hits 19761137 # DTB hits
933c934
< system.cpu1.dtb.accesses 19761274 # DTB accesses
---
> system.cpu1.dtb.accesses 19764496 # DTB accesses
955c956
< system.cpu1.itb.inst_hits 53664371 # ITB inst hits
---
> system.cpu1.itb.inst_hits 53671662 # ITB inst hits
972,973c973,974
< system.cpu1.itb.inst_accesses 53666105 # ITB inst accesses
< system.cpu1.itb.hits 53664371 # DTB hits
---
> system.cpu1.itb.inst_accesses 53673396 # ITB inst accesses
> system.cpu1.itb.hits 53671662 # DTB hits
975,976c976,977
< system.cpu1.itb.accesses 53666105 # DTB accesses
< system.cpu1.numCycles 5605295863 # number of cpu cycles simulated
---
> system.cpu1.itb.accesses 53673396 # DTB accesses
> system.cpu1.numCycles 5605296302 # number of cpu cycles simulated
979,981c980,982
< system.cpu1.committedInsts 51394160 # Number of instructions committed
< system.cpu1.committedOps 63338742 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 56976202 # Number of integer alu accesses
---
> system.cpu1.committedInsts 51401401 # Number of instructions committed
> system.cpu1.committedOps 63347692 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 56984315 # Number of integer alu accesses
983,985c984,986
< system.cpu1.num_func_calls 9170283 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 5966381 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 56976202 # number of integer instructions
---
> system.cpu1.num_func_calls 9170855 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 5967102 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 56984315 # number of integer instructions
987,988c988,989
< system.cpu1.num_int_register_reads 110660301 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 41292600 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 110674840 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 41298430 # number of times the integer registers were written
991,1000c992,1001
< system.cpu1.num_cc_register_reads 196241872 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 18891627 # number of times the CC registers were written
< system.cpu1.num_mem_refs 20022980 # number of memory refs
< system.cpu1.num_load_insts 12287666 # Number of load instructions
< system.cpu1.num_store_insts 7735314 # Number of store instructions
< system.cpu1.num_idle_cycles 5539691262.121797 # Number of idle cycles
< system.cpu1.num_busy_cycles 65604600.878203 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles
< system.cpu1.Branches 15216192 # Number of branches fetched
---
> system.cpu1.num_cc_register_reads 196268898 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 18894414 # number of times the CC registers were written
> system.cpu1.num_mem_refs 20026390 # number of memory refs
> system.cpu1.num_load_insts 12289548 # Number of load instructions
> system.cpu1.num_store_insts 7736842 # Number of store instructions
> system.cpu1.num_idle_cycles 5539682707.595543 # Number of idle cycles
> system.cpu1.num_busy_cycles 65613594.404457 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles
> system.cpu1.Branches 15217497 # Number of branches fetched
1002,1003c1003,1004
< system.cpu1.op_class::IntAlu 45395839 69.36% 69.36% # Class of executed instruction
< system.cpu1.op_class::IntMult 28345 0.04% 69.40% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 45401373 69.36% 69.36% # Class of executed instruction
> system.cpu1.op_class::IntMult 28395 0.04% 69.40% # Class of executed instruction
1027c1028
< system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction
---
> system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction
1031,1032c1032,1033
< system.cpu1.op_class::MemRead 12287666 18.77% 88.18% # Class of executed instruction
< system.cpu1.op_class::MemWrite 7735314 11.82% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::MemRead 12289548 18.77% 88.18% # Class of executed instruction
> system.cpu1.op_class::MemWrite 7736842 11.82% 100.00% # Class of executed instruction
1035c1036
< system.cpu1.op_class::total 65450545 # Class of executed instruction
---
> system.cpu1.op_class::total 65459543 # Class of executed instruction
1037,1044c1038,1045
< system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed
< system.cpu1.icache.tags.replacements 523179 # number of replacements
< system.cpu1.icache.tags.tagsinuse 499.711075 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 53141770 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 523691 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 101.475431 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 76931405000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711075 # Average occupied blocks per requestor
---
> system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
> system.cpu1.icache.tags.replacements 523402 # number of replacements
> system.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 53148838 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 101.445730 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor
1051,1076c1052,1077
< system.cpu1.icache.tags.tag_accesses 107854613 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 107854613 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 53141770 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 53141770 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 53141770 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 53141770 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 53141770 # number of overall hits
< system.cpu1.icache.overall_hits::total 53141770 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 523691 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 523691 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 523691 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 523691 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 523691 # number of overall misses
< system.cpu1.icache.overall_misses::total 523691 # number of overall misses
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 53665461 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 53665461 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 53665461 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 53665461 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 53665461 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 53665461 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.009758 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.009758 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.009758 # miss rate for overall accesses
---
> system.cpu1.icache.tags.tag_accesses 107869418 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 107869418 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 53148838 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 53148838 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 53148838 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 53148838 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 53148838 # number of overall hits
> system.cpu1.icache.overall_hits::total 53148838 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 523914 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 523914 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 523914 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 523914 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 523914 # number of overall misses
> system.cpu1.icache.overall_misses::total 523914 # number of overall misses
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672752 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 53672752 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 53672752 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 53672752 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 53672752 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 53672752 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses
1095,1099c1096,1100
< system.cpu1.l2cache.tags.replacements 48552 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15311.760536 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 716558 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 63379 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 11.305922 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.tags.replacements 48605 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15302.416394 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 716648 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 11.297716 # Average number of references to valid blocks.
1101,1113c1102,1114
< system.cpu1.l2cache.tags.occ_blocks::writebacks 8243.045220 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.958358 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015688 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3303.816337 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3759.924934 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.503116 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000181 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201649 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229488 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.934556 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14809 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 8289.635884 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.959660 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.032491 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.997092 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.791267 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.505959 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000303 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200378 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227221 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.933985 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14803 # Occupied blocks per task id
1115,1195c1116,1196
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 540 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9336 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4933 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903870 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 15206583 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 15206583 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3143 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1725 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.inst 509849 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.data 99406 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 614123 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 120669 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 120669 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19820 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 19820 # number of ReadExReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3143 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1725 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 509849 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 119226 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 633943 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3143 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1725 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 509849 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 119226 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 633943 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 348 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13842 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.data 73217 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 87678 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28845 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 28845 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22527 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 22527 # number of SCUpgradeReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43793 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 43793 # number of ReadExReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 348 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 13842 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 117010 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 131471 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 348 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 13842 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 117010 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 131471 # number of overall misses
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3491 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523691 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172623 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 701801 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 120669 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 120669 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28853 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 28853 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22527 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 22527 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63613 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 63613 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3491 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 523691 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 236236 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 765414 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3491 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 523691 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 236236 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 765414 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.135772 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026432 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424144 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.124933 # miss rate for ReadReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9351 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4901 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903503 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 15213580 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 15213580 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3243 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1759 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510095 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.data 99336 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 614433 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 120654 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 120654 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 7 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19759 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 19759 # number of ReadExReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3243 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1759 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 510095 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 119095 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 634192 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3243 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1759 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 510095 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 119095 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 634192 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 343 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13819 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.data 73339 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 87768 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28855 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 28855 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22557 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 22557 # number of SCUpgradeReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43856 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 43856 # number of ReadExReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 343 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 13819 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 117195 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 131624 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 343 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 13819 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 117195 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 131624 # number of overall misses
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3586 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2026 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523914 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172675 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 702201 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 120654 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 120654 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28862 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 28862 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22557 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 22557 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3586 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2026 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 523914 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 236290 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 765816 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3586 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2026 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 523914 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 236290 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 765816 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.131787 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026376 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424723 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.124990 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses
1198,1209c1199,1210
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688428 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688428 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.135772 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026432 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495310 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.171765 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.135772 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026432 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495310 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.171765 # miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689397 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689397 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.131787 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026376 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495980 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.171874 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.131787 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026376 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495980 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.171874 # miss rate for overall accesses
1218,1219c1219,1220
< system.cpu1.l2cache.writebacks::writebacks 33034 # number of writebacks
< system.cpu1.l2cache.writebacks::total 33034 # number of writebacks
---
> system.cpu1.l2cache.writebacks::writebacks 32966 # number of writebacks
> system.cpu1.l2cache.writebacks::total 32966 # number of writebacks
1221,1229c1222,1230
< system.cpu1.dcache.tags.replacements 191901 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 472.757627 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 19500351 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 192255 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 101.429617 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 105851562500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757627 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy
---
> system.cpu1.dcache.tags.replacements 191947 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 19503515 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 101.421807 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy
1234,1291c1235,1292
< system.cpu1.dcache.tags.tag_accesses 39745522 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 39745522 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 11856979 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 11856979 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 7396120 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 7396120 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50084 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 50084 # number of SoftPFReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91418 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 91418 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72426 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 72426 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 19253099 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 19253099 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 19303183 # number of overall hits
< system.cpu1.dcache.overall_hits::total 19303183 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 136590 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 136590 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 92466 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 92466 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30716 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 30716 # number of SoftPFReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5317 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 5317 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22527 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 22527 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 229056 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 229056 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 259772 # number of overall misses
< system.cpu1.dcache.overall_misses::total 259772 # number of overall misses
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993569 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 11993569 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488586 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 7488586 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96735 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 96735 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94953 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 94953 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 19482155 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 19482155 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 19562955 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 19562955 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011389 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.011389 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380149 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380149 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054965 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054965 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237244 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237244 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses
---
> system.cpu1.dcache.tags.tag_accesses 39752012 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 39752012 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 11858696 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 11858696 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 7397487 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 7397487 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72422 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 72422 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 19256183 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 19256183 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 19306283 # number of overall hits
> system.cpu1.dcache.overall_hits::total 19306283 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 92477 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 92477 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22557 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 22557 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 229116 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 229116 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 259834 # number of overall misses
> system.cpu1.dcache.overall_misses::total 259834 # number of overall misses
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995335 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 11995335 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489964 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 7489964 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 19485299 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 19485299 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 19566117 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 19566117 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237495 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237495 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses
1300,1301c1301,1302
< system.cpu1.dcache.writebacks::writebacks 120669 # number of writebacks
< system.cpu1.dcache.writebacks::total 120669 # number of writebacks
---
> system.cpu1.dcache.writebacks::writebacks 120654 # number of writebacks
> system.cpu1.dcache.writebacks::total 120654 # number of writebacks
1303,1314c1304,1315
< system.cpu1.toL2Bus.trans_dist::ReadReq 709063 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 709063 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 120669 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 28853 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22527 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 63613 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 63613 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1047738 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707355 # Packet count per connected master and slave (bytes)
---
> system.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 120654 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 28862 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22557 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707532 # Packet count per connected master and slave (bytes)
1317,1319c1318,1320
< system.cpu1.toL2Bus.pkt_count::total 1773789 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33516936 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22861090 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu1.toL2Bus.pkt_count::total 1774410 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22863598 # Cumulative packet size per connected master and slave (bytes)
1322,1326c1323,1327
< system.cpu1.toL2Bus.pkt_size::total 56415418 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 499577 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 1371208 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 5.313508 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.463919 # Request fanout histogram
---
> system.cpu1.toL2Bus.pkt_size::total 56432194 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 499552 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 1371519 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 5.313444 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.463893 # Request fanout histogram
1333,1334c1334,1335
< system.cpu1.toL2Bus.snoop_fanout::5 941324 68.65% 68.65% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::6 429884 31.35% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::5 941625 68.66% 68.66% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::6 429894 31.34% 100.00% # Request fanout histogram
1338c1339
< system.cpu1.toL2Bus.snoop_fanout::total 1371208 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::total 1371519 # Request fanout histogram
1340c1341
< system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use
1344,1345c1345,1346
< system.iocache.tags.warmup_cycle 246641119509 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor