Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt

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stats.txt (11530:6e143fd2cabf)	stats.txt (11547:dd6dfd38b6c2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802882797500 # Number of ticks simulated 5final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802882797500 # Number of ticks simulated 5final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1371763 # Simulator instruction rate (inst/s) 8host_op_rate 1671473 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 26186322462 # Simulator tick rate (ticks/s) 10host_mem_usage 640448 # Number of bytes of host memory used 11host_seconds 107.04 # Real time elapsed on the host	7host_inst_rate 808897 # Simulator instruction rate (inst/s) 8host_op_rate 985629 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15441476365 # Simulator tick rate (ticks/s) 10host_mem_usage 596572 # Number of bytes of host memory used 11host_seconds 181.52 # Real time elapsed on the host
12sim_insts 146828219 # Number of instructions simulated 13sim_ops 178907974 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 1081872 # Number of bytes read from this memory 23system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 24system.physmem.bytes_read::total 11758444 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 1109284 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 1263160 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 8475520 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 31system.physmem.bytes_written::total 8493084 # Number of bytes written to this memory 32system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.inst 25786 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 147579 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 16924 # Number of read requests responded to by this memory 38system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 39system.physmem.num_reads::total 192873 # Number of read requests responded to by this memory 40system.physmem.num_writes::writebacks 132430 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 43system.physmem.num_writes::total 136821 # Number of write requests responded to by this memory 44system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 395765 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3357904 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.data 385985 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 4195125 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 395765 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 450665 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3023858 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 3030125 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3023858 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.inst 395765 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.data 3364156 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.data 386000 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::total 7225250 # Total bandwidth to/from this memory (bytes/s) 68system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 69system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 85system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 87system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 88system.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 89system.bridge.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 90system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 91system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 92system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 93system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 94system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 95system.cf0.dma_write_txs 631 # Number of DMA write transactions. 96system.cpu_clk_domain.clock 500 # Clock period in ticks 97system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 98system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 106system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 128system.cpu0.dtb.walker.walks 7964 # Table walker walks requested 129system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors 130system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency 131system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 132system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency 133system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 134system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 135system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 136system.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated 137system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated 138system.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated 139system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst 140system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 141system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 142system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 143system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 144system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 145system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 146system.cpu0.dtb.inst_hits 0 # ITB inst hits 147system.cpu0.dtb.inst_misses 0 # ITB inst misses 148system.cpu0.dtb.read_hits 20339694 # DTB read hits 149system.cpu0.dtb.read_misses 6871 # DTB read misses 150system.cpu0.dtb.write_hits 16391004 # DTB write hits 151system.cpu0.dtb.write_misses 1093 # DTB write misses 152system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 153system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 154system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 155system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	12sim_insts 146828219 # Number of instructions simulated 13sim_ops 178907974 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 1081872 # Number of bytes read from this memory 23system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 24system.physmem.bytes_read::total 11758444 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 1109284 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 1263160 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 8475520 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 31system.physmem.bytes_written::total 8493084 # Number of bytes written to this memory 32system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.inst 25786 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 147579 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 16924 # Number of read requests responded to by this memory 38system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 39system.physmem.num_reads::total 192873 # Number of read requests responded to by this memory 40system.physmem.num_writes::writebacks 132430 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 43system.physmem.num_writes::total 136821 # Number of write requests responded to by this memory 44system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 395765 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3357904 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.data 385985 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 4195125 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 395765 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 450665 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3023858 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 3030125 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3023858 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.inst 395765 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.data 3364156 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.data 386000 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::total 7225250 # Total bandwidth to/from this memory (bytes/s) 68system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 69system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 85system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 87system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 88system.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 89system.bridge.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 90system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 91system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 92system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 93system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 94system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 95system.cf0.dma_write_txs 631 # Number of DMA write transactions. 96system.cpu_clk_domain.clock 500 # Clock period in ticks 97system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 98system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 106system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 128system.cpu0.dtb.walker.walks 7964 # Table walker walks requested 129system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors 130system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency 131system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 132system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency 133system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 134system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 135system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 136system.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated 137system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated 138system.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated 139system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst 140system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 141system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 142system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 143system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 144system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 145system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 146system.cpu0.dtb.inst_hits 0 # ITB inst hits 147system.cpu0.dtb.inst_misses 0 # ITB inst misses 148system.cpu0.dtb.read_hits 20339694 # DTB read hits 149system.cpu0.dtb.read_misses 6871 # DTB read misses 150system.cpu0.dtb.write_hits 16391004 # DTB write hits 151system.cpu0.dtb.write_misses 1093 # DTB write misses 152system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 153system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 154system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 155system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
156system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB	156system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB
157system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 158system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 159system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 160system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 161system.cpu0.dtb.read_accesses 20346565 # DTB read accesses 162system.cpu0.dtb.write_accesses 16392097 # DTB write accesses 163system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 164system.cpu0.dtb.hits 36730698 # DTB hits 165system.cpu0.dtb.misses 7964 # DTB misses 166system.cpu0.dtb.accesses 36738662 # DTB accesses 167system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 168system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 169system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 170system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 171system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 172system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 173system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 174system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 175system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 176system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 177system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 178system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 179system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 180system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 181system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 182system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 183system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 184system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 185system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 186system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 187system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 188system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 189system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 190system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 191system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 192system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 193system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 194system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 195system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 196system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 197system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 198system.cpu0.itb.walker.walks 3358 # Table walker walks requested 199system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 200system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 201system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 202system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 203system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 204system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 205system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 206system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 207system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 208system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 209system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 210system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 211system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 212system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 213system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 214system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 215system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 216system.cpu0.itb.inst_hits 97439155 # ITB inst hits 217system.cpu0.itb.inst_misses 3358 # ITB inst misses 218system.cpu0.itb.read_hits 0 # DTB read hits 219system.cpu0.itb.read_misses 0 # DTB read misses 220system.cpu0.itb.write_hits 0 # DTB write hits 221system.cpu0.itb.write_misses 0 # DTB write misses 222system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 223system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 224system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 225system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	157system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 158system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 159system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 160system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 161system.cpu0.dtb.read_accesses 20346565 # DTB read accesses 162system.cpu0.dtb.write_accesses 16392097 # DTB write accesses 163system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 164system.cpu0.dtb.hits 36730698 # DTB hits 165system.cpu0.dtb.misses 7964 # DTB misses 166system.cpu0.dtb.accesses 36738662 # DTB accesses 167system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 168system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 169system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 170system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 171system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 172system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 173system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 174system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 175system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 176system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 177system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 178system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 179system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 180system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 181system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 182system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 183system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 184system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 185system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 186system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 187system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 188system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 189system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 190system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 191system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 192system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 193system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 194system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 195system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 196system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 197system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 198system.cpu0.itb.walker.walks 3358 # Table walker walks requested 199system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 200system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 201system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 202system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 203system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 204system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 205system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 206system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 207system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 208system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 209system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 210system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 211system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 212system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 213system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 214system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 215system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 216system.cpu0.itb.inst_hits 97439155 # ITB inst hits 217system.cpu0.itb.inst_misses 3358 # ITB inst misses 218system.cpu0.itb.read_hits 0 # DTB read hits 219system.cpu0.itb.read_misses 0 # DTB read misses 220system.cpu0.itb.write_hits 0 # DTB write hits 221system.cpu0.itb.write_misses 0 # DTB write misses 222system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 223system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 224system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 225system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
226system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB	226system.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB
227system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 228system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 229system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 230system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu0.itb.read_accesses 0 # DTB read accesses 232system.cpu0.itb.write_accesses 0 # DTB write accesses 233system.cpu0.itb.inst_accesses 97442513 # ITB inst accesses 234system.cpu0.itb.hits 97439155 # DTB hits 235system.cpu0.itb.misses 3358 # DTB misses 236system.cpu0.itb.accesses 97442513 # DTB accesses 237system.cpu0.numPwrStateTransitions 3932 # Number of power state transitions 238system.cpu0.pwrStateClkGateDist::samples 1966 # Distribution of time spent in the clock gated state 239system.cpu0.pwrStateClkGateDist::mean 1395773493.506104 # Distribution of time spent in the clock gated state 240system.cpu0.pwrStateClkGateDist::stdev 23114974453.612934 # Distribution of time spent in the clock gated state 241system.cpu0.pwrStateClkGateDist::underflows 1154 58.70% 58.70% # Distribution of time spent in the clock gated state 242system.cpu0.pwrStateClkGateDist::1000-5e+10 806 41.00% 99.69% # Distribution of time spent in the clock gated state 243system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state 244system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state 245system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state 246system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 247system.cpu0.pwrStateClkGateDist::max_value 499983242180 # Distribution of time spent in the clock gated state 248system.cpu0.pwrStateClkGateDist::total 1966 # Distribution of time spent in the clock gated state 249system.cpu0.pwrStateResidencyTicks::ON 58792109267 # Cumulative time (in ticks) in various power states 250system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744090688233 # Cumulative time (in ticks) in various power states 251system.cpu0.numCycles 5605767562 # number of cpu cycles simulated 252system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 253system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 254system.cpu0.kern.inst.arm 0 # number of arm instructions executed 255system.cpu0.kern.inst.quiesce 1966 # number of quiesce instructions executed 256system.cpu0.committedInsts 95426725 # Number of instructions committed 257system.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed 258system.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses 259system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 260system.cpu0.num_func_calls 8000241 # number of times a function call or return occured 261system.cpu0.num_conditional_control_insts 13204192 # number of instructions that are conditional controls 262system.cpu0.num_int_insts 100762477 # number of integer instructions 263system.cpu0.num_fp_insts 9755 # number of float instructions 264system.cpu0.num_int_register_reads 182433257 # number of times the integer registers were read 265system.cpu0.num_int_register_writes 69135397 # number of times the integer registers were written 266system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 267system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 268system.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read 269system.cpu0.num_cc_register_writes 44907357 # number of times the CC registers were written 270system.cpu0.num_mem_refs 37873679 # number of memory refs 271system.cpu0.num_load_insts 20597264 # Number of load instructions 272system.cpu0.num_store_insts 17276415 # Number of store instructions 273system.cpu0.num_idle_cycles 5488183302.205065 # Number of idle cycles 274system.cpu0.num_busy_cycles 117584259.794936 # Number of busy cycles 275system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 276system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 277system.cpu0.Branches 21941548 # Number of branches fetched 278system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 279system.cpu0.op_class::IntAlu 78887162 67.49% 67.50% # Class of executed instruction 280system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction 281system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 282system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 283system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 284system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 285system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 286system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 287system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 288system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 289system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 290system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 291system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 292system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 293system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 294system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 295system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 296system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 297system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 298system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 299system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 300system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 301system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 302system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 303system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 304system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 305system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 306system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 307system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 308system.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction 309system.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction 310system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 311system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 312system.cpu0.op_class::total 116881836 # Class of executed instruction 313system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 314system.cpu0.dcache.tags.replacements 693478 # number of replacements 315system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use 316system.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks. 317system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. 318system.cpu0.dcache.tags.avg_refs 51.776416 # Average number of references to valid blocks. 319system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 320system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor 321system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 322system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 323system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 324system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 325system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 326system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 327system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 328system.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses 329system.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses 330system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 331system.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits 332system.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits 333system.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits 334system.cpu0.dcache.WriteReq_hits::total 15690320 # number of WriteReq hits 335system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits 336system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits 337system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits 338system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits 339system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits 340system.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits 341system.cpu0.dcache.demand_hits::cpu0.data 34798851 # number of demand (read+write) hits 342system.cpu0.dcache.demand_hits::total 34798851 # number of demand (read+write) hits 343system.cpu0.dcache.overall_hits::cpu0.data 35144936 # number of overall hits 344system.cpu0.dcache.overall_hits::total 35144936 # number of overall hits 345system.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses 346system.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses 347system.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses 348system.cpu0.dcache.WriteReq_misses::total 295799 # number of WriteReq misses 349system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 350system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 351system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses 352system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses 353system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18431 # number of StoreCondReq misses 354system.cpu0.dcache.StoreCondReq_misses::total 18431 # number of StoreCondReq misses 355system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses 356system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses 357system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses 358system.cpu0.dcache.overall_misses::total 769220 # number of overall misses 359system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481631 # number of ReadReq accesses(hits+misses) 360system.cpu0.dcache.ReadReq_accesses::total 19481631 # number of ReadReq accesses(hits+misses) 361system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986119 # number of WriteReq accesses(hits+misses) 362system.cpu0.dcache.WriteReq_accesses::total 15986119 # number of WriteReq accesses(hits+misses) 363system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses) 364system.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses) 365system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses) 366system.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses) 367system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses) 368system.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses) 369system.cpu0.dcache.demand_accesses::cpu0.data 35467750 # number of demand (read+write) accesses 370system.cpu0.dcache.demand_accesses::total 35467750 # number of demand (read+write) accesses 371system.cpu0.dcache.overall_accesses::cpu0.data 35914156 # number of overall (read+write) accesses 372system.cpu0.dcache.overall_accesses::total 35914156 # number of overall (read+write) accesses 373system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 374system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 375system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 376system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 377system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224730 # miss rate for SoftPFReq accesses 378system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224730 # miss rate for SoftPFReq accesses 379system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses 380system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses 381system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048315 # miss rate for StoreCondReq accesses 382system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048315 # miss rate for StoreCondReq accesses 383system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses 384system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses 385system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses 386system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses 387system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 390system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 392system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 393system.cpu0.dcache.writebacks::writebacks 693478 # number of writebacks 394system.cpu0.dcache.writebacks::total 693478 # number of writebacks 395system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 396system.cpu0.icache.tags.replacements 1109639 # number of replacements 397system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 398system.cpu0.icache.tags.total_refs 96331337 # Total number of references to valid blocks. 399system.cpu0.icache.tags.sampled_refs 1110151 # Sample count of references to valid blocks. 400system.cpu0.icache.tags.avg_refs 86.773184 # Average number of references to valid blocks. 401system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 402system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 403system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 404system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 405system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 406system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 407system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 408system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 409system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 410system.cpu0.icache.tags.tag_accesses 195993154 # Number of tag accesses 411system.cpu0.icache.tags.data_accesses 195993154 # Number of data accesses 412system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 413system.cpu0.icache.ReadReq_hits::cpu0.inst 96331337 # number of ReadReq hits 414system.cpu0.icache.ReadReq_hits::total 96331337 # number of ReadReq hits 415system.cpu0.icache.demand_hits::cpu0.inst 96331337 # number of demand (read+write) hits 416system.cpu0.icache.demand_hits::total 96331337 # number of demand (read+write) hits 417system.cpu0.icache.overall_hits::cpu0.inst 96331337 # number of overall hits 418system.cpu0.icache.overall_hits::total 96331337 # number of overall hits 419system.cpu0.icache.ReadReq_misses::cpu0.inst 1110160 # number of ReadReq misses 420system.cpu0.icache.ReadReq_misses::total 1110160 # number of ReadReq misses 421system.cpu0.icache.demand_misses::cpu0.inst 1110160 # number of demand (read+write) misses 422system.cpu0.icache.demand_misses::total 1110160 # number of demand (read+write) misses 423system.cpu0.icache.overall_misses::cpu0.inst 1110160 # number of overall misses 424system.cpu0.icache.overall_misses::total 1110160 # number of overall misses 425system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441497 # number of ReadReq accesses(hits+misses) 426system.cpu0.icache.ReadReq_accesses::total 97441497 # number of ReadReq accesses(hits+misses) 427system.cpu0.icache.demand_accesses::cpu0.inst 97441497 # number of demand (read+write) accesses 428system.cpu0.icache.demand_accesses::total 97441497 # number of demand (read+write) accesses 429system.cpu0.icache.overall_accesses::cpu0.inst 97441497 # number of overall (read+write) accesses 430system.cpu0.icache.overall_accesses::total 97441497 # number of overall (read+write) accesses 431system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses 432system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses 433system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses 434system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses 435system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses 436system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses 437system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 438system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 439system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 440system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 441system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 442system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 443system.cpu0.icache.writebacks::writebacks 1109639 # number of writebacks 444system.cpu0.icache.writebacks::total 1109639 # number of writebacks 445system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 446system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 447system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 448system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 449system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 450system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 451system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 452system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 453system.cpu0.l2cache.tags.replacements 249747 # number of replacements 454system.cpu0.l2cache.tags.tagsinuse 16131.550435 # Cycle average of tags in use 455system.cpu0.l2cache.tags.total_refs 2729892 # Total number of references to valid blocks. 456system.cpu0.l2cache.tags.sampled_refs 265865 # Sample count of references to valid blocks. 457system.cpu0.l2cache.tags.avg_refs 10.267963 # Average number of references to valid blocks. 458system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 459system.cpu0.l2cache.tags.occ_blocks::writebacks 16129.097151 # Average occupied blocks per requestor 460system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.376905 # Average occupied blocks per requestor 461system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076379 # Average occupied blocks per requestor 462system.cpu0.l2cache.tags.occ_percent::writebacks 0.984442 # Average percentage of cache occupancy 463system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy 464system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 465system.cpu0.l2cache.tags.occ_percent::total 0.984592 # Average percentage of cache occupancy 466system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 467system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16110 # Occupied blocks per task id 468system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 469system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 470system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 471system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id 472system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id 473system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5562 # Occupied blocks per task id 474system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7431 # Occupied blocks per task id 475system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2624 # Occupied blocks per task id 476system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 477system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983276 # Percentage of cache occupancy per task id 478system.cpu0.l2cache.tags.tag_accesses 59696130 # Number of tag accesses 479system.cpu0.l2cache.tags.data_accesses 59696130 # Number of data accesses 480system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 481system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10179 # number of ReadReq hits 482system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4500 # number of ReadReq hits 483system.cpu0.l2cache.ReadReq_hits::total 14679 # number of ReadReq hits 484system.cpu0.l2cache.WritebackDirty_hits::writebacks 510228 # number of WritebackDirty hits 485system.cpu0.l2cache.WritebackDirty_hits::total 510228 # number of WritebackDirty hits 486system.cpu0.l2cache.WritebackClean_hits::writebacks 1265023 # number of WritebackClean hits 487system.cpu0.l2cache.WritebackClean_hits::total 1265023 # number of WritebackClean hits 488system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94248 # number of ReadExReq hits 489system.cpu0.l2cache.ReadExReq_hits::total 94248 # number of ReadExReq hits 490system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068491 # number of ReadCleanReq hits 491system.cpu0.l2cache.ReadCleanReq_hits::total 1068491 # number of ReadCleanReq hits 492system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352197 # number of ReadSharedReq hits 493system.cpu0.l2cache.ReadSharedReq_hits::total 352197 # number of ReadSharedReq hits 494system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10179 # number of demand (read+write) hits 495system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4500 # number of demand (read+write) hits 496system.cpu0.l2cache.demand_hits::cpu0.inst 1068491 # number of demand (read+write) hits 497system.cpu0.l2cache.demand_hits::cpu0.data 446445 # number of demand (read+write) hits 498system.cpu0.l2cache.demand_hits::total 1529615 # number of demand (read+write) hits 499system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10179 # number of overall hits 500system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4500 # number of overall hits 501system.cpu0.l2cache.overall_hits::cpu0.inst 1068491 # number of overall hits 502system.cpu0.l2cache.overall_hits::cpu0.data 446445 # number of overall hits 503system.cpu0.l2cache.overall_hits::total 1529615 # number of overall hits 504system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 212 # number of ReadReq misses 505system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 127 # number of ReadReq misses 506system.cpu0.l2cache.ReadReq_misses::total 339 # number of ReadReq misses 507system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26279 # number of UpgradeReq misses 508system.cpu0.l2cache.UpgradeReq_misses::total 26279 # number of UpgradeReq misses 509system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18431 # number of SCUpgradeReq misses 510system.cpu0.l2cache.SCUpgradeReq_misses::total 18431 # number of SCUpgradeReq misses 511system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175272 # number of ReadExReq misses 512system.cpu0.l2cache.ReadExReq_misses::total 175272 # number of ReadExReq misses 513system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41669 # number of ReadCleanReq misses 514system.cpu0.l2cache.ReadCleanReq_misses::total 41669 # number of ReadCleanReq misses 515system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127964 # number of ReadSharedReq misses 516system.cpu0.l2cache.ReadSharedReq_misses::total 127964 # number of ReadSharedReq misses 517system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 212 # number of demand (read+write) misses 518system.cpu0.l2cache.demand_misses::cpu0.itb.walker 127 # number of demand (read+write) misses 519system.cpu0.l2cache.demand_misses::cpu0.inst 41669 # number of demand (read+write) misses 520system.cpu0.l2cache.demand_misses::cpu0.data 303236 # number of demand (read+write) misses 521system.cpu0.l2cache.demand_misses::total 345244 # number of demand (read+write) misses 522system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 212 # number of overall misses 523system.cpu0.l2cache.overall_misses::cpu0.itb.walker 127 # number of overall misses 524system.cpu0.l2cache.overall_misses::cpu0.inst 41669 # number of overall misses 525system.cpu0.l2cache.overall_misses::cpu0.data 303236 # number of overall misses 526system.cpu0.l2cache.overall_misses::total 345244 # number of overall misses 527system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10391 # number of ReadReq accesses(hits+misses) 528system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) 529system.cpu0.l2cache.ReadReq_accesses::total 15018 # number of ReadReq accesses(hits+misses) 530system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510228 # number of WritebackDirty accesses(hits+misses) 531system.cpu0.l2cache.WritebackDirty_accesses::total 510228 # number of WritebackDirty accesses(hits+misses) 532system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265023 # number of WritebackClean accesses(hits+misses) 533system.cpu0.l2cache.WritebackClean_accesses::total 1265023 # number of WritebackClean accesses(hits+misses) 534system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26279 # number of UpgradeReq accesses(hits+misses) 535system.cpu0.l2cache.UpgradeReq_accesses::total 26279 # number of UpgradeReq accesses(hits+misses) 536system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18431 # number of SCUpgradeReq accesses(hits+misses) 537system.cpu0.l2cache.SCUpgradeReq_accesses::total 18431 # number of SCUpgradeReq accesses(hits+misses) 538system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269520 # number of ReadExReq accesses(hits+misses) 539system.cpu0.l2cache.ReadExReq_accesses::total 269520 # number of ReadExReq accesses(hits+misses) 540system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110160 # number of ReadCleanReq accesses(hits+misses) 541system.cpu0.l2cache.ReadCleanReq_accesses::total 1110160 # number of ReadCleanReq accesses(hits+misses) 542system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480161 # number of ReadSharedReq accesses(hits+misses) 543system.cpu0.l2cache.ReadSharedReq_accesses::total 480161 # number of ReadSharedReq accesses(hits+misses) 544system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10391 # number of demand (read+write) accesses 545system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses 546system.cpu0.l2cache.demand_accesses::cpu0.inst 1110160 # number of demand (read+write) accesses 547system.cpu0.l2cache.demand_accesses::cpu0.data 749681 # number of demand (read+write) accesses 548system.cpu0.l2cache.demand_accesses::total 1874859 # number of demand (read+write) accesses 549system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10391 # number of overall (read+write) accesses 550system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses 551system.cpu0.l2cache.overall_accesses::cpu0.inst 1110160 # number of overall (read+write) accesses 552system.cpu0.l2cache.overall_accesses::cpu0.data 749681 # number of overall (read+write) accesses 553system.cpu0.l2cache.overall_accesses::total 1874859 # number of overall (read+write) accesses 554system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for ReadReq accesses 555system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027448 # miss rate for ReadReq accesses 556system.cpu0.l2cache.ReadReq_miss_rate::total 0.022573 # miss rate for ReadReq accesses 557system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 558system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 559system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 560system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 561system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650312 # miss rate for ReadExReq accesses 562system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650312 # miss rate for ReadExReq accesses 563system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037534 # miss rate for ReadCleanReq accesses 564system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037534 # miss rate for ReadCleanReq accesses 565system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266502 # miss rate for ReadSharedReq accesses 566system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266502 # miss rate for ReadSharedReq accesses 567system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for demand accesses 568system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027448 # miss rate for demand accesses 569system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037534 # miss rate for demand accesses 570system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404487 # miss rate for demand accesses 571system.cpu0.l2cache.demand_miss_rate::total 0.184144 # miss rate for demand accesses 572system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for overall accesses 573system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027448 # miss rate for overall accesses 574system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037534 # miss rate for overall accesses 575system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404487 # miss rate for overall accesses 576system.cpu0.l2cache.overall_miss_rate::total 0.184144 # miss rate for overall accesses 577system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 578system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 579system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 580system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 581system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 582system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 583system.cpu0.l2cache.writebacks::writebacks 193031 # number of writebacks 584system.cpu0.l2cache.writebacks::total 193031 # number of writebacks 585system.cpu0.toL2Bus.snoop_filter.tot_requests 3720034 # Total number of requests made to the snoop filter. 586system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860217 # Number of requests hitting in the snoop filter with a single holder of the requested data. 587system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 588system.cpu0.toL2Bus.snoop_filter.tot_snoops 218415 # Total number of snoops made to the snoop filter. 589system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215401 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 590system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3014 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 591system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 592system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution 593system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution 594system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 595system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 596system.cpu0.toL2Bus.trans_dist::WritebackDirty 510228 # Transaction distribution 597system.cpu0.toL2Bus.trans_dist::WritebackClean 1292889 # Transaction distribution 598system.cpu0.toL2Bus.trans_dist::UpgradeReq 26279 # Transaction distribution 599system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18431 # Transaction distribution 600system.cpu0.toL2Bus.trans_dist::UpgradeResp 44710 # Transaction distribution 601system.cpu0.toL2Bus.trans_dist::ReadExReq 269520 # Transaction distribution 602system.cpu0.toL2Bus.trans_dist::ReadExResp 269520 # Transaction distribution 603system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110160 # Transaction distribution 604system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480161 # Transaction distribution 605system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348003 # Packet count per connected master and slave (bytes) 606system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402094 # Packet count per connected master and slave (bytes) 607system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 608system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 609system.cpu0.toL2Bus.pkt_count::total 5791721 # Packet count per connected master and slave (bytes) 610system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142103224 # Cumulative packet size per connected master and slave (bytes) 611system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552708 # Cumulative packet size per connected master and slave (bytes) 612system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 613system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 614system.cpu0.toL2Bus.pkt_size::total 234739180 # Cumulative packet size per connected master and slave (bytes) 615system.cpu0.toL2Bus.snoops 623521 # Total snoops (count) 616system.cpu0.toL2Bus.snoop_fanout::samples 4318336 # Request fanout histogram 617system.cpu0.toL2Bus.snoop_fanout::mean 0.067052 # Request fanout histogram 618system.cpu0.toL2Bus.snoop_fanout::stdev 0.252886 # Request fanout histogram 619system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 620system.cpu0.toL2Bus.snoop_fanout::0 4031799 93.36% 93.36% # Request fanout histogram 621system.cpu0.toL2Bus.snoop_fanout::1 283523 6.57% 99.93% # Request fanout histogram 622system.cpu0.toL2Bus.snoop_fanout::2 3014 0.07% 100.00% # Request fanout histogram 623system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 624system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 625system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 626system.cpu0.toL2Bus.snoop_fanout::total 4318336 # Request fanout histogram 627system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 628system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 629system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 630system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 631system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 632system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 633system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 636system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 637system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 638system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 639system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 640system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 641system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 642system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 643system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 644system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 645system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 646system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 647system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 648system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 649system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 650system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 651system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 652system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 653system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 654system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 655system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 656system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 657system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 658system.cpu1.dtb.walker.walks 3359 # Table walker walks requested 659system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 660system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 661system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 662system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 663system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 664system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 665system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 666system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated 667system.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated 668system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated 669system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst 670system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 671system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst 672system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst 673system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 674system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst 675system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst 676system.cpu1.dtb.inst_hits 0 # ITB inst hits 677system.cpu1.dtb.inst_misses 0 # ITB inst misses 678system.cpu1.dtb.read_hits 12173945 # DTB read hits 679system.cpu1.dtb.read_misses 2853 # DTB read misses 680system.cpu1.dtb.write_hits 7587221 # DTB write hits 681system.cpu1.dtb.write_misses 506 # DTB write misses 682system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 683system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 684system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 685system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	227system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 228system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 229system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 230system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu0.itb.read_accesses 0 # DTB read accesses 232system.cpu0.itb.write_accesses 0 # DTB write accesses 233system.cpu0.itb.inst_accesses 97442513 # ITB inst accesses 234system.cpu0.itb.hits 97439155 # DTB hits 235system.cpu0.itb.misses 3358 # DTB misses 236system.cpu0.itb.accesses 97442513 # DTB accesses 237system.cpu0.numPwrStateTransitions 3932 # Number of power state transitions 238system.cpu0.pwrStateClkGateDist::samples 1966 # Distribution of time spent in the clock gated state 239system.cpu0.pwrStateClkGateDist::mean 1395773493.506104 # Distribution of time spent in the clock gated state 240system.cpu0.pwrStateClkGateDist::stdev 23114974453.612934 # Distribution of time spent in the clock gated state 241system.cpu0.pwrStateClkGateDist::underflows 1154 58.70% 58.70% # Distribution of time spent in the clock gated state 242system.cpu0.pwrStateClkGateDist::1000-5e+10 806 41.00% 99.69% # Distribution of time spent in the clock gated state 243system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state 244system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state 245system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state 246system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 247system.cpu0.pwrStateClkGateDist::max_value 499983242180 # Distribution of time spent in the clock gated state 248system.cpu0.pwrStateClkGateDist::total 1966 # Distribution of time spent in the clock gated state 249system.cpu0.pwrStateResidencyTicks::ON 58792109267 # Cumulative time (in ticks) in various power states 250system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744090688233 # Cumulative time (in ticks) in various power states 251system.cpu0.numCycles 5605767562 # number of cpu cycles simulated 252system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 253system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 254system.cpu0.kern.inst.arm 0 # number of arm instructions executed 255system.cpu0.kern.inst.quiesce 1966 # number of quiesce instructions executed 256system.cpu0.committedInsts 95426725 # Number of instructions committed 257system.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed 258system.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses 259system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 260system.cpu0.num_func_calls 8000241 # number of times a function call or return occured 261system.cpu0.num_conditional_control_insts 13204192 # number of instructions that are conditional controls 262system.cpu0.num_int_insts 100762477 # number of integer instructions 263system.cpu0.num_fp_insts 9755 # number of float instructions 264system.cpu0.num_int_register_reads 182433257 # number of times the integer registers were read 265system.cpu0.num_int_register_writes 69135397 # number of times the integer registers were written 266system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 267system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 268system.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read 269system.cpu0.num_cc_register_writes 44907357 # number of times the CC registers were written 270system.cpu0.num_mem_refs 37873679 # number of memory refs 271system.cpu0.num_load_insts 20597264 # Number of load instructions 272system.cpu0.num_store_insts 17276415 # Number of store instructions 273system.cpu0.num_idle_cycles 5488183302.205065 # Number of idle cycles 274system.cpu0.num_busy_cycles 117584259.794936 # Number of busy cycles 275system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 276system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 277system.cpu0.Branches 21941548 # Number of branches fetched 278system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 279system.cpu0.op_class::IntAlu 78887162 67.49% 67.50% # Class of executed instruction 280system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction 281system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 282system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 283system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 284system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 285system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 286system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 287system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 288system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 289system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 290system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 291system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 292system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 293system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 294system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 295system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 296system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 297system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 298system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 299system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 300system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 301system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 302system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 303system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 304system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 305system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 306system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 307system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 308system.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction 309system.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction 310system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 311system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 312system.cpu0.op_class::total 116881836 # Class of executed instruction 313system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 314system.cpu0.dcache.tags.replacements 693478 # number of replacements 315system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use 316system.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks. 317system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. 318system.cpu0.dcache.tags.avg_refs 51.776416 # Average number of references to valid blocks. 319system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 320system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor 321system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 322system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 323system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 324system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 325system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 326system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 327system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 328system.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses 329system.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses 330system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 331system.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits 332system.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits 333system.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits 334system.cpu0.dcache.WriteReq_hits::total 15690320 # number of WriteReq hits 335system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits 336system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits 337system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits 338system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits 339system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits 340system.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits 341system.cpu0.dcache.demand_hits::cpu0.data 34798851 # number of demand (read+write) hits 342system.cpu0.dcache.demand_hits::total 34798851 # number of demand (read+write) hits 343system.cpu0.dcache.overall_hits::cpu0.data 35144936 # number of overall hits 344system.cpu0.dcache.overall_hits::total 35144936 # number of overall hits 345system.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses 346system.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses 347system.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses 348system.cpu0.dcache.WriteReq_misses::total 295799 # number of WriteReq misses 349system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 350system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 351system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses 352system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses 353system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18431 # number of StoreCondReq misses 354system.cpu0.dcache.StoreCondReq_misses::total 18431 # number of StoreCondReq misses 355system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses 356system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses 357system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses 358system.cpu0.dcache.overall_misses::total 769220 # number of overall misses 359system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481631 # number of ReadReq accesses(hits+misses) 360system.cpu0.dcache.ReadReq_accesses::total 19481631 # number of ReadReq accesses(hits+misses) 361system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986119 # number of WriteReq accesses(hits+misses) 362system.cpu0.dcache.WriteReq_accesses::total 15986119 # number of WriteReq accesses(hits+misses) 363system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses) 364system.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses) 365system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses) 366system.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses) 367system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses) 368system.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses) 369system.cpu0.dcache.demand_accesses::cpu0.data 35467750 # number of demand (read+write) accesses 370system.cpu0.dcache.demand_accesses::total 35467750 # number of demand (read+write) accesses 371system.cpu0.dcache.overall_accesses::cpu0.data 35914156 # number of overall (read+write) accesses 372system.cpu0.dcache.overall_accesses::total 35914156 # number of overall (read+write) accesses 373system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 374system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 375system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 376system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 377system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224730 # miss rate for SoftPFReq accesses 378system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224730 # miss rate for SoftPFReq accesses 379system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses 380system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses 381system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048315 # miss rate for StoreCondReq accesses 382system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048315 # miss rate for StoreCondReq accesses 383system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses 384system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses 385system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses 386system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses 387system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 390system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 392system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 393system.cpu0.dcache.writebacks::writebacks 693478 # number of writebacks 394system.cpu0.dcache.writebacks::total 693478 # number of writebacks 395system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 396system.cpu0.icache.tags.replacements 1109639 # number of replacements 397system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 398system.cpu0.icache.tags.total_refs 96331337 # Total number of references to valid blocks. 399system.cpu0.icache.tags.sampled_refs 1110151 # Sample count of references to valid blocks. 400system.cpu0.icache.tags.avg_refs 86.773184 # Average number of references to valid blocks. 401system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 402system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 403system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 404system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 405system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 406system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 407system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 408system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 409system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 410system.cpu0.icache.tags.tag_accesses 195993154 # Number of tag accesses 411system.cpu0.icache.tags.data_accesses 195993154 # Number of data accesses 412system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 413system.cpu0.icache.ReadReq_hits::cpu0.inst 96331337 # number of ReadReq hits 414system.cpu0.icache.ReadReq_hits::total 96331337 # number of ReadReq hits 415system.cpu0.icache.demand_hits::cpu0.inst 96331337 # number of demand (read+write) hits 416system.cpu0.icache.demand_hits::total 96331337 # number of demand (read+write) hits 417system.cpu0.icache.overall_hits::cpu0.inst 96331337 # number of overall hits 418system.cpu0.icache.overall_hits::total 96331337 # number of overall hits 419system.cpu0.icache.ReadReq_misses::cpu0.inst 1110160 # number of ReadReq misses 420system.cpu0.icache.ReadReq_misses::total 1110160 # number of ReadReq misses 421system.cpu0.icache.demand_misses::cpu0.inst 1110160 # number of demand (read+write) misses 422system.cpu0.icache.demand_misses::total 1110160 # number of demand (read+write) misses 423system.cpu0.icache.overall_misses::cpu0.inst 1110160 # number of overall misses 424system.cpu0.icache.overall_misses::total 1110160 # number of overall misses 425system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441497 # number of ReadReq accesses(hits+misses) 426system.cpu0.icache.ReadReq_accesses::total 97441497 # number of ReadReq accesses(hits+misses) 427system.cpu0.icache.demand_accesses::cpu0.inst 97441497 # number of demand (read+write) accesses 428system.cpu0.icache.demand_accesses::total 97441497 # number of demand (read+write) accesses 429system.cpu0.icache.overall_accesses::cpu0.inst 97441497 # number of overall (read+write) accesses 430system.cpu0.icache.overall_accesses::total 97441497 # number of overall (read+write) accesses 431system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses 432system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses 433system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses 434system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses 435system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses 436system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses 437system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 438system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 439system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 440system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 441system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 442system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 443system.cpu0.icache.writebacks::writebacks 1109639 # number of writebacks 444system.cpu0.icache.writebacks::total 1109639 # number of writebacks 445system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 446system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 447system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 448system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 449system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 450system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 451system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 452system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 453system.cpu0.l2cache.tags.replacements 249747 # number of replacements 454system.cpu0.l2cache.tags.tagsinuse 16131.550435 # Cycle average of tags in use 455system.cpu0.l2cache.tags.total_refs 2729892 # Total number of references to valid blocks. 456system.cpu0.l2cache.tags.sampled_refs 265865 # Sample count of references to valid blocks. 457system.cpu0.l2cache.tags.avg_refs 10.267963 # Average number of references to valid blocks. 458system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 459system.cpu0.l2cache.tags.occ_blocks::writebacks 16129.097151 # Average occupied blocks per requestor 460system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.376905 # Average occupied blocks per requestor 461system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076379 # Average occupied blocks per requestor 462system.cpu0.l2cache.tags.occ_percent::writebacks 0.984442 # Average percentage of cache occupancy 463system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy 464system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 465system.cpu0.l2cache.tags.occ_percent::total 0.984592 # Average percentage of cache occupancy 466system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 467system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16110 # Occupied blocks per task id 468system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 469system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 470system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 471system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id 472system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id 473system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5562 # Occupied blocks per task id 474system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7431 # Occupied blocks per task id 475system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2624 # Occupied blocks per task id 476system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 477system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983276 # Percentage of cache occupancy per task id 478system.cpu0.l2cache.tags.tag_accesses 59696130 # Number of tag accesses 479system.cpu0.l2cache.tags.data_accesses 59696130 # Number of data accesses 480system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 481system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10179 # number of ReadReq hits 482system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4500 # number of ReadReq hits 483system.cpu0.l2cache.ReadReq_hits::total 14679 # number of ReadReq hits 484system.cpu0.l2cache.WritebackDirty_hits::writebacks 510228 # number of WritebackDirty hits 485system.cpu0.l2cache.WritebackDirty_hits::total 510228 # number of WritebackDirty hits 486system.cpu0.l2cache.WritebackClean_hits::writebacks 1265023 # number of WritebackClean hits 487system.cpu0.l2cache.WritebackClean_hits::total 1265023 # number of WritebackClean hits 488system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94248 # number of ReadExReq hits 489system.cpu0.l2cache.ReadExReq_hits::total 94248 # number of ReadExReq hits 490system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068491 # number of ReadCleanReq hits 491system.cpu0.l2cache.ReadCleanReq_hits::total 1068491 # number of ReadCleanReq hits 492system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352197 # number of ReadSharedReq hits 493system.cpu0.l2cache.ReadSharedReq_hits::total 352197 # number of ReadSharedReq hits 494system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10179 # number of demand (read+write) hits 495system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4500 # number of demand (read+write) hits 496system.cpu0.l2cache.demand_hits::cpu0.inst 1068491 # number of demand (read+write) hits 497system.cpu0.l2cache.demand_hits::cpu0.data 446445 # number of demand (read+write) hits 498system.cpu0.l2cache.demand_hits::total 1529615 # number of demand (read+write) hits 499system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10179 # number of overall hits 500system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4500 # number of overall hits 501system.cpu0.l2cache.overall_hits::cpu0.inst 1068491 # number of overall hits 502system.cpu0.l2cache.overall_hits::cpu0.data 446445 # number of overall hits 503system.cpu0.l2cache.overall_hits::total 1529615 # number of overall hits 504system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 212 # number of ReadReq misses 505system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 127 # number of ReadReq misses 506system.cpu0.l2cache.ReadReq_misses::total 339 # number of ReadReq misses 507system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26279 # number of UpgradeReq misses 508system.cpu0.l2cache.UpgradeReq_misses::total 26279 # number of UpgradeReq misses 509system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18431 # number of SCUpgradeReq misses 510system.cpu0.l2cache.SCUpgradeReq_misses::total 18431 # number of SCUpgradeReq misses 511system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175272 # number of ReadExReq misses 512system.cpu0.l2cache.ReadExReq_misses::total 175272 # number of ReadExReq misses 513system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41669 # number of ReadCleanReq misses 514system.cpu0.l2cache.ReadCleanReq_misses::total 41669 # number of ReadCleanReq misses 515system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127964 # number of ReadSharedReq misses 516system.cpu0.l2cache.ReadSharedReq_misses::total 127964 # number of ReadSharedReq misses 517system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 212 # number of demand (read+write) misses 518system.cpu0.l2cache.demand_misses::cpu0.itb.walker 127 # number of demand (read+write) misses 519system.cpu0.l2cache.demand_misses::cpu0.inst 41669 # number of demand (read+write) misses 520system.cpu0.l2cache.demand_misses::cpu0.data 303236 # number of demand (read+write) misses 521system.cpu0.l2cache.demand_misses::total 345244 # number of demand (read+write) misses 522system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 212 # number of overall misses 523system.cpu0.l2cache.overall_misses::cpu0.itb.walker 127 # number of overall misses 524system.cpu0.l2cache.overall_misses::cpu0.inst 41669 # number of overall misses 525system.cpu0.l2cache.overall_misses::cpu0.data 303236 # number of overall misses 526system.cpu0.l2cache.overall_misses::total 345244 # number of overall misses 527system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10391 # number of ReadReq accesses(hits+misses) 528system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) 529system.cpu0.l2cache.ReadReq_accesses::total 15018 # number of ReadReq accesses(hits+misses) 530system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510228 # number of WritebackDirty accesses(hits+misses) 531system.cpu0.l2cache.WritebackDirty_accesses::total 510228 # number of WritebackDirty accesses(hits+misses) 532system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265023 # number of WritebackClean accesses(hits+misses) 533system.cpu0.l2cache.WritebackClean_accesses::total 1265023 # number of WritebackClean accesses(hits+misses) 534system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26279 # number of UpgradeReq accesses(hits+misses) 535system.cpu0.l2cache.UpgradeReq_accesses::total 26279 # number of UpgradeReq accesses(hits+misses) 536system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18431 # number of SCUpgradeReq accesses(hits+misses) 537system.cpu0.l2cache.SCUpgradeReq_accesses::total 18431 # number of SCUpgradeReq accesses(hits+misses) 538system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269520 # number of ReadExReq accesses(hits+misses) 539system.cpu0.l2cache.ReadExReq_accesses::total 269520 # number of ReadExReq accesses(hits+misses) 540system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110160 # number of ReadCleanReq accesses(hits+misses) 541system.cpu0.l2cache.ReadCleanReq_accesses::total 1110160 # number of ReadCleanReq accesses(hits+misses) 542system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480161 # number of ReadSharedReq accesses(hits+misses) 543system.cpu0.l2cache.ReadSharedReq_accesses::total 480161 # number of ReadSharedReq accesses(hits+misses) 544system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10391 # number of demand (read+write) accesses 545system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses 546system.cpu0.l2cache.demand_accesses::cpu0.inst 1110160 # number of demand (read+write) accesses 547system.cpu0.l2cache.demand_accesses::cpu0.data 749681 # number of demand (read+write) accesses 548system.cpu0.l2cache.demand_accesses::total 1874859 # number of demand (read+write) accesses 549system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10391 # number of overall (read+write) accesses 550system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses 551system.cpu0.l2cache.overall_accesses::cpu0.inst 1110160 # number of overall (read+write) accesses 552system.cpu0.l2cache.overall_accesses::cpu0.data 749681 # number of overall (read+write) accesses 553system.cpu0.l2cache.overall_accesses::total 1874859 # number of overall (read+write) accesses 554system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for ReadReq accesses 555system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027448 # miss rate for ReadReq accesses 556system.cpu0.l2cache.ReadReq_miss_rate::total 0.022573 # miss rate for ReadReq accesses 557system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 558system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 559system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 560system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 561system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650312 # miss rate for ReadExReq accesses 562system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650312 # miss rate for ReadExReq accesses 563system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037534 # miss rate for ReadCleanReq accesses 564system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037534 # miss rate for ReadCleanReq accesses 565system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266502 # miss rate for ReadSharedReq accesses 566system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266502 # miss rate for ReadSharedReq accesses 567system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for demand accesses 568system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027448 # miss rate for demand accesses 569system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037534 # miss rate for demand accesses 570system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404487 # miss rate for demand accesses 571system.cpu0.l2cache.demand_miss_rate::total 0.184144 # miss rate for demand accesses 572system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for overall accesses 573system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027448 # miss rate for overall accesses 574system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037534 # miss rate for overall accesses 575system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404487 # miss rate for overall accesses 576system.cpu0.l2cache.overall_miss_rate::total 0.184144 # miss rate for overall accesses 577system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 578system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 579system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 580system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 581system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 582system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 583system.cpu0.l2cache.writebacks::writebacks 193031 # number of writebacks 584system.cpu0.l2cache.writebacks::total 193031 # number of writebacks 585system.cpu0.toL2Bus.snoop_filter.tot_requests 3720034 # Total number of requests made to the snoop filter. 586system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860217 # Number of requests hitting in the snoop filter with a single holder of the requested data. 587system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 588system.cpu0.toL2Bus.snoop_filter.tot_snoops 218415 # Total number of snoops made to the snoop filter. 589system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215401 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 590system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3014 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 591system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 592system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution 593system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution 594system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 595system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 596system.cpu0.toL2Bus.trans_dist::WritebackDirty 510228 # Transaction distribution 597system.cpu0.toL2Bus.trans_dist::WritebackClean 1292889 # Transaction distribution 598system.cpu0.toL2Bus.trans_dist::UpgradeReq 26279 # Transaction distribution 599system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18431 # Transaction distribution 600system.cpu0.toL2Bus.trans_dist::UpgradeResp 44710 # Transaction distribution 601system.cpu0.toL2Bus.trans_dist::ReadExReq 269520 # Transaction distribution 602system.cpu0.toL2Bus.trans_dist::ReadExResp 269520 # Transaction distribution 603system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110160 # Transaction distribution 604system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480161 # Transaction distribution 605system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348003 # Packet count per connected master and slave (bytes) 606system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402094 # Packet count per connected master and slave (bytes) 607system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 608system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 609system.cpu0.toL2Bus.pkt_count::total 5791721 # Packet count per connected master and slave (bytes) 610system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142103224 # Cumulative packet size per connected master and slave (bytes) 611system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552708 # Cumulative packet size per connected master and slave (bytes) 612system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 613system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 614system.cpu0.toL2Bus.pkt_size::total 234739180 # Cumulative packet size per connected master and slave (bytes) 615system.cpu0.toL2Bus.snoops 623521 # Total snoops (count) 616system.cpu0.toL2Bus.snoop_fanout::samples 4318336 # Request fanout histogram 617system.cpu0.toL2Bus.snoop_fanout::mean 0.067052 # Request fanout histogram 618system.cpu0.toL2Bus.snoop_fanout::stdev 0.252886 # Request fanout histogram 619system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 620system.cpu0.toL2Bus.snoop_fanout::0 4031799 93.36% 93.36% # Request fanout histogram 621system.cpu0.toL2Bus.snoop_fanout::1 283523 6.57% 99.93% # Request fanout histogram 622system.cpu0.toL2Bus.snoop_fanout::2 3014 0.07% 100.00% # Request fanout histogram 623system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 624system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 625system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 626system.cpu0.toL2Bus.snoop_fanout::total 4318336 # Request fanout histogram 627system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 628system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 629system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 630system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 631system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 632system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 633system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 636system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 637system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 638system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 639system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 640system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 641system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 642system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 643system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 644system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 645system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 646system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 647system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 648system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 649system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 650system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 651system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 652system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 653system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 654system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 655system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 656system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 657system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 658system.cpu1.dtb.walker.walks 3359 # Table walker walks requested 659system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 660system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 661system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 662system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 663system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 664system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 665system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 666system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated 667system.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated 668system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated 669system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst 670system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 671system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst 672system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst 673system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 674system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst 675system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst 676system.cpu1.dtb.inst_hits 0 # ITB inst hits 677system.cpu1.dtb.inst_misses 0 # ITB inst misses 678system.cpu1.dtb.read_hits 12173945 # DTB read hits 679system.cpu1.dtb.read_misses 2853 # DTB read misses 680system.cpu1.dtb.write_hits 7587221 # DTB write hits 681system.cpu1.dtb.write_misses 506 # DTB write misses 682system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 683system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 684system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 685system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
686system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB	686system.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB
687system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 688system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 689system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 690system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 691system.cpu1.dtb.read_accesses 12176798 # DTB read accesses 692system.cpu1.dtb.write_accesses 7587727 # DTB write accesses 693system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 694system.cpu1.dtb.hits 19761166 # DTB hits 695system.cpu1.dtb.misses 3359 # DTB misses 696system.cpu1.dtb.accesses 19764525 # DTB accesses 697system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 698system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 699system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 700system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 701system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 702system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 703system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 704system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 705system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 706system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 707system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 708system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 709system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 710system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 711system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 712system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 713system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 714system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 715system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 716system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 717system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 718system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 719system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 720system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 721system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 722system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 723system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 724system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 725system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 726system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 727system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 728system.cpu1.itb.walker.walks 1734 # Table walker walks requested 729system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 730system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 731system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 732system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 733system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 734system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 735system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 736system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 737system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 738system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 739system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 740system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 741system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 742system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 743system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 744system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 745system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 746system.cpu1.itb.inst_hits 53671758 # ITB inst hits 747system.cpu1.itb.inst_misses 1734 # ITB inst misses 748system.cpu1.itb.read_hits 0 # DTB read hits 749system.cpu1.itb.read_misses 0 # DTB read misses 750system.cpu1.itb.write_hits 0 # DTB write hits 751system.cpu1.itb.write_misses 0 # DTB write misses 752system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 753system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 754system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 755system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	687system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 688system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 689system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 690system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 691system.cpu1.dtb.read_accesses 12176798 # DTB read accesses 692system.cpu1.dtb.write_accesses 7587727 # DTB write accesses 693system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 694system.cpu1.dtb.hits 19761166 # DTB hits 695system.cpu1.dtb.misses 3359 # DTB misses 696system.cpu1.dtb.accesses 19764525 # DTB accesses 697system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 698system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 699system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 700system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 701system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 702system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 703system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 704system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 705system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 706system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 707system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 708system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 709system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 710system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 711system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 712system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 713system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 714system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 715system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 716system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 717system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 718system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 719system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 720system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 721system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 722system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 723system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 724system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 725system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 726system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 727system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 728system.cpu1.itb.walker.walks 1734 # Table walker walks requested 729system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 730system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 731system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 732system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 733system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 734system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 735system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 736system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 737system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 738system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 739system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 740system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 741system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 742system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 743system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 744system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 745system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 746system.cpu1.itb.inst_hits 53671758 # ITB inst hits 747system.cpu1.itb.inst_misses 1734 # ITB inst misses 748system.cpu1.itb.read_hits 0 # DTB read hits 749system.cpu1.itb.read_misses 0 # DTB read misses 750system.cpu1.itb.write_hits 0 # DTB write hits 751system.cpu1.itb.write_misses 0 # DTB write misses 752system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 753system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 754system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 755system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
756system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB	756system.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB
757system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 758system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 759system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 760system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 761system.cpu1.itb.read_accesses 0 # DTB read accesses 762system.cpu1.itb.write_accesses 0 # DTB write accesses 763system.cpu1.itb.inst_accesses 53673492 # ITB inst accesses 764system.cpu1.itb.hits 53671758 # DTB hits 765system.cpu1.itb.misses 1734 # DTB misses 766system.cpu1.itb.accesses 53673492 # DTB accesses 767system.cpu1.numPwrStateTransitions 5477 # Number of power state transitions 768system.cpu1.pwrStateClkGateDist::samples 2739 # Distribution of time spent in the clock gated state 769system.cpu1.pwrStateClkGateDist::mean 1011344723.290617 # Distribution of time spent in the clock gated state 770system.cpu1.pwrStateClkGateDist::stdev 25846310002.973743 # Distribution of time spent in the clock gated state 771system.cpu1.pwrStateClkGateDist::underflows 1957 71.45% 71.45% # Distribution of time spent in the clock gated state 772system.cpu1.pwrStateClkGateDist::1000-5e+10 777 28.37% 99.82% # Distribution of time spent in the clock gated state 773system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state 774system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 775system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 776system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 777system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 778system.cpu1.pwrStateClkGateDist::max_value 979984930372 # Distribution of time spent in the clock gated state 779system.cpu1.pwrStateClkGateDist::total 2739 # Distribution of time spent in the clock gated state 780system.cpu1.pwrStateResidencyTicks::ON 32809600407 # Cumulative time (in ticks) in various power states 781system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770073197093 # Cumulative time (in ticks) in various power states 782system.cpu1.numCycles 5605296470 # number of cpu cycles simulated 783system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 784system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 785system.cpu1.kern.inst.arm 0 # number of arm instructions executed 786system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 787system.cpu1.committedInsts 51401494 # Number of instructions committed 788system.cpu1.committedOps 63347804 # Number of ops (including micro ops) committed 789system.cpu1.num_int_alu_accesses 56984416 # Number of integer alu accesses 790system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 791system.cpu1.num_func_calls 9170873 # number of times a function call or return occured 792system.cpu1.num_conditional_control_insts 5967115 # number of instructions that are conditional controls 793system.cpu1.num_int_insts 56984416 # number of integer instructions 794system.cpu1.num_fp_insts 1792 # number of float instructions 795system.cpu1.num_int_register_reads 110669758 # number of times the integer registers were read 796system.cpu1.num_int_register_writes 41298494 # number of times the integer registers were written 797system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 798system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 799system.cpu1.num_cc_register_reads 196269240 # number of times the CC registers were read 800system.cpu1.num_cc_register_writes 18894452 # number of times the CC registers were written 801system.cpu1.num_mem_refs 20026424 # number of memory refs 802system.cpu1.num_load_insts 12289568 # Number of load instructions 803system.cpu1.num_store_insts 7736856 # Number of store instructions 804system.cpu1.num_idle_cycles 5539682760.605002 # Number of idle cycles 805system.cpu1.num_busy_cycles 65613709.394997 # Number of busy cycles 806system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 807system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 808system.cpu1.Branches 15217528 # Number of branches fetched 809system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 810system.cpu1.op_class::IntAlu 45401456 69.36% 69.36% # Class of executed instruction 811system.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction 812system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 813system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 814system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 815system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 816system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 817system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 818system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 819system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 820system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 821system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 822system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 823system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 824system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 825system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 826system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 827system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 828system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 829system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 830system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 831system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 832system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 833system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 834system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 835system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 836system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 837system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 838system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 839system.cpu1.op_class::MemRead 12289568 18.77% 88.18% # Class of executed instruction 840system.cpu1.op_class::MemWrite 7736856 11.82% 100.00% # Class of executed instruction 841system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 842system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 843system.cpu1.op_class::total 65459659 # Class of executed instruction 844system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 845system.cpu1.dcache.tags.replacements 191946 # number of replacements 846system.cpu1.dcache.tags.tagsinuse 472.736015 # Cycle average of tags in use 847system.cpu1.dcache.tags.total_refs 19503545 # Total number of references to valid blocks. 848system.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks. 849system.cpu1.dcache.tags.avg_refs 101.422491 # Average number of references to valid blocks. 850system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 851system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736015 # Average occupied blocks per requestor 852system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy 853system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy 854system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 855system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 856system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 857system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 858system.cpu1.dcache.tags.tag_accesses 39752069 # Number of tag accesses 859system.cpu1.dcache.tags.data_accesses 39752069 # Number of data accesses 860system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 861system.cpu1.dcache.ReadReq_hits::cpu1.data 11858716 # number of ReadReq hits 862system.cpu1.dcache.ReadReq_hits::total 11858716 # number of ReadReq hits 863system.cpu1.dcache.WriteReq_hits::cpu1.data 7397520 # number of WriteReq hits 864system.cpu1.dcache.WriteReq_hits::total 7397520 # number of WriteReq hits 865system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits 866system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits 867system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 868system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 869system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72399 # number of StoreCondReq hits 870system.cpu1.dcache.StoreCondReq_hits::total 72399 # number of StoreCondReq hits 871system.cpu1.dcache.demand_hits::cpu1.data 19256236 # number of demand (read+write) hits 872system.cpu1.dcache.demand_hits::total 19256236 # number of demand (read+write) hits 873system.cpu1.dcache.overall_hits::cpu1.data 19306336 # number of overall hits 874system.cpu1.dcache.overall_hits::total 19306336 # number of overall hits 875system.cpu1.dcache.ReadReq_misses::cpu1.data 136638 # number of ReadReq misses 876system.cpu1.dcache.ReadReq_misses::total 136638 # number of ReadReq misses 877system.cpu1.dcache.WriteReq_misses::cpu1.data 92454 # number of WriteReq misses 878system.cpu1.dcache.WriteReq_misses::total 92454 # number of WriteReq misses 879system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses 880system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses 881system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 882system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 883system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22580 # number of StoreCondReq misses 884system.cpu1.dcache.StoreCondReq_misses::total 22580 # number of StoreCondReq misses 885system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses 886system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses 887system.cpu1.dcache.overall_misses::cpu1.data 259810 # number of overall misses 888system.cpu1.dcache.overall_misses::total 259810 # number of overall misses 889system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995354 # number of ReadReq accesses(hits+misses) 890system.cpu1.dcache.ReadReq_accesses::total 11995354 # number of ReadReq accesses(hits+misses) 891system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489974 # number of WriteReq accesses(hits+misses) 892system.cpu1.dcache.WriteReq_accesses::total 7489974 # number of WriteReq accesses(hits+misses) 893system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 894system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 895system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 896system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 897system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 898system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 899system.cpu1.dcache.demand_accesses::cpu1.data 19485328 # number of demand (read+write) accesses 900system.cpu1.dcache.demand_accesses::total 19485328 # number of demand (read+write) accesses 901system.cpu1.dcache.overall_accesses::cpu1.data 19566146 # number of overall (read+write) accesses 902system.cpu1.dcache.overall_accesses::total 19566146 # number of overall (read+write) accesses 903system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses 904system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 905system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012344 # miss rate for WriteReq accesses 906system.cpu1.dcache.WriteReq_miss_rate::total 0.012344 # miss rate for WriteReq accesses 907system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses 908system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses 909system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 910system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 911system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237737 # miss rate for StoreCondReq accesses 912system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237737 # miss rate for StoreCondReq accesses 913system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 914system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 915system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 916system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 917system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 918system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 919system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 920system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 921system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 922system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 923system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks 924system.cpu1.dcache.writebacks::total 191946 # number of writebacks 925system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 926system.cpu1.icache.tags.replacements 523401 # number of replacements 927system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use 928system.cpu1.icache.tags.total_refs 53148935 # Total number of references to valid blocks. 929system.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. 930system.cpu1.icache.tags.avg_refs 101.446108 # Average number of references to valid blocks. 931system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 932system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor 933system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 934system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 935system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 936system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 937system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 938system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 939system.cpu1.icache.tags.tag_accesses 107869609 # Number of tag accesses 940system.cpu1.icache.tags.data_accesses 107869609 # Number of data accesses 941system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 942system.cpu1.icache.ReadReq_hits::cpu1.inst 53148935 # number of ReadReq hits 943system.cpu1.icache.ReadReq_hits::total 53148935 # number of ReadReq hits 944system.cpu1.icache.demand_hits::cpu1.inst 53148935 # number of demand (read+write) hits 945system.cpu1.icache.demand_hits::total 53148935 # number of demand (read+write) hits 946system.cpu1.icache.overall_hits::cpu1.inst 53148935 # number of overall hits 947system.cpu1.icache.overall_hits::total 53148935 # number of overall hits 948system.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses 949system.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses 950system.cpu1.icache.demand_misses::cpu1.inst 523913 # number of demand (read+write) misses 951system.cpu1.icache.demand_misses::total 523913 # number of demand (read+write) misses 952system.cpu1.icache.overall_misses::cpu1.inst 523913 # number of overall misses 953system.cpu1.icache.overall_misses::total 523913 # number of overall misses 954system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672848 # number of ReadReq accesses(hits+misses) 955system.cpu1.icache.ReadReq_accesses::total 53672848 # number of ReadReq accesses(hits+misses) 956system.cpu1.icache.demand_accesses::cpu1.inst 53672848 # number of demand (read+write) accesses 957system.cpu1.icache.demand_accesses::total 53672848 # number of demand (read+write) accesses 958system.cpu1.icache.overall_accesses::cpu1.inst 53672848 # number of overall (read+write) accesses 959system.cpu1.icache.overall_accesses::total 53672848 # number of overall (read+write) accesses 960system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 961system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 962system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 963system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 964system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 965system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 966system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 967system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 968system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 969system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 970system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 971system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 972system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks 973system.cpu1.icache.writebacks::total 523401 # number of writebacks 974system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 975system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 976system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 977system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 978system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 979system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 980system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 981system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 982system.cpu1.l2cache.tags.replacements 47503 # number of replacements 983system.cpu1.l2cache.tags.tagsinuse 15229.973296 # Cycle average of tags in use 984system.cpu1.l2cache.tags.total_refs 1184897 # Total number of references to valid blocks. 985system.cpu1.l2cache.tags.sampled_refs 62526 # Sample count of references to valid blocks. 986system.cpu1.l2cache.tags.avg_refs 18.950469 # Average number of references to valid blocks. 987system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 988system.cpu1.l2cache.tags.occ_blocks::writebacks 15227.338556 # Average occupied blocks per requestor 989system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 0.619660 # Average occupied blocks per requestor 990system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015081 # Average occupied blocks per requestor 991system.cpu1.l2cache.tags.occ_percent::writebacks 0.929403 # Average percentage of cache occupancy 992system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000038 # Average percentage of cache occupancy 993system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 994system.cpu1.l2cache.tags.occ_percent::total 0.929564 # Average percentage of cache occupancy 995system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id 996system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15005 # Occupied blocks per task id 997system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 998system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 999system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 1000system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id 1001system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9469 # Occupied blocks per task id 1002system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5007 # Occupied blocks per task id 1003system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id 1004system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.915833 # Percentage of cache occupancy per task id 1005system.cpu1.l2cache.tags.tag_accesses 24502168 # Number of tag accesses 1006system.cpu1.l2cache.tags.data_accesses 24502168 # Number of data accesses 1007system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1008system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits 1009system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1918 # number of ReadReq hits 1010system.cpu1.l2cache.ReadReq_hits::total 5539 # number of ReadReq hits 1011system.cpu1.l2cache.WritebackDirty_hits::writebacks 121092 # number of WritebackDirty hits 1012system.cpu1.l2cache.WritebackDirty_hits::total 121092 # number of WritebackDirty hits 1013system.cpu1.l2cache.WritebackClean_hits::writebacks 583097 # number of WritebackClean hits 1014system.cpu1.l2cache.WritebackClean_hits::total 583097 # number of WritebackClean hits 1015system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19779 # number of ReadExReq hits 1016system.cpu1.l2cache.ReadExReq_hits::total 19779 # number of ReadExReq hits 1017system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510372 # number of ReadCleanReq hits 1018system.cpu1.l2cache.ReadCleanReq_hits::total 510372 # number of ReadCleanReq hits 1019system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99144 # number of ReadSharedReq hits 1020system.cpu1.l2cache.ReadSharedReq_hits::total 99144 # number of ReadSharedReq hits 1021system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits 1022system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1918 # number of demand (read+write) hits 1023system.cpu1.l2cache.demand_hits::cpu1.inst 510372 # number of demand (read+write) hits 1024system.cpu1.l2cache.demand_hits::cpu1.data 118923 # number of demand (read+write) hits 1025system.cpu1.l2cache.demand_hits::total 634834 # number of demand (read+write) hits 1026system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits 1027system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1918 # number of overall hits 1028system.cpu1.l2cache.overall_hits::cpu1.inst 510372 # number of overall hits 1029system.cpu1.l2cache.overall_hits::cpu1.data 118923 # number of overall hits 1030system.cpu1.l2cache.overall_hits::total 634834 # number of overall hits 1031system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses 1032system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 273 # number of ReadReq misses 1033system.cpu1.l2cache.ReadReq_misses::total 617 # number of ReadReq misses 1034system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28839 # number of UpgradeReq misses 1035system.cpu1.l2cache.UpgradeReq_misses::total 28839 # number of UpgradeReq misses 1036system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22580 # number of SCUpgradeReq misses 1037system.cpu1.l2cache.SCUpgradeReq_misses::total 22580 # number of SCUpgradeReq misses 1038system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43836 # number of ReadExReq misses 1039system.cpu1.l2cache.ReadExReq_misses::total 43836 # number of ReadExReq misses 1040system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13541 # number of ReadCleanReq misses 1041system.cpu1.l2cache.ReadCleanReq_misses::total 13541 # number of ReadCleanReq misses 1042system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73530 # number of ReadSharedReq misses 1043system.cpu1.l2cache.ReadSharedReq_misses::total 73530 # number of ReadSharedReq misses 1044system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses 1045system.cpu1.l2cache.demand_misses::cpu1.itb.walker 273 # number of demand (read+write) misses 1046system.cpu1.l2cache.demand_misses::cpu1.inst 13541 # number of demand (read+write) misses 1047system.cpu1.l2cache.demand_misses::cpu1.data 117366 # number of demand (read+write) misses 1048system.cpu1.l2cache.demand_misses::total 131524 # number of demand (read+write) misses 1049system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses 1050system.cpu1.l2cache.overall_misses::cpu1.itb.walker 273 # number of overall misses 1051system.cpu1.l2cache.overall_misses::cpu1.inst 13541 # number of overall misses 1052system.cpu1.l2cache.overall_misses::cpu1.data 117366 # number of overall misses 1053system.cpu1.l2cache.overall_misses::total 131524 # number of overall misses 1054system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses) 1055system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) 1056system.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses) 1057system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121092 # number of WritebackDirty accesses(hits+misses) 1058system.cpu1.l2cache.WritebackDirty_accesses::total 121092 # number of WritebackDirty accesses(hits+misses) 1059system.cpu1.l2cache.WritebackClean_accesses::writebacks 583097 # number of WritebackClean accesses(hits+misses) 1060system.cpu1.l2cache.WritebackClean_accesses::total 583097 # number of WritebackClean accesses(hits+misses) 1061system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28839 # number of UpgradeReq accesses(hits+misses) 1062system.cpu1.l2cache.UpgradeReq_accesses::total 28839 # number of UpgradeReq accesses(hits+misses) 1063system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22580 # number of SCUpgradeReq accesses(hits+misses) 1064system.cpu1.l2cache.SCUpgradeReq_accesses::total 22580 # number of SCUpgradeReq accesses(hits+misses) 1065system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 1066system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 1067system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523913 # number of ReadCleanReq accesses(hits+misses) 1068system.cpu1.l2cache.ReadCleanReq_accesses::total 523913 # number of ReadCleanReq accesses(hits+misses) 1069system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172674 # number of ReadSharedReq accesses(hits+misses) 1070system.cpu1.l2cache.ReadSharedReq_accesses::total 172674 # number of ReadSharedReq accesses(hits+misses) 1071system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3965 # number of demand (read+write) accesses 1072system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses 1073system.cpu1.l2cache.demand_accesses::cpu1.inst 523913 # number of demand (read+write) accesses 1074system.cpu1.l2cache.demand_accesses::cpu1.data 236289 # number of demand (read+write) accesses 1075system.cpu1.l2cache.demand_accesses::total 766358 # number of demand (read+write) accesses 1076system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3965 # number of overall (read+write) accesses 1077system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses 1078system.cpu1.l2cache.overall_accesses::cpu1.inst 523913 # number of overall (read+write) accesses 1079system.cpu1.l2cache.overall_accesses::cpu1.data 236289 # number of overall (read+write) accesses 1080system.cpu1.l2cache.overall_accesses::total 766358 # number of overall (read+write) accesses 1081system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for ReadReq accesses 1082system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124601 # miss rate for ReadReq accesses 1083system.cpu1.l2cache.ReadReq_miss_rate::total 0.100227 # miss rate for ReadReq accesses 1084system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1085system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1086system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1087system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1088system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689083 # miss rate for ReadExReq accesses 1089system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689083 # miss rate for ReadExReq accesses 1090system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025846 # miss rate for ReadCleanReq accesses 1091system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025846 # miss rate for ReadCleanReq accesses 1092system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425831 # miss rate for ReadSharedReq accesses 1093system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425831 # miss rate for ReadSharedReq accesses 1094system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for demand accesses 1095system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124601 # miss rate for demand accesses 1096system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025846 # miss rate for demand accesses 1097system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496705 # miss rate for demand accesses 1098system.cpu1.l2cache.demand_miss_rate::total 0.171622 # miss rate for demand accesses 1099system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for overall accesses 1100system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124601 # miss rate for overall accesses 1101system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025846 # miss rate for overall accesses 1102system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496705 # miss rate for overall accesses 1103system.cpu1.l2cache.overall_miss_rate::total 0.171622 # miss rate for overall accesses 1104system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1105system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1106system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1107system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1108system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1109system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1110system.cpu1.l2cache.writebacks::writebacks 32790 # number of writebacks 1111system.cpu1.l2cache.writebacks::total 32790 # number of writebacks 1112system.cpu1.toL2Bus.snoop_filter.tot_requests 1533520 # Total number of requests made to the snoop filter. 1113system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773321 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1114system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1115system.cpu1.toL2Bus.snoop_filter.tot_snoops 166202 # Total number of snoops made to the snoop filter. 1116system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1117system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1963 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1118system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1119system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution 1120system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution 1121system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 1122system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 1123system.cpu1.toL2Bus.trans_dist::WritebackDirty 121092 # Transaction distribution 1124system.cpu1.toL2Bus.trans_dist::WritebackClean 594255 # Transaction distribution 1125system.cpu1.toL2Bus.trans_dist::UpgradeReq 28839 # Transaction distribution 1126system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22580 # Transaction distribution 1127system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution 1128system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 1129system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 1130system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523913 # Transaction distribution 1131system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172674 # Transaction distribution 1132system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571581 # Packet count per connected master and slave (bytes) 1133system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778822 # Packet count per connected master and slave (bytes) 1134system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 1135system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 1136system.cpu1.toL2Bus.pkt_count::total 2369099 # Packet count per connected master and slave (bytes) 1137system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67028804 # Cumulative packet size per connected master and slave (bytes) 1138system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27426222 # Cumulative packet size per connected master and slave (bytes) 1139system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 1140system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 1141system.cpu1.toL2Bus.pkt_size::total 94492418 # Cumulative packet size per connected master and slave (bytes) 1142system.cpu1.toL2Bus.snoops 347973 # Total snoops (count) 1143system.cpu1.toL2Bus.snoop_fanout::samples 1820541 # Request fanout histogram 1144system.cpu1.toL2Bus.snoop_fanout::mean 0.108229 # Request fanout histogram 1145system.cpu1.toL2Bus.snoop_fanout::stdev 0.314122 # Request fanout histogram 1146system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1147system.cpu1.toL2Bus.snoop_fanout::0 1625468 89.28% 89.28% # Request fanout histogram 1148system.cpu1.toL2Bus.snoop_fanout::1 193110 10.61% 99.89% # Request fanout histogram 1149system.cpu1.toL2Bus.snoop_fanout::2 1963 0.11% 100.00% # Request fanout histogram 1150system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1151system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1152system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1153system.cpu1.toL2Bus.snoop_fanout::total 1820541 # Request fanout histogram 1154system.iobus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1155system.iobus.trans_dist::ReadReq 30995 # Transaction distribution 1156system.iobus.trans_dist::ReadResp 30995 # Transaction distribution 1157system.iobus.trans_dist::WriteReq 59419 # Transaction distribution 1158system.iobus.trans_dist::WriteResp 59419 # Transaction distribution 1159system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 1160system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1161system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1162system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1163system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1164system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 1165system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1199system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 1202system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 1205system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1206system.iocache.tags.replacements 36442 # number of replacements 1207system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use 1208system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1209system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1210system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1211system.iocache.tags.warmup_cycle 246641287009 # Cycle when the warmup percentage was hit. 1212system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor 1213system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 1214system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 1215system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1216system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1217system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1218system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1219system.iocache.tags.data_accesses 328284 # Number of data accesses 1220system.iocache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1221system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1222system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 1223system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1224system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1225system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 1226system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 1227system.iocache.overall_misses::realview.ide 36476 # number of overall misses 1228system.iocache.overall_misses::total 36476 # number of overall misses 1229system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 1230system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 1231system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1232system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1233system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 1234system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 1235system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 1236system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 1237system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1238system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1239system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1240system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1241system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1242system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1243system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1244system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1245system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1246system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1247system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1248system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1249system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1250system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1251system.iocache.writebacks::writebacks 36190 # number of writebacks 1252system.iocache.writebacks::total 36190 # number of writebacks 1253system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1254system.l2c.tags.replacements 107745 # number of replacements 1255system.l2c.tags.tagsinuse 62386.756535 # Cycle average of tags in use 1256system.l2c.tags.total_refs 243993 # Total number of references to valid blocks. 1257system.l2c.tags.sampled_refs 168404 # Sample count of references to valid blocks. 1258system.l2c.tags.avg_refs 1.448855 # Average number of references to valid blocks. 1259system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1260system.l2c.tags.occ_blocks::writebacks 48109.911781 # Average occupied blocks per requestor 1261system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010811 # Average occupied blocks per requestor 1262system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030814 # Average occupied blocks per requestor 1263system.l2c.tags.occ_blocks::cpu0.inst 7778.233869 # Average occupied blocks per requestor 1264system.l2c.tags.occ_blocks::cpu0.data 4058.534945 # Average occupied blocks per requestor 1265system.l2c.tags.occ_blocks::cpu1.inst 1666.123091 # Average occupied blocks per requestor 1266system.l2c.tags.occ_blocks::cpu1.data 768.911224 # Average occupied blocks per requestor 1267system.l2c.tags.occ_percent::writebacks 0.734099 # Average percentage of cache occupancy 1268system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy 1269system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 1270system.l2c.tags.occ_percent::cpu0.inst 0.118686 # Average percentage of cache occupancy 1271system.l2c.tags.occ_percent::cpu0.data 0.061928 # Average percentage of cache occupancy 1272system.l2c.tags.occ_percent::cpu1.inst 0.025423 # Average percentage of cache occupancy 1273system.l2c.tags.occ_percent::cpu1.data 0.011733 # Average percentage of cache occupancy 1274system.l2c.tags.occ_percent::total 0.951946 # Average percentage of cache occupancy 1275system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1276system.l2c.tags.occ_task_id_blocks::1024 60653 # Occupied blocks per task id 1277system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1278system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 1279system.l2c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id 1280system.l2c.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id 1281system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id 1282system.l2c.tags.age_task_id_blocks_1024::4 45523 # Occupied blocks per task id 1283system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 1284system.l2c.tags.occ_task_id_percent::1024 0.925491 # Percentage of cache occupancy per task id 1285system.l2c.tags.tag_accesses 5181909 # Number of tag accesses 1286system.l2c.tags.data_accesses 5181909 # Number of data accesses 1287system.l2c.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1288system.l2c.WritebackDirty_hits::writebacks 225821 # number of WritebackDirty hits 1289system.l2c.WritebackDirty_hits::total 225821 # number of WritebackDirty hits 1290system.l2c.UpgradeReq_hits::cpu0.data 557 # number of UpgradeReq hits 1291system.l2c.UpgradeReq_hits::cpu1.data 103 # number of UpgradeReq hits 1292system.l2c.UpgradeReq_hits::total 660 # number of UpgradeReq hits 1293system.l2c.SCUpgradeReq_hits::cpu0.data 84 # number of SCUpgradeReq hits 1294system.l2c.SCUpgradeReq_hits::cpu1.data 42 # number of SCUpgradeReq hits 1295system.l2c.SCUpgradeReq_hits::total 126 # number of SCUpgradeReq hits 1296system.l2c.ReadExReq_hits::cpu0.data 14022 # number of ReadExReq hits 1297system.l2c.ReadExReq_hits::cpu1.data 3121 # number of ReadExReq hits 1298system.l2c.ReadExReq_hits::total 17143 # number of ReadExReq hits 1299system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 71 # number of ReadSharedReq hits 1300system.l2c.ReadSharedReq_hits::cpu0.itb.walker 67 # number of ReadSharedReq hits 1301system.l2c.ReadSharedReq_hits::cpu0.inst 24898 # number of ReadSharedReq hits 1302system.l2c.ReadSharedReq_hits::cpu0.data 76097 # number of ReadSharedReq hits 1303system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits 1304system.l2c.ReadSharedReq_hits::cpu1.itb.walker 38 # number of ReadSharedReq hits 1305system.l2c.ReadSharedReq_hits::cpu1.inst 11147 # number of ReadSharedReq hits 1306system.l2c.ReadSharedReq_hits::cpu1.data 11696 # number of ReadSharedReq hits 1307system.l2c.ReadSharedReq_hits::total 124060 # number of ReadSharedReq hits 1308system.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits 1309system.l2c.demand_hits::cpu0.itb.walker 67 # number of demand (read+write) hits 1310system.l2c.demand_hits::cpu0.inst 24898 # number of demand (read+write) hits 1311system.l2c.demand_hits::cpu0.data 90119 # number of demand (read+write) hits 1312system.l2c.demand_hits::cpu1.dtb.walker 46 # number of demand (read+write) hits 1313system.l2c.demand_hits::cpu1.itb.walker 38 # number of demand (read+write) hits 1314system.l2c.demand_hits::cpu1.inst 11147 # number of demand (read+write) hits 1315system.l2c.demand_hits::cpu1.data 14817 # number of demand (read+write) hits 1316system.l2c.demand_hits::total 141203 # number of demand (read+write) hits 1317system.l2c.overall_hits::cpu0.dtb.walker 71 # number of overall hits 1318system.l2c.overall_hits::cpu0.itb.walker 67 # number of overall hits 1319system.l2c.overall_hits::cpu0.inst 24898 # number of overall hits 1320system.l2c.overall_hits::cpu0.data 90119 # number of overall hits 1321system.l2c.overall_hits::cpu1.dtb.walker 46 # number of overall hits 1322system.l2c.overall_hits::cpu1.itb.walker 38 # number of overall hits 1323system.l2c.overall_hits::cpu1.inst 11147 # number of overall hits 1324system.l2c.overall_hits::cpu1.data 14817 # number of overall hits 1325system.l2c.overall_hits::total 141203 # number of overall hits 1326system.l2c.UpgradeReq_misses::cpu0.data 9957 # number of UpgradeReq misses 1327system.l2c.UpgradeReq_misses::cpu1.data 3262 # number of UpgradeReq misses 1328system.l2c.UpgradeReq_misses::total 13219 # number of UpgradeReq misses 1329system.l2c.SCUpgradeReq_misses::cpu0.data 737 # number of SCUpgradeReq misses 1330system.l2c.SCUpgradeReq_misses::cpu1.data 1139 # number of SCUpgradeReq misses 1331system.l2c.SCUpgradeReq_misses::total 1876 # number of SCUpgradeReq misses 1332system.l2c.ReadExReq_misses::cpu0.data 136539 # number of ReadExReq misses 1333system.l2c.ReadExReq_misses::cpu1.data 15807 # number of ReadExReq misses 1334system.l2c.ReadExReq_misses::total 152346 # number of ReadExReq misses 1335system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses 1336system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 1337system.l2c.ReadSharedReq_misses::cpu0.inst 16771 # number of ReadSharedReq misses 1338system.l2c.ReadSharedReq_misses::cpu0.data 11196 # number of ReadSharedReq misses 1339system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses 1340system.l2c.ReadSharedReq_misses::cpu1.data 1129 # number of ReadSharedReq misses 1341system.l2c.ReadSharedReq_misses::total 31500 # number of ReadSharedReq misses 1342system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 1343system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 1344system.l2c.demand_misses::cpu0.inst 16771 # number of demand (read+write) misses 1345system.l2c.demand_misses::cpu0.data 147735 # number of demand (read+write) misses 1346system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses 1347system.l2c.demand_misses::cpu1.data 16936 # number of demand (read+write) misses 1348system.l2c.demand_misses::total 183846 # number of demand (read+write) misses 1349system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 1350system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 1351system.l2c.overall_misses::cpu0.inst 16771 # number of overall misses 1352system.l2c.overall_misses::cpu0.data 147735 # number of overall misses 1353system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses 1354system.l2c.overall_misses::cpu1.data 16936 # number of overall misses 1355system.l2c.overall_misses::total 183846 # number of overall misses 1356system.l2c.WritebackDirty_accesses::writebacks 225821 # number of WritebackDirty accesses(hits+misses) 1357system.l2c.WritebackDirty_accesses::total 225821 # number of WritebackDirty accesses(hits+misses) 1358system.l2c.UpgradeReq_accesses::cpu0.data 10514 # number of UpgradeReq accesses(hits+misses) 1359system.l2c.UpgradeReq_accesses::cpu1.data 3365 # number of UpgradeReq accesses(hits+misses) 1360system.l2c.UpgradeReq_accesses::total 13879 # number of UpgradeReq accesses(hits+misses) 1361system.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) 1362system.l2c.SCUpgradeReq_accesses::cpu1.data 1181 # number of SCUpgradeReq accesses(hits+misses) 1363system.l2c.SCUpgradeReq_accesses::total 2002 # number of SCUpgradeReq accesses(hits+misses) 1364system.l2c.ReadExReq_accesses::cpu0.data 150561 # number of ReadExReq accesses(hits+misses) 1365system.l2c.ReadExReq_accesses::cpu1.data 18928 # number of ReadExReq accesses(hits+misses) 1366system.l2c.ReadExReq_accesses::total 169489 # number of ReadExReq accesses(hits+misses) 1367system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 79 # number of ReadSharedReq accesses(hits+misses) 1368system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 69 # number of ReadSharedReq accesses(hits+misses) 1369system.l2c.ReadSharedReq_accesses::cpu0.inst 41669 # number of ReadSharedReq accesses(hits+misses) 1370system.l2c.ReadSharedReq_accesses::cpu0.data 87293 # number of ReadSharedReq accesses(hits+misses) 1371system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 46 # number of ReadSharedReq accesses(hits+misses) 1372system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 38 # number of ReadSharedReq accesses(hits+misses) 1373system.l2c.ReadSharedReq_accesses::cpu1.inst 13541 # number of ReadSharedReq accesses(hits+misses) 1374system.l2c.ReadSharedReq_accesses::cpu1.data 12825 # number of ReadSharedReq accesses(hits+misses) 1375system.l2c.ReadSharedReq_accesses::total 155560 # number of ReadSharedReq accesses(hits+misses) 1376system.l2c.demand_accesses::cpu0.dtb.walker 79 # number of demand (read+write) accesses 1377system.l2c.demand_accesses::cpu0.itb.walker 69 # number of demand (read+write) accesses 1378system.l2c.demand_accesses::cpu0.inst 41669 # number of demand (read+write) accesses 1379system.l2c.demand_accesses::cpu0.data 237854 # number of demand (read+write) accesses 1380system.l2c.demand_accesses::cpu1.dtb.walker 46 # number of demand (read+write) accesses 1381system.l2c.demand_accesses::cpu1.itb.walker 38 # number of demand (read+write) accesses 1382system.l2c.demand_accesses::cpu1.inst 13541 # number of demand (read+write) accesses 1383system.l2c.demand_accesses::cpu1.data 31753 # number of demand (read+write) accesses 1384system.l2c.demand_accesses::total 325049 # number of demand (read+write) accesses 1385system.l2c.overall_accesses::cpu0.dtb.walker 79 # number of overall (read+write) accesses 1386system.l2c.overall_accesses::cpu0.itb.walker 69 # number of overall (read+write) accesses 1387system.l2c.overall_accesses::cpu0.inst 41669 # number of overall (read+write) accesses 1388system.l2c.overall_accesses::cpu0.data 237854 # number of overall (read+write) accesses 1389system.l2c.overall_accesses::cpu1.dtb.walker 46 # number of overall (read+write) accesses 1390system.l2c.overall_accesses::cpu1.itb.walker 38 # number of overall (read+write) accesses 1391system.l2c.overall_accesses::cpu1.inst 13541 # number of overall (read+write) accesses 1392system.l2c.overall_accesses::cpu1.data 31753 # number of overall (read+write) accesses 1393system.l2c.overall_accesses::total 325049 # number of overall (read+write) accesses 1394system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947023 # miss rate for UpgradeReq accesses 1395system.l2c.UpgradeReq_miss_rate::cpu1.data 0.969391 # miss rate for UpgradeReq accesses 1396system.l2c.UpgradeReq_miss_rate::total 0.952446 # miss rate for UpgradeReq accesses 1397system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.897686 # miss rate for SCUpgradeReq accesses 1398system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.964437 # miss rate for SCUpgradeReq accesses 1399system.l2c.SCUpgradeReq_miss_rate::total 0.937063 # miss rate for SCUpgradeReq accesses 1400system.l2c.ReadExReq_miss_rate::cpu0.data 0.906868 # miss rate for ReadExReq accesses 1401system.l2c.ReadExReq_miss_rate::cpu1.data 0.835112 # miss rate for ReadExReq accesses 1402system.l2c.ReadExReq_miss_rate::total 0.898855 # miss rate for ReadExReq accesses 1403system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for ReadSharedReq accesses 1404system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028986 # miss rate for ReadSharedReq accesses 1405system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402481 # miss rate for ReadSharedReq accesses 1406system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128258 # miss rate for ReadSharedReq accesses 1407system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176796 # miss rate for ReadSharedReq accesses 1408system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.088031 # miss rate for ReadSharedReq accesses 1409system.l2c.ReadSharedReq_miss_rate::total 0.202494 # miss rate for ReadSharedReq accesses 1410system.l2c.demand_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for demand accesses 1411system.l2c.demand_miss_rate::cpu0.itb.walker 0.028986 # miss rate for demand accesses 1412system.l2c.demand_miss_rate::cpu0.inst 0.402481 # miss rate for demand accesses 1413system.l2c.demand_miss_rate::cpu0.data 0.621116 # miss rate for demand accesses 1414system.l2c.demand_miss_rate::cpu1.inst 0.176796 # miss rate for demand accesses 1415system.l2c.demand_miss_rate::cpu1.data 0.533367 # miss rate for demand accesses 1416system.l2c.demand_miss_rate::total 0.565595 # miss rate for demand accesses 1417system.l2c.overall_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for overall accesses 1418system.l2c.overall_miss_rate::cpu0.itb.walker 0.028986 # miss rate for overall accesses 1419system.l2c.overall_miss_rate::cpu0.inst 0.402481 # miss rate for overall accesses 1420system.l2c.overall_miss_rate::cpu0.data 0.621116 # miss rate for overall accesses 1421system.l2c.overall_miss_rate::cpu1.inst 0.176796 # miss rate for overall accesses 1422system.l2c.overall_miss_rate::cpu1.data 0.533367 # miss rate for overall accesses 1423system.l2c.overall_miss_rate::total 0.565595 # miss rate for overall accesses 1424system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1425system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1426system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1427system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1428system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1429system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1430system.l2c.writebacks::writebacks 96240 # number of writebacks 1431system.l2c.writebacks::total 96240 # number of writebacks 1432system.membus.snoop_filter.tot_requests 462691 # Total number of requests made to the snoop filter. 1433system.membus.snoop_filter.hit_single_requests 248163 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1434system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1435system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1436system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1437system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1438system.membus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1439system.membus.trans_dist::ReadReq 43996 # Transaction distribution 1440system.membus.trans_dist::ReadResp 75748 # Transaction distribution 1441system.membus.trans_dist::WriteReq 30846 # Transaction distribution 1442system.membus.trans_dist::WriteResp 30846 # Transaction distribution 1443system.membus.trans_dist::WritebackDirty 132430 # Transaction distribution 1444system.membus.trans_dist::CleanEvict 8725 # Transaction distribution 1445system.membus.trans_dist::UpgradeReq 60386 # Transaction distribution 1446system.membus.trans_dist::SCUpgradeReq 40885 # Transaction distribution 1447system.membus.trans_dist::UpgradeResp 15565 # Transaction distribution 1448system.membus.trans_dist::ReadExReq 152277 # Transaction distribution 1449system.membus.trans_dist::ReadExResp 151876 # Transaction distribution 1450system.membus.trans_dist::ReadSharedReq 31752 # Transaction distribution 1451system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1452system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1453system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 1454system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 1455system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 1456system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617002 # Packet count per connected master and slave (bytes) 1457system.membus.pkt_count_system.l2c.mem_side::total 738386 # Packet count per connected master and slave (bytes) 1458system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 1459system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) 1460system.membus.pkt_count::total 847780 # Packet count per connected master and slave (bytes) 1461system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 1462system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 1463system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 1464system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17952136 # Cumulative packet size per connected master and slave (bytes) 1465system.membus.pkt_size_system.l2c.mem_side::total 18141918 # Cumulative packet size per connected master and slave (bytes) 1466system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 1467system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 1468system.membus.pkt_size::total 20474206 # Cumulative packet size per connected master and slave (bytes) 1469system.membus.snoops 0 # Total snoops (count) 1470system.membus.snoop_fanout::samples 537521 # Request fanout histogram 1471system.membus.snoop_fanout::mean 0.010364 # Request fanout histogram 1472system.membus.snoop_fanout::stdev 0.101276 # Request fanout histogram 1473system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1474system.membus.snoop_fanout::0 531950 98.96% 98.96% # Request fanout histogram 1475system.membus.snoop_fanout::1 5571 1.04% 100.00% # Request fanout histogram 1476system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1477system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1478system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1479system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1480system.membus.snoop_fanout::total 537521 # Request fanout histogram 1481system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1482system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1483system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1484system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1485system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1486system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1487system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1488system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1489system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1490system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1491system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1492system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1493system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1494system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1495system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1496system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1497system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1498system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1499system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1500system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1501system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1502system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1503system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1504system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1505system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1506system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1507system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1508system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1509system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1510system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1511system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1512system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1513system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1514system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1515system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1516system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1517system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1518system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1519system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1520system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1521system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1522system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1523system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1524system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1525system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1526system.realview.ethernet.droppedPackets 0 # number of packets dropped 1527system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1528system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1529system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1530system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1531system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1532system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1533system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1534system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1535system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1536system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1537system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1538system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1539system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1540system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1541system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1542system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1543system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1544system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1545system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1546system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1547system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1548system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1549system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1550system.toL2Bus.snoop_filter.tot_requests 863181 # Total number of requests made to the snoop filter. 1551system.toL2Bus.snoop_filter.hit_single_requests 444499 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1552system.toL2Bus.snoop_filter.hit_multi_requests 128781 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1553system.toL2Bus.snoop_filter.tot_snoops 9832 # Total number of snoops made to the snoop filter. 1554system.toL2Bus.snoop_filter.hit_single_snoops 9332 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1555system.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1556system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1557system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution 1558system.toL2Bus.trans_dist::ReadResp 301660 # Transaction distribution 1559system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 1560system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 1561system.toL2Bus.trans_dist::WritebackDirty 225821 # Transaction distribution 1562system.toL2Bus.trans_dist::CleanEvict 64447 # Transaction distribution 1563system.toL2Bus.trans_dist::UpgradeReq 60576 # Transaction distribution 1564system.toL2Bus.trans_dist::SCUpgradeReq 41011 # Transaction distribution 1565system.toL2Bus.trans_dist::UpgradeResp 101587 # Transaction distribution 1566system.toL2Bus.trans_dist::ReadExReq 213650 # Transaction distribution 1567system.toL2Bus.trans_dist::ReadExResp 213650 # Transaction distribution 1568system.toL2Bus.trans_dist::ReadSharedReq 257660 # Transaction distribution 1569system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1162060 # Packet count per connected master and slave (bytes) 1570system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423694 # Packet count per connected master and slave (bytes) 1571system.toL2Bus.pkt_count::total 1585754 # Packet count per connected master and slave (bytes) 1572system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34449020 # Cumulative packet size per connected master and slave (bytes) 1573system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10413874 # Cumulative packet size per connected master and slave (bytes) 1574system.toL2Bus.pkt_size::total 44862894 # Cumulative packet size per connected master and slave (bytes) 1575system.toL2Bus.snoops 113289 # Total snoops (count) 1576system.toL2Bus.snoop_fanout::samples 1051063 # Request fanout histogram 1577system.toL2Bus.snoop_fanout::mean 0.300803 # Request fanout histogram 1578system.toL2Bus.snoop_fanout::stdev 0.459644 # Request fanout histogram 1579system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1580system.toL2Bus.snoop_fanout::0 735400 69.97% 69.97% # Request fanout histogram 1581system.toL2Bus.snoop_fanout::1 315163 29.99% 99.95% # Request fanout histogram 1582system.toL2Bus.snoop_fanout::2 500 0.05% 100.00% # Request fanout histogram 1583system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1584system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1585system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1586system.toL2Bus.snoop_fanout::total 1051063 # Request fanout histogram 1587 1588---------- End Simulation Statistics ----------	757system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 758system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 759system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 760system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 761system.cpu1.itb.read_accesses 0 # DTB read accesses 762system.cpu1.itb.write_accesses 0 # DTB write accesses 763system.cpu1.itb.inst_accesses 53673492 # ITB inst accesses 764system.cpu1.itb.hits 53671758 # DTB hits 765system.cpu1.itb.misses 1734 # DTB misses 766system.cpu1.itb.accesses 53673492 # DTB accesses 767system.cpu1.numPwrStateTransitions 5477 # Number of power state transitions 768system.cpu1.pwrStateClkGateDist::samples 2739 # Distribution of time spent in the clock gated state 769system.cpu1.pwrStateClkGateDist::mean 1011344723.290617 # Distribution of time spent in the clock gated state 770system.cpu1.pwrStateClkGateDist::stdev 25846310002.973743 # Distribution of time spent in the clock gated state 771system.cpu1.pwrStateClkGateDist::underflows 1957 71.45% 71.45% # Distribution of time spent in the clock gated state 772system.cpu1.pwrStateClkGateDist::1000-5e+10 777 28.37% 99.82% # Distribution of time spent in the clock gated state 773system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state 774system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 775system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 776system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 777system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 778system.cpu1.pwrStateClkGateDist::max_value 979984930372 # Distribution of time spent in the clock gated state 779system.cpu1.pwrStateClkGateDist::total 2739 # Distribution of time spent in the clock gated state 780system.cpu1.pwrStateResidencyTicks::ON 32809600407 # Cumulative time (in ticks) in various power states 781system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770073197093 # Cumulative time (in ticks) in various power states 782system.cpu1.numCycles 5605296470 # number of cpu cycles simulated 783system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 784system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 785system.cpu1.kern.inst.arm 0 # number of arm instructions executed 786system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 787system.cpu1.committedInsts 51401494 # Number of instructions committed 788system.cpu1.committedOps 63347804 # Number of ops (including micro ops) committed 789system.cpu1.num_int_alu_accesses 56984416 # Number of integer alu accesses 790system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 791system.cpu1.num_func_calls 9170873 # number of times a function call or return occured 792system.cpu1.num_conditional_control_insts 5967115 # number of instructions that are conditional controls 793system.cpu1.num_int_insts 56984416 # number of integer instructions 794system.cpu1.num_fp_insts 1792 # number of float instructions 795system.cpu1.num_int_register_reads 110669758 # number of times the integer registers were read 796system.cpu1.num_int_register_writes 41298494 # number of times the integer registers were written 797system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 798system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 799system.cpu1.num_cc_register_reads 196269240 # number of times the CC registers were read 800system.cpu1.num_cc_register_writes 18894452 # number of times the CC registers were written 801system.cpu1.num_mem_refs 20026424 # number of memory refs 802system.cpu1.num_load_insts 12289568 # Number of load instructions 803system.cpu1.num_store_insts 7736856 # Number of store instructions 804system.cpu1.num_idle_cycles 5539682760.605002 # Number of idle cycles 805system.cpu1.num_busy_cycles 65613709.394997 # Number of busy cycles 806system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 807system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 808system.cpu1.Branches 15217528 # Number of branches fetched 809system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 810system.cpu1.op_class::IntAlu 45401456 69.36% 69.36% # Class of executed instruction 811system.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction 812system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 813system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 814system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 815system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 816system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 817system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 818system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 819system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 820system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 821system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 822system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 823system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 824system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 825system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 826system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 827system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 828system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 829system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 830system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 831system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 832system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 833system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 834system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 835system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 836system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 837system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 838system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 839system.cpu1.op_class::MemRead 12289568 18.77% 88.18% # Class of executed instruction 840system.cpu1.op_class::MemWrite 7736856 11.82% 100.00% # Class of executed instruction 841system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 842system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 843system.cpu1.op_class::total 65459659 # Class of executed instruction 844system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 845system.cpu1.dcache.tags.replacements 191946 # number of replacements 846system.cpu1.dcache.tags.tagsinuse 472.736015 # Cycle average of tags in use 847system.cpu1.dcache.tags.total_refs 19503545 # Total number of references to valid blocks. 848system.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks. 849system.cpu1.dcache.tags.avg_refs 101.422491 # Average number of references to valid blocks. 850system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 851system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736015 # Average occupied blocks per requestor 852system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy 853system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy 854system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 855system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 856system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 857system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 858system.cpu1.dcache.tags.tag_accesses 39752069 # Number of tag accesses 859system.cpu1.dcache.tags.data_accesses 39752069 # Number of data accesses 860system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 861system.cpu1.dcache.ReadReq_hits::cpu1.data 11858716 # number of ReadReq hits 862system.cpu1.dcache.ReadReq_hits::total 11858716 # number of ReadReq hits 863system.cpu1.dcache.WriteReq_hits::cpu1.data 7397520 # number of WriteReq hits 864system.cpu1.dcache.WriteReq_hits::total 7397520 # number of WriteReq hits 865system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits 866system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits 867system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 868system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 869system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72399 # number of StoreCondReq hits 870system.cpu1.dcache.StoreCondReq_hits::total 72399 # number of StoreCondReq hits 871system.cpu1.dcache.demand_hits::cpu1.data 19256236 # number of demand (read+write) hits 872system.cpu1.dcache.demand_hits::total 19256236 # number of demand (read+write) hits 873system.cpu1.dcache.overall_hits::cpu1.data 19306336 # number of overall hits 874system.cpu1.dcache.overall_hits::total 19306336 # number of overall hits 875system.cpu1.dcache.ReadReq_misses::cpu1.data 136638 # number of ReadReq misses 876system.cpu1.dcache.ReadReq_misses::total 136638 # number of ReadReq misses 877system.cpu1.dcache.WriteReq_misses::cpu1.data 92454 # number of WriteReq misses 878system.cpu1.dcache.WriteReq_misses::total 92454 # number of WriteReq misses 879system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses 880system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses 881system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 882system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 883system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22580 # number of StoreCondReq misses 884system.cpu1.dcache.StoreCondReq_misses::total 22580 # number of StoreCondReq misses 885system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses 886system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses 887system.cpu1.dcache.overall_misses::cpu1.data 259810 # number of overall misses 888system.cpu1.dcache.overall_misses::total 259810 # number of overall misses 889system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995354 # number of ReadReq accesses(hits+misses) 890system.cpu1.dcache.ReadReq_accesses::total 11995354 # number of ReadReq accesses(hits+misses) 891system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489974 # number of WriteReq accesses(hits+misses) 892system.cpu1.dcache.WriteReq_accesses::total 7489974 # number of WriteReq accesses(hits+misses) 893system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 894system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 895system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 896system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 897system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 898system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 899system.cpu1.dcache.demand_accesses::cpu1.data 19485328 # number of demand (read+write) accesses 900system.cpu1.dcache.demand_accesses::total 19485328 # number of demand (read+write) accesses 901system.cpu1.dcache.overall_accesses::cpu1.data 19566146 # number of overall (read+write) accesses 902system.cpu1.dcache.overall_accesses::total 19566146 # number of overall (read+write) accesses 903system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses 904system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 905system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012344 # miss rate for WriteReq accesses 906system.cpu1.dcache.WriteReq_miss_rate::total 0.012344 # miss rate for WriteReq accesses 907system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses 908system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses 909system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 910system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 911system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237737 # miss rate for StoreCondReq accesses 912system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237737 # miss rate for StoreCondReq accesses 913system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 914system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 915system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 916system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 917system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 918system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 919system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 920system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 921system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 922system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 923system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks 924system.cpu1.dcache.writebacks::total 191946 # number of writebacks 925system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 926system.cpu1.icache.tags.replacements 523401 # number of replacements 927system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use 928system.cpu1.icache.tags.total_refs 53148935 # Total number of references to valid blocks. 929system.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. 930system.cpu1.icache.tags.avg_refs 101.446108 # Average number of references to valid blocks. 931system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 932system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor 933system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 934system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 935system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 936system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 937system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 938system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 939system.cpu1.icache.tags.tag_accesses 107869609 # Number of tag accesses 940system.cpu1.icache.tags.data_accesses 107869609 # Number of data accesses 941system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 942system.cpu1.icache.ReadReq_hits::cpu1.inst 53148935 # number of ReadReq hits 943system.cpu1.icache.ReadReq_hits::total 53148935 # number of ReadReq hits 944system.cpu1.icache.demand_hits::cpu1.inst 53148935 # number of demand (read+write) hits 945system.cpu1.icache.demand_hits::total 53148935 # number of demand (read+write) hits 946system.cpu1.icache.overall_hits::cpu1.inst 53148935 # number of overall hits 947system.cpu1.icache.overall_hits::total 53148935 # number of overall hits 948system.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses 949system.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses 950system.cpu1.icache.demand_misses::cpu1.inst 523913 # number of demand (read+write) misses 951system.cpu1.icache.demand_misses::total 523913 # number of demand (read+write) misses 952system.cpu1.icache.overall_misses::cpu1.inst 523913 # number of overall misses 953system.cpu1.icache.overall_misses::total 523913 # number of overall misses 954system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672848 # number of ReadReq accesses(hits+misses) 955system.cpu1.icache.ReadReq_accesses::total 53672848 # number of ReadReq accesses(hits+misses) 956system.cpu1.icache.demand_accesses::cpu1.inst 53672848 # number of demand (read+write) accesses 957system.cpu1.icache.demand_accesses::total 53672848 # number of demand (read+write) accesses 958system.cpu1.icache.overall_accesses::cpu1.inst 53672848 # number of overall (read+write) accesses 959system.cpu1.icache.overall_accesses::total 53672848 # number of overall (read+write) accesses 960system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 961system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 962system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 963system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 964system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 965system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 966system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 967system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 968system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 969system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 970system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 971system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 972system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks 973system.cpu1.icache.writebacks::total 523401 # number of writebacks 974system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 975system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 976system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 977system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 978system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 979system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 980system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 981system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 982system.cpu1.l2cache.tags.replacements 47503 # number of replacements 983system.cpu1.l2cache.tags.tagsinuse 15229.973296 # Cycle average of tags in use 984system.cpu1.l2cache.tags.total_refs 1184897 # Total number of references to valid blocks. 985system.cpu1.l2cache.tags.sampled_refs 62526 # Sample count of references to valid blocks. 986system.cpu1.l2cache.tags.avg_refs 18.950469 # Average number of references to valid blocks. 987system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 988system.cpu1.l2cache.tags.occ_blocks::writebacks 15227.338556 # Average occupied blocks per requestor 989system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 0.619660 # Average occupied blocks per requestor 990system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015081 # Average occupied blocks per requestor 991system.cpu1.l2cache.tags.occ_percent::writebacks 0.929403 # Average percentage of cache occupancy 992system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000038 # Average percentage of cache occupancy 993system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 994system.cpu1.l2cache.tags.occ_percent::total 0.929564 # Average percentage of cache occupancy 995system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id 996system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15005 # Occupied blocks per task id 997system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 998system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 999system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 1000system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id 1001system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9469 # Occupied blocks per task id 1002system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5007 # Occupied blocks per task id 1003system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id 1004system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.915833 # Percentage of cache occupancy per task id 1005system.cpu1.l2cache.tags.tag_accesses 24502168 # Number of tag accesses 1006system.cpu1.l2cache.tags.data_accesses 24502168 # Number of data accesses 1007system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1008system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits 1009system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1918 # number of ReadReq hits 1010system.cpu1.l2cache.ReadReq_hits::total 5539 # number of ReadReq hits 1011system.cpu1.l2cache.WritebackDirty_hits::writebacks 121092 # number of WritebackDirty hits 1012system.cpu1.l2cache.WritebackDirty_hits::total 121092 # number of WritebackDirty hits 1013system.cpu1.l2cache.WritebackClean_hits::writebacks 583097 # number of WritebackClean hits 1014system.cpu1.l2cache.WritebackClean_hits::total 583097 # number of WritebackClean hits 1015system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19779 # number of ReadExReq hits 1016system.cpu1.l2cache.ReadExReq_hits::total 19779 # number of ReadExReq hits 1017system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510372 # number of ReadCleanReq hits 1018system.cpu1.l2cache.ReadCleanReq_hits::total 510372 # number of ReadCleanReq hits 1019system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99144 # number of ReadSharedReq hits 1020system.cpu1.l2cache.ReadSharedReq_hits::total 99144 # number of ReadSharedReq hits 1021system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits 1022system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1918 # number of demand (read+write) hits 1023system.cpu1.l2cache.demand_hits::cpu1.inst 510372 # number of demand (read+write) hits 1024system.cpu1.l2cache.demand_hits::cpu1.data 118923 # number of demand (read+write) hits 1025system.cpu1.l2cache.demand_hits::total 634834 # number of demand (read+write) hits 1026system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits 1027system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1918 # number of overall hits 1028system.cpu1.l2cache.overall_hits::cpu1.inst 510372 # number of overall hits 1029system.cpu1.l2cache.overall_hits::cpu1.data 118923 # number of overall hits 1030system.cpu1.l2cache.overall_hits::total 634834 # number of overall hits 1031system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses 1032system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 273 # number of ReadReq misses 1033system.cpu1.l2cache.ReadReq_misses::total 617 # number of ReadReq misses 1034system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28839 # number of UpgradeReq misses 1035system.cpu1.l2cache.UpgradeReq_misses::total 28839 # number of UpgradeReq misses 1036system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22580 # number of SCUpgradeReq misses 1037system.cpu1.l2cache.SCUpgradeReq_misses::total 22580 # number of SCUpgradeReq misses 1038system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43836 # number of ReadExReq misses 1039system.cpu1.l2cache.ReadExReq_misses::total 43836 # number of ReadExReq misses 1040system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13541 # number of ReadCleanReq misses 1041system.cpu1.l2cache.ReadCleanReq_misses::total 13541 # number of ReadCleanReq misses 1042system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73530 # number of ReadSharedReq misses 1043system.cpu1.l2cache.ReadSharedReq_misses::total 73530 # number of ReadSharedReq misses 1044system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses 1045system.cpu1.l2cache.demand_misses::cpu1.itb.walker 273 # number of demand (read+write) misses 1046system.cpu1.l2cache.demand_misses::cpu1.inst 13541 # number of demand (read+write) misses 1047system.cpu1.l2cache.demand_misses::cpu1.data 117366 # number of demand (read+write) misses 1048system.cpu1.l2cache.demand_misses::total 131524 # number of demand (read+write) misses 1049system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses 1050system.cpu1.l2cache.overall_misses::cpu1.itb.walker 273 # number of overall misses 1051system.cpu1.l2cache.overall_misses::cpu1.inst 13541 # number of overall misses 1052system.cpu1.l2cache.overall_misses::cpu1.data 117366 # number of overall misses 1053system.cpu1.l2cache.overall_misses::total 131524 # number of overall misses 1054system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses) 1055system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) 1056system.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses) 1057system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121092 # number of WritebackDirty accesses(hits+misses) 1058system.cpu1.l2cache.WritebackDirty_accesses::total 121092 # number of WritebackDirty accesses(hits+misses) 1059system.cpu1.l2cache.WritebackClean_accesses::writebacks 583097 # number of WritebackClean accesses(hits+misses) 1060system.cpu1.l2cache.WritebackClean_accesses::total 583097 # number of WritebackClean accesses(hits+misses) 1061system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28839 # number of UpgradeReq accesses(hits+misses) 1062system.cpu1.l2cache.UpgradeReq_accesses::total 28839 # number of UpgradeReq accesses(hits+misses) 1063system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22580 # number of SCUpgradeReq accesses(hits+misses) 1064system.cpu1.l2cache.SCUpgradeReq_accesses::total 22580 # number of SCUpgradeReq accesses(hits+misses) 1065system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 1066system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 1067system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523913 # number of ReadCleanReq accesses(hits+misses) 1068system.cpu1.l2cache.ReadCleanReq_accesses::total 523913 # number of ReadCleanReq accesses(hits+misses) 1069system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172674 # number of ReadSharedReq accesses(hits+misses) 1070system.cpu1.l2cache.ReadSharedReq_accesses::total 172674 # number of ReadSharedReq accesses(hits+misses) 1071system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3965 # number of demand (read+write) accesses 1072system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses 1073system.cpu1.l2cache.demand_accesses::cpu1.inst 523913 # number of demand (read+write) accesses 1074system.cpu1.l2cache.demand_accesses::cpu1.data 236289 # number of demand (read+write) accesses 1075system.cpu1.l2cache.demand_accesses::total 766358 # number of demand (read+write) accesses 1076system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3965 # number of overall (read+write) accesses 1077system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses 1078system.cpu1.l2cache.overall_accesses::cpu1.inst 523913 # number of overall (read+write) accesses 1079system.cpu1.l2cache.overall_accesses::cpu1.data 236289 # number of overall (read+write) accesses 1080system.cpu1.l2cache.overall_accesses::total 766358 # number of overall (read+write) accesses 1081system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for ReadReq accesses 1082system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124601 # miss rate for ReadReq accesses 1083system.cpu1.l2cache.ReadReq_miss_rate::total 0.100227 # miss rate for ReadReq accesses 1084system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1085system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1086system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1087system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1088system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689083 # miss rate for ReadExReq accesses 1089system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689083 # miss rate for ReadExReq accesses 1090system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025846 # miss rate for ReadCleanReq accesses 1091system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025846 # miss rate for ReadCleanReq accesses 1092system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425831 # miss rate for ReadSharedReq accesses 1093system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425831 # miss rate for ReadSharedReq accesses 1094system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for demand accesses 1095system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124601 # miss rate for demand accesses 1096system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025846 # miss rate for demand accesses 1097system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496705 # miss rate for demand accesses 1098system.cpu1.l2cache.demand_miss_rate::total 0.171622 # miss rate for demand accesses 1099system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for overall accesses 1100system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124601 # miss rate for overall accesses 1101system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025846 # miss rate for overall accesses 1102system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496705 # miss rate for overall accesses 1103system.cpu1.l2cache.overall_miss_rate::total 0.171622 # miss rate for overall accesses 1104system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1105system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1106system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1107system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1108system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1109system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1110system.cpu1.l2cache.writebacks::writebacks 32790 # number of writebacks 1111system.cpu1.l2cache.writebacks::total 32790 # number of writebacks 1112system.cpu1.toL2Bus.snoop_filter.tot_requests 1533520 # Total number of requests made to the snoop filter. 1113system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773321 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1114system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1115system.cpu1.toL2Bus.snoop_filter.tot_snoops 166202 # Total number of snoops made to the snoop filter. 1116system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1117system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1963 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1118system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1119system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution 1120system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution 1121system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 1122system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 1123system.cpu1.toL2Bus.trans_dist::WritebackDirty 121092 # Transaction distribution 1124system.cpu1.toL2Bus.trans_dist::WritebackClean 594255 # Transaction distribution 1125system.cpu1.toL2Bus.trans_dist::UpgradeReq 28839 # Transaction distribution 1126system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22580 # Transaction distribution 1127system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution 1128system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 1129system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 1130system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523913 # Transaction distribution 1131system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172674 # Transaction distribution 1132system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571581 # Packet count per connected master and slave (bytes) 1133system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778822 # Packet count per connected master and slave (bytes) 1134system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 1135system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 1136system.cpu1.toL2Bus.pkt_count::total 2369099 # Packet count per connected master and slave (bytes) 1137system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67028804 # Cumulative packet size per connected master and slave (bytes) 1138system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27426222 # Cumulative packet size per connected master and slave (bytes) 1139system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 1140system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 1141system.cpu1.toL2Bus.pkt_size::total 94492418 # Cumulative packet size per connected master and slave (bytes) 1142system.cpu1.toL2Bus.snoops 347973 # Total snoops (count) 1143system.cpu1.toL2Bus.snoop_fanout::samples 1820541 # Request fanout histogram 1144system.cpu1.toL2Bus.snoop_fanout::mean 0.108229 # Request fanout histogram 1145system.cpu1.toL2Bus.snoop_fanout::stdev 0.314122 # Request fanout histogram 1146system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1147system.cpu1.toL2Bus.snoop_fanout::0 1625468 89.28% 89.28% # Request fanout histogram 1148system.cpu1.toL2Bus.snoop_fanout::1 193110 10.61% 99.89% # Request fanout histogram 1149system.cpu1.toL2Bus.snoop_fanout::2 1963 0.11% 100.00% # Request fanout histogram 1150system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1151system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1152system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1153system.cpu1.toL2Bus.snoop_fanout::total 1820541 # Request fanout histogram 1154system.iobus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1155system.iobus.trans_dist::ReadReq 30995 # Transaction distribution 1156system.iobus.trans_dist::ReadResp 30995 # Transaction distribution 1157system.iobus.trans_dist::WriteReq 59419 # Transaction distribution 1158system.iobus.trans_dist::WriteResp 59419 # Transaction distribution 1159system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 1160system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1161system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1162system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1163system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1164system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 1165system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1199system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 1202system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 1205system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1206system.iocache.tags.replacements 36442 # number of replacements 1207system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use 1208system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1209system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1210system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1211system.iocache.tags.warmup_cycle 246641287009 # Cycle when the warmup percentage was hit. 1212system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor 1213system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 1214system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 1215system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1216system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1217system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1218system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1219system.iocache.tags.data_accesses 328284 # Number of data accesses 1220system.iocache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1221system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1222system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 1223system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1224system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1225system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 1226system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 1227system.iocache.overall_misses::realview.ide 36476 # number of overall misses 1228system.iocache.overall_misses::total 36476 # number of overall misses 1229system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 1230system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 1231system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1232system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1233system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 1234system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 1235system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 1236system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 1237system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1238system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1239system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1240system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1241system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1242system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1243system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1244system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1245system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1246system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1247system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1248system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1249system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1250system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1251system.iocache.writebacks::writebacks 36190 # number of writebacks 1252system.iocache.writebacks::total 36190 # number of writebacks 1253system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1254system.l2c.tags.replacements 107745 # number of replacements 1255system.l2c.tags.tagsinuse 62386.756535 # Cycle average of tags in use 1256system.l2c.tags.total_refs 243993 # Total number of references to valid blocks. 1257system.l2c.tags.sampled_refs 168404 # Sample count of references to valid blocks. 1258system.l2c.tags.avg_refs 1.448855 # Average number of references to valid blocks. 1259system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1260system.l2c.tags.occ_blocks::writebacks 48109.911781 # Average occupied blocks per requestor 1261system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010811 # Average occupied blocks per requestor 1262system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030814 # Average occupied blocks per requestor 1263system.l2c.tags.occ_blocks::cpu0.inst 7778.233869 # Average occupied blocks per requestor 1264system.l2c.tags.occ_blocks::cpu0.data 4058.534945 # Average occupied blocks per requestor 1265system.l2c.tags.occ_blocks::cpu1.inst 1666.123091 # Average occupied blocks per requestor 1266system.l2c.tags.occ_blocks::cpu1.data 768.911224 # Average occupied blocks per requestor 1267system.l2c.tags.occ_percent::writebacks 0.734099 # Average percentage of cache occupancy 1268system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy 1269system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 1270system.l2c.tags.occ_percent::cpu0.inst 0.118686 # Average percentage of cache occupancy 1271system.l2c.tags.occ_percent::cpu0.data 0.061928 # Average percentage of cache occupancy 1272system.l2c.tags.occ_percent::cpu1.inst 0.025423 # Average percentage of cache occupancy 1273system.l2c.tags.occ_percent::cpu1.data 0.011733 # Average percentage of cache occupancy 1274system.l2c.tags.occ_percent::total 0.951946 # Average percentage of cache occupancy 1275system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1276system.l2c.tags.occ_task_id_blocks::1024 60653 # Occupied blocks per task id 1277system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1278system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 1279system.l2c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id 1280system.l2c.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id 1281system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id 1282system.l2c.tags.age_task_id_blocks_1024::4 45523 # Occupied blocks per task id 1283system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 1284system.l2c.tags.occ_task_id_percent::1024 0.925491 # Percentage of cache occupancy per task id 1285system.l2c.tags.tag_accesses 5181909 # Number of tag accesses 1286system.l2c.tags.data_accesses 5181909 # Number of data accesses 1287system.l2c.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1288system.l2c.WritebackDirty_hits::writebacks 225821 # number of WritebackDirty hits 1289system.l2c.WritebackDirty_hits::total 225821 # number of WritebackDirty hits 1290system.l2c.UpgradeReq_hits::cpu0.data 557 # number of UpgradeReq hits 1291system.l2c.UpgradeReq_hits::cpu1.data 103 # number of UpgradeReq hits 1292system.l2c.UpgradeReq_hits::total 660 # number of UpgradeReq hits 1293system.l2c.SCUpgradeReq_hits::cpu0.data 84 # number of SCUpgradeReq hits 1294system.l2c.SCUpgradeReq_hits::cpu1.data 42 # number of SCUpgradeReq hits 1295system.l2c.SCUpgradeReq_hits::total 126 # number of SCUpgradeReq hits 1296system.l2c.ReadExReq_hits::cpu0.data 14022 # number of ReadExReq hits 1297system.l2c.ReadExReq_hits::cpu1.data 3121 # number of ReadExReq hits 1298system.l2c.ReadExReq_hits::total 17143 # number of ReadExReq hits 1299system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 71 # number of ReadSharedReq hits 1300system.l2c.ReadSharedReq_hits::cpu0.itb.walker 67 # number of ReadSharedReq hits 1301system.l2c.ReadSharedReq_hits::cpu0.inst 24898 # number of ReadSharedReq hits 1302system.l2c.ReadSharedReq_hits::cpu0.data 76097 # number of ReadSharedReq hits 1303system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits 1304system.l2c.ReadSharedReq_hits::cpu1.itb.walker 38 # number of ReadSharedReq hits 1305system.l2c.ReadSharedReq_hits::cpu1.inst 11147 # number of ReadSharedReq hits 1306system.l2c.ReadSharedReq_hits::cpu1.data 11696 # number of ReadSharedReq hits 1307system.l2c.ReadSharedReq_hits::total 124060 # number of ReadSharedReq hits 1308system.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits 1309system.l2c.demand_hits::cpu0.itb.walker 67 # number of demand (read+write) hits 1310system.l2c.demand_hits::cpu0.inst 24898 # number of demand (read+write) hits 1311system.l2c.demand_hits::cpu0.data 90119 # number of demand (read+write) hits 1312system.l2c.demand_hits::cpu1.dtb.walker 46 # number of demand (read+write) hits 1313system.l2c.demand_hits::cpu1.itb.walker 38 # number of demand (read+write) hits 1314system.l2c.demand_hits::cpu1.inst 11147 # number of demand (read+write) hits 1315system.l2c.demand_hits::cpu1.data 14817 # number of demand (read+write) hits 1316system.l2c.demand_hits::total 141203 # number of demand (read+write) hits 1317system.l2c.overall_hits::cpu0.dtb.walker 71 # number of overall hits 1318system.l2c.overall_hits::cpu0.itb.walker 67 # number of overall hits 1319system.l2c.overall_hits::cpu0.inst 24898 # number of overall hits 1320system.l2c.overall_hits::cpu0.data 90119 # number of overall hits 1321system.l2c.overall_hits::cpu1.dtb.walker 46 # number of overall hits 1322system.l2c.overall_hits::cpu1.itb.walker 38 # number of overall hits 1323system.l2c.overall_hits::cpu1.inst 11147 # number of overall hits 1324system.l2c.overall_hits::cpu1.data 14817 # number of overall hits 1325system.l2c.overall_hits::total 141203 # number of overall hits 1326system.l2c.UpgradeReq_misses::cpu0.data 9957 # number of UpgradeReq misses 1327system.l2c.UpgradeReq_misses::cpu1.data 3262 # number of UpgradeReq misses 1328system.l2c.UpgradeReq_misses::total 13219 # number of UpgradeReq misses 1329system.l2c.SCUpgradeReq_misses::cpu0.data 737 # number of SCUpgradeReq misses 1330system.l2c.SCUpgradeReq_misses::cpu1.data 1139 # number of SCUpgradeReq misses 1331system.l2c.SCUpgradeReq_misses::total 1876 # number of SCUpgradeReq misses 1332system.l2c.ReadExReq_misses::cpu0.data 136539 # number of ReadExReq misses 1333system.l2c.ReadExReq_misses::cpu1.data 15807 # number of ReadExReq misses 1334system.l2c.ReadExReq_misses::total 152346 # number of ReadExReq misses 1335system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses 1336system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 1337system.l2c.ReadSharedReq_misses::cpu0.inst 16771 # number of ReadSharedReq misses 1338system.l2c.ReadSharedReq_misses::cpu0.data 11196 # number of ReadSharedReq misses 1339system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses 1340system.l2c.ReadSharedReq_misses::cpu1.data 1129 # number of ReadSharedReq misses 1341system.l2c.ReadSharedReq_misses::total 31500 # number of ReadSharedReq misses 1342system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 1343system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 1344system.l2c.demand_misses::cpu0.inst 16771 # number of demand (read+write) misses 1345system.l2c.demand_misses::cpu0.data 147735 # number of demand (read+write) misses 1346system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses 1347system.l2c.demand_misses::cpu1.data 16936 # number of demand (read+write) misses 1348system.l2c.demand_misses::total 183846 # number of demand (read+write) misses 1349system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 1350system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 1351system.l2c.overall_misses::cpu0.inst 16771 # number of overall misses 1352system.l2c.overall_misses::cpu0.data 147735 # number of overall misses 1353system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses 1354system.l2c.overall_misses::cpu1.data 16936 # number of overall misses 1355system.l2c.overall_misses::total 183846 # number of overall misses 1356system.l2c.WritebackDirty_accesses::writebacks 225821 # number of WritebackDirty accesses(hits+misses) 1357system.l2c.WritebackDirty_accesses::total 225821 # number of WritebackDirty accesses(hits+misses) 1358system.l2c.UpgradeReq_accesses::cpu0.data 10514 # number of UpgradeReq accesses(hits+misses) 1359system.l2c.UpgradeReq_accesses::cpu1.data 3365 # number of UpgradeReq accesses(hits+misses) 1360system.l2c.UpgradeReq_accesses::total 13879 # number of UpgradeReq accesses(hits+misses) 1361system.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) 1362system.l2c.SCUpgradeReq_accesses::cpu1.data 1181 # number of SCUpgradeReq accesses(hits+misses) 1363system.l2c.SCUpgradeReq_accesses::total 2002 # number of SCUpgradeReq accesses(hits+misses) 1364system.l2c.ReadExReq_accesses::cpu0.data 150561 # number of ReadExReq accesses(hits+misses) 1365system.l2c.ReadExReq_accesses::cpu1.data 18928 # number of ReadExReq accesses(hits+misses) 1366system.l2c.ReadExReq_accesses::total 169489 # number of ReadExReq accesses(hits+misses) 1367system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 79 # number of ReadSharedReq accesses(hits+misses) 1368system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 69 # number of ReadSharedReq accesses(hits+misses) 1369system.l2c.ReadSharedReq_accesses::cpu0.inst 41669 # number of ReadSharedReq accesses(hits+misses) 1370system.l2c.ReadSharedReq_accesses::cpu0.data 87293 # number of ReadSharedReq accesses(hits+misses) 1371system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 46 # number of ReadSharedReq accesses(hits+misses) 1372system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 38 # number of ReadSharedReq accesses(hits+misses) 1373system.l2c.ReadSharedReq_accesses::cpu1.inst 13541 # number of ReadSharedReq accesses(hits+misses) 1374system.l2c.ReadSharedReq_accesses::cpu1.data 12825 # number of ReadSharedReq accesses(hits+misses) 1375system.l2c.ReadSharedReq_accesses::total 155560 # number of ReadSharedReq accesses(hits+misses) 1376system.l2c.demand_accesses::cpu0.dtb.walker 79 # number of demand (read+write) accesses 1377system.l2c.demand_accesses::cpu0.itb.walker 69 # number of demand (read+write) accesses 1378system.l2c.demand_accesses::cpu0.inst 41669 # number of demand (read+write) accesses 1379system.l2c.demand_accesses::cpu0.data 237854 # number of demand (read+write) accesses 1380system.l2c.demand_accesses::cpu1.dtb.walker 46 # number of demand (read+write) accesses 1381system.l2c.demand_accesses::cpu1.itb.walker 38 # number of demand (read+write) accesses 1382system.l2c.demand_accesses::cpu1.inst 13541 # number of demand (read+write) accesses 1383system.l2c.demand_accesses::cpu1.data 31753 # number of demand (read+write) accesses 1384system.l2c.demand_accesses::total 325049 # number of demand (read+write) accesses 1385system.l2c.overall_accesses::cpu0.dtb.walker 79 # number of overall (read+write) accesses 1386system.l2c.overall_accesses::cpu0.itb.walker 69 # number of overall (read+write) accesses 1387system.l2c.overall_accesses::cpu0.inst 41669 # number of overall (read+write) accesses 1388system.l2c.overall_accesses::cpu0.data 237854 # number of overall (read+write) accesses 1389system.l2c.overall_accesses::cpu1.dtb.walker 46 # number of overall (read+write) accesses 1390system.l2c.overall_accesses::cpu1.itb.walker 38 # number of overall (read+write) accesses 1391system.l2c.overall_accesses::cpu1.inst 13541 # number of overall (read+write) accesses 1392system.l2c.overall_accesses::cpu1.data 31753 # number of overall (read+write) accesses 1393system.l2c.overall_accesses::total 325049 # number of overall (read+write) accesses 1394system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947023 # miss rate for UpgradeReq accesses 1395system.l2c.UpgradeReq_miss_rate::cpu1.data 0.969391 # miss rate for UpgradeReq accesses 1396system.l2c.UpgradeReq_miss_rate::total 0.952446 # miss rate for UpgradeReq accesses 1397system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.897686 # miss rate for SCUpgradeReq accesses 1398system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.964437 # miss rate for SCUpgradeReq accesses 1399system.l2c.SCUpgradeReq_miss_rate::total 0.937063 # miss rate for SCUpgradeReq accesses 1400system.l2c.ReadExReq_miss_rate::cpu0.data 0.906868 # miss rate for ReadExReq accesses 1401system.l2c.ReadExReq_miss_rate::cpu1.data 0.835112 # miss rate for ReadExReq accesses 1402system.l2c.ReadExReq_miss_rate::total 0.898855 # miss rate for ReadExReq accesses 1403system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for ReadSharedReq accesses 1404system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028986 # miss rate for ReadSharedReq accesses 1405system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402481 # miss rate for ReadSharedReq accesses 1406system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128258 # miss rate for ReadSharedReq accesses 1407system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176796 # miss rate for ReadSharedReq accesses 1408system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.088031 # miss rate for ReadSharedReq accesses 1409system.l2c.ReadSharedReq_miss_rate::total 0.202494 # miss rate for ReadSharedReq accesses 1410system.l2c.demand_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for demand accesses 1411system.l2c.demand_miss_rate::cpu0.itb.walker 0.028986 # miss rate for demand accesses 1412system.l2c.demand_miss_rate::cpu0.inst 0.402481 # miss rate for demand accesses 1413system.l2c.demand_miss_rate::cpu0.data 0.621116 # miss rate for demand accesses 1414system.l2c.demand_miss_rate::cpu1.inst 0.176796 # miss rate for demand accesses 1415system.l2c.demand_miss_rate::cpu1.data 0.533367 # miss rate for demand accesses 1416system.l2c.demand_miss_rate::total 0.565595 # miss rate for demand accesses 1417system.l2c.overall_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for overall accesses 1418system.l2c.overall_miss_rate::cpu0.itb.walker 0.028986 # miss rate for overall accesses 1419system.l2c.overall_miss_rate::cpu0.inst 0.402481 # miss rate for overall accesses 1420system.l2c.overall_miss_rate::cpu0.data 0.621116 # miss rate for overall accesses 1421system.l2c.overall_miss_rate::cpu1.inst 0.176796 # miss rate for overall accesses 1422system.l2c.overall_miss_rate::cpu1.data 0.533367 # miss rate for overall accesses 1423system.l2c.overall_miss_rate::total 0.565595 # miss rate for overall accesses 1424system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1425system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1426system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1427system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1428system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1429system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1430system.l2c.writebacks::writebacks 96240 # number of writebacks 1431system.l2c.writebacks::total 96240 # number of writebacks 1432system.membus.snoop_filter.tot_requests 462691 # Total number of requests made to the snoop filter. 1433system.membus.snoop_filter.hit_single_requests 248163 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1434system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1435system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1436system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1437system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1438system.membus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1439system.membus.trans_dist::ReadReq 43996 # Transaction distribution 1440system.membus.trans_dist::ReadResp 75748 # Transaction distribution 1441system.membus.trans_dist::WriteReq 30846 # Transaction distribution 1442system.membus.trans_dist::WriteResp 30846 # Transaction distribution 1443system.membus.trans_dist::WritebackDirty 132430 # Transaction distribution 1444system.membus.trans_dist::CleanEvict 8725 # Transaction distribution 1445system.membus.trans_dist::UpgradeReq 60386 # Transaction distribution 1446system.membus.trans_dist::SCUpgradeReq 40885 # Transaction distribution 1447system.membus.trans_dist::UpgradeResp 15565 # Transaction distribution 1448system.membus.trans_dist::ReadExReq 152277 # Transaction distribution 1449system.membus.trans_dist::ReadExResp 151876 # Transaction distribution 1450system.membus.trans_dist::ReadSharedReq 31752 # Transaction distribution 1451system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1452system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1453system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 1454system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 1455system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 1456system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617002 # Packet count per connected master and slave (bytes) 1457system.membus.pkt_count_system.l2c.mem_side::total 738386 # Packet count per connected master and slave (bytes) 1458system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 1459system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) 1460system.membus.pkt_count::total 847780 # Packet count per connected master and slave (bytes) 1461system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 1462system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 1463system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 1464system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17952136 # Cumulative packet size per connected master and slave (bytes) 1465system.membus.pkt_size_system.l2c.mem_side::total 18141918 # Cumulative packet size per connected master and slave (bytes) 1466system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 1467system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 1468system.membus.pkt_size::total 20474206 # Cumulative packet size per connected master and slave (bytes) 1469system.membus.snoops 0 # Total snoops (count) 1470system.membus.snoop_fanout::samples 537521 # Request fanout histogram 1471system.membus.snoop_fanout::mean 0.010364 # Request fanout histogram 1472system.membus.snoop_fanout::stdev 0.101276 # Request fanout histogram 1473system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1474system.membus.snoop_fanout::0 531950 98.96% 98.96% # Request fanout histogram 1475system.membus.snoop_fanout::1 5571 1.04% 100.00% # Request fanout histogram 1476system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1477system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1478system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1479system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1480system.membus.snoop_fanout::total 537521 # Request fanout histogram 1481system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1482system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1483system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1484system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1485system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1486system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1487system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1488system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1489system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1490system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1491system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1492system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1493system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1494system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1495system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1496system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1497system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1498system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1499system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1500system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1501system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1502system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1503system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1504system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1505system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1506system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1507system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1508system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1509system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1510system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1511system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1512system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1513system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1514system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1515system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1516system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1517system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1518system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1519system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1520system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1521system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1522system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1523system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1524system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1525system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1526system.realview.ethernet.droppedPackets 0 # number of packets dropped 1527system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1528system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1529system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1530system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1531system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1532system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1533system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1534system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1535system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1536system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1537system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1538system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1539system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1540system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1541system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1542system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1543system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1544system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1545system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1546system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1547system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1548system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1549system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1550system.toL2Bus.snoop_filter.tot_requests 863181 # Total number of requests made to the snoop filter. 1551system.toL2Bus.snoop_filter.hit_single_requests 444499 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1552system.toL2Bus.snoop_filter.hit_multi_requests 128781 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1553system.toL2Bus.snoop_filter.tot_snoops 9832 # Total number of snoops made to the snoop filter. 1554system.toL2Bus.snoop_filter.hit_single_snoops 9332 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1555system.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1556system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1557system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution 1558system.toL2Bus.trans_dist::ReadResp 301660 # Transaction distribution 1559system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 1560system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 1561system.toL2Bus.trans_dist::WritebackDirty 225821 # Transaction distribution 1562system.toL2Bus.trans_dist::CleanEvict 64447 # Transaction distribution 1563system.toL2Bus.trans_dist::UpgradeReq 60576 # Transaction distribution 1564system.toL2Bus.trans_dist::SCUpgradeReq 41011 # Transaction distribution 1565system.toL2Bus.trans_dist::UpgradeResp 101587 # Transaction distribution 1566system.toL2Bus.trans_dist::ReadExReq 213650 # Transaction distribution 1567system.toL2Bus.trans_dist::ReadExResp 213650 # Transaction distribution 1568system.toL2Bus.trans_dist::ReadSharedReq 257660 # Transaction distribution 1569system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1162060 # Packet count per connected master and slave (bytes) 1570system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423694 # Packet count per connected master and slave (bytes) 1571system.toL2Bus.pkt_count::total 1585754 # Packet count per connected master and slave (bytes) 1572system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34449020 # Cumulative packet size per connected master and slave (bytes) 1573system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10413874 # Cumulative packet size per connected master and slave (bytes) 1574system.toL2Bus.pkt_size::total 44862894 # Cumulative packet size per connected master and slave (bytes) 1575system.toL2Bus.snoops 113289 # Total snoops (count) 1576system.toL2Bus.snoop_fanout::samples 1051063 # Request fanout histogram 1577system.toL2Bus.snoop_fanout::mean 0.300803 # Request fanout histogram 1578system.toL2Bus.snoop_fanout::stdev 0.459644 # Request fanout histogram 1579system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1580system.toL2Bus.snoop_fanout::0 735400 69.97% 69.97% # Request fanout histogram 1581system.toL2Bus.snoop_fanout::1 315163 29.99% 99.95% # Request fanout histogram 1582system.toL2Bus.snoop_fanout::2 500 0.05% 100.00% # Request fanout histogram 1583system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1584system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1585system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1586system.toL2Bus.snoop_fanout::total 1051063 # Request fanout histogram 1587 1588---------- End Simulation Statistics ----------