Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt

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stats.txt (11239:3be64e1f80ed)	stats.txt (11245:1c5102c0a7a9)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802895 # Number of seconds simulated 4sim_ticks 2802894699500 # Number of ticks simulated 5final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802895 # Number of seconds simulated 4sim_ticks 2802894699500 # Number of ticks simulated 5final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 515393 # Simulator instruction rate (inst/s) 8host_op_rate 627998 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9838648327 # Simulator tick rate (ticks/s) 10host_mem_usage 594196 # Number of bytes of host memory used 11host_seconds 284.89 # Real time elapsed on the host	7host_inst_rate 917511 # Simulator instruction rate (inst/s) 8host_op_rate 1117974 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17514936450 # Simulator tick rate (ticks/s) 10host_mem_usage 594132 # Number of bytes of host memory used 11host_seconds 160.03 # Real time elapsed on the host
12sim_insts 146828240 # Number of instructions simulated 13sim_ops 178908039 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1108644 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 9410404 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 1082576 # Number of bytes read from this memory 22system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 23system.physmem.bytes_read::total 11757100 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 1108644 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 1262520 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 8452288 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 30system.physmem.bytes_written::total 8469852 # Number of bytes written to this memory 31system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 25776 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 147557 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.data 16935 # Number of read requests responded to by this memory 37system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 192852 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 132067 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 136458 # Number of write requests responded to by this memory 43system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.inst 395535 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.data 3357388 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.data 386235 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::total 4194628 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu0.inst 395535 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 450434 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_write::writebacks 3015557 # Write bandwidth from this memory (bytes/s) 55system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::total 3021823 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_total::writebacks 3015557 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.inst 395535 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.data 3363640 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu1.data 386249 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::total 7216451 # Total bandwidth to/from this memory (bytes/s) 67system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 68system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 69system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 70system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 71system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 72system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 73system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 74system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 75system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 76system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 77system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 78system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 83system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 84system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 85system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 86system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 87system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 88system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 89system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 90system.cf0.dma_write_txs 631 # Number of DMA write transactions. 91system.cpu_clk_domain.clock 500 # Clock period in ticks 92system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 93system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 94system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 95system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 96system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 97system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 98system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 99system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 100system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 101system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 102system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 103system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 104system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 105system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 106system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 107system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 108system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 109system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 110system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 111system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 112system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 113system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 114system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 115system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 116system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 117system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 118system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 119system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 120system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 121system.cpu0.dtb.walker.walks 7967 # Table walker walks requested 122system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors 123system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency 124system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency 125system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency 126system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 127system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 128system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 129system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated 130system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated 131system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated 132system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst 133system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 134system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst 135system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst 136system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 137system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst 138system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst 139system.cpu0.dtb.inst_hits 0 # ITB inst hits 140system.cpu0.dtb.inst_misses 0 # ITB inst misses 141system.cpu0.dtb.read_hits 20339720 # DTB read hits 142system.cpu0.dtb.read_misses 6874 # DTB read misses 143system.cpu0.dtb.write_hits 16391078 # DTB write hits 144system.cpu0.dtb.write_misses 1093 # DTB write misses 145system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 146system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 147system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 148system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 149system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 150system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 151system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 152system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 153system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 154system.cpu0.dtb.read_accesses 20346594 # DTB read accesses 155system.cpu0.dtb.write_accesses 16392171 # DTB write accesses 156system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 157system.cpu0.dtb.hits 36730798 # DTB hits 158system.cpu0.dtb.misses 7967 # DTB misses 159system.cpu0.dtb.accesses 36738765 # DTB accesses 160system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 161system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 162system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 163system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 164system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 165system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 166system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 167system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 168system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 169system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 170system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 171system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 172system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 173system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 174system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 175system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 176system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 177system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 178system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 179system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 180system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 181system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 182system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 183system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 184system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 185system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 186system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 187system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 188system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 189system.cpu0.itb.walker.walks 3358 # Table walker walks requested 190system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 191system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 192system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 193system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 194system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 195system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 196system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 197system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 198system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 199system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 200system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 201system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 202system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 203system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 204system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 205system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 206system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 207system.cpu0.itb.inst_hits 97439331 # ITB inst hits 208system.cpu0.itb.inst_misses 3358 # ITB inst misses 209system.cpu0.itb.read_hits 0 # DTB read hits 210system.cpu0.itb.read_misses 0 # DTB read misses 211system.cpu0.itb.write_hits 0 # DTB write hits 212system.cpu0.itb.write_misses 0 # DTB write misses 213system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 214system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 215system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 216system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 217system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 218system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 219system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 220system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 221system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 222system.cpu0.itb.read_accesses 0 # DTB read accesses 223system.cpu0.itb.write_accesses 0 # DTB write accesses 224system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses 225system.cpu0.itb.hits 97439331 # DTB hits 226system.cpu0.itb.misses 3358 # DTB misses 227system.cpu0.itb.accesses 97442689 # DTB accesses 228system.cpu0.numCycles 5605791368 # number of cpu cycles simulated 229system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 230system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 231system.cpu0.kern.inst.arm 0 # number of arm instructions executed 232system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed 233system.cpu0.committedInsts 95426926 # Number of instructions committed 234system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed 235system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses 236system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 237system.cpu0.num_func_calls 8000180 # number of times a function call or return occured 238system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls 239system.cpu0.num_int_insts 100762696 # number of integer instructions 240system.cpu0.num_fp_insts 9755 # number of float instructions 241system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read 242system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written 243system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 244system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 245system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read 246system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written 247system.cpu0.num_mem_refs 37873810 # number of memory refs 248system.cpu0.num_load_insts 20597310 # Number of load instructions 249system.cpu0.num_store_insts 17276500 # Number of store instructions 250system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles 251system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles 252system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 253system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 254system.cpu0.Branches 21941499 # Number of branches fetched 255system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 256system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction 257system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction 258system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 259system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 260system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 261system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 262system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 263system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 264system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 265system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 266system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 267system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 268system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 269system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 270system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 271system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 272system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 273system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 274system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 275system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 276system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 277system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 278system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 279system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 280system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 281system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 282system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 283system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 284system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 285system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction 286system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction 287system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 288system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 289system.cpu0.op_class::total 116882065 # Class of executed instruction 290system.cpu0.dcache.tags.replacements 693486 # number of replacements 291system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use 292system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. 293system.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks. 294system.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks. 295system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 296system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor 297system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 298system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 299system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 300system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 301system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 302system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 303system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 304system.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses 305system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses 306system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits 307system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits 308system.cpu0.dcache.WriteReq_hits::cpu0.data 15690389 # number of WriteReq hits 309system.cpu0.dcache.WriteReq_hits::total 15690389 # number of WriteReq hits 310system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits 311system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits 312system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits 313system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits 314system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363050 # number of StoreCondReq hits 315system.cpu0.dcache.StoreCondReq_hits::total 363050 # number of StoreCondReq hits 316system.cpu0.dcache.demand_hits::cpu0.data 34798930 # number of demand (read+write) hits 317system.cpu0.dcache.demand_hits::total 34798930 # number of demand (read+write) hits 318system.cpu0.dcache.overall_hits::cpu0.data 35145023 # number of overall hits 319system.cpu0.dcache.overall_hits::total 35145023 # number of overall hits 320system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses 321system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses 322system.cpu0.dcache.WriteReq_misses::cpu0.data 295796 # number of WriteReq misses 323system.cpu0.dcache.WriteReq_misses::total 295796 # number of WriteReq misses 324system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 325system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 326system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses 327system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses 328system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18435 # number of StoreCondReq misses 329system.cpu0.dcache.StoreCondReq_misses::total 18435 # number of StoreCondReq misses 330system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses 331system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses 332system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses 333system.cpu0.dcache.overall_misses::total 769220 # number of overall misses 334system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) 335system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) 336system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) 337system.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses) 338system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) 339system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) 340system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) 341system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) 342system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) 343system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) 344system.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses 345system.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses 346system.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses 347system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses 348system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses 349system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses 350system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 351system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 352system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses 353system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses 354system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses 355system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses 356system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048324 # miss rate for StoreCondReq accesses 357system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048324 # miss rate for StoreCondReq accesses 358system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses 359system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses 360system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses 361system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses 362system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu0.dcache.fast_writes 0 # number of fast writes performed 369system.cpu0.dcache.cache_copies 0 # number of cache copies performed 370system.cpu0.dcache.writebacks::writebacks 693486 # number of writebacks 371system.cpu0.dcache.writebacks::total 693486 # number of writebacks 372system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 373system.cpu0.icache.tags.replacements 1109735 # number of replacements 374system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use 375system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks. 376system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks. 377system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks. 378system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 379system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor 380system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 381system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 382system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 383system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 384system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 385system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 386system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 387system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses 388system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses 389system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits 390system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits 391system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits 392system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits 393system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits 394system.cpu0.icache.overall_hits::total 96331417 # number of overall hits 395system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses 396system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses 397system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses 398system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses 399system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses 400system.cpu0.icache.overall_misses::total 1110256 # number of overall misses 401system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses) 402system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses) 403system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses 404system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses 405system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses 406system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses 407system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses 408system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses 409system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses 410system.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses 411system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses 412system.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses 413system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 414system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 415system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 416system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 417system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 418system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.cpu0.icache.fast_writes 0 # number of fast writes performed 420system.cpu0.icache.cache_copies 0 # number of cache copies performed 421system.cpu0.icache.writebacks::writebacks 1109735 # number of writebacks 422system.cpu0.icache.writebacks::total 1109735 # number of writebacks 423system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 424system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 425system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 426system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 427system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 428system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 429system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 430system.cpu0.l2cache.tags.replacements 249527 # number of replacements 431system.cpu0.l2cache.tags.tagsinuse 16129.991654 # Cycle average of tags in use 432system.cpu0.l2cache.tags.total_refs 2731505 # Total number of references to valid blocks. 433system.cpu0.l2cache.tags.sampled_refs 265646 # Sample count of references to valid blocks. 434system.cpu0.l2cache.tags.avg_refs 10.282500 # Average number of references to valid blocks. 435system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 436system.cpu0.l2cache.tags.occ_blocks::writebacks 16127.358870 # Average occupied blocks per requestor 437system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.556147 # Average occupied blocks per requestor 438system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076637 # Average occupied blocks per requestor 439system.cpu0.l2cache.tags.occ_percent::writebacks 0.984336 # Average percentage of cache occupancy 440system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000156 # Average percentage of cache occupancy 441system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 442system.cpu0.l2cache.tags.occ_percent::total 0.984497 # Average percentage of cache occupancy 443system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 444system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16112 # Occupied blocks per task id 445system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 446system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 447system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id 448system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id 449system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5452 # Occupied blocks per task id 450system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7536 # Occupied blocks per task id 451system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2638 # Occupied blocks per task id 452system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id 453system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983398 # Percentage of cache occupancy per task id 454system.cpu0.l2cache.tags.tag_accesses 59699237 # Number of tag accesses 455system.cpu0.l2cache.tags.data_accesses 59699237 # Number of data accesses 456system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10182 # number of ReadReq hits 457system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4496 # number of ReadReq hits 458system.cpu0.l2cache.ReadReq_hits::total 14678 # number of ReadReq hits 459system.cpu0.l2cache.WritebackDirty_hits::writebacks 510201 # number of WritebackDirty hits 460system.cpu0.l2cache.WritebackDirty_hits::total 510201 # number of WritebackDirty hits 461system.cpu0.l2cache.WritebackClean_hits::writebacks 1265145 # number of WritebackClean hits 462system.cpu0.l2cache.WritebackClean_hits::total 1265145 # number of WritebackClean hits 463system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94344 # number of ReadExReq hits 464system.cpu0.l2cache.ReadExReq_hits::total 94344 # number of ReadExReq hits 465system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068613 # number of ReadCleanReq hits 466system.cpu0.l2cache.ReadCleanReq_hits::total 1068613 # number of ReadCleanReq hits 467system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352244 # number of ReadSharedReq hits 468system.cpu0.l2cache.ReadSharedReq_hits::total 352244 # number of ReadSharedReq hits 469system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10182 # number of demand (read+write) hits 470system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4496 # number of demand (read+write) hits 471system.cpu0.l2cache.demand_hits::cpu0.inst 1068613 # number of demand (read+write) hits 472system.cpu0.l2cache.demand_hits::cpu0.data 446588 # number of demand (read+write) hits 473system.cpu0.l2cache.demand_hits::total 1529879 # number of demand (read+write) hits 474system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10182 # number of overall hits 475system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4496 # number of overall hits 476system.cpu0.l2cache.overall_hits::cpu0.inst 1068613 # number of overall hits 477system.cpu0.l2cache.overall_hits::cpu0.data 446588 # number of overall hits 478system.cpu0.l2cache.overall_hits::total 1529879 # number of overall hits 479system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses 480system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 130 # number of ReadReq misses 481system.cpu0.l2cache.ReadReq_misses::total 344 # number of ReadReq misses 482system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26273 # number of UpgradeReq misses 483system.cpu0.l2cache.UpgradeReq_misses::total 26273 # number of UpgradeReq misses 484system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18435 # number of SCUpgradeReq misses 485system.cpu0.l2cache.SCUpgradeReq_misses::total 18435 # number of SCUpgradeReq misses 486system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175179 # number of ReadExReq misses 487system.cpu0.l2cache.ReadExReq_misses::total 175179 # number of ReadExReq misses 488system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41643 # number of ReadCleanReq misses 489system.cpu0.l2cache.ReadCleanReq_misses::total 41643 # number of ReadCleanReq misses 490system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127922 # number of ReadSharedReq misses 491system.cpu0.l2cache.ReadSharedReq_misses::total 127922 # number of ReadSharedReq misses 492system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses 493system.cpu0.l2cache.demand_misses::cpu0.itb.walker 130 # number of demand (read+write) misses 494system.cpu0.l2cache.demand_misses::cpu0.inst 41643 # number of demand (read+write) misses 495system.cpu0.l2cache.demand_misses::cpu0.data 303101 # number of demand (read+write) misses 496system.cpu0.l2cache.demand_misses::total 345088 # number of demand (read+write) misses 497system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses 498system.cpu0.l2cache.overall_misses::cpu0.itb.walker 130 # number of overall misses 499system.cpu0.l2cache.overall_misses::cpu0.inst 41643 # number of overall misses 500system.cpu0.l2cache.overall_misses::cpu0.data 303101 # number of overall misses 501system.cpu0.l2cache.overall_misses::total 345088 # number of overall misses 502system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10396 # number of ReadReq accesses(hits+misses) 503system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4626 # number of ReadReq accesses(hits+misses) 504system.cpu0.l2cache.ReadReq_accesses::total 15022 # number of ReadReq accesses(hits+misses) 505system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510201 # number of WritebackDirty accesses(hits+misses) 506system.cpu0.l2cache.WritebackDirty_accesses::total 510201 # number of WritebackDirty accesses(hits+misses) 507system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265145 # number of WritebackClean accesses(hits+misses) 508system.cpu0.l2cache.WritebackClean_accesses::total 1265145 # number of WritebackClean accesses(hits+misses) 509system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) 510system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) 511system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18435 # number of SCUpgradeReq accesses(hits+misses) 512system.cpu0.l2cache.SCUpgradeReq_accesses::total 18435 # number of SCUpgradeReq accesses(hits+misses) 513system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) 514system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) 515system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses) 516system.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses) 517system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480166 # number of ReadSharedReq accesses(hits+misses) 518system.cpu0.l2cache.ReadSharedReq_accesses::total 480166 # number of ReadSharedReq accesses(hits+misses) 519system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10396 # number of demand (read+write) accesses 520system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4626 # number of demand (read+write) accesses 521system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses 522system.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses 523system.cpu0.l2cache.demand_accesses::total 1874967 # number of demand (read+write) accesses 524system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10396 # number of overall (read+write) accesses 525system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4626 # number of overall (read+write) accesses 526system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses 527system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses 528system.cpu0.l2cache.overall_accesses::total 1874967 # number of overall (read+write) accesses 529system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for ReadReq accesses 530system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028102 # miss rate for ReadReq accesses 531system.cpu0.l2cache.ReadReq_miss_rate::total 0.022900 # miss rate for ReadReq accesses 532system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 533system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 534system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 535system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 536system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649959 # miss rate for ReadExReq accesses 537system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649959 # miss rate for ReadExReq accesses 538system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037508 # miss rate for ReadCleanReq accesses 539system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037508 # miss rate for ReadCleanReq accesses 540system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266412 # miss rate for ReadSharedReq accesses 541system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266412 # miss rate for ReadSharedReq accesses 542system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for demand accesses 543system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028102 # miss rate for demand accesses 544system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037508 # miss rate for demand accesses 545system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404302 # miss rate for demand accesses 546system.cpu0.l2cache.demand_miss_rate::total 0.184050 # miss rate for demand accesses 547system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for overall accesses 548system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028102 # miss rate for overall accesses 549system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037508 # miss rate for overall accesses 550system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404302 # miss rate for overall accesses 551system.cpu0.l2cache.overall_miss_rate::total 0.184050 # miss rate for overall accesses 552system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 553system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 555system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 557system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 559system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 560system.cpu0.l2cache.writebacks::writebacks 192911 # number of writebacks 561system.cpu0.l2cache.writebacks::total 192911 # number of writebacks 562system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 563system.cpu0.toL2Bus.snoop_filter.tot_requests 3720245 # Total number of requests made to the snoop filter. 564system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860324 # Number of requests hitting in the snoop filter with a single holder of the requested data. 565system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 566system.cpu0.toL2Bus.snoop_filter.tot_snoops 218142 # Total number of snoops made to the snoop filter. 567system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 568system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2894 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 569system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution 570system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution 571system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 572system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 573system.cpu0.toL2Bus.trans_dist::WritebackDirty 510201 # Transaction distribution 574system.cpu0.toL2Bus.trans_dist::WritebackClean 1265145 # Transaction distribution 575system.cpu0.toL2Bus.trans_dist::UpgradeReq 26273 # Transaction distribution 576system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18435 # Transaction distribution 577system.cpu0.toL2Bus.trans_dist::UpgradeResp 44708 # Transaction distribution 578system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution 579system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution 580system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution 581system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution 582system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes) 583system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395284 # Packet count per connected master and slave (bytes) 584system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 585system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) 586system.cpu0.toL2Bus.pkt_count::total 5764166 # Packet count per connected master and slave (bytes) 587system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140768632 # Cumulative packet size per connected master and slave (bytes) 588system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92116612 # Cumulative packet size per connected master and slave (bytes) 589system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 590system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) 591system.cpu0.toL2Bus.pkt_size::total 232968516 # Cumulative packet size per connected master and slave (bytes) 592system.cpu0.toL2Bus.snoops 623122 # Total snoops (count) 593system.cpu0.toL2Bus.snoop_fanout::samples 4318148 # Request fanout histogram 594system.cpu0.toL2Bus.snoop_fanout::mean 0.066969 # Request fanout histogram 595system.cpu0.toL2Bus.snoop_fanout::stdev 0.252635 # Request fanout histogram 596system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 597system.cpu0.toL2Bus.snoop_fanout::0 4031861 93.37% 93.37% # Request fanout histogram 598system.cpu0.toL2Bus.snoop_fanout::1 283393 6.56% 99.93% # Request fanout histogram 599system.cpu0.toL2Bus.snoop_fanout::2 2894 0.07% 100.00% # Request fanout histogram 600system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 601system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 602system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 603system.cpu0.toL2Bus.snoop_fanout::total 4318148 # Request fanout histogram 604system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 605system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 606system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 607system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 608system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 609system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 610system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 611system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 612system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 613system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 614system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 615system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 616system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 617system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 618system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 619system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 620system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 621system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 622system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 623system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 624system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 625system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 626system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 627system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 628system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 629system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 630system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 631system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 632system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 633system.cpu1.dtb.walker.walks 3358 # Table walker walks requested 634system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 635system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 636system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 637system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 638system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 639system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 640system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 641system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated 642system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated 643system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated 644system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst 645system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 646system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 647system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst 648system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 649system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst 650system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst 651system.cpu1.dtb.inst_hits 0 # ITB inst hits 652system.cpu1.dtb.inst_misses 0 # ITB inst misses 653system.cpu1.dtb.read_hits 12173916 # DTB read hits 654system.cpu1.dtb.read_misses 2852 # DTB read misses 655system.cpu1.dtb.write_hits 7587209 # DTB write hits 656system.cpu1.dtb.write_misses 506 # DTB write misses 657system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 658system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 659system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 660system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 661system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 662system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 663system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 664system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 665system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 666system.cpu1.dtb.read_accesses 12176768 # DTB read accesses 667system.cpu1.dtb.write_accesses 7587715 # DTB write accesses 668system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 669system.cpu1.dtb.hits 19761125 # DTB hits 670system.cpu1.dtb.misses 3358 # DTB misses 671system.cpu1.dtb.accesses 19764483 # DTB accesses 672system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 673system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 674system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 675system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 676system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 677system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 678system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 679system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 680system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 681system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 682system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 683system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 684system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 685system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 686system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 687system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 688system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 689system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 690system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 691system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 692system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 693system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 694system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 695system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 696system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 697system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 698system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 699system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 700system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 701system.cpu1.itb.walker.walks 1734 # Table walker walks requested 702system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 703system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 704system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 705system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 706system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 707system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 708system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 709system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 710system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 711system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 712system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 713system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 714system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 715system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 716system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 717system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 718system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 719system.cpu1.itb.inst_hits 53671575 # ITB inst hits 720system.cpu1.itb.inst_misses 1734 # ITB inst misses 721system.cpu1.itb.read_hits 0 # DTB read hits 722system.cpu1.itb.read_misses 0 # DTB read misses 723system.cpu1.itb.write_hits 0 # DTB write hits 724system.cpu1.itb.write_misses 0 # DTB write misses 725system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 726system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 727system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 728system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 729system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 730system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 731system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 732system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 733system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 734system.cpu1.itb.read_accesses 0 # DTB read accesses 735system.cpu1.itb.write_accesses 0 # DTB write accesses 736system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses 737system.cpu1.itb.hits 53671575 # DTB hits 738system.cpu1.itb.misses 1734 # DTB misses 739system.cpu1.itb.accesses 53673309 # DTB accesses 740system.cpu1.numCycles 5605320274 # number of cpu cycles simulated 741system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 742system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 743system.cpu1.kern.inst.arm 0 # number of arm instructions executed 744system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 745system.cpu1.committedInsts 51401314 # Number of instructions committed 746system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed 747system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses 748system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 749system.cpu1.num_func_calls 9170855 # number of times a function call or return occured 750system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls 751system.cpu1.num_int_insts 56984241 # number of integer instructions 752system.cpu1.num_fp_insts 1792 # number of float instructions 753system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read 754system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written 755system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 756system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 757system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read 758system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written 759system.cpu1.num_mem_refs 20026381 # number of memory refs 760system.cpu1.num_load_insts 12289537 # Number of load instructions 761system.cpu1.num_store_insts 7736844 # Number of store instructions 762system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles 763system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles 764system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 765system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 766system.cpu1.Branches 15217493 # Number of branches fetched 767system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 768system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction 769system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction 770system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 771system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 772system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 773system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 774system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 775system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 776system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 777system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 778system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 779system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 780system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 781system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 782system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 783system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 784system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 785system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 786system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 787system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 788system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 789system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 790system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 791system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 792system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 793system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 794system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 795system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 796system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 797system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction 798system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction 799system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 800system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 801system.cpu1.op_class::total 65459464 # Class of executed instruction 802system.cpu1.dcache.tags.replacements 191938 # number of replacements 803system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use 804system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. 805system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. 806system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks. 807system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 808system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor 809system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy 810system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy 811system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 812system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 813system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 814system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 815system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses 816system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses 817system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits 818system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits 819system.cpu1.dcache.WriteReq_hits::cpu1.data 7397500 # number of WriteReq hits 820system.cpu1.dcache.WriteReq_hits::total 7397500 # number of WriteReq hits 821system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits 822system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits 823system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 824system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 825system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits 826system.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits 827system.cpu1.dcache.demand_hits::cpu1.data 19256194 # number of demand (read+write) hits 828system.cpu1.dcache.demand_hits::total 19256194 # number of demand (read+write) hits 829system.cpu1.dcache.overall_hits::cpu1.data 19306293 # number of overall hits 830system.cpu1.dcache.overall_hits::total 19306293 # number of overall hits 831system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses 832system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses 833system.cpu1.dcache.WriteReq_misses::cpu1.data 92462 # number of WriteReq misses 834system.cpu1.dcache.WriteReq_misses::total 92462 # number of WriteReq misses 835system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses 836system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses 837system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 838system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 839system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses 840system.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses 841system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses 842system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses 843system.cpu1.dcache.overall_misses::cpu1.data 259811 # number of overall misses 844system.cpu1.dcache.overall_misses::total 259811 # number of overall misses 845system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) 846system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) 847system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) 848system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses) 849system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 850system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 851system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 852system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 853system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 854system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 855system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses 856system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses 857system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses 858system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses 859system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses 860system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses 861system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses 862system.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses 863system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses 864system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses 865system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 866system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 867system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237347 # miss rate for StoreCondReq accesses 868system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237347 # miss rate for StoreCondReq accesses 869system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 870system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 871system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 872system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 873system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 874system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 875system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 876system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 877system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 878system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 879system.cpu1.dcache.fast_writes 0 # number of fast writes performed 880system.cpu1.dcache.cache_copies 0 # number of cache copies performed 881system.cpu1.dcache.writebacks::writebacks 191938 # number of writebacks 882system.cpu1.dcache.writebacks::total 191938 # number of writebacks 883system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 884system.cpu1.icache.tags.replacements 523373 # number of replacements 885system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use 886system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks. 887system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. 888system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks. 889system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 890system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor 891system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 892system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 893system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 894system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 895system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 896system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 897system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses 898system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses 899system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits 900system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits 901system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits 902system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits 903system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits 904system.cpu1.icache.overall_hits::total 53148780 # number of overall hits 905system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses 906system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses 907system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses 908system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses 909system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses 910system.cpu1.icache.overall_misses::total 523885 # number of overall misses 911system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses) 912system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses) 913system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses 914system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses 915system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses 916system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses 917system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 918system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 919system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 920system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 921system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 922system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 923system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 924system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 925system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 926system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 927system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 928system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 929system.cpu1.icache.fast_writes 0 # number of fast writes performed 930system.cpu1.icache.cache_copies 0 # number of cache copies performed 931system.cpu1.icache.writebacks::writebacks 523373 # number of writebacks 932system.cpu1.icache.writebacks::total 523373 # number of writebacks 933system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 934system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 935system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 936system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 937system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 938system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 939system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 940system.cpu1.l2cache.tags.replacements 47555 # number of replacements 941system.cpu1.l2cache.tags.tagsinuse 15235.297156 # Cycle average of tags in use 942system.cpu1.l2cache.tags.total_refs 1184961 # Total number of references to valid blocks. 943system.cpu1.l2cache.tags.sampled_refs 62593 # Sample count of references to valid blocks. 944system.cpu1.l2cache.tags.avg_refs 18.931206 # Average number of references to valid blocks. 945system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 946system.cpu1.l2cache.tags.occ_blocks::writebacks 15230.950549 # Average occupied blocks per requestor 947system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.335617 # Average occupied blocks per requestor 948system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010990 # Average occupied blocks per requestor 949system.cpu1.l2cache.tags.occ_percent::writebacks 0.929623 # Average percentage of cache occupancy 950system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy 951system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 952system.cpu1.l2cache.tags.occ_percent::total 0.929889 # Average percentage of cache occupancy 953system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 954system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15019 # Occupied blocks per task id 955system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 956system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 957system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 958system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 530 # Occupied blocks per task id 959system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9526 # Occupied blocks per task id 960system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4963 # Occupied blocks per task id 961system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id 962system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.916687 # Percentage of cache occupancy per task id 963system.cpu1.l2cache.tags.tag_accesses 24500378 # Number of tag accesses 964system.cpu1.l2cache.tags.data_accesses 24500378 # Number of data accesses 965system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits 966system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1913 # number of ReadReq hits 967system.cpu1.l2cache.ReadReq_hits::total 5534 # number of ReadReq hits 968system.cpu1.l2cache.WritebackDirty_hits::writebacks 121109 # number of WritebackDirty hits 969system.cpu1.l2cache.WritebackDirty_hits::total 121109 # number of WritebackDirty hits 970system.cpu1.l2cache.WritebackClean_hits::writebacks 583044 # number of WritebackClean hits 971system.cpu1.l2cache.WritebackClean_hits::total 583044 # number of WritebackClean hits 972system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19763 # number of ReadExReq hits 973system.cpu1.l2cache.ReadExReq_hits::total 19763 # number of ReadExReq hits 974system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510346 # number of ReadCleanReq hits 975system.cpu1.l2cache.ReadCleanReq_hits::total 510346 # number of ReadCleanReq hits 976system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99093 # number of ReadSharedReq hits 977system.cpu1.l2cache.ReadSharedReq_hits::total 99093 # number of ReadSharedReq hits 978system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits 979system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1913 # number of demand (read+write) hits 980system.cpu1.l2cache.demand_hits::cpu1.inst 510346 # number of demand (read+write) hits 981system.cpu1.l2cache.demand_hits::cpu1.data 118856 # number of demand (read+write) hits 982system.cpu1.l2cache.demand_hits::total 634736 # number of demand (read+write) hits 983system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits 984system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1913 # number of overall hits 985system.cpu1.l2cache.overall_hits::cpu1.inst 510346 # number of overall hits 986system.cpu1.l2cache.overall_hits::cpu1.data 118856 # number of overall hits 987system.cpu1.l2cache.overall_hits::total 634736 # number of overall hits 988system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses 989system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses 990system.cpu1.l2cache.ReadReq_misses::total 607 # number of ReadReq misses 991system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses 992system.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses 993system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses 994system.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses 995system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43853 # number of ReadExReq misses 996system.cpu1.l2cache.ReadExReq_misses::total 43853 # number of ReadExReq misses 997system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13539 # number of ReadCleanReq misses 998system.cpu1.l2cache.ReadCleanReq_misses::total 13539 # number of ReadCleanReq misses 999system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73574 # number of ReadSharedReq misses 1000system.cpu1.l2cache.ReadSharedReq_misses::total 73574 # number of ReadSharedReq misses 1001system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses 1002system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses 1003system.cpu1.l2cache.demand_misses::cpu1.inst 13539 # number of demand (read+write) misses 1004system.cpu1.l2cache.demand_misses::cpu1.data 117427 # number of demand (read+write) misses 1005system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses 1006system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses 1007system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses 1008system.cpu1.l2cache.overall_misses::cpu1.inst 13539 # number of overall misses 1009system.cpu1.l2cache.overall_misses::cpu1.data 117427 # number of overall misses 1010system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses 1011system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3957 # number of ReadReq accesses(hits+misses) 1012system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2184 # number of ReadReq accesses(hits+misses) 1013system.cpu1.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) 1014system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121109 # number of WritebackDirty accesses(hits+misses) 1015system.cpu1.l2cache.WritebackDirty_accesses::total 121109 # number of WritebackDirty accesses(hits+misses) 1016system.cpu1.l2cache.WritebackClean_accesses::writebacks 583044 # number of WritebackClean accesses(hits+misses) 1017system.cpu1.l2cache.WritebackClean_accesses::total 583044 # number of WritebackClean accesses(hits+misses) 1018system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses) 1019system.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses) 1020system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) 1021system.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses) 1022system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) 1023system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) 1024system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 # number of ReadCleanReq accesses(hits+misses) 1025system.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses) 1026system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172667 # number of ReadSharedReq accesses(hits+misses) 1027system.cpu1.l2cache.ReadSharedReq_accesses::total 172667 # number of ReadSharedReq accesses(hits+misses) 1028system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3957 # number of demand (read+write) accesses 1029system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2184 # number of demand (read+write) accesses 1030system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses 1031system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses 1032system.cpu1.l2cache.demand_accesses::total 766309 # number of demand (read+write) accesses 1033system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3957 # number of overall (read+write) accesses 1034system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2184 # number of overall (read+write) accesses 1035system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses 1036system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses 1037system.cpu1.l2cache.overall_accesses::total 766309 # number of overall (read+write) accesses 1038system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for ReadReq accesses 1039system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124084 # miss rate for ReadReq accesses 1040system.cpu1.l2cache.ReadReq_miss_rate::total 0.098844 # miss rate for ReadReq accesses 1041system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1042system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1043system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1044system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1045system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689339 # miss rate for ReadExReq accesses 1046system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689339 # miss rate for ReadExReq accesses 1047system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025843 # miss rate for ReadCleanReq accesses 1048system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025843 # miss rate for ReadCleanReq accesses 1049system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.426103 # miss rate for ReadSharedReq accesses 1050system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.426103 # miss rate for ReadSharedReq accesses 1051system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for demand accesses 1052system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124084 # miss rate for demand accesses 1053system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025843 # miss rate for demand accesses 1054system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496976 # miss rate for demand accesses 1055system.cpu1.l2cache.demand_miss_rate::total 0.171697 # miss rate for demand accesses 1056system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for overall accesses 1057system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124084 # miss rate for overall accesses 1058system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025843 # miss rate for overall accesses 1059system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496976 # miss rate for overall accesses 1060system.cpu1.l2cache.overall_miss_rate::total 0.171697 # miss rate for overall accesses 1061system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1062system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1063system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1064system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1065system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1066system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1067system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1068system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1069system.cpu1.l2cache.writebacks::writebacks 32818 # number of writebacks 1070system.cpu1.l2cache.writebacks::total 32818 # number of writebacks 1071system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1072system.cpu1.toL2Bus.snoop_filter.tot_requests 1533421 # Total number of requests made to the snoop filter. 1073system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773256 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1074system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1075system.cpu1.toL2Bus.snoop_filter.tot_snoops 165978 # Total number of snoops made to the snoop filter. 1076system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164041 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1077system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1078system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution 1079system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution 1080system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 1081system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 1082system.cpu1.toL2Bus.trans_dist::WritebackDirty 121109 # Transaction distribution 1083system.cpu1.toL2Bus.trans_dist::WritebackClean 583044 # Transaction distribution 1084system.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution 1085system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution 1086system.cpu1.toL2Bus.trans_dist::UpgradeResp 51389 # Transaction distribution 1087system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution 1088system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution 1089system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution 1090system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution 1091system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes) 1092system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776509 # Packet count per connected master and slave (bytes) 1093system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 1094system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) 1095system.cpu1.toL2Bus.pkt_count::total 2357775 # Packet count per connected master and slave (bytes) 1096system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66454020 # Cumulative packet size per connected master and slave (bytes) 1097system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27282414 # Cumulative packet size per connected master and slave (bytes) 1098system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 1099system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) 1100system.cpu1.toL2Bus.pkt_size::total 93773822 # Cumulative packet size per connected master and slave (bytes) 1101system.cpu1.toL2Bus.snoops 347349 # Total snoops (count) 1102system.cpu1.toL2Bus.snoop_fanout::samples 1819817 # Request fanout histogram 1103system.cpu1.toL2Bus.snoop_fanout::mean 0.108136 # Request fanout histogram 1104system.cpu1.toL2Bus.snoop_fanout::stdev 0.313960 # Request fanout histogram 1105system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1106system.cpu1.toL2Bus.snoop_fanout::0 1624967 89.29% 89.29% # Request fanout histogram 1107system.cpu1.toL2Bus.snoop_fanout::1 192913 10.60% 99.89% # Request fanout histogram 1108system.cpu1.toL2Bus.snoop_fanout::2 1937 0.11% 100.00% # Request fanout histogram 1109system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1110system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1111system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1112system.cpu1.toL2Bus.snoop_fanout::total 1819817 # Request fanout histogram 1113system.iobus.trans_dist::ReadReq 30995 # Transaction distribution 1114system.iobus.trans_dist::ReadResp 30995 # Transaction distribution 1115system.iobus.trans_dist::WriteReq 59419 # Transaction distribution 1116system.iobus.trans_dist::WriteResp 59419 # Transaction distribution 1117system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 1118system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)	12sim_insts 146828240 # Number of instructions simulated 13sim_ops 178908039 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1108644 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 9410404 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 1082576 # Number of bytes read from this memory 22system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 23system.physmem.bytes_read::total 11757100 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 1108644 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 1262520 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 8452288 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 30system.physmem.bytes_written::total 8469852 # Number of bytes written to this memory 31system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 25776 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 147557 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.data 16935 # Number of read requests responded to by this memory 37system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 192852 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 132067 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 136458 # Number of write requests responded to by this memory 43system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.inst 395535 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.data 3357388 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.data 386235 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::total 4194628 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu0.inst 395535 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 450434 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_write::writebacks 3015557 # Write bandwidth from this memory (bytes/s) 55system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::total 3021823 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_total::writebacks 3015557 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.inst 395535 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.data 3363640 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu1.data 386249 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::total 7216451 # Total bandwidth to/from this memory (bytes/s) 67system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 68system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 69system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 70system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 71system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 72system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 73system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 74system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 75system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 76system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 77system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 78system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 83system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 84system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 85system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 86system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 87system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 88system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 89system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 90system.cf0.dma_write_txs 631 # Number of DMA write transactions. 91system.cpu_clk_domain.clock 500 # Clock period in ticks 92system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 93system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 94system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 95system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 96system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 97system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 98system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 99system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 100system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 101system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 102system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 103system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 104system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 105system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 106system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 107system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 108system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 109system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 110system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 111system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 112system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 113system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 114system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 115system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 116system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 117system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 118system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 119system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 120system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 121system.cpu0.dtb.walker.walks 7967 # Table walker walks requested 122system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors 123system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency 124system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency 125system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency 126system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 127system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 128system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 129system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated 130system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated 131system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated 132system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst 133system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 134system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst 135system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst 136system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 137system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst 138system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst 139system.cpu0.dtb.inst_hits 0 # ITB inst hits 140system.cpu0.dtb.inst_misses 0 # ITB inst misses 141system.cpu0.dtb.read_hits 20339720 # DTB read hits 142system.cpu0.dtb.read_misses 6874 # DTB read misses 143system.cpu0.dtb.write_hits 16391078 # DTB write hits 144system.cpu0.dtb.write_misses 1093 # DTB write misses 145system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 146system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 147system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 148system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 149system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 150system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 151system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 152system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 153system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 154system.cpu0.dtb.read_accesses 20346594 # DTB read accesses 155system.cpu0.dtb.write_accesses 16392171 # DTB write accesses 156system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 157system.cpu0.dtb.hits 36730798 # DTB hits 158system.cpu0.dtb.misses 7967 # DTB misses 159system.cpu0.dtb.accesses 36738765 # DTB accesses 160system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 161system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 162system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 163system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 164system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 165system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 166system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 167system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 168system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 169system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 170system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 171system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 172system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 173system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 174system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 175system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 176system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 177system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 178system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 179system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 180system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 181system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 182system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 183system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 184system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 185system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 186system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 187system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 188system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 189system.cpu0.itb.walker.walks 3358 # Table walker walks requested 190system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 191system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 192system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 193system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 194system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 195system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 196system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 197system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 198system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 199system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 200system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 201system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 202system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 203system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 204system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 205system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 206system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 207system.cpu0.itb.inst_hits 97439331 # ITB inst hits 208system.cpu0.itb.inst_misses 3358 # ITB inst misses 209system.cpu0.itb.read_hits 0 # DTB read hits 210system.cpu0.itb.read_misses 0 # DTB read misses 211system.cpu0.itb.write_hits 0 # DTB write hits 212system.cpu0.itb.write_misses 0 # DTB write misses 213system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 214system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 215system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 216system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 217system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 218system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 219system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 220system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 221system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 222system.cpu0.itb.read_accesses 0 # DTB read accesses 223system.cpu0.itb.write_accesses 0 # DTB write accesses 224system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses 225system.cpu0.itb.hits 97439331 # DTB hits 226system.cpu0.itb.misses 3358 # DTB misses 227system.cpu0.itb.accesses 97442689 # DTB accesses 228system.cpu0.numCycles 5605791368 # number of cpu cycles simulated 229system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 230system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 231system.cpu0.kern.inst.arm 0 # number of arm instructions executed 232system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed 233system.cpu0.committedInsts 95426926 # Number of instructions committed 234system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed 235system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses 236system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 237system.cpu0.num_func_calls 8000180 # number of times a function call or return occured 238system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls 239system.cpu0.num_int_insts 100762696 # number of integer instructions 240system.cpu0.num_fp_insts 9755 # number of float instructions 241system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read 242system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written 243system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 244system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 245system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read 246system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written 247system.cpu0.num_mem_refs 37873810 # number of memory refs 248system.cpu0.num_load_insts 20597310 # Number of load instructions 249system.cpu0.num_store_insts 17276500 # Number of store instructions 250system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles 251system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles 252system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 253system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 254system.cpu0.Branches 21941499 # Number of branches fetched 255system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 256system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction 257system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction 258system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 259system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 260system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 261system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 262system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 263system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 264system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 265system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 266system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 267system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 268system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 269system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 270system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 271system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 272system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 273system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 274system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 275system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 276system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 277system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 278system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 279system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 280system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 281system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 282system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 283system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 284system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 285system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction 286system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction 287system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 288system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 289system.cpu0.op_class::total 116882065 # Class of executed instruction 290system.cpu0.dcache.tags.replacements 693486 # number of replacements 291system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use 292system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. 293system.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks. 294system.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks. 295system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 296system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor 297system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 298system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 299system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 300system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 301system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 302system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 303system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 304system.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses 305system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses 306system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits 307system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits 308system.cpu0.dcache.WriteReq_hits::cpu0.data 15690389 # number of WriteReq hits 309system.cpu0.dcache.WriteReq_hits::total 15690389 # number of WriteReq hits 310system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits 311system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits 312system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits 313system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits 314system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363050 # number of StoreCondReq hits 315system.cpu0.dcache.StoreCondReq_hits::total 363050 # number of StoreCondReq hits 316system.cpu0.dcache.demand_hits::cpu0.data 34798930 # number of demand (read+write) hits 317system.cpu0.dcache.demand_hits::total 34798930 # number of demand (read+write) hits 318system.cpu0.dcache.overall_hits::cpu0.data 35145023 # number of overall hits 319system.cpu0.dcache.overall_hits::total 35145023 # number of overall hits 320system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses 321system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses 322system.cpu0.dcache.WriteReq_misses::cpu0.data 295796 # number of WriteReq misses 323system.cpu0.dcache.WriteReq_misses::total 295796 # number of WriteReq misses 324system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 325system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 326system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses 327system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses 328system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18435 # number of StoreCondReq misses 329system.cpu0.dcache.StoreCondReq_misses::total 18435 # number of StoreCondReq misses 330system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses 331system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses 332system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses 333system.cpu0.dcache.overall_misses::total 769220 # number of overall misses 334system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) 335system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) 336system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) 337system.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses) 338system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) 339system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) 340system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) 341system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) 342system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) 343system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) 344system.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses 345system.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses 346system.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses 347system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses 348system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses 349system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses 350system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 351system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 352system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses 353system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses 354system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses 355system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses 356system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048324 # miss rate for StoreCondReq accesses 357system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048324 # miss rate for StoreCondReq accesses 358system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses 359system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses 360system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses 361system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses 362system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu0.dcache.fast_writes 0 # number of fast writes performed 369system.cpu0.dcache.cache_copies 0 # number of cache copies performed 370system.cpu0.dcache.writebacks::writebacks 693486 # number of writebacks 371system.cpu0.dcache.writebacks::total 693486 # number of writebacks 372system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 373system.cpu0.icache.tags.replacements 1109735 # number of replacements 374system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use 375system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks. 376system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks. 377system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks. 378system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 379system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor 380system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 381system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 382system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 383system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 384system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 385system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 386system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 387system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses 388system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses 389system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits 390system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits 391system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits 392system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits 393system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits 394system.cpu0.icache.overall_hits::total 96331417 # number of overall hits 395system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses 396system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses 397system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses 398system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses 399system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses 400system.cpu0.icache.overall_misses::total 1110256 # number of overall misses 401system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses) 402system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses) 403system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses 404system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses 405system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses 406system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses 407system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses 408system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses 409system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses 410system.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses 411system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses 412system.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses 413system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 414system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 415system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 416system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 417system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 418system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.cpu0.icache.fast_writes 0 # number of fast writes performed 420system.cpu0.icache.cache_copies 0 # number of cache copies performed 421system.cpu0.icache.writebacks::writebacks 1109735 # number of writebacks 422system.cpu0.icache.writebacks::total 1109735 # number of writebacks 423system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 424system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 425system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 426system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 427system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 428system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 429system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 430system.cpu0.l2cache.tags.replacements 249527 # number of replacements 431system.cpu0.l2cache.tags.tagsinuse 16129.991654 # Cycle average of tags in use 432system.cpu0.l2cache.tags.total_refs 2731505 # Total number of references to valid blocks. 433system.cpu0.l2cache.tags.sampled_refs 265646 # Sample count of references to valid blocks. 434system.cpu0.l2cache.tags.avg_refs 10.282500 # Average number of references to valid blocks. 435system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 436system.cpu0.l2cache.tags.occ_blocks::writebacks 16127.358870 # Average occupied blocks per requestor 437system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.556147 # Average occupied blocks per requestor 438system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076637 # Average occupied blocks per requestor 439system.cpu0.l2cache.tags.occ_percent::writebacks 0.984336 # Average percentage of cache occupancy 440system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000156 # Average percentage of cache occupancy 441system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 442system.cpu0.l2cache.tags.occ_percent::total 0.984497 # Average percentage of cache occupancy 443system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 444system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16112 # Occupied blocks per task id 445system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 446system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 447system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id 448system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id 449system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5452 # Occupied blocks per task id 450system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7536 # Occupied blocks per task id 451system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2638 # Occupied blocks per task id 452system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id 453system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983398 # Percentage of cache occupancy per task id 454system.cpu0.l2cache.tags.tag_accesses 59699237 # Number of tag accesses 455system.cpu0.l2cache.tags.data_accesses 59699237 # Number of data accesses 456system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10182 # number of ReadReq hits 457system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4496 # number of ReadReq hits 458system.cpu0.l2cache.ReadReq_hits::total 14678 # number of ReadReq hits 459system.cpu0.l2cache.WritebackDirty_hits::writebacks 510201 # number of WritebackDirty hits 460system.cpu0.l2cache.WritebackDirty_hits::total 510201 # number of WritebackDirty hits 461system.cpu0.l2cache.WritebackClean_hits::writebacks 1265145 # number of WritebackClean hits 462system.cpu0.l2cache.WritebackClean_hits::total 1265145 # number of WritebackClean hits 463system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94344 # number of ReadExReq hits 464system.cpu0.l2cache.ReadExReq_hits::total 94344 # number of ReadExReq hits 465system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068613 # number of ReadCleanReq hits 466system.cpu0.l2cache.ReadCleanReq_hits::total 1068613 # number of ReadCleanReq hits 467system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352244 # number of ReadSharedReq hits 468system.cpu0.l2cache.ReadSharedReq_hits::total 352244 # number of ReadSharedReq hits 469system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10182 # number of demand (read+write) hits 470system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4496 # number of demand (read+write) hits 471system.cpu0.l2cache.demand_hits::cpu0.inst 1068613 # number of demand (read+write) hits 472system.cpu0.l2cache.demand_hits::cpu0.data 446588 # number of demand (read+write) hits 473system.cpu0.l2cache.demand_hits::total 1529879 # number of demand (read+write) hits 474system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10182 # number of overall hits 475system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4496 # number of overall hits 476system.cpu0.l2cache.overall_hits::cpu0.inst 1068613 # number of overall hits 477system.cpu0.l2cache.overall_hits::cpu0.data 446588 # number of overall hits 478system.cpu0.l2cache.overall_hits::total 1529879 # number of overall hits 479system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses 480system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 130 # number of ReadReq misses 481system.cpu0.l2cache.ReadReq_misses::total 344 # number of ReadReq misses 482system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26273 # number of UpgradeReq misses 483system.cpu0.l2cache.UpgradeReq_misses::total 26273 # number of UpgradeReq misses 484system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18435 # number of SCUpgradeReq misses 485system.cpu0.l2cache.SCUpgradeReq_misses::total 18435 # number of SCUpgradeReq misses 486system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175179 # number of ReadExReq misses 487system.cpu0.l2cache.ReadExReq_misses::total 175179 # number of ReadExReq misses 488system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41643 # number of ReadCleanReq misses 489system.cpu0.l2cache.ReadCleanReq_misses::total 41643 # number of ReadCleanReq misses 490system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127922 # number of ReadSharedReq misses 491system.cpu0.l2cache.ReadSharedReq_misses::total 127922 # number of ReadSharedReq misses 492system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses 493system.cpu0.l2cache.demand_misses::cpu0.itb.walker 130 # number of demand (read+write) misses 494system.cpu0.l2cache.demand_misses::cpu0.inst 41643 # number of demand (read+write) misses 495system.cpu0.l2cache.demand_misses::cpu0.data 303101 # number of demand (read+write) misses 496system.cpu0.l2cache.demand_misses::total 345088 # number of demand (read+write) misses 497system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses 498system.cpu0.l2cache.overall_misses::cpu0.itb.walker 130 # number of overall misses 499system.cpu0.l2cache.overall_misses::cpu0.inst 41643 # number of overall misses 500system.cpu0.l2cache.overall_misses::cpu0.data 303101 # number of overall misses 501system.cpu0.l2cache.overall_misses::total 345088 # number of overall misses 502system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10396 # number of ReadReq accesses(hits+misses) 503system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4626 # number of ReadReq accesses(hits+misses) 504system.cpu0.l2cache.ReadReq_accesses::total 15022 # number of ReadReq accesses(hits+misses) 505system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510201 # number of WritebackDirty accesses(hits+misses) 506system.cpu0.l2cache.WritebackDirty_accesses::total 510201 # number of WritebackDirty accesses(hits+misses) 507system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265145 # number of WritebackClean accesses(hits+misses) 508system.cpu0.l2cache.WritebackClean_accesses::total 1265145 # number of WritebackClean accesses(hits+misses) 509system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) 510system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) 511system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18435 # number of SCUpgradeReq accesses(hits+misses) 512system.cpu0.l2cache.SCUpgradeReq_accesses::total 18435 # number of SCUpgradeReq accesses(hits+misses) 513system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) 514system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) 515system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses) 516system.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses) 517system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480166 # number of ReadSharedReq accesses(hits+misses) 518system.cpu0.l2cache.ReadSharedReq_accesses::total 480166 # number of ReadSharedReq accesses(hits+misses) 519system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10396 # number of demand (read+write) accesses 520system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4626 # number of demand (read+write) accesses 521system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses 522system.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses 523system.cpu0.l2cache.demand_accesses::total 1874967 # number of demand (read+write) accesses 524system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10396 # number of overall (read+write) accesses 525system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4626 # number of overall (read+write) accesses 526system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses 527system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses 528system.cpu0.l2cache.overall_accesses::total 1874967 # number of overall (read+write) accesses 529system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for ReadReq accesses 530system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028102 # miss rate for ReadReq accesses 531system.cpu0.l2cache.ReadReq_miss_rate::total 0.022900 # miss rate for ReadReq accesses 532system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 533system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 534system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 535system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 536system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649959 # miss rate for ReadExReq accesses 537system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649959 # miss rate for ReadExReq accesses 538system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037508 # miss rate for ReadCleanReq accesses 539system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037508 # miss rate for ReadCleanReq accesses 540system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266412 # miss rate for ReadSharedReq accesses 541system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266412 # miss rate for ReadSharedReq accesses 542system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for demand accesses 543system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028102 # miss rate for demand accesses 544system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037508 # miss rate for demand accesses 545system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404302 # miss rate for demand accesses 546system.cpu0.l2cache.demand_miss_rate::total 0.184050 # miss rate for demand accesses 547system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for overall accesses 548system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028102 # miss rate for overall accesses 549system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037508 # miss rate for overall accesses 550system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404302 # miss rate for overall accesses 551system.cpu0.l2cache.overall_miss_rate::total 0.184050 # miss rate for overall accesses 552system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 553system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 555system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 557system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 559system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 560system.cpu0.l2cache.writebacks::writebacks 192911 # number of writebacks 561system.cpu0.l2cache.writebacks::total 192911 # number of writebacks 562system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 563system.cpu0.toL2Bus.snoop_filter.tot_requests 3720245 # Total number of requests made to the snoop filter. 564system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860324 # Number of requests hitting in the snoop filter with a single holder of the requested data. 565system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 566system.cpu0.toL2Bus.snoop_filter.tot_snoops 218142 # Total number of snoops made to the snoop filter. 567system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 568system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2894 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 569system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution 570system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution 571system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 572system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 573system.cpu0.toL2Bus.trans_dist::WritebackDirty 510201 # Transaction distribution 574system.cpu0.toL2Bus.trans_dist::WritebackClean 1265145 # Transaction distribution 575system.cpu0.toL2Bus.trans_dist::UpgradeReq 26273 # Transaction distribution 576system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18435 # Transaction distribution 577system.cpu0.toL2Bus.trans_dist::UpgradeResp 44708 # Transaction distribution 578system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution 579system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution 580system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution 581system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution 582system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes) 583system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395284 # Packet count per connected master and slave (bytes) 584system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 585system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) 586system.cpu0.toL2Bus.pkt_count::total 5764166 # Packet count per connected master and slave (bytes) 587system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140768632 # Cumulative packet size per connected master and slave (bytes) 588system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92116612 # Cumulative packet size per connected master and slave (bytes) 589system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 590system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) 591system.cpu0.toL2Bus.pkt_size::total 232968516 # Cumulative packet size per connected master and slave (bytes) 592system.cpu0.toL2Bus.snoops 623122 # Total snoops (count) 593system.cpu0.toL2Bus.snoop_fanout::samples 4318148 # Request fanout histogram 594system.cpu0.toL2Bus.snoop_fanout::mean 0.066969 # Request fanout histogram 595system.cpu0.toL2Bus.snoop_fanout::stdev 0.252635 # Request fanout histogram 596system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 597system.cpu0.toL2Bus.snoop_fanout::0 4031861 93.37% 93.37% # Request fanout histogram 598system.cpu0.toL2Bus.snoop_fanout::1 283393 6.56% 99.93% # Request fanout histogram 599system.cpu0.toL2Bus.snoop_fanout::2 2894 0.07% 100.00% # Request fanout histogram 600system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 601system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 602system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 603system.cpu0.toL2Bus.snoop_fanout::total 4318148 # Request fanout histogram 604system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 605system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 606system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 607system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 608system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 609system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 610system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 611system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 612system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 613system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 614system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 615system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 616system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 617system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 618system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 619system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 620system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 621system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 622system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 623system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 624system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 625system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 626system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 627system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 628system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 629system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 630system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 631system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 632system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 633system.cpu1.dtb.walker.walks 3358 # Table walker walks requested 634system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 635system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 636system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 637system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 638system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 639system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 640system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 641system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated 642system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated 643system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated 644system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst 645system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 646system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 647system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst 648system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 649system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst 650system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst 651system.cpu1.dtb.inst_hits 0 # ITB inst hits 652system.cpu1.dtb.inst_misses 0 # ITB inst misses 653system.cpu1.dtb.read_hits 12173916 # DTB read hits 654system.cpu1.dtb.read_misses 2852 # DTB read misses 655system.cpu1.dtb.write_hits 7587209 # DTB write hits 656system.cpu1.dtb.write_misses 506 # DTB write misses 657system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 658system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 659system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 660system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 661system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 662system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 663system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 664system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 665system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 666system.cpu1.dtb.read_accesses 12176768 # DTB read accesses 667system.cpu1.dtb.write_accesses 7587715 # DTB write accesses 668system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 669system.cpu1.dtb.hits 19761125 # DTB hits 670system.cpu1.dtb.misses 3358 # DTB misses 671system.cpu1.dtb.accesses 19764483 # DTB accesses 672system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 673system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 674system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 675system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 676system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 677system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 678system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 679system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 680system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 681system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 682system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 683system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 684system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 685system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 686system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 687system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 688system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 689system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 690system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 691system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 692system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 693system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 694system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 695system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 696system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 697system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 698system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 699system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 700system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 701system.cpu1.itb.walker.walks 1734 # Table walker walks requested 702system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 703system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 704system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 705system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 706system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 707system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 708system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 709system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 710system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 711system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 712system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 713system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 714system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 715system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 716system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 717system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 718system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 719system.cpu1.itb.inst_hits 53671575 # ITB inst hits 720system.cpu1.itb.inst_misses 1734 # ITB inst misses 721system.cpu1.itb.read_hits 0 # DTB read hits 722system.cpu1.itb.read_misses 0 # DTB read misses 723system.cpu1.itb.write_hits 0 # DTB write hits 724system.cpu1.itb.write_misses 0 # DTB write misses 725system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 726system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 727system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 728system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 729system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 730system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 731system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 732system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 733system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 734system.cpu1.itb.read_accesses 0 # DTB read accesses 735system.cpu1.itb.write_accesses 0 # DTB write accesses 736system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses 737system.cpu1.itb.hits 53671575 # DTB hits 738system.cpu1.itb.misses 1734 # DTB misses 739system.cpu1.itb.accesses 53673309 # DTB accesses 740system.cpu1.numCycles 5605320274 # number of cpu cycles simulated 741system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 742system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 743system.cpu1.kern.inst.arm 0 # number of arm instructions executed 744system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 745system.cpu1.committedInsts 51401314 # Number of instructions committed 746system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed 747system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses 748system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 749system.cpu1.num_func_calls 9170855 # number of times a function call or return occured 750system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls 751system.cpu1.num_int_insts 56984241 # number of integer instructions 752system.cpu1.num_fp_insts 1792 # number of float instructions 753system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read 754system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written 755system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 756system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 757system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read 758system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written 759system.cpu1.num_mem_refs 20026381 # number of memory refs 760system.cpu1.num_load_insts 12289537 # Number of load instructions 761system.cpu1.num_store_insts 7736844 # Number of store instructions 762system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles 763system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles 764system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 765system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 766system.cpu1.Branches 15217493 # Number of branches fetched 767system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 768system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction 769system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction 770system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 771system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 772system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 773system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 774system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 775system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 776system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 777system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 778system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 779system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 780system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 781system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 782system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 783system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 784system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 785system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 786system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 787system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 788system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 789system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 790system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 791system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 792system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 793system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 794system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 795system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 796system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 797system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction 798system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction 799system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 800system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 801system.cpu1.op_class::total 65459464 # Class of executed instruction 802system.cpu1.dcache.tags.replacements 191938 # number of replacements 803system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use 804system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. 805system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. 806system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks. 807system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 808system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor 809system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy 810system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy 811system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 812system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 813system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 814system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 815system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses 816system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses 817system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits 818system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits 819system.cpu1.dcache.WriteReq_hits::cpu1.data 7397500 # number of WriteReq hits 820system.cpu1.dcache.WriteReq_hits::total 7397500 # number of WriteReq hits 821system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits 822system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits 823system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 824system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 825system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits 826system.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits 827system.cpu1.dcache.demand_hits::cpu1.data 19256194 # number of demand (read+write) hits 828system.cpu1.dcache.demand_hits::total 19256194 # number of demand (read+write) hits 829system.cpu1.dcache.overall_hits::cpu1.data 19306293 # number of overall hits 830system.cpu1.dcache.overall_hits::total 19306293 # number of overall hits 831system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses 832system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses 833system.cpu1.dcache.WriteReq_misses::cpu1.data 92462 # number of WriteReq misses 834system.cpu1.dcache.WriteReq_misses::total 92462 # number of WriteReq misses 835system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses 836system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses 837system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 838system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 839system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses 840system.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses 841system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses 842system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses 843system.cpu1.dcache.overall_misses::cpu1.data 259811 # number of overall misses 844system.cpu1.dcache.overall_misses::total 259811 # number of overall misses 845system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) 846system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) 847system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) 848system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses) 849system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 850system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 851system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 852system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 853system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 854system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 855system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses 856system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses 857system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses 858system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses 859system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses 860system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses 861system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses 862system.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses 863system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses 864system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses 865system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 866system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 867system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237347 # miss rate for StoreCondReq accesses 868system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237347 # miss rate for StoreCondReq accesses 869system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 870system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 871system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 872system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 873system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 874system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 875system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 876system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 877system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 878system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 879system.cpu1.dcache.fast_writes 0 # number of fast writes performed 880system.cpu1.dcache.cache_copies 0 # number of cache copies performed 881system.cpu1.dcache.writebacks::writebacks 191938 # number of writebacks 882system.cpu1.dcache.writebacks::total 191938 # number of writebacks 883system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 884system.cpu1.icache.tags.replacements 523373 # number of replacements 885system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use 886system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks. 887system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. 888system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks. 889system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 890system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor 891system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 892system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 893system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 894system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 895system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 896system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 897system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses 898system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses 899system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits 900system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits 901system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits 902system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits 903system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits 904system.cpu1.icache.overall_hits::total 53148780 # number of overall hits 905system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses 906system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses 907system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses 908system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses 909system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses 910system.cpu1.icache.overall_misses::total 523885 # number of overall misses 911system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses) 912system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses) 913system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses 914system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses 915system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses 916system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses 917system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 918system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 919system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 920system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 921system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 922system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 923system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 924system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 925system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 926system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 927system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 928system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 929system.cpu1.icache.fast_writes 0 # number of fast writes performed 930system.cpu1.icache.cache_copies 0 # number of cache copies performed 931system.cpu1.icache.writebacks::writebacks 523373 # number of writebacks 932system.cpu1.icache.writebacks::total 523373 # number of writebacks 933system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 934system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 935system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 936system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 937system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 938system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 939system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 940system.cpu1.l2cache.tags.replacements 47555 # number of replacements 941system.cpu1.l2cache.tags.tagsinuse 15235.297156 # Cycle average of tags in use 942system.cpu1.l2cache.tags.total_refs 1184961 # Total number of references to valid blocks. 943system.cpu1.l2cache.tags.sampled_refs 62593 # Sample count of references to valid blocks. 944system.cpu1.l2cache.tags.avg_refs 18.931206 # Average number of references to valid blocks. 945system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 946system.cpu1.l2cache.tags.occ_blocks::writebacks 15230.950549 # Average occupied blocks per requestor 947system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.335617 # Average occupied blocks per requestor 948system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010990 # Average occupied blocks per requestor 949system.cpu1.l2cache.tags.occ_percent::writebacks 0.929623 # Average percentage of cache occupancy 950system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy 951system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 952system.cpu1.l2cache.tags.occ_percent::total 0.929889 # Average percentage of cache occupancy 953system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 954system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15019 # Occupied blocks per task id 955system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 956system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 957system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 958system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 530 # Occupied blocks per task id 959system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9526 # Occupied blocks per task id 960system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4963 # Occupied blocks per task id 961system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id 962system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.916687 # Percentage of cache occupancy per task id 963system.cpu1.l2cache.tags.tag_accesses 24500378 # Number of tag accesses 964system.cpu1.l2cache.tags.data_accesses 24500378 # Number of data accesses 965system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits 966system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1913 # number of ReadReq hits 967system.cpu1.l2cache.ReadReq_hits::total 5534 # number of ReadReq hits 968system.cpu1.l2cache.WritebackDirty_hits::writebacks 121109 # number of WritebackDirty hits 969system.cpu1.l2cache.WritebackDirty_hits::total 121109 # number of WritebackDirty hits 970system.cpu1.l2cache.WritebackClean_hits::writebacks 583044 # number of WritebackClean hits 971system.cpu1.l2cache.WritebackClean_hits::total 583044 # number of WritebackClean hits 972system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19763 # number of ReadExReq hits 973system.cpu1.l2cache.ReadExReq_hits::total 19763 # number of ReadExReq hits 974system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510346 # number of ReadCleanReq hits 975system.cpu1.l2cache.ReadCleanReq_hits::total 510346 # number of ReadCleanReq hits 976system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99093 # number of ReadSharedReq hits 977system.cpu1.l2cache.ReadSharedReq_hits::total 99093 # number of ReadSharedReq hits 978system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits 979system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1913 # number of demand (read+write) hits 980system.cpu1.l2cache.demand_hits::cpu1.inst 510346 # number of demand (read+write) hits 981system.cpu1.l2cache.demand_hits::cpu1.data 118856 # number of demand (read+write) hits 982system.cpu1.l2cache.demand_hits::total 634736 # number of demand (read+write) hits 983system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits 984system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1913 # number of overall hits 985system.cpu1.l2cache.overall_hits::cpu1.inst 510346 # number of overall hits 986system.cpu1.l2cache.overall_hits::cpu1.data 118856 # number of overall hits 987system.cpu1.l2cache.overall_hits::total 634736 # number of overall hits 988system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses 989system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses 990system.cpu1.l2cache.ReadReq_misses::total 607 # number of ReadReq misses 991system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses 992system.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses 993system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses 994system.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses 995system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43853 # number of ReadExReq misses 996system.cpu1.l2cache.ReadExReq_misses::total 43853 # number of ReadExReq misses 997system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13539 # number of ReadCleanReq misses 998system.cpu1.l2cache.ReadCleanReq_misses::total 13539 # number of ReadCleanReq misses 999system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73574 # number of ReadSharedReq misses 1000system.cpu1.l2cache.ReadSharedReq_misses::total 73574 # number of ReadSharedReq misses 1001system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses 1002system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses 1003system.cpu1.l2cache.demand_misses::cpu1.inst 13539 # number of demand (read+write) misses 1004system.cpu1.l2cache.demand_misses::cpu1.data 117427 # number of demand (read+write) misses 1005system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses 1006system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses 1007system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses 1008system.cpu1.l2cache.overall_misses::cpu1.inst 13539 # number of overall misses 1009system.cpu1.l2cache.overall_misses::cpu1.data 117427 # number of overall misses 1010system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses 1011system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3957 # number of ReadReq accesses(hits+misses) 1012system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2184 # number of ReadReq accesses(hits+misses) 1013system.cpu1.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) 1014system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121109 # number of WritebackDirty accesses(hits+misses) 1015system.cpu1.l2cache.WritebackDirty_accesses::total 121109 # number of WritebackDirty accesses(hits+misses) 1016system.cpu1.l2cache.WritebackClean_accesses::writebacks 583044 # number of WritebackClean accesses(hits+misses) 1017system.cpu1.l2cache.WritebackClean_accesses::total 583044 # number of WritebackClean accesses(hits+misses) 1018system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses) 1019system.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses) 1020system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) 1021system.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses) 1022system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) 1023system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) 1024system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 # number of ReadCleanReq accesses(hits+misses) 1025system.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses) 1026system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172667 # number of ReadSharedReq accesses(hits+misses) 1027system.cpu1.l2cache.ReadSharedReq_accesses::total 172667 # number of ReadSharedReq accesses(hits+misses) 1028system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3957 # number of demand (read+write) accesses 1029system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2184 # number of demand (read+write) accesses 1030system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses 1031system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses 1032system.cpu1.l2cache.demand_accesses::total 766309 # number of demand (read+write) accesses 1033system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3957 # number of overall (read+write) accesses 1034system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2184 # number of overall (read+write) accesses 1035system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses 1036system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses 1037system.cpu1.l2cache.overall_accesses::total 766309 # number of overall (read+write) accesses 1038system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for ReadReq accesses 1039system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124084 # miss rate for ReadReq accesses 1040system.cpu1.l2cache.ReadReq_miss_rate::total 0.098844 # miss rate for ReadReq accesses 1041system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1042system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1043system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1044system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1045system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689339 # miss rate for ReadExReq accesses 1046system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689339 # miss rate for ReadExReq accesses 1047system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025843 # miss rate for ReadCleanReq accesses 1048system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025843 # miss rate for ReadCleanReq accesses 1049system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.426103 # miss rate for ReadSharedReq accesses 1050system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.426103 # miss rate for ReadSharedReq accesses 1051system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for demand accesses 1052system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124084 # miss rate for demand accesses 1053system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025843 # miss rate for demand accesses 1054system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496976 # miss rate for demand accesses 1055system.cpu1.l2cache.demand_miss_rate::total 0.171697 # miss rate for demand accesses 1056system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for overall accesses 1057system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124084 # miss rate for overall accesses 1058system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025843 # miss rate for overall accesses 1059system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496976 # miss rate for overall accesses 1060system.cpu1.l2cache.overall_miss_rate::total 0.171697 # miss rate for overall accesses 1061system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1062system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1063system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1064system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1065system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1066system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1067system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1068system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1069system.cpu1.l2cache.writebacks::writebacks 32818 # number of writebacks 1070system.cpu1.l2cache.writebacks::total 32818 # number of writebacks 1071system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1072system.cpu1.toL2Bus.snoop_filter.tot_requests 1533421 # Total number of requests made to the snoop filter. 1073system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773256 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1074system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1075system.cpu1.toL2Bus.snoop_filter.tot_snoops 165978 # Total number of snoops made to the snoop filter. 1076system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164041 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1077system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1078system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution 1079system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution 1080system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 1081system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 1082system.cpu1.toL2Bus.trans_dist::WritebackDirty 121109 # Transaction distribution 1083system.cpu1.toL2Bus.trans_dist::WritebackClean 583044 # Transaction distribution 1084system.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution 1085system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution 1086system.cpu1.toL2Bus.trans_dist::UpgradeResp 51389 # Transaction distribution 1087system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution 1088system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution 1089system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution 1090system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution 1091system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes) 1092system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776509 # Packet count per connected master and slave (bytes) 1093system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 1094system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) 1095system.cpu1.toL2Bus.pkt_count::total 2357775 # Packet count per connected master and slave (bytes) 1096system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66454020 # Cumulative packet size per connected master and slave (bytes) 1097system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27282414 # Cumulative packet size per connected master and slave (bytes) 1098system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 1099system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) 1100system.cpu1.toL2Bus.pkt_size::total 93773822 # Cumulative packet size per connected master and slave (bytes) 1101system.cpu1.toL2Bus.snoops 347349 # Total snoops (count) 1102system.cpu1.toL2Bus.snoop_fanout::samples 1819817 # Request fanout histogram 1103system.cpu1.toL2Bus.snoop_fanout::mean 0.108136 # Request fanout histogram 1104system.cpu1.toL2Bus.snoop_fanout::stdev 0.313960 # Request fanout histogram 1105system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1106system.cpu1.toL2Bus.snoop_fanout::0 1624967 89.29% 89.29% # Request fanout histogram 1107system.cpu1.toL2Bus.snoop_fanout::1 192913 10.60% 99.89% # Request fanout histogram 1108system.cpu1.toL2Bus.snoop_fanout::2 1937 0.11% 100.00% # Request fanout histogram 1109system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1110system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1111system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1112system.cpu1.toL2Bus.snoop_fanout::total 1819817 # Request fanout histogram 1113system.iobus.trans_dist::ReadReq 30995 # Transaction distribution 1114system.iobus.trans_dist::ReadResp 30995 # Transaction distribution 1115system.iobus.trans_dist::WriteReq 59419 # Transaction distribution 1116system.iobus.trans_dist::WriteResp 59419 # Transaction distribution 1117system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 1118system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
	1119system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1119system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1120system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1121system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 1122system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 1123system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1124system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1125system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1126system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1127system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1128system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1129system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1130system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1131system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1132system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1133system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)	1120system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1121system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1122system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 1123system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 1124system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1125system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1126system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1127system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1128system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1129system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1130system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1131system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1132system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1133system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1134system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
1134system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1135system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)	1135system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
1136system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1137system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1138system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 1139system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 1140system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 1141system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 1142system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 1143system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)	1136system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 1137system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 1138system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 1139system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 1140system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 1141system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
	1142system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
1144system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1145system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1146system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 1147system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 1148system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1149system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1150system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1151system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1152system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1153system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1154system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1155system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1156system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1157system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1158system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)	1143system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1144system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1145system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 1146system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 1147system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1148system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1149system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1150system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1151system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1152system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1153system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1154system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1155system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1156system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1157system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1159system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
1160system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)	1158system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1161system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1162system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1163system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 1164system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 1165system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 1166system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 1167system.iocache.tags.replacements 36442 # number of replacements 1168system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use 1169system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1170system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1171system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1172system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. 1173system.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor 1174system.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy 1175system.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy 1176system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1177system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1178system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1179system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1180system.iocache.tags.data_accesses 328284 # Number of data accesses 1181system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1182system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 1183system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1184system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1185system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 1186system.iocache.demand_misses::total 252 # number of demand (read+write) misses 1187system.iocache.overall_misses::realview.ide 252 # number of overall misses 1188system.iocache.overall_misses::total 252 # number of overall misses 1189system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 1190system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 1191system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1192system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1193system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 1194system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 1195system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 1196system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 1197system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1198system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1199system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1200system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1201system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1202system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1203system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1204system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1205system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1206system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1207system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1208system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1209system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1210system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1211system.iocache.fast_writes 0 # number of fast writes performed 1212system.iocache.cache_copies 0 # number of cache copies performed 1213system.iocache.writebacks::writebacks 36190 # number of writebacks 1214system.iocache.writebacks::total 36190 # number of writebacks 1215system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1216system.l2c.tags.replacements 107037 # number of replacements 1217system.l2c.tags.tagsinuse 62176.956554 # Cycle average of tags in use 1218system.l2c.tags.total_refs 241620 # Total number of references to valid blocks. 1219system.l2c.tags.sampled_refs 167464 # Sample count of references to valid blocks. 1220system.l2c.tags.avg_refs 1.442818 # Average number of references to valid blocks. 1221system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1222system.l2c.tags.occ_blocks::writebacks 47954.224141 # Average occupied blocks per requestor 1223system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010653 # Average occupied blocks per requestor 1224system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030815 # Average occupied blocks per requestor 1225system.l2c.tags.occ_blocks::cpu0.inst 7778.474758 # Average occupied blocks per requestor 1226system.l2c.tags.occ_blocks::cpu0.data 4056.241083 # Average occupied blocks per requestor 1227system.l2c.tags.occ_blocks::cpu1.inst 1664.556464 # Average occupied blocks per requestor 1228system.l2c.tags.occ_blocks::cpu1.data 718.418639 # Average occupied blocks per requestor 1229system.l2c.tags.occ_percent::writebacks 0.731723 # Average percentage of cache occupancy 1230system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy 1231system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 1232system.l2c.tags.occ_percent::cpu0.inst 0.118690 # Average percentage of cache occupancy 1233system.l2c.tags.occ_percent::cpu0.data 0.061893 # Average percentage of cache occupancy 1234system.l2c.tags.occ_percent::cpu1.inst 0.025399 # Average percentage of cache occupancy 1235system.l2c.tags.occ_percent::cpu1.data 0.010962 # Average percentage of cache occupancy 1236system.l2c.tags.occ_percent::total 0.948745 # Average percentage of cache occupancy 1237system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1238system.l2c.tags.occ_task_id_blocks::1024 60421 # Occupied blocks per task id 1239system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1240system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 1241system.l2c.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 1242system.l2c.tags.age_task_id_blocks_1024::2 1839 # Occupied blocks per task id 1243system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id 1244system.l2c.tags.age_task_id_blocks_1024::4 45269 # Occupied blocks per task id 1245system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 1246system.l2c.tags.occ_task_id_percent::1024 0.921951 # Percentage of cache occupancy per task id 1247system.l2c.tags.tag_accesses 5183068 # Number of tag accesses 1248system.l2c.tags.data_accesses 5183068 # Number of data accesses 1249system.l2c.WritebackDirty_hits::writebacks 225729 # number of WritebackDirty hits 1250system.l2c.WritebackDirty_hits::total 225729 # number of WritebackDirty hits 1251system.l2c.UpgradeReq_hits::cpu0.data 511 # number of UpgradeReq hits 1252system.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits 1253system.l2c.UpgradeReq_hits::total 575 # number of UpgradeReq hits 1254system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits 1255system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits 1256system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits 1257system.l2c.ReadExReq_hits::cpu0.data 13894 # number of ReadExReq hits 1258system.l2c.ReadExReq_hits::cpu1.data 3132 # number of ReadExReq hits 1259system.l2c.ReadExReq_hits::total 17026 # number of ReadExReq hits 1260system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 74 # number of ReadSharedReq hits 1261system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits 1262system.l2c.ReadSharedReq_hits::cpu0.inst 24882 # number of ReadSharedReq hits 1263system.l2c.ReadSharedReq_hits::cpu0.data 76059 # number of ReadSharedReq hits 1264system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits 1265system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits 1266system.l2c.ReadSharedReq_hits::cpu1.inst 11145 # number of ReadSharedReq hits 1267system.l2c.ReadSharedReq_hits::cpu1.data 11759 # number of ReadSharedReq hits 1268system.l2c.ReadSharedReq_hits::total 124050 # number of ReadSharedReq hits 1269system.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits 1270system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits 1271system.l2c.demand_hits::cpu0.inst 24882 # number of demand (read+write) hits 1272system.l2c.demand_hits::cpu0.data 89953 # number of demand (read+write) hits 1273system.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits 1274system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits 1275system.l2c.demand_hits::cpu1.inst 11145 # number of demand (read+write) hits 1276system.l2c.demand_hits::cpu1.data 14891 # number of demand (read+write) hits 1277system.l2c.demand_hits::total 141076 # number of demand (read+write) hits 1278system.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits 1279system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits 1280system.l2c.overall_hits::cpu0.inst 24882 # number of overall hits 1281system.l2c.overall_hits::cpu0.data 89953 # number of overall hits 1282system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits 1283system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits 1284system.l2c.overall_hits::cpu1.inst 11145 # number of overall hits 1285system.l2c.overall_hits::cpu1.data 14891 # number of overall hits 1286system.l2c.overall_hits::total 141076 # number of overall hits 1287system.l2c.UpgradeReq_misses::cpu0.data 10043 # number of UpgradeReq misses 1288system.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses 1289system.l2c.UpgradeReq_misses::total 13338 # number of UpgradeReq misses 1290system.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses 1291system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses 1292system.l2c.SCUpgradeReq_misses::total 1932 # number of SCUpgradeReq misses 1293system.l2c.ReadExReq_misses::cpu0.data 136525 # number of ReadExReq misses 1294system.l2c.ReadExReq_misses::cpu1.data 15837 # number of ReadExReq misses 1295system.l2c.ReadExReq_misses::total 152362 # number of ReadExReq misses 1296system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses 1297system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 1298system.l2c.ReadSharedReq_misses::cpu0.inst 16761 # number of ReadSharedReq misses 1299system.l2c.ReadSharedReq_misses::cpu0.data 11173 # number of ReadSharedReq misses 1300system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses 1301system.l2c.ReadSharedReq_misses::cpu1.data 1126 # number of ReadSharedReq misses 1302system.l2c.ReadSharedReq_misses::total 31464 # number of ReadSharedReq misses 1303system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 1304system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 1305system.l2c.demand_misses::cpu0.inst 16761 # number of demand (read+write) misses 1306system.l2c.demand_misses::cpu0.data 147698 # number of demand (read+write) misses 1307system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses 1308system.l2c.demand_misses::cpu1.data 16963 # number of demand (read+write) misses 1309system.l2c.demand_misses::total 183826 # number of demand (read+write) misses 1310system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 1311system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 1312system.l2c.overall_misses::cpu0.inst 16761 # number of overall misses 1313system.l2c.overall_misses::cpu0.data 147698 # number of overall misses 1314system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses 1315system.l2c.overall_misses::cpu1.data 16963 # number of overall misses 1316system.l2c.overall_misses::total 183826 # number of overall misses 1317system.l2c.WritebackDirty_accesses::writebacks 225729 # number of WritebackDirty accesses(hits+misses) 1318system.l2c.WritebackDirty_accesses::total 225729 # number of WritebackDirty accesses(hits+misses) 1319system.l2c.UpgradeReq_accesses::cpu0.data 10554 # number of UpgradeReq accesses(hits+misses) 1320system.l2c.UpgradeReq_accesses::cpu1.data 3359 # number of UpgradeReq accesses(hits+misses) 1321system.l2c.UpgradeReq_accesses::total 13913 # number of UpgradeReq accesses(hits+misses) 1322system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses) 1323system.l2c.SCUpgradeReq_accesses::cpu1.data 1185 # number of SCUpgradeReq accesses(hits+misses) 1324system.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses) 1325system.l2c.ReadExReq_accesses::cpu0.data 150419 # number of ReadExReq accesses(hits+misses) 1326system.l2c.ReadExReq_accesses::cpu1.data 18969 # number of ReadExReq accesses(hits+misses) 1327system.l2c.ReadExReq_accesses::total 169388 # number of ReadExReq accesses(hits+misses) 1328system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 82 # number of ReadSharedReq accesses(hits+misses) 1329system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 70 # number of ReadSharedReq accesses(hits+misses) 1330system.l2c.ReadSharedReq_accesses::cpu0.inst 41643 # number of ReadSharedReq accesses(hits+misses) 1331system.l2c.ReadSharedReq_accesses::cpu0.data 87232 # number of ReadSharedReq accesses(hits+misses) 1332system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) 1333system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 27 # number of ReadSharedReq accesses(hits+misses) 1334system.l2c.ReadSharedReq_accesses::cpu1.inst 13539 # number of ReadSharedReq accesses(hits+misses) 1335system.l2c.ReadSharedReq_accesses::cpu1.data 12885 # number of ReadSharedReq accesses(hits+misses) 1336system.l2c.ReadSharedReq_accesses::total 155514 # number of ReadSharedReq accesses(hits+misses) 1337system.l2c.demand_accesses::cpu0.dtb.walker 82 # number of demand (read+write) accesses 1338system.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses 1339system.l2c.demand_accesses::cpu0.inst 41643 # number of demand (read+write) accesses 1340system.l2c.demand_accesses::cpu0.data 237651 # number of demand (read+write) accesses 1341system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses 1342system.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses 1343system.l2c.demand_accesses::cpu1.inst 13539 # number of demand (read+write) accesses 1344system.l2c.demand_accesses::cpu1.data 31854 # number of demand (read+write) accesses 1345system.l2c.demand_accesses::total 324902 # number of demand (read+write) accesses 1346system.l2c.overall_accesses::cpu0.dtb.walker 82 # number of overall (read+write) accesses 1347system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses 1348system.l2c.overall_accesses::cpu0.inst 41643 # number of overall (read+write) accesses 1349system.l2c.overall_accesses::cpu0.data 237651 # number of overall (read+write) accesses 1350system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses 1351system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses 1352system.l2c.overall_accesses::cpu1.inst 13539 # number of overall (read+write) accesses 1353system.l2c.overall_accesses::cpu1.data 31854 # number of overall (read+write) accesses 1354system.l2c.overall_accesses::total 324902 # number of overall (read+write) accesses 1355system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951582 # miss rate for UpgradeReq accesses 1356system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980947 # miss rate for UpgradeReq accesses 1357system.l2c.UpgradeReq_miss_rate::total 0.958672 # miss rate for UpgradeReq accesses 1358system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920635 # miss rate for SCUpgradeReq accesses 1359system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994093 # miss rate for SCUpgradeReq accesses 1360system.l2c.SCUpgradeReq_miss_rate::total 0.964072 # miss rate for SCUpgradeReq accesses 1361system.l2c.ReadExReq_miss_rate::cpu0.data 0.907631 # miss rate for ReadExReq accesses 1362system.l2c.ReadExReq_miss_rate::cpu1.data 0.834889 # miss rate for ReadExReq accesses 1363system.l2c.ReadExReq_miss_rate::total 0.899485 # miss rate for ReadExReq accesses 1364system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for ReadSharedReq accesses 1365system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028571 # miss rate for ReadSharedReq accesses 1366system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402493 # miss rate for ReadSharedReq accesses 1367system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128084 # miss rate for ReadSharedReq accesses 1368system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176823 # miss rate for ReadSharedReq accesses 1369system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087388 # miss rate for ReadSharedReq accesses 1370system.l2c.ReadSharedReq_miss_rate::total 0.202323 # miss rate for ReadSharedReq accesses 1371system.l2c.demand_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for demand accesses 1372system.l2c.demand_miss_rate::cpu0.itb.walker 0.028571 # miss rate for demand accesses 1373system.l2c.demand_miss_rate::cpu0.inst 0.402493 # miss rate for demand accesses 1374system.l2c.demand_miss_rate::cpu0.data 0.621491 # miss rate for demand accesses 1375system.l2c.demand_miss_rate::cpu1.inst 0.176823 # miss rate for demand accesses 1376system.l2c.demand_miss_rate::cpu1.data 0.532523 # miss rate for demand accesses 1377system.l2c.demand_miss_rate::total 0.565789 # miss rate for demand accesses 1378system.l2c.overall_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for overall accesses 1379system.l2c.overall_miss_rate::cpu0.itb.walker 0.028571 # miss rate for overall accesses 1380system.l2c.overall_miss_rate::cpu0.inst 0.402493 # miss rate for overall accesses 1381system.l2c.overall_miss_rate::cpu0.data 0.621491 # miss rate for overall accesses 1382system.l2c.overall_miss_rate::cpu1.inst 0.176823 # miss rate for overall accesses 1383system.l2c.overall_miss_rate::cpu1.data 0.532523 # miss rate for overall accesses 1384system.l2c.overall_miss_rate::total 0.565789 # miss rate for overall accesses 1385system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1386system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1387system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1388system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1389system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1390system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1391system.l2c.fast_writes 0 # number of fast writes performed 1392system.l2c.cache_copies 0 # number of cache copies performed 1393system.l2c.writebacks::writebacks 95877 # number of writebacks 1394system.l2c.writebacks::total 95877 # number of writebacks 1395system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1396system.membus.trans_dist::ReadReq 43996 # Transaction distribution 1397system.membus.trans_dist::ReadResp 75712 # Transaction distribution 1398system.membus.trans_dist::WriteReq 30846 # Transaction distribution 1399system.membus.trans_dist::WriteResp 30846 # Transaction distribution 1400system.membus.trans_dist::WritebackDirty 132067 # Transaction distribution 1401system.membus.trans_dist::CleanEvict 8465 # Transaction distribution 1402system.membus.trans_dist::UpgradeReq 60519 # Transaction distribution 1403system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution 1404system.membus.trans_dist::UpgradeResp 15741 # Transaction distribution 1405system.membus.trans_dist::ReadExReq 196031 # Transaction distribution 1406system.membus.trans_dist::ReadExResp 151891 # Transaction distribution 1407system.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution 1408system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1409system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1410system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 1411system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 1412system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 1413system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660645 # Packet count per connected master and slave (bytes) 1414system.membus.pkt_count_system.l2c.mem_side::total 782029 # Packet count per connected master and slave (bytes) 1415system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes) 1416system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes) 1417system.membus.pkt_count::total 891184 # Packet count per connected master and slave (bytes) 1418system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 1419system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 1420system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 1421system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17927560 # Cumulative packet size per connected master and slave (bytes) 1422system.membus.pkt_size_system.l2c.mem_side::total 18117342 # Cumulative packet size per connected master and slave (bytes) 1423system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 1424system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 1425system.membus.pkt_size::total 20449630 # Cumulative packet size per connected master and slave (bytes) 1426system.membus.snoops 0 # Total snoops (count) 1427system.membus.snoop_fanout::samples 581009 # Request fanout histogram 1428system.membus.snoop_fanout::mean 1 # Request fanout histogram 1429system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1430system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1431system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1432system.membus.snoop_fanout::1 581009 100.00% 100.00% # Request fanout histogram 1433system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1434system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1435system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1436system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1437system.membus.snoop_fanout::total 581009 # Request fanout histogram 1438system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1439system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1440system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1441system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1442system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1443system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1444system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1445system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1446system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1447system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1448system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1449system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1450system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1451system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1452system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1453system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1454system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1455system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1456system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1457system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1458system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1459system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1460system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1461system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1462system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1463system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1464system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1465system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1466system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1467system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1468system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1469system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1470system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1471system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1472system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1473system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1474system.realview.ethernet.droppedPackets 0 # number of packets dropped 1475system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1476system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1477system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1478system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1479system.toL2Bus.snoop_filter.tot_requests 863003 # Total number of requests made to the snoop filter. 1480system.toL2Bus.snoop_filter.hit_single_requests 444472 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1481system.toL2Bus.snoop_filter.hit_multi_requests 128485 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1482system.toL2Bus.snoop_filter.tot_snoops 9552 # Total number of snoops made to the snoop filter. 1483system.toL2Bus.snoop_filter.hit_single_snoops 9071 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1484system.toL2Bus.snoop_filter.hit_multi_snoops 481 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1485system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution 1486system.toL2Bus.trans_dist::ReadResp 301629 # Transaction distribution 1487system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 1488system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 1489system.toL2Bus.trans_dist::WritebackDirty 225729 # Transaction distribution 1490system.toL2Bus.trans_dist::CleanEvict 38612 # Transaction distribution 1491system.toL2Bus.trans_dist::UpgradeReq 60623 # Transaction distribution 1492system.toL2Bus.trans_dist::SCUpgradeReq 40978 # Transaction distribution 1493system.toL2Bus.trans_dist::UpgradeResp 101601 # Transaction distribution 1494system.toL2Bus.trans_dist::ReadExReq 213528 # Transaction distribution 1495system.toL2Bus.trans_dist::ReadExResp 213528 # Transaction distribution 1496system.toL2Bus.trans_dist::ReadSharedReq 257629 # Transaction distribution 1497system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1143706 # Packet count per connected master and slave (bytes) 1498system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 415843 # Packet count per connected master and slave (bytes) 1499system.toL2Bus.pkt_count::total 1559549 # Packet count per connected master and slave (bytes) 1500system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34428348 # Cumulative packet size per connected master and slave (bytes) 1501system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10418866 # Cumulative packet size per connected master and slave (bytes) 1502system.toL2Bus.pkt_size::total 44847214 # Cumulative packet size per connected master and slave (bytes) 1503system.toL2Bus.snoops 180208 # Total snoops (count) 1504system.toL2Bus.snoop_fanout::samples 1117804 # Request fanout histogram 1505system.toL2Bus.snoop_fanout::mean 0.282168 # Request fanout histogram 1506system.toL2Bus.snoop_fanout::stdev 0.451010 # Request fanout histogram 1507system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1508system.toL2Bus.snoop_fanout::0 802876 71.83% 71.83% # Request fanout histogram 1509system.toL2Bus.snoop_fanout::1 314447 28.13% 99.96% # Request fanout histogram 1510system.toL2Bus.snoop_fanout::2 481 0.04% 100.00% # Request fanout histogram 1511system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1512system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1513system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1514system.toL2Bus.snoop_fanout::total 1117804 # Request fanout histogram 1515 1516---------- End Simulation Statistics ----------	1159system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 1160system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 1161system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 1162system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 1163system.iocache.tags.replacements 36442 # number of replacements 1164system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use 1165system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1166system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1167system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1168system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. 1169system.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor 1170system.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy 1171system.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy 1172system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1173system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1174system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1175system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1176system.iocache.tags.data_accesses 328284 # Number of data accesses 1177system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1178system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 1179system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1180system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1181system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 1182system.iocache.demand_misses::total 252 # number of demand (read+write) misses 1183system.iocache.overall_misses::realview.ide 252 # number of overall misses 1184system.iocache.overall_misses::total 252 # number of overall misses 1185system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 1186system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 1187system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1188system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1189system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 1190system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 1191system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 1192system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 1193system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1194system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1195system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1196system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1197system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1198system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1199system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1200system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1201system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1202system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1203system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1204system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1205system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1206system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1207system.iocache.fast_writes 0 # number of fast writes performed 1208system.iocache.cache_copies 0 # number of cache copies performed 1209system.iocache.writebacks::writebacks 36190 # number of writebacks 1210system.iocache.writebacks::total 36190 # number of writebacks 1211system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1212system.l2c.tags.replacements 107037 # number of replacements 1213system.l2c.tags.tagsinuse 62176.956554 # Cycle average of tags in use 1214system.l2c.tags.total_refs 241620 # Total number of references to valid blocks. 1215system.l2c.tags.sampled_refs 167464 # Sample count of references to valid blocks. 1216system.l2c.tags.avg_refs 1.442818 # Average number of references to valid blocks. 1217system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1218system.l2c.tags.occ_blocks::writebacks 47954.224141 # Average occupied blocks per requestor 1219system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010653 # Average occupied blocks per requestor 1220system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030815 # Average occupied blocks per requestor 1221system.l2c.tags.occ_blocks::cpu0.inst 7778.474758 # Average occupied blocks per requestor 1222system.l2c.tags.occ_blocks::cpu0.data 4056.241083 # Average occupied blocks per requestor 1223system.l2c.tags.occ_blocks::cpu1.inst 1664.556464 # Average occupied blocks per requestor 1224system.l2c.tags.occ_blocks::cpu1.data 718.418639 # Average occupied blocks per requestor 1225system.l2c.tags.occ_percent::writebacks 0.731723 # Average percentage of cache occupancy 1226system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy 1227system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 1228system.l2c.tags.occ_percent::cpu0.inst 0.118690 # Average percentage of cache occupancy 1229system.l2c.tags.occ_percent::cpu0.data 0.061893 # Average percentage of cache occupancy 1230system.l2c.tags.occ_percent::cpu1.inst 0.025399 # Average percentage of cache occupancy 1231system.l2c.tags.occ_percent::cpu1.data 0.010962 # Average percentage of cache occupancy 1232system.l2c.tags.occ_percent::total 0.948745 # Average percentage of cache occupancy 1233system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1234system.l2c.tags.occ_task_id_blocks::1024 60421 # Occupied blocks per task id 1235system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1236system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 1237system.l2c.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 1238system.l2c.tags.age_task_id_blocks_1024::2 1839 # Occupied blocks per task id 1239system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id 1240system.l2c.tags.age_task_id_blocks_1024::4 45269 # Occupied blocks per task id 1241system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 1242system.l2c.tags.occ_task_id_percent::1024 0.921951 # Percentage of cache occupancy per task id 1243system.l2c.tags.tag_accesses 5183068 # Number of tag accesses 1244system.l2c.tags.data_accesses 5183068 # Number of data accesses 1245system.l2c.WritebackDirty_hits::writebacks 225729 # number of WritebackDirty hits 1246system.l2c.WritebackDirty_hits::total 225729 # number of WritebackDirty hits 1247system.l2c.UpgradeReq_hits::cpu0.data 511 # number of UpgradeReq hits 1248system.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits 1249system.l2c.UpgradeReq_hits::total 575 # number of UpgradeReq hits 1250system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits 1251system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits 1252system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits 1253system.l2c.ReadExReq_hits::cpu0.data 13894 # number of ReadExReq hits 1254system.l2c.ReadExReq_hits::cpu1.data 3132 # number of ReadExReq hits 1255system.l2c.ReadExReq_hits::total 17026 # number of ReadExReq hits 1256system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 74 # number of ReadSharedReq hits 1257system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits 1258system.l2c.ReadSharedReq_hits::cpu0.inst 24882 # number of ReadSharedReq hits 1259system.l2c.ReadSharedReq_hits::cpu0.data 76059 # number of ReadSharedReq hits 1260system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits 1261system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits 1262system.l2c.ReadSharedReq_hits::cpu1.inst 11145 # number of ReadSharedReq hits 1263system.l2c.ReadSharedReq_hits::cpu1.data 11759 # number of ReadSharedReq hits 1264system.l2c.ReadSharedReq_hits::total 124050 # number of ReadSharedReq hits 1265system.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits 1266system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits 1267system.l2c.demand_hits::cpu0.inst 24882 # number of demand (read+write) hits 1268system.l2c.demand_hits::cpu0.data 89953 # number of demand (read+write) hits 1269system.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits 1270system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits 1271system.l2c.demand_hits::cpu1.inst 11145 # number of demand (read+write) hits 1272system.l2c.demand_hits::cpu1.data 14891 # number of demand (read+write) hits 1273system.l2c.demand_hits::total 141076 # number of demand (read+write) hits 1274system.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits 1275system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits 1276system.l2c.overall_hits::cpu0.inst 24882 # number of overall hits 1277system.l2c.overall_hits::cpu0.data 89953 # number of overall hits 1278system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits 1279system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits 1280system.l2c.overall_hits::cpu1.inst 11145 # number of overall hits 1281system.l2c.overall_hits::cpu1.data 14891 # number of overall hits 1282system.l2c.overall_hits::total 141076 # number of overall hits 1283system.l2c.UpgradeReq_misses::cpu0.data 10043 # number of UpgradeReq misses 1284system.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses 1285system.l2c.UpgradeReq_misses::total 13338 # number of UpgradeReq misses 1286system.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses 1287system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses 1288system.l2c.SCUpgradeReq_misses::total 1932 # number of SCUpgradeReq misses 1289system.l2c.ReadExReq_misses::cpu0.data 136525 # number of ReadExReq misses 1290system.l2c.ReadExReq_misses::cpu1.data 15837 # number of ReadExReq misses 1291system.l2c.ReadExReq_misses::total 152362 # number of ReadExReq misses 1292system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses 1293system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 1294system.l2c.ReadSharedReq_misses::cpu0.inst 16761 # number of ReadSharedReq misses 1295system.l2c.ReadSharedReq_misses::cpu0.data 11173 # number of ReadSharedReq misses 1296system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses 1297system.l2c.ReadSharedReq_misses::cpu1.data 1126 # number of ReadSharedReq misses 1298system.l2c.ReadSharedReq_misses::total 31464 # number of ReadSharedReq misses 1299system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 1300system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 1301system.l2c.demand_misses::cpu0.inst 16761 # number of demand (read+write) misses 1302system.l2c.demand_misses::cpu0.data 147698 # number of demand (read+write) misses 1303system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses 1304system.l2c.demand_misses::cpu1.data 16963 # number of demand (read+write) misses 1305system.l2c.demand_misses::total 183826 # number of demand (read+write) misses 1306system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 1307system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 1308system.l2c.overall_misses::cpu0.inst 16761 # number of overall misses 1309system.l2c.overall_misses::cpu0.data 147698 # number of overall misses 1310system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses 1311system.l2c.overall_misses::cpu1.data 16963 # number of overall misses 1312system.l2c.overall_misses::total 183826 # number of overall misses 1313system.l2c.WritebackDirty_accesses::writebacks 225729 # number of WritebackDirty accesses(hits+misses) 1314system.l2c.WritebackDirty_accesses::total 225729 # number of WritebackDirty accesses(hits+misses) 1315system.l2c.UpgradeReq_accesses::cpu0.data 10554 # number of UpgradeReq accesses(hits+misses) 1316system.l2c.UpgradeReq_accesses::cpu1.data 3359 # number of UpgradeReq accesses(hits+misses) 1317system.l2c.UpgradeReq_accesses::total 13913 # number of UpgradeReq accesses(hits+misses) 1318system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses) 1319system.l2c.SCUpgradeReq_accesses::cpu1.data 1185 # number of SCUpgradeReq accesses(hits+misses) 1320system.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses) 1321system.l2c.ReadExReq_accesses::cpu0.data 150419 # number of ReadExReq accesses(hits+misses) 1322system.l2c.ReadExReq_accesses::cpu1.data 18969 # number of ReadExReq accesses(hits+misses) 1323system.l2c.ReadExReq_accesses::total 169388 # number of ReadExReq accesses(hits+misses) 1324system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 82 # number of ReadSharedReq accesses(hits+misses) 1325system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 70 # number of ReadSharedReq accesses(hits+misses) 1326system.l2c.ReadSharedReq_accesses::cpu0.inst 41643 # number of ReadSharedReq accesses(hits+misses) 1327system.l2c.ReadSharedReq_accesses::cpu0.data 87232 # number of ReadSharedReq accesses(hits+misses) 1328system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) 1329system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 27 # number of ReadSharedReq accesses(hits+misses) 1330system.l2c.ReadSharedReq_accesses::cpu1.inst 13539 # number of ReadSharedReq accesses(hits+misses) 1331system.l2c.ReadSharedReq_accesses::cpu1.data 12885 # number of ReadSharedReq accesses(hits+misses) 1332system.l2c.ReadSharedReq_accesses::total 155514 # number of ReadSharedReq accesses(hits+misses) 1333system.l2c.demand_accesses::cpu0.dtb.walker 82 # number of demand (read+write) accesses 1334system.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses 1335system.l2c.demand_accesses::cpu0.inst 41643 # number of demand (read+write) accesses 1336system.l2c.demand_accesses::cpu0.data 237651 # number of demand (read+write) accesses 1337system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses 1338system.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses 1339system.l2c.demand_accesses::cpu1.inst 13539 # number of demand (read+write) accesses 1340system.l2c.demand_accesses::cpu1.data 31854 # number of demand (read+write) accesses 1341system.l2c.demand_accesses::total 324902 # number of demand (read+write) accesses 1342system.l2c.overall_accesses::cpu0.dtb.walker 82 # number of overall (read+write) accesses 1343system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses 1344system.l2c.overall_accesses::cpu0.inst 41643 # number of overall (read+write) accesses 1345system.l2c.overall_accesses::cpu0.data 237651 # number of overall (read+write) accesses 1346system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses 1347system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses 1348system.l2c.overall_accesses::cpu1.inst 13539 # number of overall (read+write) accesses 1349system.l2c.overall_accesses::cpu1.data 31854 # number of overall (read+write) accesses 1350system.l2c.overall_accesses::total 324902 # number of overall (read+write) accesses 1351system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951582 # miss rate for UpgradeReq accesses 1352system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980947 # miss rate for UpgradeReq accesses 1353system.l2c.UpgradeReq_miss_rate::total 0.958672 # miss rate for UpgradeReq accesses 1354system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920635 # miss rate for SCUpgradeReq accesses 1355system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994093 # miss rate for SCUpgradeReq accesses 1356system.l2c.SCUpgradeReq_miss_rate::total 0.964072 # miss rate for SCUpgradeReq accesses 1357system.l2c.ReadExReq_miss_rate::cpu0.data 0.907631 # miss rate for ReadExReq accesses 1358system.l2c.ReadExReq_miss_rate::cpu1.data 0.834889 # miss rate for ReadExReq accesses 1359system.l2c.ReadExReq_miss_rate::total 0.899485 # miss rate for ReadExReq accesses 1360system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for ReadSharedReq accesses 1361system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028571 # miss rate for ReadSharedReq accesses 1362system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402493 # miss rate for ReadSharedReq accesses 1363system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128084 # miss rate for ReadSharedReq accesses 1364system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176823 # miss rate for ReadSharedReq accesses 1365system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087388 # miss rate for ReadSharedReq accesses 1366system.l2c.ReadSharedReq_miss_rate::total 0.202323 # miss rate for ReadSharedReq accesses 1367system.l2c.demand_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for demand accesses 1368system.l2c.demand_miss_rate::cpu0.itb.walker 0.028571 # miss rate for demand accesses 1369system.l2c.demand_miss_rate::cpu0.inst 0.402493 # miss rate for demand accesses 1370system.l2c.demand_miss_rate::cpu0.data 0.621491 # miss rate for demand accesses 1371system.l2c.demand_miss_rate::cpu1.inst 0.176823 # miss rate for demand accesses 1372system.l2c.demand_miss_rate::cpu1.data 0.532523 # miss rate for demand accesses 1373system.l2c.demand_miss_rate::total 0.565789 # miss rate for demand accesses 1374system.l2c.overall_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for overall accesses 1375system.l2c.overall_miss_rate::cpu0.itb.walker 0.028571 # miss rate for overall accesses 1376system.l2c.overall_miss_rate::cpu0.inst 0.402493 # miss rate for overall accesses 1377system.l2c.overall_miss_rate::cpu0.data 0.621491 # miss rate for overall accesses 1378system.l2c.overall_miss_rate::cpu1.inst 0.176823 # miss rate for overall accesses 1379system.l2c.overall_miss_rate::cpu1.data 0.532523 # miss rate for overall accesses 1380system.l2c.overall_miss_rate::total 0.565789 # miss rate for overall accesses 1381system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1382system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1383system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1384system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1385system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1386system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1387system.l2c.fast_writes 0 # number of fast writes performed 1388system.l2c.cache_copies 0 # number of cache copies performed 1389system.l2c.writebacks::writebacks 95877 # number of writebacks 1390system.l2c.writebacks::total 95877 # number of writebacks 1391system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1392system.membus.trans_dist::ReadReq 43996 # Transaction distribution 1393system.membus.trans_dist::ReadResp 75712 # Transaction distribution 1394system.membus.trans_dist::WriteReq 30846 # Transaction distribution 1395system.membus.trans_dist::WriteResp 30846 # Transaction distribution 1396system.membus.trans_dist::WritebackDirty 132067 # Transaction distribution 1397system.membus.trans_dist::CleanEvict 8465 # Transaction distribution 1398system.membus.trans_dist::UpgradeReq 60519 # Transaction distribution 1399system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution 1400system.membus.trans_dist::UpgradeResp 15741 # Transaction distribution 1401system.membus.trans_dist::ReadExReq 196031 # Transaction distribution 1402system.membus.trans_dist::ReadExResp 151891 # Transaction distribution 1403system.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution 1404system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1405system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1406system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 1407system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 1408system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 1409system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660645 # Packet count per connected master and slave (bytes) 1410system.membus.pkt_count_system.l2c.mem_side::total 782029 # Packet count per connected master and slave (bytes) 1411system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes) 1412system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes) 1413system.membus.pkt_count::total 891184 # Packet count per connected master and slave (bytes) 1414system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 1415system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 1416system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 1417system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17927560 # Cumulative packet size per connected master and slave (bytes) 1418system.membus.pkt_size_system.l2c.mem_side::total 18117342 # Cumulative packet size per connected master and slave (bytes) 1419system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 1420system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 1421system.membus.pkt_size::total 20449630 # Cumulative packet size per connected master and slave (bytes) 1422system.membus.snoops 0 # Total snoops (count) 1423system.membus.snoop_fanout::samples 581009 # Request fanout histogram 1424system.membus.snoop_fanout::mean 1 # Request fanout histogram 1425system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1426system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1427system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1428system.membus.snoop_fanout::1 581009 100.00% 100.00% # Request fanout histogram 1429system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1430system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1431system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1432system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1433system.membus.snoop_fanout::total 581009 # Request fanout histogram 1434system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1435system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1436system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1437system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1438system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1439system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1440system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1441system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1442system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1443system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1444system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1445system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1446system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1447system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1448system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1449system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1450system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1451system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1452system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1453system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1454system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1455system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1456system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1457system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1458system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1459system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1460system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1461system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1462system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1463system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1464system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1465system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1466system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1467system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1468system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1469system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1470system.realview.ethernet.droppedPackets 0 # number of packets dropped 1471system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1472system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1473system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1474system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1475system.toL2Bus.snoop_filter.tot_requests 863003 # Total number of requests made to the snoop filter. 1476system.toL2Bus.snoop_filter.hit_single_requests 444472 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1477system.toL2Bus.snoop_filter.hit_multi_requests 128485 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1478system.toL2Bus.snoop_filter.tot_snoops 9552 # Total number of snoops made to the snoop filter. 1479system.toL2Bus.snoop_filter.hit_single_snoops 9071 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1480system.toL2Bus.snoop_filter.hit_multi_snoops 481 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1481system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution 1482system.toL2Bus.trans_dist::ReadResp 301629 # Transaction distribution 1483system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 1484system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 1485system.toL2Bus.trans_dist::WritebackDirty 225729 # Transaction distribution 1486system.toL2Bus.trans_dist::CleanEvict 38612 # Transaction distribution 1487system.toL2Bus.trans_dist::UpgradeReq 60623 # Transaction distribution 1488system.toL2Bus.trans_dist::SCUpgradeReq 40978 # Transaction distribution 1489system.toL2Bus.trans_dist::UpgradeResp 101601 # Transaction distribution 1490system.toL2Bus.trans_dist::ReadExReq 213528 # Transaction distribution 1491system.toL2Bus.trans_dist::ReadExResp 213528 # Transaction distribution 1492system.toL2Bus.trans_dist::ReadSharedReq 257629 # Transaction distribution 1493system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1143706 # Packet count per connected master and slave (bytes) 1494system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 415843 # Packet count per connected master and slave (bytes) 1495system.toL2Bus.pkt_count::total 1559549 # Packet count per connected master and slave (bytes) 1496system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34428348 # Cumulative packet size per connected master and slave (bytes) 1497system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10418866 # Cumulative packet size per connected master and slave (bytes) 1498system.toL2Bus.pkt_size::total 44847214 # Cumulative packet size per connected master and slave (bytes) 1499system.toL2Bus.snoops 180208 # Total snoops (count) 1500system.toL2Bus.snoop_fanout::samples 1117804 # Request fanout histogram 1501system.toL2Bus.snoop_fanout::mean 0.282168 # Request fanout histogram 1502system.toL2Bus.snoop_fanout::stdev 0.451010 # Request fanout histogram 1503system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1504system.toL2Bus.snoop_fanout::0 802876 71.83% 71.83% # Request fanout histogram 1505system.toL2Bus.snoop_fanout::1 314447 28.13% 99.96% # Request fanout histogram 1506system.toL2Bus.snoop_fanout::2 481 0.04% 100.00% # Request fanout histogram 1507system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1508system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1509system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1510system.toL2Bus.snoop_fanout::total 1117804 # Request fanout histogram 1511 1512---------- End Simulation Statistics ----------