1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.912098 # Number of seconds simulated
4sim_ticks 912098398000 # Number of ticks simulated
5final_tick 912098398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.912098 # Number of seconds simulated
4sim_ticks 912098398000 # Number of ticks simulated
5final_tick 912098398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1169212 # Simulator instruction rate (inst/s)
8host_op_rate 1505339 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 17301899059 # Simulator tick rate (ticks/s)
10host_mem_usage 421332 # Number of bytes of host memory used
11host_seconds 52.72 # Real time elapsed on the host
| 7host_inst_rate 1024713 # Simulator instruction rate (inst/s)
8host_op_rate 1319299 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 15163617701 # Simulator tick rate (ticks/s)
10host_mem_usage 465872 # Number of bytes of host memory used
11host_seconds 60.15 # Real time elapsed on the host
|
12sim_insts 61636937 # Number of instructions simulated
13sim_ops 79356422 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
| 12sim_insts 61636937 # Number of instructions simulated
13sim_ops 79356422 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
|
16system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
17system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
18system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
19system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
20system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
21system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
22system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
23system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
24system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
25system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
26system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
27system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
28system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
29system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
30system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
32system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
33system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
| |
34system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
35system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
36system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
37system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory
38system.physmem.bytes_read::cpu0.data 6235260 # Number of bytes read from this memory
39system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
40system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory
41system.physmem.bytes_read::cpu1.data 3364600 # Number of bytes read from this memory
42system.physmem.bytes_read::total 49638724 # Number of bytes read from this memory
43system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory
44system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory
45system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory
46system.physmem.bytes_written::writebacks 4195904 # Number of bytes written to this memory
47system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
48system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory
49system.physmem.bytes_written::total 7222992 # Number of bytes written to this memory
50system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
51system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
52system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
53system.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory
54system.physmem.num_reads::cpu0.data 97500 # Number of read requests responded to by this memory
55system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
56system.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory
57system.physmem.num_reads::cpu1.data 52600 # Number of read requests responded to by this memory
58system.physmem.num_reads::total 5082826 # Number of read requests responded to by this memory
59system.physmem.num_writes::writebacks 65561 # Number of write requests responded to by this memory
60system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
61system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
62system.physmem.num_writes::total 822333 # Number of write requests responded to by this memory
63system.physmem.bw_read::realview.clcd 43111138 # Total read bandwidth from this memory (bytes/s)
64system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s)
65system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
66system.physmem.bw_read::cpu0.inst 550620 # Total read bandwidth from this memory (bytes/s)
67system.physmem.bw_read::cpu0.data 6836170 # Total read bandwidth from this memory (bytes/s)
68system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s)
69system.physmem.bw_read::cpu1.inst 235277 # Total read bandwidth from this memory (bytes/s)
70system.physmem.bw_read::cpu1.data 3688856 # Total read bandwidth from this memory (bytes/s)
71system.physmem.bw_read::total 54422554 # Total read bandwidth from this memory (bytes/s)
72system.physmem.bw_inst_read::cpu0.inst 550620 # Instruction read bandwidth from this memory (bytes/s)
73system.physmem.bw_inst_read::cpu1.inst 235277 # Instruction read bandwidth from this memory (bytes/s)
74system.physmem.bw_inst_read::total 785898 # Instruction read bandwidth from this memory (bytes/s)
75system.physmem.bw_write::writebacks 4600276 # Write bandwidth from this memory (bytes/s)
76system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s)
77system.physmem.bw_write::cpu1.data 3300179 # Write bandwidth from this memory (bytes/s)
78system.physmem.bw_write::total 7919093 # Write bandwidth from this memory (bytes/s)
79system.physmem.bw_total::writebacks 4600276 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::realview.clcd 43111138 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.bw_total::cpu0.inst 550620 # Total bandwidth to/from this memory (bytes/s)
84system.physmem.bw_total::cpu0.data 6854809 # Total bandwidth to/from this memory (bytes/s)
85system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s)
86system.physmem.bw_total::cpu1.inst 235277 # Total bandwidth to/from this memory (bytes/s)
87system.physmem.bw_total::cpu1.data 6989035 # Total bandwidth to/from this memory (bytes/s)
88system.physmem.bw_total::total 62341647 # Total bandwidth to/from this memory (bytes/s)
| 16system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 502220 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 6235260 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.inst 214596 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.data 3364600 # Number of bytes read from this memory
24system.physmem.bytes_read::total 49638724 # Number of bytes read from this memory
25system.physmem.bytes_inst_read::cpu0.inst 502220 # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu1.inst 214596 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::total 716816 # Number of instructions bytes read from this memory
28system.physmem.bytes_written::writebacks 4195904 # Number of bytes written to this memory
29system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
30system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory
31system.physmem.bytes_written::total 7222992 # Number of bytes written to this memory
32system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.inst 14075 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.data 97500 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.inst 3444 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.data 52600 # Number of read requests responded to by this memory
40system.physmem.num_reads::total 5082826 # Number of read requests responded to by this memory
41system.physmem.num_writes::writebacks 65561 # Number of write requests responded to by this memory
42system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
43system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
44system.physmem.num_writes::total 822333 # Number of write requests responded to by this memory
45system.physmem.bw_read::realview.clcd 43111138 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.inst 550620 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.data 6836170 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu1.inst 235277 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.data 3688856 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::total 54422554 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_inst_read::cpu0.inst 550620 # Instruction read bandwidth from this memory (bytes/s)
55system.physmem.bw_inst_read::cpu1.inst 235277 # Instruction read bandwidth from this memory (bytes/s)
56system.physmem.bw_inst_read::total 785898 # Instruction read bandwidth from this memory (bytes/s)
57system.physmem.bw_write::writebacks 4600276 # Write bandwidth from this memory (bytes/s)
58system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s)
59system.physmem.bw_write::cpu1.data 3300179 # Write bandwidth from this memory (bytes/s)
60system.physmem.bw_write::total 7919093 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_total::writebacks 4600276 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::realview.clcd 43111138 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s)
64system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.inst 550620 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.data 6854809 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu1.inst 235277 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu1.data 6989035 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::total 62341647 # Total bandwidth to/from this memory (bytes/s)
|
| 71system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
72system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
73system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
74system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
75system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
76system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
77system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
78system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
79system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
80system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
81system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
82system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
83system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
84system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
85system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
86system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
87system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
88system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
|
89system.membus.throughput 64987015 # Throughput (bytes/s)
90system.membus.data_through_bus 59274552 # Total data (bytes)
91system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
92system.cpu_clk_domain.clock 500 # Clock period in ticks
93system.l2c.tags.replacements 70660 # number of replacements
94system.l2c.tags.tagsinuse 51560.418077 # Cycle average of tags in use
95system.l2c.tags.total_refs 1623334 # Total number of references to valid blocks.
96system.l2c.tags.sampled_refs 135812 # Sample count of references to valid blocks.
97system.l2c.tags.avg_refs 11.952802 # Average number of references to valid blocks.
98system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
99system.l2c.tags.occ_blocks::writebacks 39278.982234 # Average occupied blocks per requestor
100system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
101system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001109 # Average occupied blocks per requestor
102system.l2c.tags.occ_blocks::cpu0.inst 4358.948754 # Average occupied blocks per requestor
103system.l2c.tags.occ_blocks::cpu0.data 2482.442784 # Average occupied blocks per requestor
104system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678936 # Average occupied blocks per requestor
105system.l2c.tags.occ_blocks::cpu1.inst 2126.447479 # Average occupied blocks per requestor
106system.l2c.tags.occ_blocks::cpu1.data 3310.916734 # Average occupied blocks per requestor
107system.l2c.tags.occ_percent::writebacks 0.599350 # Average percentage of cache occupancy
108system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
109system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
110system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy
111system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy
112system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
113system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy
114system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy
115system.l2c.tags.occ_percent::total 0.786750 # Average percentage of cache occupancy
116system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
117system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id
118system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
119system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
120system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
121system.l2c.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
122system.l2c.tags.age_task_id_blocks_1024::2 3771 # Occupied blocks per task id
123system.l2c.tags.age_task_id_blocks_1024::3 12549 # Occupied blocks per task id
124system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id
125system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
126system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id
127system.l2c.tags.tag_accesses 16908072 # Number of tag accesses
128system.l2c.tags.data_accesses 16908072 # Number of data accesses
129system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits
130system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits
131system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits
132system.l2c.ReadReq_hits::cpu0.data 175187 # number of ReadReq hits
133system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits
134system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits
135system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits
136system.l2c.ReadReq_hits::cpu1.data 169510 # number of ReadReq hits
137system.l2c.ReadReq_hits::total 1209104 # number of ReadReq hits
138system.l2c.Writeback_hits::writebacks 567806 # number of Writeback hits
139system.l2c.Writeback_hits::total 567806 # number of Writeback hits
140system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits
141system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits
142system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits
143system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits
144system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
145system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits
146system.l2c.ReadExReq_hits::cpu0.data 58145 # number of ReadExReq hits
147system.l2c.ReadExReq_hits::cpu1.data 50213 # number of ReadExReq hits
148system.l2c.ReadExReq_hits::total 108358 # number of ReadExReq hits
149system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits
150system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits
151system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits
152system.l2c.demand_hits::cpu0.data 233332 # number of demand (read+write) hits
153system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits
154system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits
155system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits
156system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits
157system.l2c.demand_hits::total 1317462 # number of demand (read+write) hits
158system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits
159system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits
160system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits
161system.l2c.overall_hits::cpu0.data 233332 # number of overall hits
162system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits
163system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits
164system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits
165system.l2c.overall_hits::cpu1.data 219723 # number of overall hits
166system.l2c.overall_hits::total 1317462 # number of overall hits
167system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
168system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
169system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses
170system.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses
171system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses
172system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses
173system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses
174system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses
175system.l2c.UpgradeReq_misses::cpu0.data 4941 # number of UpgradeReq misses
176system.l2c.UpgradeReq_misses::cpu1.data 4450 # number of UpgradeReq misses
177system.l2c.UpgradeReq_misses::total 9391 # number of UpgradeReq misses
178system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses
179system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses
180system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses
181system.l2c.ReadExReq_misses::cpu0.data 92465 # number of ReadExReq misses
182system.l2c.ReadExReq_misses::cpu1.data 48373 # number of ReadExReq misses
183system.l2c.ReadExReq_misses::total 140838 # number of ReadExReq misses
184system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
185system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
186system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses
187system.l2c.demand_misses::cpu0.data 98857 # number of demand (read+write) misses
188system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
189system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses
190system.l2c.demand_misses::cpu1.data 53649 # number of demand (read+write) misses
191system.l2c.demand_misses::total 163292 # number of demand (read+write) misses
192system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
193system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
194system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses
195system.l2c.overall_misses::cpu0.data 98857 # number of overall misses
196system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
197system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses
198system.l2c.overall_misses::cpu1.data 53649 # number of overall misses
199system.l2c.overall_misses::total 163292 # number of overall misses
200system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses)
201system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses)
202system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses)
203system.l2c.ReadReq_accesses::cpu0.data 181579 # number of ReadReq accesses(hits+misses)
204system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses)
205system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses)
206system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses)
207system.l2c.ReadReq_accesses::cpu1.data 174786 # number of ReadReq accesses(hits+misses)
208system.l2c.ReadReq_accesses::total 1231558 # number of ReadReq accesses(hits+misses)
209system.l2c.Writeback_accesses::writebacks 567806 # number of Writeback accesses(hits+misses)
210system.l2c.Writeback_accesses::total 567806 # number of Writeback accesses(hits+misses)
211system.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses)
212system.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses)
213system.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses)
214system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses)
215system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses)
216system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses)
217system.l2c.ReadExReq_accesses::cpu0.data 150610 # number of ReadExReq accesses(hits+misses)
218system.l2c.ReadExReq_accesses::cpu1.data 98586 # number of ReadExReq accesses(hits+misses)
219system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses)
220system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses
221system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses
222system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses
223system.l2c.demand_accesses::cpu0.data 332189 # number of demand (read+write) accesses
224system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses
225system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses
226system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses
227system.l2c.demand_accesses::cpu1.data 273372 # number of demand (read+write) accesses
228system.l2c.demand_accesses::total 1480754 # number of demand (read+write) accesses
229system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses
230system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses
231system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses
232system.l2c.overall_accesses::cpu0.data 332189 # number of overall (read+write) accesses
233system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses
234system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses
235system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses
236system.l2c.overall_accesses::cpu1.data 273372 # number of overall (read+write) accesses
237system.l2c.overall_accesses::total 1480754 # number of overall (read+write) accesses
238system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses
239system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses
240system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses
241system.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses
242system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses
243system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses
244system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses
245system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses
246system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889950 # miss rate for UpgradeReq accesses
247system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870331 # miss rate for UpgradeReq accesses
248system.l2c.UpgradeReq_miss_rate::total 0.880544 # miss rate for UpgradeReq accesses
249system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses
250system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses
251system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses
252system.l2c.ReadExReq_miss_rate::cpu0.data 0.613937 # miss rate for ReadExReq accesses
253system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses
254system.l2c.ReadExReq_miss_rate::total 0.565170 # miss rate for ReadExReq accesses
255system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses
256system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses
257system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses
258system.l2c.demand_miss_rate::cpu0.data 0.297593 # miss rate for demand accesses
259system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses
260system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses
261system.l2c.demand_miss_rate::cpu1.data 0.196249 # miss rate for demand accesses
262system.l2c.demand_miss_rate::total 0.110276 # miss rate for demand accesses
263system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses
264system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses
265system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses
266system.l2c.overall_miss_rate::cpu0.data 0.297593 # miss rate for overall accesses
267system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses
268system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses
269system.l2c.overall_miss_rate::cpu1.data 0.196249 # miss rate for overall accesses
270system.l2c.overall_miss_rate::total 0.110276 # miss rate for overall accesses
271system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
272system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
273system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
274system.l2c.blocked::no_targets 0 # number of cycles access was blocked
275system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
276system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
277system.l2c.fast_writes 0 # number of fast writes performed
278system.l2c.cache_copies 0 # number of cache copies performed
279system.l2c.writebacks::writebacks 65561 # number of writebacks
280system.l2c.writebacks::total 65561 # number of writebacks
281system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
282system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
283system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
284system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
285system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
286system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
287system.cf0.dma_write_txs 0 # Number of DMA write transactions.
288system.toL2Bus.throughput 154019817 # Throughput (bytes/s)
289system.toL2Bus.data_through_bus 140481228 # Total data (bytes)
290system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
291system.iobus.throughput 45731035 # Throughput (bytes/s)
292system.iobus.data_through_bus 41711204 # Total data (bytes)
293system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
294system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
295system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
296system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
297system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
298system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
299system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
300system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
301system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
302system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
303system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
304system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
305system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
306system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
307system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
308system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
309system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
310system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
311system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
312system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
313system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
314system.cpu0.dtb.inst_hits 0 # ITB inst hits
315system.cpu0.dtb.inst_misses 0 # ITB inst misses
316system.cpu0.dtb.read_hits 7977762 # DTB read hits
317system.cpu0.dtb.read_misses 3611 # DTB read misses
318system.cpu0.dtb.write_hits 5967140 # DTB write hits
319system.cpu0.dtb.write_misses 672 # DTB write misses
320system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
321system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
322system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
323system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
324system.cpu0.dtb.flush_entries 1905 # Number of entries that have been flushed from TLB
325system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
326system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch
327system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
328system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
329system.cpu0.dtb.read_accesses 7981373 # DTB read accesses
330system.cpu0.dtb.write_accesses 5967812 # DTB write accesses
331system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
332system.cpu0.dtb.hits 13944902 # DTB hits
333system.cpu0.dtb.misses 4283 # DTB misses
334system.cpu0.dtb.accesses 13949185 # DTB accesses
335system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
336system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
337system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
338system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
339system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
340system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
341system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
342system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
343system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
344system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
345system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
346system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
347system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
348system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
349system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
350system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
351system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
352system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
353system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
354system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
355system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
356system.cpu0.itb.inst_hits 30248608 # ITB inst hits
357system.cpu0.itb.inst_misses 2175 # ITB inst misses
358system.cpu0.itb.read_hits 0 # DTB read hits
359system.cpu0.itb.read_misses 0 # DTB read misses
360system.cpu0.itb.write_hits 0 # DTB write hits
361system.cpu0.itb.write_misses 0 # DTB write misses
362system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
363system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
364system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
365system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
366system.cpu0.itb.flush_entries 1280 # Number of entries that have been flushed from TLB
367system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
368system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
369system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
370system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
371system.cpu0.itb.read_accesses 0 # DTB read accesses
372system.cpu0.itb.write_accesses 0 # DTB write accesses
373system.cpu0.itb.inst_accesses 30250783 # ITB inst accesses
374system.cpu0.itb.hits 30248608 # DTB hits
375system.cpu0.itb.misses 2175 # DTB misses
376system.cpu0.itb.accesses 30250783 # DTB accesses
377system.cpu0.numCycles 1823674676 # number of cpu cycles simulated
378system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
379system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
380system.cpu0.committedInsts 29759626 # Number of instructions committed
381system.cpu0.committedOps 39141026 # Number of ops (including micro ops) committed
382system.cpu0.num_int_alu_accesses 34755088 # Number of integer alu accesses
383system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses
384system.cpu0.num_func_calls 1242746 # number of times a function call or return occured
385system.cpu0.num_conditional_control_insts 4045769 # number of instructions that are conditional controls
386system.cpu0.num_int_insts 34755088 # number of integer instructions
387system.cpu0.num_fp_insts 5449 # number of float instructions
388system.cpu0.num_int_register_reads 179913159 # number of times the integer registers were read
389system.cpu0.num_int_register_writes 36837171 # number of times the integer registers were written
390system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read
391system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written
392system.cpu0.num_mem_refs 14629859 # number of memory refs
393system.cpu0.num_load_insts 8359235 # Number of load instructions
394system.cpu0.num_store_insts 6270624 # Number of store instructions
395system.cpu0.num_idle_cycles 1783997876.499954 # Number of idle cycles
396system.cpu0.num_busy_cycles 39676799.500046 # Number of busy cycles
397system.cpu0.not_idle_fraction 0.021757 # Percentage of non-idle cycles
398system.cpu0.idle_fraction 0.978243 # Percentage of idle cycles
399system.cpu0.Branches 5492144 # Number of branches fetched
| 89system.membus.throughput 64987015 # Throughput (bytes/s)
90system.membus.data_through_bus 59274552 # Total data (bytes)
91system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
92system.cpu_clk_domain.clock 500 # Clock period in ticks
93system.l2c.tags.replacements 70660 # number of replacements
94system.l2c.tags.tagsinuse 51560.418077 # Cycle average of tags in use
95system.l2c.tags.total_refs 1623334 # Total number of references to valid blocks.
96system.l2c.tags.sampled_refs 135812 # Sample count of references to valid blocks.
97system.l2c.tags.avg_refs 11.952802 # Average number of references to valid blocks.
98system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
99system.l2c.tags.occ_blocks::writebacks 39278.982234 # Average occupied blocks per requestor
100system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
101system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001109 # Average occupied blocks per requestor
102system.l2c.tags.occ_blocks::cpu0.inst 4358.948754 # Average occupied blocks per requestor
103system.l2c.tags.occ_blocks::cpu0.data 2482.442784 # Average occupied blocks per requestor
104system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678936 # Average occupied blocks per requestor
105system.l2c.tags.occ_blocks::cpu1.inst 2126.447479 # Average occupied blocks per requestor
106system.l2c.tags.occ_blocks::cpu1.data 3310.916734 # Average occupied blocks per requestor
107system.l2c.tags.occ_percent::writebacks 0.599350 # Average percentage of cache occupancy
108system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
109system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
110system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy
111system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy
112system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
113system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy
114system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy
115system.l2c.tags.occ_percent::total 0.786750 # Average percentage of cache occupancy
116system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
117system.l2c.tags.occ_task_id_blocks::1024 65148 # Occupied blocks per task id
118system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
119system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
120system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
121system.l2c.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
122system.l2c.tags.age_task_id_blocks_1024::2 3771 # Occupied blocks per task id
123system.l2c.tags.age_task_id_blocks_1024::3 12549 # Occupied blocks per task id
124system.l2c.tags.age_task_id_blocks_1024::4 48575 # Occupied blocks per task id
125system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
126system.l2c.tags.occ_task_id_percent::1024 0.994080 # Percentage of cache occupancy per task id
127system.l2c.tags.tag_accesses 16908072 # Number of tag accesses
128system.l2c.tags.data_accesses 16908072 # Number of data accesses
129system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits
130system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits
131system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits
132system.l2c.ReadReq_hits::cpu0.data 175187 # number of ReadReq hits
133system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits
134system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits
135system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits
136system.l2c.ReadReq_hits::cpu1.data 169510 # number of ReadReq hits
137system.l2c.ReadReq_hits::total 1209104 # number of ReadReq hits
138system.l2c.Writeback_hits::writebacks 567806 # number of Writeback hits
139system.l2c.Writeback_hits::total 567806 # number of Writeback hits
140system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits
141system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits
142system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits
143system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits
144system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
145system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits
146system.l2c.ReadExReq_hits::cpu0.data 58145 # number of ReadExReq hits
147system.l2c.ReadExReq_hits::cpu1.data 50213 # number of ReadExReq hits
148system.l2c.ReadExReq_hits::total 108358 # number of ReadExReq hits
149system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits
150system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits
151system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits
152system.l2c.demand_hits::cpu0.data 233332 # number of demand (read+write) hits
153system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits
154system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits
155system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits
156system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits
157system.l2c.demand_hits::total 1317462 # number of demand (read+write) hits
158system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits
159system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits
160system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits
161system.l2c.overall_hits::cpu0.data 233332 # number of overall hits
162system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits
163system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits
164system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits
165system.l2c.overall_hits::cpu1.data 219723 # number of overall hits
166system.l2c.overall_hits::total 1317462 # number of overall hits
167system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
168system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
169system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses
170system.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses
171system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses
172system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses
173system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses
174system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses
175system.l2c.UpgradeReq_misses::cpu0.data 4941 # number of UpgradeReq misses
176system.l2c.UpgradeReq_misses::cpu1.data 4450 # number of UpgradeReq misses
177system.l2c.UpgradeReq_misses::total 9391 # number of UpgradeReq misses
178system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses
179system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses
180system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses
181system.l2c.ReadExReq_misses::cpu0.data 92465 # number of ReadExReq misses
182system.l2c.ReadExReq_misses::cpu1.data 48373 # number of ReadExReq misses
183system.l2c.ReadExReq_misses::total 140838 # number of ReadExReq misses
184system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
185system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
186system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses
187system.l2c.demand_misses::cpu0.data 98857 # number of demand (read+write) misses
188system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
189system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses
190system.l2c.demand_misses::cpu1.data 53649 # number of demand (read+write) misses
191system.l2c.demand_misses::total 163292 # number of demand (read+write) misses
192system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
193system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
194system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses
195system.l2c.overall_misses::cpu0.data 98857 # number of overall misses
196system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
197system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses
198system.l2c.overall_misses::cpu1.data 53649 # number of overall misses
199system.l2c.overall_misses::total 163292 # number of overall misses
200system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses)
201system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses)
202system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses)
203system.l2c.ReadReq_accesses::cpu0.data 181579 # number of ReadReq accesses(hits+misses)
204system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses)
205system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses)
206system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses)
207system.l2c.ReadReq_accesses::cpu1.data 174786 # number of ReadReq accesses(hits+misses)
208system.l2c.ReadReq_accesses::total 1231558 # number of ReadReq accesses(hits+misses)
209system.l2c.Writeback_accesses::writebacks 567806 # number of Writeback accesses(hits+misses)
210system.l2c.Writeback_accesses::total 567806 # number of Writeback accesses(hits+misses)
211system.l2c.UpgradeReq_accesses::cpu0.data 5552 # number of UpgradeReq accesses(hits+misses)
212system.l2c.UpgradeReq_accesses::cpu1.data 5113 # number of UpgradeReq accesses(hits+misses)
213system.l2c.UpgradeReq_accesses::total 10665 # number of UpgradeReq accesses(hits+misses)
214system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses)
215system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses)
216system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses)
217system.l2c.ReadExReq_accesses::cpu0.data 150610 # number of ReadExReq accesses(hits+misses)
218system.l2c.ReadExReq_accesses::cpu1.data 98586 # number of ReadExReq accesses(hits+misses)
219system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses)
220system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses
221system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses
222system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses
223system.l2c.demand_accesses::cpu0.data 332189 # number of demand (read+write) accesses
224system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses
225system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses
226system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses
227system.l2c.demand_accesses::cpu1.data 273372 # number of demand (read+write) accesses
228system.l2c.demand_accesses::total 1480754 # number of demand (read+write) accesses
229system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses
230system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses
231system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses
232system.l2c.overall_accesses::cpu0.data 332189 # number of overall (read+write) accesses
233system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses
234system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses
235system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses
236system.l2c.overall_accesses::cpu1.data 273372 # number of overall (read+write) accesses
237system.l2c.overall_accesses::total 1480754 # number of overall (read+write) accesses
238system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses
239system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses
240system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses
241system.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses
242system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses
243system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses
244system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses
245system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses
246system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889950 # miss rate for UpgradeReq accesses
247system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870331 # miss rate for UpgradeReq accesses
248system.l2c.UpgradeReq_miss_rate::total 0.880544 # miss rate for UpgradeReq accesses
249system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses
250system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses
251system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses
252system.l2c.ReadExReq_miss_rate::cpu0.data 0.613937 # miss rate for ReadExReq accesses
253system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses
254system.l2c.ReadExReq_miss_rate::total 0.565170 # miss rate for ReadExReq accesses
255system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses
256system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses
257system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses
258system.l2c.demand_miss_rate::cpu0.data 0.297593 # miss rate for demand accesses
259system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses
260system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses
261system.l2c.demand_miss_rate::cpu1.data 0.196249 # miss rate for demand accesses
262system.l2c.demand_miss_rate::total 0.110276 # miss rate for demand accesses
263system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses
264system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses
265system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses
266system.l2c.overall_miss_rate::cpu0.data 0.297593 # miss rate for overall accesses
267system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses
268system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses
269system.l2c.overall_miss_rate::cpu1.data 0.196249 # miss rate for overall accesses
270system.l2c.overall_miss_rate::total 0.110276 # miss rate for overall accesses
271system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
272system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
273system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
274system.l2c.blocked::no_targets 0 # number of cycles access was blocked
275system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
276system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
277system.l2c.fast_writes 0 # number of fast writes performed
278system.l2c.cache_copies 0 # number of cache copies performed
279system.l2c.writebacks::writebacks 65561 # number of writebacks
280system.l2c.writebacks::total 65561 # number of writebacks
281system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
282system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
283system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
284system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
285system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
286system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
287system.cf0.dma_write_txs 0 # Number of DMA write transactions.
288system.toL2Bus.throughput 154019817 # Throughput (bytes/s)
289system.toL2Bus.data_through_bus 140481228 # Total data (bytes)
290system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
291system.iobus.throughput 45731035 # Throughput (bytes/s)
292system.iobus.data_through_bus 41711204 # Total data (bytes)
293system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
294system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
295system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
296system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
297system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
298system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
299system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
300system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
301system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
302system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
303system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
304system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
305system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
306system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
307system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
308system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
309system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
310system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
311system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
312system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
313system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
314system.cpu0.dtb.inst_hits 0 # ITB inst hits
315system.cpu0.dtb.inst_misses 0 # ITB inst misses
316system.cpu0.dtb.read_hits 7977762 # DTB read hits
317system.cpu0.dtb.read_misses 3611 # DTB read misses
318system.cpu0.dtb.write_hits 5967140 # DTB write hits
319system.cpu0.dtb.write_misses 672 # DTB write misses
320system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
321system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
322system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
323system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
324system.cpu0.dtb.flush_entries 1905 # Number of entries that have been flushed from TLB
325system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
326system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch
327system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
328system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
329system.cpu0.dtb.read_accesses 7981373 # DTB read accesses
330system.cpu0.dtb.write_accesses 5967812 # DTB write accesses
331system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
332system.cpu0.dtb.hits 13944902 # DTB hits
333system.cpu0.dtb.misses 4283 # DTB misses
334system.cpu0.dtb.accesses 13949185 # DTB accesses
335system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
336system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
337system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
338system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
339system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
340system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
341system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
342system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
343system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
344system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
345system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
346system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
347system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
348system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
349system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
350system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
351system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
352system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
353system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
354system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
355system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
356system.cpu0.itb.inst_hits 30248608 # ITB inst hits
357system.cpu0.itb.inst_misses 2175 # ITB inst misses
358system.cpu0.itb.read_hits 0 # DTB read hits
359system.cpu0.itb.read_misses 0 # DTB read misses
360system.cpu0.itb.write_hits 0 # DTB write hits
361system.cpu0.itb.write_misses 0 # DTB write misses
362system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
363system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
364system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
365system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
366system.cpu0.itb.flush_entries 1280 # Number of entries that have been flushed from TLB
367system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
368system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
369system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
370system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
371system.cpu0.itb.read_accesses 0 # DTB read accesses
372system.cpu0.itb.write_accesses 0 # DTB write accesses
373system.cpu0.itb.inst_accesses 30250783 # ITB inst accesses
374system.cpu0.itb.hits 30248608 # DTB hits
375system.cpu0.itb.misses 2175 # DTB misses
376system.cpu0.itb.accesses 30250783 # DTB accesses
377system.cpu0.numCycles 1823674676 # number of cpu cycles simulated
378system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
379system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
380system.cpu0.committedInsts 29759626 # Number of instructions committed
381system.cpu0.committedOps 39141026 # Number of ops (including micro ops) committed
382system.cpu0.num_int_alu_accesses 34755088 # Number of integer alu accesses
383system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses
384system.cpu0.num_func_calls 1242746 # number of times a function call or return occured
385system.cpu0.num_conditional_control_insts 4045769 # number of instructions that are conditional controls
386system.cpu0.num_int_insts 34755088 # number of integer instructions
387system.cpu0.num_fp_insts 5449 # number of float instructions
388system.cpu0.num_int_register_reads 179913159 # number of times the integer registers were read
389system.cpu0.num_int_register_writes 36837171 # number of times the integer registers were written
390system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read
391system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written
392system.cpu0.num_mem_refs 14629859 # number of memory refs
393system.cpu0.num_load_insts 8359235 # Number of load instructions
394system.cpu0.num_store_insts 6270624 # Number of store instructions
395system.cpu0.num_idle_cycles 1783997876.499954 # Number of idle cycles
396system.cpu0.num_busy_cycles 39676799.500046 # Number of busy cycles
397system.cpu0.not_idle_fraction 0.021757 # Percentage of non-idle cycles
398system.cpu0.idle_fraction 0.978243 # Percentage of idle cycles
399system.cpu0.Branches 5492144 # Number of branches fetched
|
| 400system.cpu0.op_class::No_OpClass 16326 0.04% 0.04% # Class of executed instruction
401system.cpu0.op_class::IntAlu 24520115 62.53% 62.57% # Class of executed instruction
402system.cpu0.op_class::IntMult 45259 0.12% 62.69% # Class of executed instruction
403system.cpu0.op_class::IntDiv 0 0.00% 62.69% # Class of executed instruction
404system.cpu0.op_class::FloatAdd 0 0.00% 62.69% # Class of executed instruction
405system.cpu0.op_class::FloatCmp 0 0.00% 62.69% # Class of executed instruction
406system.cpu0.op_class::FloatCvt 0 0.00% 62.69% # Class of executed instruction
407system.cpu0.op_class::FloatMult 0 0.00% 62.69% # Class of executed instruction
408system.cpu0.op_class::FloatDiv 0 0.00% 62.69% # Class of executed instruction
409system.cpu0.op_class::FloatSqrt 0 0.00% 62.69% # Class of executed instruction
410system.cpu0.op_class::SimdAdd 0 0.00% 62.69% # Class of executed instruction
411system.cpu0.op_class::SimdAddAcc 0 0.00% 62.69% # Class of executed instruction
412system.cpu0.op_class::SimdAlu 0 0.00% 62.69% # Class of executed instruction
413system.cpu0.op_class::SimdCmp 0 0.00% 62.69% # Class of executed instruction
414system.cpu0.op_class::SimdCvt 0 0.00% 62.69% # Class of executed instruction
415system.cpu0.op_class::SimdMisc 0 0.00% 62.69% # Class of executed instruction
416system.cpu0.op_class::SimdMult 0 0.00% 62.69% # Class of executed instruction
417system.cpu0.op_class::SimdMultAcc 0 0.00% 62.69% # Class of executed instruction
418system.cpu0.op_class::SimdShift 0 0.00% 62.69% # Class of executed instruction
419system.cpu0.op_class::SimdShiftAcc 0 0.00% 62.69% # Class of executed instruction
420system.cpu0.op_class::SimdSqrt 0 0.00% 62.69% # Class of executed instruction
421system.cpu0.op_class::SimdFloatAdd 0 0.00% 62.69% # Class of executed instruction
422system.cpu0.op_class::SimdFloatAlu 0 0.00% 62.69% # Class of executed instruction
423system.cpu0.op_class::SimdFloatCmp 0 0.00% 62.69% # Class of executed instruction
424system.cpu0.op_class::SimdFloatCvt 0 0.00% 62.69% # Class of executed instruction
425system.cpu0.op_class::SimdFloatDiv 0 0.00% 62.69% # Class of executed instruction
426system.cpu0.op_class::SimdFloatMisc 1421 0.00% 62.69% # Class of executed instruction
427system.cpu0.op_class::SimdFloatMult 0 0.00% 62.69% # Class of executed instruction
428system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 62.69% # Class of executed instruction
429system.cpu0.op_class::SimdFloatSqrt 0 0.00% 62.69% # Class of executed instruction
430system.cpu0.op_class::MemRead 8359235 21.32% 84.01% # Class of executed instruction
431system.cpu0.op_class::MemWrite 6270624 15.99% 100.00% # Class of executed instruction
432system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
433system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
434system.cpu0.op_class::total 39212980 # Class of executed instruction
|
400system.cpu0.kern.inst.arm 0 # number of arm instructions executed
401system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed
402system.cpu0.icache.tags.replacements 428546 # number of replacements
403system.cpu0.icache.tags.tagsinuse 511.014878 # Cycle average of tags in use
404system.cpu0.icache.tags.total_refs 29820919 # Total number of references to valid blocks.
405system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks.
406system.cpu0.icache.tags.avg_refs 69.503235 # Average number of references to valid blocks.
407system.cpu0.icache.tags.warmup_cycle 64538774500 # Cycle when the warmup percentage was hit.
408system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.014878 # Average occupied blocks per requestor
409system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy
410system.cpu0.icache.tags.occ_percent::total 0.998076 # Average percentage of cache occupancy
411system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
412system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id
413system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
414system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
415system.cpu0.icache.tags.tag_accesses 30679037 # Number of tag accesses
416system.cpu0.icache.tags.data_accesses 30679037 # Number of data accesses
417system.cpu0.icache.ReadReq_hits::cpu0.inst 29820919 # number of ReadReq hits
418system.cpu0.icache.ReadReq_hits::total 29820919 # number of ReadReq hits
419system.cpu0.icache.demand_hits::cpu0.inst 29820919 # number of demand (read+write) hits
420system.cpu0.icache.demand_hits::total 29820919 # number of demand (read+write) hits
421system.cpu0.icache.overall_hits::cpu0.inst 29820919 # number of overall hits
422system.cpu0.icache.overall_hits::total 29820919 # number of overall hits
423system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses
424system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses
425system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses
426system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses
427system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses
428system.cpu0.icache.overall_misses::total 429059 # number of overall misses
429system.cpu0.icache.ReadReq_accesses::cpu0.inst 30249978 # number of ReadReq accesses(hits+misses)
430system.cpu0.icache.ReadReq_accesses::total 30249978 # number of ReadReq accesses(hits+misses)
431system.cpu0.icache.demand_accesses::cpu0.inst 30249978 # number of demand (read+write) accesses
432system.cpu0.icache.demand_accesses::total 30249978 # number of demand (read+write) accesses
433system.cpu0.icache.overall_accesses::cpu0.inst 30249978 # number of overall (read+write) accesses
434system.cpu0.icache.overall_accesses::total 30249978 # number of overall (read+write) accesses
435system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014184 # miss rate for ReadReq accesses
436system.cpu0.icache.ReadReq_miss_rate::total 0.014184 # miss rate for ReadReq accesses
437system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014184 # miss rate for demand accesses
438system.cpu0.icache.demand_miss_rate::total 0.014184 # miss rate for demand accesses
439system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014184 # miss rate for overall accesses
440system.cpu0.icache.overall_miss_rate::total 0.014184 # miss rate for overall accesses
441system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
442system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
443system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
444system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
445system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
446system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
447system.cpu0.icache.fast_writes 0 # number of fast writes performed
448system.cpu0.icache.cache_copies 0 # number of cache copies performed
449system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
450system.cpu0.dcache.tags.replacements 323608 # number of replacements
451system.cpu0.dcache.tags.tagsinuse 494.763142 # Cycle average of tags in use
452system.cpu0.dcache.tags.total_refs 12469968 # Total number of references to valid blocks.
453system.cpu0.dcache.tags.sampled_refs 323980 # Sample count of references to valid blocks.
454system.cpu0.dcache.tags.avg_refs 38.489931 # Average number of references to valid blocks.
455system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit.
456system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763142 # Average occupied blocks per requestor
457system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy
458system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy
459system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id
460system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id
461system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id
462system.cpu0.dcache.tags.tag_accesses 51685336 # Number of tag accesses
463system.cpu0.dcache.tags.data_accesses 51685336 # Number of data accesses
464system.cpu0.dcache.ReadReq_hits::cpu0.data 6513975 # number of ReadReq hits
465system.cpu0.dcache.ReadReq_hits::total 6513975 # number of ReadReq hits
466system.cpu0.dcache.WriteReq_hits::cpu0.data 5631422 # number of WriteReq hits
467system.cpu0.dcache.WriteReq_hits::total 5631422 # number of WriteReq hits
468system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits
469system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits
470system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits
471system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits
472system.cpu0.dcache.demand_hits::cpu0.data 12145397 # number of demand (read+write) hits
473system.cpu0.dcache.demand_hits::total 12145397 # number of demand (read+write) hits
474system.cpu0.dcache.overall_hits::cpu0.data 12145397 # number of overall hits
475system.cpu0.dcache.overall_hits::total 12145397 # number of overall hits
476system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses
477system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses
478system.cpu0.dcache.WriteReq_misses::cpu0.data 167350 # number of WriteReq misses
479system.cpu0.dcache.WriteReq_misses::total 167350 # number of WriteReq misses
480system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses
481system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses
482system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses
483system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses
484system.cpu0.dcache.demand_misses::cpu0.data 364517 # number of demand (read+write) misses
485system.cpu0.dcache.demand_misses::total 364517 # number of demand (read+write) misses
486system.cpu0.dcache.overall_misses::cpu0.data 364517 # number of overall misses
487system.cpu0.dcache.overall_misses::total 364517 # number of overall misses
488system.cpu0.dcache.ReadReq_accesses::cpu0.data 6711142 # number of ReadReq accesses(hits+misses)
489system.cpu0.dcache.ReadReq_accesses::total 6711142 # number of ReadReq accesses(hits+misses)
490system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798772 # number of WriteReq accesses(hits+misses)
491system.cpu0.dcache.WriteReq_accesses::total 5798772 # number of WriteReq accesses(hits+misses)
492system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses)
493system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses)
494system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses)
495system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses)
496system.cpu0.dcache.demand_accesses::cpu0.data 12509914 # number of demand (read+write) accesses
497system.cpu0.dcache.demand_accesses::total 12509914 # number of demand (read+write) accesses
498system.cpu0.dcache.overall_accesses::cpu0.data 12509914 # number of overall (read+write) accesses
499system.cpu0.dcache.overall_accesses::total 12509914 # number of overall (read+write) accesses
500system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029379 # miss rate for ReadReq accesses
501system.cpu0.dcache.ReadReq_miss_rate::total 0.029379 # miss rate for ReadReq accesses
502system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028860 # miss rate for WriteReq accesses
503system.cpu0.dcache.WriteReq_miss_rate::total 0.028860 # miss rate for WriteReq accesses
504system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses
505system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses
506system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses
507system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses
508system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029138 # miss rate for demand accesses
509system.cpu0.dcache.demand_miss_rate::total 0.029138 # miss rate for demand accesses
510system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029138 # miss rate for overall accesses
511system.cpu0.dcache.overall_miss_rate::total 0.029138 # miss rate for overall accesses
512system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
513system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
514system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
515system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
516system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
517system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
518system.cpu0.dcache.fast_writes 0 # number of fast writes performed
519system.cpu0.dcache.cache_copies 0 # number of cache copies performed
520system.cpu0.dcache.writebacks::writebacks 300957 # number of writebacks
521system.cpu0.dcache.writebacks::total 300957 # number of writebacks
522system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
523system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
524system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
525system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
526system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
527system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
528system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
529system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
530system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
531system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
532system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
533system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
534system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
535system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
536system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
537system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
538system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
539system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
540system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
541system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
542system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
543system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
544system.cpu1.dtb.inst_hits 0 # ITB inst hits
545system.cpu1.dtb.inst_misses 0 # ITB inst misses
546system.cpu1.dtb.read_hits 7365100 # DTB read hits
547system.cpu1.dtb.read_misses 3705 # DTB read misses
548system.cpu1.dtb.write_hits 5489754 # DTB write hits
549system.cpu1.dtb.write_misses 1595 # DTB write misses
550system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
551system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
552system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
553system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
554system.cpu1.dtb.flush_entries 1696 # Number of entries that have been flushed from TLB
555system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
556system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch
557system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
558system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
559system.cpu1.dtb.read_accesses 7368805 # DTB read accesses
560system.cpu1.dtb.write_accesses 5491349 # DTB write accesses
561system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
562system.cpu1.dtb.hits 12854854 # DTB hits
563system.cpu1.dtb.misses 5300 # DTB misses
564system.cpu1.dtb.accesses 12860154 # DTB accesses
565system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
566system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
567system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
568system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
569system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
570system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
571system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
572system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
573system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
574system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
575system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
576system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
577system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
578system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
579system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
580system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
581system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
582system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
583system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
584system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
585system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
586system.cpu1.itb.inst_hits 32413691 # ITB inst hits
587system.cpu1.itb.inst_misses 2200 # ITB inst misses
588system.cpu1.itb.read_hits 0 # DTB read hits
589system.cpu1.itb.read_misses 0 # DTB read misses
590system.cpu1.itb.write_hits 0 # DTB write hits
591system.cpu1.itb.write_misses 0 # DTB write misses
592system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
593system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
594system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
595system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
596system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB
597system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
598system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
599system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
600system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
601system.cpu1.itb.read_accesses 0 # DTB read accesses
602system.cpu1.itb.write_accesses 0 # DTB write accesses
603system.cpu1.itb.inst_accesses 32415891 # ITB inst accesses
604system.cpu1.itb.hits 32413691 # DTB hits
605system.cpu1.itb.misses 2200 # DTB misses
606system.cpu1.itb.accesses 32415891 # DTB accesses
607system.cpu1.numCycles 1824196797 # number of cpu cycles simulated
608system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
609system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
610system.cpu1.committedInsts 31877311 # Number of instructions committed
611system.cpu1.committedOps 40215396 # Number of ops (including micro ops) committed
612system.cpu1.num_int_alu_accesses 35862250 # Number of integer alu accesses
613system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses
614system.cpu1.num_func_calls 955425 # number of times a function call or return occured
615system.cpu1.num_conditional_control_insts 4048275 # number of instructions that are conditional controls
616system.cpu1.num_int_insts 35862250 # number of integer instructions
617system.cpu1.num_fp_insts 4436 # number of float instructions
618system.cpu1.num_int_register_reads 183631460 # number of times the integer registers were read
619system.cpu1.num_int_register_writes 39072446 # number of times the integer registers were written
620system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read
621system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written
622system.cpu1.num_mem_refs 13371151 # number of memory refs
623system.cpu1.num_load_insts 7642991 # Number of load instructions
624system.cpu1.num_store_insts 5728160 # Number of store instructions
625system.cpu1.num_idle_cycles 1783402877.755682 # Number of idle cycles
626system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles
627system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles
628system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles
629system.cpu1.Branches 5037975 # Number of branches fetched
| 435system.cpu0.kern.inst.arm 0 # number of arm instructions executed
436system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed
437system.cpu0.icache.tags.replacements 428546 # number of replacements
438system.cpu0.icache.tags.tagsinuse 511.014878 # Cycle average of tags in use
439system.cpu0.icache.tags.total_refs 29820919 # Total number of references to valid blocks.
440system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks.
441system.cpu0.icache.tags.avg_refs 69.503235 # Average number of references to valid blocks.
442system.cpu0.icache.tags.warmup_cycle 64538774500 # Cycle when the warmup percentage was hit.
443system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.014878 # Average occupied blocks per requestor
444system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy
445system.cpu0.icache.tags.occ_percent::total 0.998076 # Average percentage of cache occupancy
446system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
447system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id
448system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
449system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
450system.cpu0.icache.tags.tag_accesses 30679037 # Number of tag accesses
451system.cpu0.icache.tags.data_accesses 30679037 # Number of data accesses
452system.cpu0.icache.ReadReq_hits::cpu0.inst 29820919 # number of ReadReq hits
453system.cpu0.icache.ReadReq_hits::total 29820919 # number of ReadReq hits
454system.cpu0.icache.demand_hits::cpu0.inst 29820919 # number of demand (read+write) hits
455system.cpu0.icache.demand_hits::total 29820919 # number of demand (read+write) hits
456system.cpu0.icache.overall_hits::cpu0.inst 29820919 # number of overall hits
457system.cpu0.icache.overall_hits::total 29820919 # number of overall hits
458system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses
459system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses
460system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses
461system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses
462system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses
463system.cpu0.icache.overall_misses::total 429059 # number of overall misses
464system.cpu0.icache.ReadReq_accesses::cpu0.inst 30249978 # number of ReadReq accesses(hits+misses)
465system.cpu0.icache.ReadReq_accesses::total 30249978 # number of ReadReq accesses(hits+misses)
466system.cpu0.icache.demand_accesses::cpu0.inst 30249978 # number of demand (read+write) accesses
467system.cpu0.icache.demand_accesses::total 30249978 # number of demand (read+write) accesses
468system.cpu0.icache.overall_accesses::cpu0.inst 30249978 # number of overall (read+write) accesses
469system.cpu0.icache.overall_accesses::total 30249978 # number of overall (read+write) accesses
470system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014184 # miss rate for ReadReq accesses
471system.cpu0.icache.ReadReq_miss_rate::total 0.014184 # miss rate for ReadReq accesses
472system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014184 # miss rate for demand accesses
473system.cpu0.icache.demand_miss_rate::total 0.014184 # miss rate for demand accesses
474system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014184 # miss rate for overall accesses
475system.cpu0.icache.overall_miss_rate::total 0.014184 # miss rate for overall accesses
476system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
477system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
478system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
479system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
480system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
481system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
482system.cpu0.icache.fast_writes 0 # number of fast writes performed
483system.cpu0.icache.cache_copies 0 # number of cache copies performed
484system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
485system.cpu0.dcache.tags.replacements 323608 # number of replacements
486system.cpu0.dcache.tags.tagsinuse 494.763142 # Cycle average of tags in use
487system.cpu0.dcache.tags.total_refs 12469968 # Total number of references to valid blocks.
488system.cpu0.dcache.tags.sampled_refs 323980 # Sample count of references to valid blocks.
489system.cpu0.dcache.tags.avg_refs 38.489931 # Average number of references to valid blocks.
490system.cpu0.dcache.tags.warmup_cycle 22120000 # Cycle when the warmup percentage was hit.
491system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763142 # Average occupied blocks per requestor
492system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy
493system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy
494system.cpu0.dcache.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id
495system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id
496system.cpu0.dcache.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id
497system.cpu0.dcache.tags.tag_accesses 51685336 # Number of tag accesses
498system.cpu0.dcache.tags.data_accesses 51685336 # Number of data accesses
499system.cpu0.dcache.ReadReq_hits::cpu0.data 6513975 # number of ReadReq hits
500system.cpu0.dcache.ReadReq_hits::total 6513975 # number of ReadReq hits
501system.cpu0.dcache.WriteReq_hits::cpu0.data 5631422 # number of WriteReq hits
502system.cpu0.dcache.WriteReq_hits::total 5631422 # number of WriteReq hits
503system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151763 # number of LoadLockedReq hits
504system.cpu0.dcache.LoadLockedReq_hits::total 151763 # number of LoadLockedReq hits
505system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits
506system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits
507system.cpu0.dcache.demand_hits::cpu0.data 12145397 # number of demand (read+write) hits
508system.cpu0.dcache.demand_hits::total 12145397 # number of demand (read+write) hits
509system.cpu0.dcache.overall_hits::cpu0.data 12145397 # number of overall hits
510system.cpu0.dcache.overall_hits::total 12145397 # number of overall hits
511system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses
512system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses
513system.cpu0.dcache.WriteReq_misses::cpu0.data 167350 # number of WriteReq misses
514system.cpu0.dcache.WriteReq_misses::total 167350 # number of WriteReq misses
515system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9208 # number of LoadLockedReq misses
516system.cpu0.dcache.LoadLockedReq_misses::total 9208 # number of LoadLockedReq misses
517system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7466 # number of StoreCondReq misses
518system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses
519system.cpu0.dcache.demand_misses::cpu0.data 364517 # number of demand (read+write) misses
520system.cpu0.dcache.demand_misses::total 364517 # number of demand (read+write) misses
521system.cpu0.dcache.overall_misses::cpu0.data 364517 # number of overall misses
522system.cpu0.dcache.overall_misses::total 364517 # number of overall misses
523system.cpu0.dcache.ReadReq_accesses::cpu0.data 6711142 # number of ReadReq accesses(hits+misses)
524system.cpu0.dcache.ReadReq_accesses::total 6711142 # number of ReadReq accesses(hits+misses)
525system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798772 # number of WriteReq accesses(hits+misses)
526system.cpu0.dcache.WriteReq_accesses::total 5798772 # number of WriteReq accesses(hits+misses)
527system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160971 # number of LoadLockedReq accesses(hits+misses)
528system.cpu0.dcache.LoadLockedReq_accesses::total 160971 # number of LoadLockedReq accesses(hits+misses)
529system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160646 # number of StoreCondReq accesses(hits+misses)
530system.cpu0.dcache.StoreCondReq_accesses::total 160646 # number of StoreCondReq accesses(hits+misses)
531system.cpu0.dcache.demand_accesses::cpu0.data 12509914 # number of demand (read+write) accesses
532system.cpu0.dcache.demand_accesses::total 12509914 # number of demand (read+write) accesses
533system.cpu0.dcache.overall_accesses::cpu0.data 12509914 # number of overall (read+write) accesses
534system.cpu0.dcache.overall_accesses::total 12509914 # number of overall (read+write) accesses
535system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029379 # miss rate for ReadReq accesses
536system.cpu0.dcache.ReadReq_miss_rate::total 0.029379 # miss rate for ReadReq accesses
537system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028860 # miss rate for WriteReq accesses
538system.cpu0.dcache.WriteReq_miss_rate::total 0.028860 # miss rate for WriteReq accesses
539system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057203 # miss rate for LoadLockedReq accesses
540system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.057203 # miss rate for LoadLockedReq accesses
541system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046475 # miss rate for StoreCondReq accesses
542system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046475 # miss rate for StoreCondReq accesses
543system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029138 # miss rate for demand accesses
544system.cpu0.dcache.demand_miss_rate::total 0.029138 # miss rate for demand accesses
545system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029138 # miss rate for overall accesses
546system.cpu0.dcache.overall_miss_rate::total 0.029138 # miss rate for overall accesses
547system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
548system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
549system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
550system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
551system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
552system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
553system.cpu0.dcache.fast_writes 0 # number of fast writes performed
554system.cpu0.dcache.cache_copies 0 # number of cache copies performed
555system.cpu0.dcache.writebacks::writebacks 300957 # number of writebacks
556system.cpu0.dcache.writebacks::total 300957 # number of writebacks
557system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
558system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
559system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
560system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
561system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
562system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
563system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
564system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
565system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
566system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
567system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
568system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
569system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
570system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
571system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
572system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
573system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
574system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
575system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
576system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
577system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
578system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
579system.cpu1.dtb.inst_hits 0 # ITB inst hits
580system.cpu1.dtb.inst_misses 0 # ITB inst misses
581system.cpu1.dtb.read_hits 7365100 # DTB read hits
582system.cpu1.dtb.read_misses 3705 # DTB read misses
583system.cpu1.dtb.write_hits 5489754 # DTB write hits
584system.cpu1.dtb.write_misses 1595 # DTB write misses
585system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
586system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
587system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
588system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
589system.cpu1.dtb.flush_entries 1696 # Number of entries that have been flushed from TLB
590system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
591system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch
592system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
593system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
594system.cpu1.dtb.read_accesses 7368805 # DTB read accesses
595system.cpu1.dtb.write_accesses 5491349 # DTB write accesses
596system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
597system.cpu1.dtb.hits 12854854 # DTB hits
598system.cpu1.dtb.misses 5300 # DTB misses
599system.cpu1.dtb.accesses 12860154 # DTB accesses
600system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
601system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
602system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
603system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
604system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
605system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
606system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
607system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
608system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
609system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
610system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
611system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
612system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
613system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
614system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
615system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
616system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
617system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
618system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
619system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
620system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
621system.cpu1.itb.inst_hits 32413691 # ITB inst hits
622system.cpu1.itb.inst_misses 2200 # ITB inst misses
623system.cpu1.itb.read_hits 0 # DTB read hits
624system.cpu1.itb.read_misses 0 # DTB read misses
625system.cpu1.itb.write_hits 0 # DTB write hits
626system.cpu1.itb.write_misses 0 # DTB write misses
627system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
628system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
629system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
630system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
631system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB
632system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
633system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
634system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
635system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
636system.cpu1.itb.read_accesses 0 # DTB read accesses
637system.cpu1.itb.write_accesses 0 # DTB write accesses
638system.cpu1.itb.inst_accesses 32415891 # ITB inst accesses
639system.cpu1.itb.hits 32413691 # DTB hits
640system.cpu1.itb.misses 2200 # DTB misses
641system.cpu1.itb.accesses 32415891 # DTB accesses
642system.cpu1.numCycles 1824196797 # number of cpu cycles simulated
643system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
644system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
645system.cpu1.committedInsts 31877311 # Number of instructions committed
646system.cpu1.committedOps 40215396 # Number of ops (including micro ops) committed
647system.cpu1.num_int_alu_accesses 35862250 # Number of integer alu accesses
648system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses
649system.cpu1.num_func_calls 955425 # number of times a function call or return occured
650system.cpu1.num_conditional_control_insts 4048275 # number of instructions that are conditional controls
651system.cpu1.num_int_insts 35862250 # number of integer instructions
652system.cpu1.num_fp_insts 4436 # number of float instructions
653system.cpu1.num_int_register_reads 183631460 # number of times the integer registers were read
654system.cpu1.num_int_register_writes 39072446 # number of times the integer registers were written
655system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read
656system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written
657system.cpu1.num_mem_refs 13371151 # number of memory refs
658system.cpu1.num_load_insts 7642991 # Number of load instructions
659system.cpu1.num_store_insts 5728160 # Number of store instructions
660system.cpu1.num_idle_cycles 1783402877.755682 # Number of idle cycles
661system.cpu1.num_busy_cycles 40793919.244318 # Number of busy cycles
662system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles
663system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles
664system.cpu1.Branches 5037975 # Number of branches fetched
|
| 665system.cpu1.op_class::No_OpClass 12508 0.03% 0.03% # Class of executed instruction
666system.cpu1.op_class::IntAlu 26844895 66.65% 66.68% # Class of executed instruction
667system.cpu1.op_class::IntMult 49628 0.12% 66.80% # Class of executed instruction
668system.cpu1.op_class::IntDiv 0 0.00% 66.80% # Class of executed instruction
669system.cpu1.op_class::FloatAdd 0 0.00% 66.80% # Class of executed instruction
670system.cpu1.op_class::FloatCmp 0 0.00% 66.80% # Class of executed instruction
671system.cpu1.op_class::FloatCvt 0 0.00% 66.80% # Class of executed instruction
672system.cpu1.op_class::FloatMult 0 0.00% 66.80% # Class of executed instruction
673system.cpu1.op_class::FloatDiv 0 0.00% 66.80% # Class of executed instruction
674system.cpu1.op_class::FloatSqrt 0 0.00% 66.80% # Class of executed instruction
675system.cpu1.op_class::SimdAdd 0 0.00% 66.80% # Class of executed instruction
676system.cpu1.op_class::SimdAddAcc 0 0.00% 66.80% # Class of executed instruction
677system.cpu1.op_class::SimdAlu 0 0.00% 66.80% # Class of executed instruction
678system.cpu1.op_class::SimdCmp 0 0.00% 66.80% # Class of executed instruction
679system.cpu1.op_class::SimdCvt 0 0.00% 66.80% # Class of executed instruction
680system.cpu1.op_class::SimdMisc 0 0.00% 66.80% # Class of executed instruction
681system.cpu1.op_class::SimdMult 0 0.00% 66.80% # Class of executed instruction
682system.cpu1.op_class::SimdMultAcc 0 0.00% 66.80% # Class of executed instruction
683system.cpu1.op_class::SimdShift 0 0.00% 66.80% # Class of executed instruction
684system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.80% # Class of executed instruction
685system.cpu1.op_class::SimdSqrt 0 0.00% 66.80% # Class of executed instruction
686system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.80% # Class of executed instruction
687system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.80% # Class of executed instruction
688system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.80% # Class of executed instruction
689system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.80% # Class of executed instruction
690system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.80% # Class of executed instruction
691system.cpu1.op_class::SimdFloatMisc 737 0.00% 66.80% # Class of executed instruction
692system.cpu1.op_class::SimdFloatMult 0 0.00% 66.80% # Class of executed instruction
693system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.80% # Class of executed instruction
694system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.80% # Class of executed instruction
695system.cpu1.op_class::MemRead 7642991 18.98% 85.78% # Class of executed instruction
696system.cpu1.op_class::MemWrite 5728160 14.22% 100.00% # Class of executed instruction
697system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
698system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
699system.cpu1.op_class::total 40278919 # Class of executed instruction
|
630system.cpu1.kern.inst.arm 0 # number of arm instructions executed
631system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed
632system.cpu1.icache.tags.replacements 433942 # number of replacements
633system.cpu1.icache.tags.tagsinuse 475.447061 # Cycle average of tags in use
634system.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks.
635system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks.
636system.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks.
637system.cpu1.icache.tags.warmup_cycle 69969391500 # Cycle when the warmup percentage was hit.
638system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447061 # Average occupied blocks per requestor
639system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928608 # Average percentage of cache occupancy
640system.cpu1.icache.tags.occ_percent::total 0.928608 # Average percentage of cache occupancy
641system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
642system.cpu1.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
643system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
644system.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id
645system.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
646system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
647system.cpu1.icache.tags.tag_accesses 32849418 # Number of tag accesses
648system.cpu1.icache.tags.data_accesses 32849418 # Number of data accesses
649system.cpu1.icache.ReadReq_hits::cpu1.inst 31980510 # number of ReadReq hits
650system.cpu1.icache.ReadReq_hits::total 31980510 # number of ReadReq hits
651system.cpu1.icache.demand_hits::cpu1.inst 31980510 # number of demand (read+write) hits
652system.cpu1.icache.demand_hits::total 31980510 # number of demand (read+write) hits
653system.cpu1.icache.overall_hits::cpu1.inst 31980510 # number of overall hits
654system.cpu1.icache.overall_hits::total 31980510 # number of overall hits
655system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses
656system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses
657system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses
658system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses
659system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses
660system.cpu1.icache.overall_misses::total 434454 # number of overall misses
661system.cpu1.icache.ReadReq_accesses::cpu1.inst 32414964 # number of ReadReq accesses(hits+misses)
662system.cpu1.icache.ReadReq_accesses::total 32414964 # number of ReadReq accesses(hits+misses)
663system.cpu1.icache.demand_accesses::cpu1.inst 32414964 # number of demand (read+write) accesses
664system.cpu1.icache.demand_accesses::total 32414964 # number of demand (read+write) accesses
665system.cpu1.icache.overall_accesses::cpu1.inst 32414964 # number of overall (read+write) accesses
666system.cpu1.icache.overall_accesses::total 32414964 # number of overall (read+write) accesses
667system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses
668system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses
669system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses
670system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses
671system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses
672system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses
673system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
674system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
675system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
676system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
677system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
678system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
679system.cpu1.icache.fast_writes 0 # number of fast writes performed
680system.cpu1.icache.cache_copies 0 # number of cache copies performed
681system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
682system.cpu1.dcache.tags.replacements 294289 # number of replacements
683system.cpu1.dcache.tags.tagsinuse 447.572964 # Cycle average of tags in use
684system.cpu1.dcache.tags.total_refs 11708149 # Total number of references to valid blocks.
685system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks.
686system.cpu1.dcache.tags.avg_refs 39.715432 # Average number of references to valid blocks.
687system.cpu1.dcache.tags.warmup_cycle 67295121500 # Cycle when the warmup percentage was hit.
688system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.572964 # Average occupied blocks per requestor
689system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874166 # Average percentage of cache occupancy
690system.cpu1.dcache.tags.occ_percent::total 0.874166 # Average percentage of cache occupancy
691system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
692system.cpu1.dcache.tags.age_task_id_blocks_1024::0 267 # Occupied blocks per task id
693system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
694system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
695system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
696system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
697system.cpu1.dcache.tags.tag_accesses 48419346 # Number of tag accesses
698system.cpu1.dcache.tags.data_accesses 48419346 # Number of data accesses
699system.cpu1.dcache.ReadReq_hits::cpu1.data 7002504 # number of ReadReq hits
700system.cpu1.dcache.ReadReq_hits::total 7002504 # number of ReadReq hits
701system.cpu1.dcache.WriteReq_hits::cpu1.data 4520263 # number of WriteReq hits
702system.cpu1.dcache.WriteReq_hits::total 4520263 # number of WriteReq hits
703system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits
704system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits
705system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits
706system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits
707system.cpu1.dcache.demand_hits::cpu1.data 11522767 # number of demand (read+write) hits
708system.cpu1.dcache.demand_hits::total 11522767 # number of demand (read+write) hits
709system.cpu1.dcache.overall_hits::cpu1.data 11522767 # number of overall hits
710system.cpu1.dcache.overall_hits::total 11522767 # number of overall hits
711system.cpu1.dcache.ReadReq_misses::cpu1.data 198274 # number of ReadReq misses
712system.cpu1.dcache.ReadReq_misses::total 198274 # number of ReadReq misses
713system.cpu1.dcache.WriteReq_misses::cpu1.data 126068 # number of WriteReq misses
714system.cpu1.dcache.WriteReq_misses::total 126068 # number of WriteReq misses
715system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses
716system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses
717system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses
718system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses
719system.cpu1.dcache.demand_misses::cpu1.data 324342 # number of demand (read+write) misses
720system.cpu1.dcache.demand_misses::total 324342 # number of demand (read+write) misses
721system.cpu1.dcache.overall_misses::cpu1.data 324342 # number of overall misses
722system.cpu1.dcache.overall_misses::total 324342 # number of overall misses
723system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses)
724system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses)
725system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses)
726system.cpu1.dcache.WriteReq_accesses::total 4646331 # number of WriteReq accesses(hits+misses)
727system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89227 # number of LoadLockedReq accesses(hits+misses)
728system.cpu1.dcache.LoadLockedReq_accesses::total 89227 # number of LoadLockedReq accesses(hits+misses)
729system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses)
730system.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses)
731system.cpu1.dcache.demand_accesses::cpu1.data 11847109 # number of demand (read+write) accesses
732system.cpu1.dcache.demand_accesses::total 11847109 # number of demand (read+write) accesses
733system.cpu1.dcache.overall_accesses::cpu1.data 11847109 # number of overall (read+write) accesses
734system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses
735system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses
736system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses
737system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027133 # miss rate for WriteReq accesses
738system.cpu1.dcache.WriteReq_miss_rate::total 0.027133 # miss rate for WriteReq accesses
739system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses
740system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses
741system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses
742system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses
743system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027377 # miss rate for demand accesses
744system.cpu1.dcache.demand_miss_rate::total 0.027377 # miss rate for demand accesses
745system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027377 # miss rate for overall accesses
746system.cpu1.dcache.overall_miss_rate::total 0.027377 # miss rate for overall accesses
747system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
748system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
749system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
750system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
751system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
752system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
753system.cpu1.dcache.fast_writes 0 # number of fast writes performed
754system.cpu1.dcache.cache_copies 0 # number of cache copies performed
755system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks
756system.cpu1.dcache.writebacks::total 266849 # number of writebacks
757system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
758system.iocache.tags.replacements 0 # number of replacements
759system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
760system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
761system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
762system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
763system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
764system.iocache.tags.tag_accesses 0 # Number of tag accesses
765system.iocache.tags.data_accesses 0 # Number of data accesses
766system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
767system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
768system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
769system.iocache.blocked::no_targets 0 # number of cycles access was blocked
770system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
771system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
772system.iocache.fast_writes 0 # number of fast writes performed
773system.iocache.cache_copies 0 # number of cache copies performed
774system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
775
776---------- End Simulation Statistics ----------
| 700system.cpu1.kern.inst.arm 0 # number of arm instructions executed
701system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed
702system.cpu1.icache.tags.replacements 433942 # number of replacements
703system.cpu1.icache.tags.tagsinuse 475.447061 # Cycle average of tags in use
704system.cpu1.icache.tags.total_refs 31980510 # Total number of references to valid blocks.
705system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks.
706system.cpu1.icache.tags.avg_refs 73.610808 # Average number of references to valid blocks.
707system.cpu1.icache.tags.warmup_cycle 69969391500 # Cycle when the warmup percentage was hit.
708system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447061 # Average occupied blocks per requestor
709system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928608 # Average percentage of cache occupancy
710system.cpu1.icache.tags.occ_percent::total 0.928608 # Average percentage of cache occupancy
711system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
712system.cpu1.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
713system.cpu1.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
714system.cpu1.icache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id
715system.cpu1.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
716system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
717system.cpu1.icache.tags.tag_accesses 32849418 # Number of tag accesses
718system.cpu1.icache.tags.data_accesses 32849418 # Number of data accesses
719system.cpu1.icache.ReadReq_hits::cpu1.inst 31980510 # number of ReadReq hits
720system.cpu1.icache.ReadReq_hits::total 31980510 # number of ReadReq hits
721system.cpu1.icache.demand_hits::cpu1.inst 31980510 # number of demand (read+write) hits
722system.cpu1.icache.demand_hits::total 31980510 # number of demand (read+write) hits
723system.cpu1.icache.overall_hits::cpu1.inst 31980510 # number of overall hits
724system.cpu1.icache.overall_hits::total 31980510 # number of overall hits
725system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses
726system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses
727system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses
728system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses
729system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses
730system.cpu1.icache.overall_misses::total 434454 # number of overall misses
731system.cpu1.icache.ReadReq_accesses::cpu1.inst 32414964 # number of ReadReq accesses(hits+misses)
732system.cpu1.icache.ReadReq_accesses::total 32414964 # number of ReadReq accesses(hits+misses)
733system.cpu1.icache.demand_accesses::cpu1.inst 32414964 # number of demand (read+write) accesses
734system.cpu1.icache.demand_accesses::total 32414964 # number of demand (read+write) accesses
735system.cpu1.icache.overall_accesses::cpu1.inst 32414964 # number of overall (read+write) accesses
736system.cpu1.icache.overall_accesses::total 32414964 # number of overall (read+write) accesses
737system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses
738system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses
739system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses
740system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses
741system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses
742system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses
743system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
744system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
745system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
746system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
747system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
748system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
749system.cpu1.icache.fast_writes 0 # number of fast writes performed
750system.cpu1.icache.cache_copies 0 # number of cache copies performed
751system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
752system.cpu1.dcache.tags.replacements 294289 # number of replacements
753system.cpu1.dcache.tags.tagsinuse 447.572964 # Cycle average of tags in use
754system.cpu1.dcache.tags.total_refs 11708149 # Total number of references to valid blocks.
755system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks.
756system.cpu1.dcache.tags.avg_refs 39.715432 # Average number of references to valid blocks.
757system.cpu1.dcache.tags.warmup_cycle 67295121500 # Cycle when the warmup percentage was hit.
758system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.572964 # Average occupied blocks per requestor
759system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874166 # Average percentage of cache occupancy
760system.cpu1.dcache.tags.occ_percent::total 0.874166 # Average percentage of cache occupancy
761system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
762system.cpu1.dcache.tags.age_task_id_blocks_1024::0 267 # Occupied blocks per task id
763system.cpu1.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
764system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
765system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
766system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
767system.cpu1.dcache.tags.tag_accesses 48419346 # Number of tag accesses
768system.cpu1.dcache.tags.data_accesses 48419346 # Number of data accesses
769system.cpu1.dcache.ReadReq_hits::cpu1.data 7002504 # number of ReadReq hits
770system.cpu1.dcache.ReadReq_hits::total 7002504 # number of ReadReq hits
771system.cpu1.dcache.WriteReq_hits::cpu1.data 4520263 # number of WriteReq hits
772system.cpu1.dcache.WriteReq_hits::total 4520263 # number of WriteReq hits
773system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77967 # number of LoadLockedReq hits
774system.cpu1.dcache.LoadLockedReq_hits::total 77967 # number of LoadLockedReq hits
775system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits
776system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits
777system.cpu1.dcache.demand_hits::cpu1.data 11522767 # number of demand (read+write) hits
778system.cpu1.dcache.demand_hits::total 11522767 # number of demand (read+write) hits
779system.cpu1.dcache.overall_hits::cpu1.data 11522767 # number of overall hits
780system.cpu1.dcache.overall_hits::total 11522767 # number of overall hits
781system.cpu1.dcache.ReadReq_misses::cpu1.data 198274 # number of ReadReq misses
782system.cpu1.dcache.ReadReq_misses::total 198274 # number of ReadReq misses
783system.cpu1.dcache.WriteReq_misses::cpu1.data 126068 # number of WriteReq misses
784system.cpu1.dcache.WriteReq_misses::total 126068 # number of WriteReq misses
785system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11260 # number of LoadLockedReq misses
786system.cpu1.dcache.LoadLockedReq_misses::total 11260 # number of LoadLockedReq misses
787system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10133 # number of StoreCondReq misses
788system.cpu1.dcache.StoreCondReq_misses::total 10133 # number of StoreCondReq misses
789system.cpu1.dcache.demand_misses::cpu1.data 324342 # number of demand (read+write) misses
790system.cpu1.dcache.demand_misses::total 324342 # number of demand (read+write) misses
791system.cpu1.dcache.overall_misses::cpu1.data 324342 # number of overall misses
792system.cpu1.dcache.overall_misses::total 324342 # number of overall misses
793system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200778 # number of ReadReq accesses(hits+misses)
794system.cpu1.dcache.ReadReq_accesses::total 7200778 # number of ReadReq accesses(hits+misses)
795system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646331 # number of WriteReq accesses(hits+misses)
796system.cpu1.dcache.WriteReq_accesses::total 4646331 # number of WriteReq accesses(hits+misses)
797system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89227 # number of LoadLockedReq accesses(hits+misses)
798system.cpu1.dcache.LoadLockedReq_accesses::total 89227 # number of LoadLockedReq accesses(hits+misses)
799system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89163 # number of StoreCondReq accesses(hits+misses)
800system.cpu1.dcache.StoreCondReq_accesses::total 89163 # number of StoreCondReq accesses(hits+misses)
801system.cpu1.dcache.demand_accesses::cpu1.data 11847109 # number of demand (read+write) accesses
802system.cpu1.dcache.demand_accesses::total 11847109 # number of demand (read+write) accesses
803system.cpu1.dcache.overall_accesses::cpu1.data 11847109 # number of overall (read+write) accesses
804system.cpu1.dcache.overall_accesses::total 11847109 # number of overall (read+write) accesses
805system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027535 # miss rate for ReadReq accesses
806system.cpu1.dcache.ReadReq_miss_rate::total 0.027535 # miss rate for ReadReq accesses
807system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027133 # miss rate for WriteReq accesses
808system.cpu1.dcache.WriteReq_miss_rate::total 0.027133 # miss rate for WriteReq accesses
809system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126195 # miss rate for LoadLockedReq accesses
810system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126195 # miss rate for LoadLockedReq accesses
811system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113646 # miss rate for StoreCondReq accesses
812system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113646 # miss rate for StoreCondReq accesses
813system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027377 # miss rate for demand accesses
814system.cpu1.dcache.demand_miss_rate::total 0.027377 # miss rate for demand accesses
815system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027377 # miss rate for overall accesses
816system.cpu1.dcache.overall_miss_rate::total 0.027377 # miss rate for overall accesses
817system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
818system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
819system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
820system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
821system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
822system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
823system.cpu1.dcache.fast_writes 0 # number of fast writes performed
824system.cpu1.dcache.cache_copies 0 # number of cache copies performed
825system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks
826system.cpu1.dcache.writebacks::total 266849 # number of writebacks
827system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
828system.iocache.tags.replacements 0 # number of replacements
829system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
830system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
831system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
832system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
833system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
834system.iocache.tags.tag_accesses 0 # Number of tag accesses
835system.iocache.tags.data_accesses 0 # Number of data accesses
836system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
837system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
838system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
839system.iocache.blocked::no_targets 0 # number of cycles access was blocked
840system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
841system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
842system.iocache.fast_writes 0 # number of fast writes performed
843system.iocache.cache_copies 0 # number of cache copies performed
844system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
845
846---------- End Simulation Statistics ----------
|