1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.802883 # Number of seconds simulated
4sim_ticks 2802882797500 # Number of ticks simulated
5final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1600792 # Simulator instruction rate (inst/s)
8host_op_rate 1950541 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 30558377305 # Simulator tick rate (ticks/s)
10host_mem_usage 639316 # Number of bytes of host memory used
11host_seconds 91.72 # Real time elapsed on the host
12sim_insts 146828219 # Number of instructions simulated
13sim_ops 178907974 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.data 1081872 # Number of bytes read from this memory
22system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
23system.physmem.bytes_read::total 11758444 # Number of bytes read from this memory
--- 35 unchanged lines hidden (view full) ---
59system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu0.inst 395765 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::cpu0.data 3364156 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s)
64system.physmem.bw_total::cpu1.data 386000 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::total 7225250 # Total bandwidth to/from this memory (bytes/s)
67system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
68system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
69system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
70system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
71system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
72system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
73system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
74system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
75system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
76system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
77system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
78system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
79system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
80system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
81system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
82system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
83system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
84system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
85system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
86system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
87system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
88system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
89system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
90system.cf0.dma_write_txs 631 # Number of DMA write transactions.
91system.cpu_clk_domain.clock 500 # Clock period in ticks
92system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
93system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
94system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
95system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
96system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
97system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
98system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
99system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
113system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
114system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
115system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
116system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
117system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
118system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
119system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
120system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
121system.cpu0.dtb.walker.walks 7964 # Table walker walks requested
122system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors
123system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency
124system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency
125system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency
126system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
127system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
128system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
--- 23 unchanged lines hidden (view full) ---
152system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
153system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
154system.cpu0.dtb.read_accesses 20346565 # DTB read accesses
155system.cpu0.dtb.write_accesses 16392097 # DTB write accesses
156system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
157system.cpu0.dtb.hits 36730698 # DTB hits
158system.cpu0.dtb.misses 7964 # DTB misses
159system.cpu0.dtb.accesses 36738662 # DTB accesses
160system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
161system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
162system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
163system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
164system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
165system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
166system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
167system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
181system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
182system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
183system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
184system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
185system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
186system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
187system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
188system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
189system.cpu0.itb.walker.walks 3358 # Table walker walks requested
190system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors
191system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency
192system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency
193system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency
194system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
195system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
196system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
--- 23 unchanged lines hidden (view full) ---
220system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
221system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
222system.cpu0.itb.read_accesses 0 # DTB read accesses
223system.cpu0.itb.write_accesses 0 # DTB write accesses
224system.cpu0.itb.inst_accesses 97442513 # ITB inst accesses
225system.cpu0.itb.hits 97439155 # DTB hits
226system.cpu0.itb.misses 3358 # DTB misses
227system.cpu0.itb.accesses 97442513 # DTB accesses
228system.cpu0.numCycles 5605767562 # number of cpu cycles simulated
229system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
230system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
231system.cpu0.kern.inst.arm 0 # number of arm instructions executed
232system.cpu0.kern.inst.quiesce 1966 # number of quiesce instructions executed
233system.cpu0.committedInsts 95426725 # Number of instructions committed
234system.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed
235system.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses
--- 46 unchanged lines hidden (view full) ---
282system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
283system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
284system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
285system.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction
286system.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction
287system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
288system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
289system.cpu0.op_class::total 116881836 # Class of executed instruction
290system.cpu0.dcache.tags.replacements 693478 # number of replacements
291system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use
292system.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks.
293system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks.
294system.cpu0.dcache.tags.avg_refs 51.776416 # Average number of references to valid blocks.
295system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
296system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor
297system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
298system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy
299system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
300system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
301system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
302system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
303system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
304system.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses
305system.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses
306system.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits
307system.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits
308system.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits
309system.cpu0.dcache.WriteReq_hits::total 15690320 # number of WriteReq hits
310system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits
311system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits
312system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits
313system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits
--- 48 unchanged lines hidden (view full) ---
362system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
363system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
364system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
365system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
366system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
367system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
368system.cpu0.dcache.writebacks::writebacks 693478 # number of writebacks
369system.cpu0.dcache.writebacks::total 693478 # number of writebacks
370system.cpu0.icache.tags.replacements 1109639 # number of replacements
371system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use
372system.cpu0.icache.tags.total_refs 96331337 # Total number of references to valid blocks.
373system.cpu0.icache.tags.sampled_refs 1110151 # Sample count of references to valid blocks.
374system.cpu0.icache.tags.avg_refs 86.773184 # Average number of references to valid blocks.
375system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit.
376system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor
377system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy
378system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy
379system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
380system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
381system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
382system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
383system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
384system.cpu0.icache.tags.tag_accesses 195993154 # Number of tag accesses
385system.cpu0.icache.tags.data_accesses 195993154 # Number of data accesses
386system.cpu0.icache.ReadReq_hits::cpu0.inst 96331337 # number of ReadReq hits
387system.cpu0.icache.ReadReq_hits::total 96331337 # number of ReadReq hits
388system.cpu0.icache.demand_hits::cpu0.inst 96331337 # number of demand (read+write) hits
389system.cpu0.icache.demand_hits::total 96331337 # number of demand (read+write) hits
390system.cpu0.icache.overall_hits::cpu0.inst 96331337 # number of overall hits
391system.cpu0.icache.overall_hits::total 96331337 # number of overall hits
392system.cpu0.icache.ReadReq_misses::cpu0.inst 1110160 # number of ReadReq misses
393system.cpu0.icache.ReadReq_misses::total 1110160 # number of ReadReq misses
--- 16 unchanged lines hidden (view full) ---
410system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
411system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
412system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
413system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
414system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
415system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
416system.cpu0.icache.writebacks::writebacks 1109639 # number of writebacks
417system.cpu0.icache.writebacks::total 1109639 # number of writebacks
418system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
419system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
420system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
421system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
422system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
423system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
424system.cpu0.l2cache.tags.replacements 249747 # number of replacements
425system.cpu0.l2cache.tags.tagsinuse 16131.550435 # Cycle average of tags in use
426system.cpu0.l2cache.tags.total_refs 2729892 # Total number of references to valid blocks.
427system.cpu0.l2cache.tags.sampled_refs 265865 # Sample count of references to valid blocks.
428system.cpu0.l2cache.tags.avg_refs 10.267963 # Average number of references to valid blocks.
429system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit.
430system.cpu0.l2cache.tags.occ_blocks::writebacks 16129.097151 # Average occupied blocks per requestor
431system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.376905 # Average occupied blocks per requestor
--- 11 unchanged lines hidden (view full) ---
443system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id
444system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5562 # Occupied blocks per task id
445system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7431 # Occupied blocks per task id
446system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2624 # Occupied blocks per task id
447system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
448system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983276 # Percentage of cache occupancy per task id
449system.cpu0.l2cache.tags.tag_accesses 59696130 # Number of tag accesses
450system.cpu0.l2cache.tags.data_accesses 59696130 # Number of data accesses
451system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10179 # number of ReadReq hits
452system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4500 # number of ReadReq hits
453system.cpu0.l2cache.ReadReq_hits::total 14679 # number of ReadReq hits
454system.cpu0.l2cache.WritebackDirty_hits::writebacks 510228 # number of WritebackDirty hits
455system.cpu0.l2cache.WritebackDirty_hits::total 510228 # number of WritebackDirty hits
456system.cpu0.l2cache.WritebackClean_hits::writebacks 1265023 # number of WritebackClean hits
457system.cpu0.l2cache.WritebackClean_hits::total 1265023 # number of WritebackClean hits
458system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94248 # number of ReadExReq hits
--- 94 unchanged lines hidden (view full) ---
553system.cpu0.l2cache.writebacks::writebacks 193031 # number of writebacks
554system.cpu0.l2cache.writebacks::total 193031 # number of writebacks
555system.cpu0.toL2Bus.snoop_filter.tot_requests 3720034 # Total number of requests made to the snoop filter.
556system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860217 # Number of requests hitting in the snoop filter with a single holder of the requested data.
557system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
558system.cpu0.toL2Bus.snoop_filter.tot_snoops 218415 # Total number of snoops made to the snoop filter.
559system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215401 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
560system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3014 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
561system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution
562system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution
563system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution
564system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution
565system.cpu0.toL2Bus.trans_dist::WritebackDirty 510228 # Transaction distribution
566system.cpu0.toL2Bus.trans_dist::WritebackClean 1292889 # Transaction distribution
567system.cpu0.toL2Bus.trans_dist::UpgradeReq 26279 # Transaction distribution
568system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18431 # Transaction distribution
--- 19 unchanged lines hidden (view full) ---
588system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
589system.cpu0.toL2Bus.snoop_fanout::0 4031799 93.36% 93.36% # Request fanout histogram
590system.cpu0.toL2Bus.snoop_fanout::1 283523 6.57% 99.93% # Request fanout histogram
591system.cpu0.toL2Bus.snoop_fanout::2 3014 0.07% 100.00% # Request fanout histogram
592system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
593system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
594system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
595system.cpu0.toL2Bus.snoop_fanout::total 4318336 # Request fanout histogram
596system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
597system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
598system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
599system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
600system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
601system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
602system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
603system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
617system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
618system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
619system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
620system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
621system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
622system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
623system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
624system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
625system.cpu1.dtb.walker.walks 3359 # Table walker walks requested
626system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors
627system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency
628system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency
629system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency
630system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution
631system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution
632system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution
--- 23 unchanged lines hidden (view full) ---
656system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
657system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
658system.cpu1.dtb.read_accesses 12176798 # DTB read accesses
659system.cpu1.dtb.write_accesses 7587727 # DTB write accesses
660system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
661system.cpu1.dtb.hits 19761166 # DTB hits
662system.cpu1.dtb.misses 3359 # DTB misses
663system.cpu1.dtb.accesses 19764525 # DTB accesses
664system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
665system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
666system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
667system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
668system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
669system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
670system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
671system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
685system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
686system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
687system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
688system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
689system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
690system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
691system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
692system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
693system.cpu1.itb.walker.walks 1734 # Table walker walks requested
694system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors
695system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency
696system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency
697system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency
698system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution
699system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution
700system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution
--- 23 unchanged lines hidden (view full) ---
724system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
725system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
726system.cpu1.itb.read_accesses 0 # DTB read accesses
727system.cpu1.itb.write_accesses 0 # DTB write accesses
728system.cpu1.itb.inst_accesses 53673492 # ITB inst accesses
729system.cpu1.itb.hits 53671758 # DTB hits
730system.cpu1.itb.misses 1734 # DTB misses
731system.cpu1.itb.accesses 53673492 # DTB accesses
732system.cpu1.numCycles 5605296470 # number of cpu cycles simulated
733system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
734system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
735system.cpu1.kern.inst.arm 0 # number of arm instructions executed
736system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
737system.cpu1.committedInsts 51401494 # Number of instructions committed
738system.cpu1.committedOps 63347804 # Number of ops (including micro ops) committed
739system.cpu1.num_int_alu_accesses 56984416 # Number of integer alu accesses
--- 46 unchanged lines hidden (view full) ---
786system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
787system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
788system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
789system.cpu1.op_class::MemRead 12289568 18.77% 88.18% # Class of executed instruction
790system.cpu1.op_class::MemWrite 7736856 11.82% 100.00% # Class of executed instruction
791system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
792system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
793system.cpu1.op_class::total 65459659 # Class of executed instruction
794system.cpu1.dcache.tags.replacements 191946 # number of replacements
795system.cpu1.dcache.tags.tagsinuse 472.736015 # Cycle average of tags in use
796system.cpu1.dcache.tags.total_refs 19503545 # Total number of references to valid blocks.
797system.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks.
798system.cpu1.dcache.tags.avg_refs 101.422491 # Average number of references to valid blocks.
799system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit.
800system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736015 # Average occupied blocks per requestor
801system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy
802system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy
803system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
804system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
805system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
806system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
807system.cpu1.dcache.tags.tag_accesses 39752069 # Number of tag accesses
808system.cpu1.dcache.tags.data_accesses 39752069 # Number of data accesses
809system.cpu1.dcache.ReadReq_hits::cpu1.data 11858716 # number of ReadReq hits
810system.cpu1.dcache.ReadReq_hits::total 11858716 # number of ReadReq hits
811system.cpu1.dcache.WriteReq_hits::cpu1.data 7397520 # number of WriteReq hits
812system.cpu1.dcache.WriteReq_hits::total 7397520 # number of WriteReq hits
813system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits
814system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits
815system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits
816system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits
--- 48 unchanged lines hidden (view full) ---
865system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
866system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
867system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
868system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
869system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
870system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
871system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks
872system.cpu1.dcache.writebacks::total 191946 # number of writebacks
873system.cpu1.icache.tags.replacements 523401 # number of replacements
874system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use
875system.cpu1.icache.tags.total_refs 53148935 # Total number of references to valid blocks.
876system.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks.
877system.cpu1.icache.tags.avg_refs 101.446108 # Average number of references to valid blocks.
878system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit.
879system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor
880system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy
881system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy
882system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
883system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
884system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
885system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
886system.cpu1.icache.tags.tag_accesses 107869609 # Number of tag accesses
887system.cpu1.icache.tags.data_accesses 107869609 # Number of data accesses
888system.cpu1.icache.ReadReq_hits::cpu1.inst 53148935 # number of ReadReq hits
889system.cpu1.icache.ReadReq_hits::total 53148935 # number of ReadReq hits
890system.cpu1.icache.demand_hits::cpu1.inst 53148935 # number of demand (read+write) hits
891system.cpu1.icache.demand_hits::total 53148935 # number of demand (read+write) hits
892system.cpu1.icache.overall_hits::cpu1.inst 53148935 # number of overall hits
893system.cpu1.icache.overall_hits::total 53148935 # number of overall hits
894system.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses
895system.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses
--- 16 unchanged lines hidden (view full) ---
912system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
913system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
914system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
915system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
916system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
917system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
918system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks
919system.cpu1.icache.writebacks::total 523401 # number of writebacks
920system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
921system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
922system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
923system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
924system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
925system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
926system.cpu1.l2cache.tags.replacements 47503 # number of replacements
927system.cpu1.l2cache.tags.tagsinuse 15229.973296 # Cycle average of tags in use
928system.cpu1.l2cache.tags.total_refs 1184897 # Total number of references to valid blocks.
929system.cpu1.l2cache.tags.sampled_refs 62526 # Sample count of references to valid blocks.
930system.cpu1.l2cache.tags.avg_refs 18.950469 # Average number of references to valid blocks.
931system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
932system.cpu1.l2cache.tags.occ_blocks::writebacks 15227.338556 # Average occupied blocks per requestor
933system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 0.619660 # Average occupied blocks per requestor
--- 9 unchanged lines hidden (view full) ---
943system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
944system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id
945system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9469 # Occupied blocks per task id
946system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5007 # Occupied blocks per task id
947system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id
948system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.915833 # Percentage of cache occupancy per task id
949system.cpu1.l2cache.tags.tag_accesses 24502168 # Number of tag accesses
950system.cpu1.l2cache.tags.data_accesses 24502168 # Number of data accesses
951system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits
952system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1918 # number of ReadReq hits
953system.cpu1.l2cache.ReadReq_hits::total 5539 # number of ReadReq hits
954system.cpu1.l2cache.WritebackDirty_hits::writebacks 121092 # number of WritebackDirty hits
955system.cpu1.l2cache.WritebackDirty_hits::total 121092 # number of WritebackDirty hits
956system.cpu1.l2cache.WritebackClean_hits::writebacks 583097 # number of WritebackClean hits
957system.cpu1.l2cache.WritebackClean_hits::total 583097 # number of WritebackClean hits
958system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19779 # number of ReadExReq hits
--- 94 unchanged lines hidden (view full) ---
1053system.cpu1.l2cache.writebacks::writebacks 32790 # number of writebacks
1054system.cpu1.l2cache.writebacks::total 32790 # number of writebacks
1055system.cpu1.toL2Bus.snoop_filter.tot_requests 1533520 # Total number of requests made to the snoop filter.
1056system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773321 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1057system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1058system.cpu1.toL2Bus.snoop_filter.tot_snoops 166202 # Total number of snoops made to the snoop filter.
1059system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164239 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1060system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1963 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1061system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution
1062system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution
1063system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
1064system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution
1065system.cpu1.toL2Bus.trans_dist::WritebackDirty 121092 # Transaction distribution
1066system.cpu1.toL2Bus.trans_dist::WritebackClean 594255 # Transaction distribution
1067system.cpu1.toL2Bus.trans_dist::UpgradeReq 28839 # Transaction distribution
1068system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22580 # Transaction distribution
--- 19 unchanged lines hidden (view full) ---
1088system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1089system.cpu1.toL2Bus.snoop_fanout::0 1625468 89.28% 89.28% # Request fanout histogram
1090system.cpu1.toL2Bus.snoop_fanout::1 193110 10.61% 99.89% # Request fanout histogram
1091system.cpu1.toL2Bus.snoop_fanout::2 1963 0.11% 100.00% # Request fanout histogram
1092system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1093system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1094system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1095system.cpu1.toL2Bus.snoop_fanout::total 1820541 # Request fanout histogram
1096system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
1097system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
1098system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
1099system.iobus.trans_dist::WriteResp 59419 # Transaction distribution
1100system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes)
1101system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
1102system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1103system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
--- 34 unchanged lines hidden (view full) ---
1138system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1139system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1140system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1141system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1142system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes)
1143system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
1144system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
1145system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes)
1146system.iocache.tags.replacements 36442 # number of replacements
1147system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use
1148system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1149system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
1150system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1151system.iocache.tags.warmup_cycle 246641287009 # Cycle when the warmup percentage was hit.
1152system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor
1153system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy
1154system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy
1155system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1156system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1157system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1158system.iocache.tags.tag_accesses 328284 # Number of tag accesses
1159system.iocache.tags.data_accesses 328284 # Number of data accesses
1160system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
1161system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
1162system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1163system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1164system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses
1165system.iocache.demand_misses::total 36476 # number of demand (read+write) misses
1166system.iocache.overall_misses::realview.ide 36476 # number of overall misses
1167system.iocache.overall_misses::total 36476 # number of overall misses
--- 16 unchanged lines hidden (view full) ---
1184system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1185system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1186system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1187system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1188system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1189system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1190system.iocache.writebacks::writebacks 36190 # number of writebacks
1191system.iocache.writebacks::total 36190 # number of writebacks
1192system.l2c.tags.replacements 107745 # number of replacements
1193system.l2c.tags.tagsinuse 62386.756535 # Cycle average of tags in use
1194system.l2c.tags.total_refs 243993 # Total number of references to valid blocks.
1195system.l2c.tags.sampled_refs 168404 # Sample count of references to valid blocks.
1196system.l2c.tags.avg_refs 1.448855 # Average number of references to valid blocks.
1197system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1198system.l2c.tags.occ_blocks::writebacks 48109.911781 # Average occupied blocks per requestor
1199system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010811 # Average occupied blocks per requestor
--- 17 unchanged lines hidden (view full) ---
1217system.l2c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
1218system.l2c.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id
1219system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id
1220system.l2c.tags.age_task_id_blocks_1024::4 45523 # Occupied blocks per task id
1221system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
1222system.l2c.tags.occ_task_id_percent::1024 0.925491 # Percentage of cache occupancy per task id
1223system.l2c.tags.tag_accesses 5181909 # Number of tag accesses
1224system.l2c.tags.data_accesses 5181909 # Number of data accesses
1225system.l2c.WritebackDirty_hits::writebacks 225821 # number of WritebackDirty hits
1226system.l2c.WritebackDirty_hits::total 225821 # number of WritebackDirty hits
1227system.l2c.UpgradeReq_hits::cpu0.data 557 # number of UpgradeReq hits
1228system.l2c.UpgradeReq_hits::cpu1.data 103 # number of UpgradeReq hits
1229system.l2c.UpgradeReq_hits::total 660 # number of UpgradeReq hits
1230system.l2c.SCUpgradeReq_hits::cpu0.data 84 # number of SCUpgradeReq hits
1231system.l2c.SCUpgradeReq_hits::cpu1.data 42 # number of SCUpgradeReq hits
1232system.l2c.SCUpgradeReq_hits::total 126 # number of SCUpgradeReq hits
--- 134 unchanged lines hidden (view full) ---
1367system.l2c.writebacks::writebacks 96240 # number of writebacks
1368system.l2c.writebacks::total 96240 # number of writebacks
1369system.membus.snoop_filter.tot_requests 462691 # Total number of requests made to the snoop filter.
1370system.membus.snoop_filter.hit_single_requests 248163 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1371system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1372system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1373system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1374system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1375system.membus.trans_dist::ReadReq 43996 # Transaction distribution
1376system.membus.trans_dist::ReadResp 75748 # Transaction distribution
1377system.membus.trans_dist::WriteReq 30846 # Transaction distribution
1378system.membus.trans_dist::WriteResp 30846 # Transaction distribution
1379system.membus.trans_dist::WritebackDirty 132430 # Transaction distribution
1380system.membus.trans_dist::CleanEvict 8725 # Transaction distribution
1381system.membus.trans_dist::UpgradeReq 60386 # Transaction distribution
1382system.membus.trans_dist::SCUpgradeReq 40885 # Transaction distribution
--- 26 unchanged lines hidden (view full) ---
1409system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1410system.membus.snoop_fanout::0 531950 98.96% 98.96% # Request fanout histogram
1411system.membus.snoop_fanout::1 5571 1.04% 100.00% # Request fanout histogram
1412system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1413system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1414system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1415system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1416system.membus.snoop_fanout::total 537521 # Request fanout histogram
1417system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1418system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1419system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1420system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1421system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1422system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1423system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1424system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1425system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1426system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1427system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1428system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1429system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1430system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
--- 15 unchanged lines hidden (view full) ---
1446system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1447system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1448system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1449system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1450system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1451system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1452system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1453system.realview.ethernet.droppedPackets 0 # number of packets dropped
1454system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1455system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1456system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1457system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1458system.toL2Bus.snoop_filter.tot_requests 863181 # Total number of requests made to the snoop filter.
1459system.toL2Bus.snoop_filter.hit_single_requests 444499 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1460system.toL2Bus.snoop_filter.hit_multi_requests 128781 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1461system.toL2Bus.snoop_filter.tot_snoops 9832 # Total number of snoops made to the snoop filter.
1462system.toL2Bus.snoop_filter.hit_single_snoops 9332 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1463system.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1464system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution
1465system.toL2Bus.trans_dist::ReadResp 301660 # Transaction distribution
1466system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution
1467system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution
1468system.toL2Bus.trans_dist::WritebackDirty 225821 # Transaction distribution
1469system.toL2Bus.trans_dist::CleanEvict 64447 # Transaction distribution
1470system.toL2Bus.trans_dist::UpgradeReq 60576 # Transaction distribution
1471system.toL2Bus.trans_dist::SCUpgradeReq 41011 # Transaction distribution
--- 24 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.802883 # Number of seconds simulated
4sim_ticks 2802882797500 # Number of ticks simulated
5final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1600792 # Simulator instruction rate (inst/s)
8host_op_rate 1950541 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 30558377305 # Simulator tick rate (ticks/s)
10host_mem_usage 639316 # Number of bytes of host memory used
11host_seconds 91.72 # Real time elapsed on the host
12sim_insts 146828219 # Number of instructions simulated
13sim_ops 178907974 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.data 1081872 # Number of bytes read from this memory
22system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
23system.physmem.bytes_read::total 11758444 # Number of bytes read from this memory
--- 35 unchanged lines hidden (view full) ---
59system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu0.inst 395765 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::cpu0.data 3364156 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s)
64system.physmem.bw_total::cpu1.data 386000 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::total 7225250 # Total bandwidth to/from this memory (bytes/s)
67system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
68system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
69system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
70system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
71system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
72system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
73system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
74system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
75system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
76system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
77system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
78system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
79system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
80system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
81system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
82system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
83system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
84system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
85system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
86system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
87system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
88system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
89system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
90system.cf0.dma_write_txs 631 # Number of DMA write transactions.
91system.cpu_clk_domain.clock 500 # Clock period in ticks
92system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
93system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
94system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
95system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
96system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
97system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
98system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
99system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
113system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
114system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
115system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
116system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
117system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
118system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
119system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
120system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
121system.cpu0.dtb.walker.walks 7964 # Table walker walks requested
122system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors
123system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency
124system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency
125system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency
126system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
127system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
128system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
--- 23 unchanged lines hidden (view full) ---
152system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
153system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
154system.cpu0.dtb.read_accesses 20346565 # DTB read accesses
155system.cpu0.dtb.write_accesses 16392097 # DTB write accesses
156system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
157system.cpu0.dtb.hits 36730698 # DTB hits
158system.cpu0.dtb.misses 7964 # DTB misses
159system.cpu0.dtb.accesses 36738662 # DTB accesses
160system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
161system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
162system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
163system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
164system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
165system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
166system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
167system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
181system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
182system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
183system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
184system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
185system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
186system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
187system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
188system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
189system.cpu0.itb.walker.walks 3358 # Table walker walks requested
190system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors
191system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency
192system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency
193system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency
194system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
195system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
196system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
--- 23 unchanged lines hidden (view full) ---
220system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
221system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
222system.cpu0.itb.read_accesses 0 # DTB read accesses
223system.cpu0.itb.write_accesses 0 # DTB write accesses
224system.cpu0.itb.inst_accesses 97442513 # ITB inst accesses
225system.cpu0.itb.hits 97439155 # DTB hits
226system.cpu0.itb.misses 3358 # DTB misses
227system.cpu0.itb.accesses 97442513 # DTB accesses
228system.cpu0.numCycles 5605767562 # number of cpu cycles simulated
229system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
230system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
231system.cpu0.kern.inst.arm 0 # number of arm instructions executed
232system.cpu0.kern.inst.quiesce 1966 # number of quiesce instructions executed
233system.cpu0.committedInsts 95426725 # Number of instructions committed
234system.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed
235system.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses
--- 46 unchanged lines hidden (view full) ---
282system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
283system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
284system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
285system.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction
286system.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction
287system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
288system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
289system.cpu0.op_class::total 116881836 # Class of executed instruction
290system.cpu0.dcache.tags.replacements 693478 # number of replacements
291system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use
292system.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks.
293system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks.
294system.cpu0.dcache.tags.avg_refs 51.776416 # Average number of references to valid blocks.
295system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
296system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor
297system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
298system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy
299system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
300system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
301system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
302system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
303system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
304system.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses
305system.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses
306system.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits
307system.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits
308system.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits
309system.cpu0.dcache.WriteReq_hits::total 15690320 # number of WriteReq hits
310system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits
311system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits
312system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits
313system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits
--- 48 unchanged lines hidden (view full) ---
362system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
363system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
364system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
365system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
366system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
367system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
368system.cpu0.dcache.writebacks::writebacks 693478 # number of writebacks
369system.cpu0.dcache.writebacks::total 693478 # number of writebacks
370system.cpu0.icache.tags.replacements 1109639 # number of replacements
371system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use
372system.cpu0.icache.tags.total_refs 96331337 # Total number of references to valid blocks.
373system.cpu0.icache.tags.sampled_refs 1110151 # Sample count of references to valid blocks.
374system.cpu0.icache.tags.avg_refs 86.773184 # Average number of references to valid blocks.
375system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit.
376system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor
377system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy
378system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy
379system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
380system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
381system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
382system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
383system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
384system.cpu0.icache.tags.tag_accesses 195993154 # Number of tag accesses
385system.cpu0.icache.tags.data_accesses 195993154 # Number of data accesses
386system.cpu0.icache.ReadReq_hits::cpu0.inst 96331337 # number of ReadReq hits
387system.cpu0.icache.ReadReq_hits::total 96331337 # number of ReadReq hits
388system.cpu0.icache.demand_hits::cpu0.inst 96331337 # number of demand (read+write) hits
389system.cpu0.icache.demand_hits::total 96331337 # number of demand (read+write) hits
390system.cpu0.icache.overall_hits::cpu0.inst 96331337 # number of overall hits
391system.cpu0.icache.overall_hits::total 96331337 # number of overall hits
392system.cpu0.icache.ReadReq_misses::cpu0.inst 1110160 # number of ReadReq misses
393system.cpu0.icache.ReadReq_misses::total 1110160 # number of ReadReq misses
--- 16 unchanged lines hidden (view full) ---
410system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
411system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
412system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
413system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
414system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
415system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
416system.cpu0.icache.writebacks::writebacks 1109639 # number of writebacks
417system.cpu0.icache.writebacks::total 1109639 # number of writebacks
418system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
419system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
420system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
421system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
422system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
423system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
424system.cpu0.l2cache.tags.replacements 249747 # number of replacements
425system.cpu0.l2cache.tags.tagsinuse 16131.550435 # Cycle average of tags in use
426system.cpu0.l2cache.tags.total_refs 2729892 # Total number of references to valid blocks.
427system.cpu0.l2cache.tags.sampled_refs 265865 # Sample count of references to valid blocks.
428system.cpu0.l2cache.tags.avg_refs 10.267963 # Average number of references to valid blocks.
429system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit.
430system.cpu0.l2cache.tags.occ_blocks::writebacks 16129.097151 # Average occupied blocks per requestor
431system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.376905 # Average occupied blocks per requestor
--- 11 unchanged lines hidden (view full) ---
443system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id
444system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5562 # Occupied blocks per task id
445system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7431 # Occupied blocks per task id
446system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2624 # Occupied blocks per task id
447system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
448system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983276 # Percentage of cache occupancy per task id
449system.cpu0.l2cache.tags.tag_accesses 59696130 # Number of tag accesses
450system.cpu0.l2cache.tags.data_accesses 59696130 # Number of data accesses
451system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10179 # number of ReadReq hits
452system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4500 # number of ReadReq hits
453system.cpu0.l2cache.ReadReq_hits::total 14679 # number of ReadReq hits
454system.cpu0.l2cache.WritebackDirty_hits::writebacks 510228 # number of WritebackDirty hits
455system.cpu0.l2cache.WritebackDirty_hits::total 510228 # number of WritebackDirty hits
456system.cpu0.l2cache.WritebackClean_hits::writebacks 1265023 # number of WritebackClean hits
457system.cpu0.l2cache.WritebackClean_hits::total 1265023 # number of WritebackClean hits
458system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94248 # number of ReadExReq hits
--- 94 unchanged lines hidden (view full) ---
553system.cpu0.l2cache.writebacks::writebacks 193031 # number of writebacks
554system.cpu0.l2cache.writebacks::total 193031 # number of writebacks
555system.cpu0.toL2Bus.snoop_filter.tot_requests 3720034 # Total number of requests made to the snoop filter.
556system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860217 # Number of requests hitting in the snoop filter with a single holder of the requested data.
557system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
558system.cpu0.toL2Bus.snoop_filter.tot_snoops 218415 # Total number of snoops made to the snoop filter.
559system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215401 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
560system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3014 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
561system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution
562system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution
563system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution
564system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution
565system.cpu0.toL2Bus.trans_dist::WritebackDirty 510228 # Transaction distribution
566system.cpu0.toL2Bus.trans_dist::WritebackClean 1292889 # Transaction distribution
567system.cpu0.toL2Bus.trans_dist::UpgradeReq 26279 # Transaction distribution
568system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18431 # Transaction distribution
--- 19 unchanged lines hidden (view full) ---
588system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
589system.cpu0.toL2Bus.snoop_fanout::0 4031799 93.36% 93.36% # Request fanout histogram
590system.cpu0.toL2Bus.snoop_fanout::1 283523 6.57% 99.93% # Request fanout histogram
591system.cpu0.toL2Bus.snoop_fanout::2 3014 0.07% 100.00% # Request fanout histogram
592system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
593system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
594system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
595system.cpu0.toL2Bus.snoop_fanout::total 4318336 # Request fanout histogram
596system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
597system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
598system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
599system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
600system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
601system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
602system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
603system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
617system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
618system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
619system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
620system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
621system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
622system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
623system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
624system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
625system.cpu1.dtb.walker.walks 3359 # Table walker walks requested
626system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors
627system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency
628system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency
629system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency
630system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution
631system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution
632system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution
--- 23 unchanged lines hidden (view full) ---
656system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
657system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
658system.cpu1.dtb.read_accesses 12176798 # DTB read accesses
659system.cpu1.dtb.write_accesses 7587727 # DTB write accesses
660system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
661system.cpu1.dtb.hits 19761166 # DTB hits
662system.cpu1.dtb.misses 3359 # DTB misses
663system.cpu1.dtb.accesses 19764525 # DTB accesses
664system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
665system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
666system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
667system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
668system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
669system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
670system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
671system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
685system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
686system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
687system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
688system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
689system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
690system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
691system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
692system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
693system.cpu1.itb.walker.walks 1734 # Table walker walks requested
694system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors
695system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency
696system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency
697system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency
698system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution
699system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution
700system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution
--- 23 unchanged lines hidden (view full) ---
724system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
725system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
726system.cpu1.itb.read_accesses 0 # DTB read accesses
727system.cpu1.itb.write_accesses 0 # DTB write accesses
728system.cpu1.itb.inst_accesses 53673492 # ITB inst accesses
729system.cpu1.itb.hits 53671758 # DTB hits
730system.cpu1.itb.misses 1734 # DTB misses
731system.cpu1.itb.accesses 53673492 # DTB accesses
732system.cpu1.numCycles 5605296470 # number of cpu cycles simulated
733system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
734system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
735system.cpu1.kern.inst.arm 0 # number of arm instructions executed
736system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
737system.cpu1.committedInsts 51401494 # Number of instructions committed
738system.cpu1.committedOps 63347804 # Number of ops (including micro ops) committed
739system.cpu1.num_int_alu_accesses 56984416 # Number of integer alu accesses
--- 46 unchanged lines hidden (view full) ---
786system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
787system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
788system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
789system.cpu1.op_class::MemRead 12289568 18.77% 88.18% # Class of executed instruction
790system.cpu1.op_class::MemWrite 7736856 11.82% 100.00% # Class of executed instruction
791system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
792system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
793system.cpu1.op_class::total 65459659 # Class of executed instruction
794system.cpu1.dcache.tags.replacements 191946 # number of replacements
795system.cpu1.dcache.tags.tagsinuse 472.736015 # Cycle average of tags in use
796system.cpu1.dcache.tags.total_refs 19503545 # Total number of references to valid blocks.
797system.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks.
798system.cpu1.dcache.tags.avg_refs 101.422491 # Average number of references to valid blocks.
799system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit.
800system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736015 # Average occupied blocks per requestor
801system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy
802system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy
803system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
804system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
805system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
806system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
807system.cpu1.dcache.tags.tag_accesses 39752069 # Number of tag accesses
808system.cpu1.dcache.tags.data_accesses 39752069 # Number of data accesses
809system.cpu1.dcache.ReadReq_hits::cpu1.data 11858716 # number of ReadReq hits
810system.cpu1.dcache.ReadReq_hits::total 11858716 # number of ReadReq hits
811system.cpu1.dcache.WriteReq_hits::cpu1.data 7397520 # number of WriteReq hits
812system.cpu1.dcache.WriteReq_hits::total 7397520 # number of WriteReq hits
813system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits
814system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits
815system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits
816system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits
--- 48 unchanged lines hidden (view full) ---
865system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
866system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
867system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
868system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
869system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
870system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
871system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks
872system.cpu1.dcache.writebacks::total 191946 # number of writebacks
873system.cpu1.icache.tags.replacements 523401 # number of replacements
874system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use
875system.cpu1.icache.tags.total_refs 53148935 # Total number of references to valid blocks.
876system.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks.
877system.cpu1.icache.tags.avg_refs 101.446108 # Average number of references to valid blocks.
878system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit.
879system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor
880system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy
881system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy
882system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
883system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
884system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
885system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
886system.cpu1.icache.tags.tag_accesses 107869609 # Number of tag accesses
887system.cpu1.icache.tags.data_accesses 107869609 # Number of data accesses
888system.cpu1.icache.ReadReq_hits::cpu1.inst 53148935 # number of ReadReq hits
889system.cpu1.icache.ReadReq_hits::total 53148935 # number of ReadReq hits
890system.cpu1.icache.demand_hits::cpu1.inst 53148935 # number of demand (read+write) hits
891system.cpu1.icache.demand_hits::total 53148935 # number of demand (read+write) hits
892system.cpu1.icache.overall_hits::cpu1.inst 53148935 # number of overall hits
893system.cpu1.icache.overall_hits::total 53148935 # number of overall hits
894system.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses
895system.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses
--- 16 unchanged lines hidden (view full) ---
912system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
913system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
914system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
915system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
916system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
917system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
918system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks
919system.cpu1.icache.writebacks::total 523401 # number of writebacks
920system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
921system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
922system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
923system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
924system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
925system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
926system.cpu1.l2cache.tags.replacements 47503 # number of replacements
927system.cpu1.l2cache.tags.tagsinuse 15229.973296 # Cycle average of tags in use
928system.cpu1.l2cache.tags.total_refs 1184897 # Total number of references to valid blocks.
929system.cpu1.l2cache.tags.sampled_refs 62526 # Sample count of references to valid blocks.
930system.cpu1.l2cache.tags.avg_refs 18.950469 # Average number of references to valid blocks.
931system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
932system.cpu1.l2cache.tags.occ_blocks::writebacks 15227.338556 # Average occupied blocks per requestor
933system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 0.619660 # Average occupied blocks per requestor
--- 9 unchanged lines hidden (view full) ---
943system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
944system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id
945system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9469 # Occupied blocks per task id
946system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5007 # Occupied blocks per task id
947system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id
948system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.915833 # Percentage of cache occupancy per task id
949system.cpu1.l2cache.tags.tag_accesses 24502168 # Number of tag accesses
950system.cpu1.l2cache.tags.data_accesses 24502168 # Number of data accesses
951system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits
952system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1918 # number of ReadReq hits
953system.cpu1.l2cache.ReadReq_hits::total 5539 # number of ReadReq hits
954system.cpu1.l2cache.WritebackDirty_hits::writebacks 121092 # number of WritebackDirty hits
955system.cpu1.l2cache.WritebackDirty_hits::total 121092 # number of WritebackDirty hits
956system.cpu1.l2cache.WritebackClean_hits::writebacks 583097 # number of WritebackClean hits
957system.cpu1.l2cache.WritebackClean_hits::total 583097 # number of WritebackClean hits
958system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19779 # number of ReadExReq hits
--- 94 unchanged lines hidden (view full) ---
1053system.cpu1.l2cache.writebacks::writebacks 32790 # number of writebacks
1054system.cpu1.l2cache.writebacks::total 32790 # number of writebacks
1055system.cpu1.toL2Bus.snoop_filter.tot_requests 1533520 # Total number of requests made to the snoop filter.
1056system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773321 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1057system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1058system.cpu1.toL2Bus.snoop_filter.tot_snoops 166202 # Total number of snoops made to the snoop filter.
1059system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164239 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1060system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1963 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1061system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution
1062system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution
1063system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
1064system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution
1065system.cpu1.toL2Bus.trans_dist::WritebackDirty 121092 # Transaction distribution
1066system.cpu1.toL2Bus.trans_dist::WritebackClean 594255 # Transaction distribution
1067system.cpu1.toL2Bus.trans_dist::UpgradeReq 28839 # Transaction distribution
1068system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22580 # Transaction distribution
--- 19 unchanged lines hidden (view full) ---
1088system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1089system.cpu1.toL2Bus.snoop_fanout::0 1625468 89.28% 89.28% # Request fanout histogram
1090system.cpu1.toL2Bus.snoop_fanout::1 193110 10.61% 99.89% # Request fanout histogram
1091system.cpu1.toL2Bus.snoop_fanout::2 1963 0.11% 100.00% # Request fanout histogram
1092system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1093system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1094system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1095system.cpu1.toL2Bus.snoop_fanout::total 1820541 # Request fanout histogram
1096system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
1097system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
1098system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
1099system.iobus.trans_dist::WriteResp 59419 # Transaction distribution
1100system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes)
1101system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
1102system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
1103system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
--- 34 unchanged lines hidden (view full) ---
1138system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
1139system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1140system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
1141system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
1142system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes)
1143system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
1144system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
1145system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes)
1146system.iocache.tags.replacements 36442 # number of replacements
1147system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use
1148system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1149system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
1150system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1151system.iocache.tags.warmup_cycle 246641287009 # Cycle when the warmup percentage was hit.
1152system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor
1153system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy
1154system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy
1155system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1156system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1157system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1158system.iocache.tags.tag_accesses 328284 # Number of tag accesses
1159system.iocache.tags.data_accesses 328284 # Number of data accesses
1160system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
1161system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
1162system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
1163system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
1164system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses
1165system.iocache.demand_misses::total 36476 # number of demand (read+write) misses
1166system.iocache.overall_misses::realview.ide 36476 # number of overall misses
1167system.iocache.overall_misses::total 36476 # number of overall misses
--- 16 unchanged lines hidden (view full) ---
1184system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1185system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1186system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1187system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1188system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1189system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1190system.iocache.writebacks::writebacks 36190 # number of writebacks
1191system.iocache.writebacks::total 36190 # number of writebacks
1192system.l2c.tags.replacements 107745 # number of replacements
1193system.l2c.tags.tagsinuse 62386.756535 # Cycle average of tags in use
1194system.l2c.tags.total_refs 243993 # Total number of references to valid blocks.
1195system.l2c.tags.sampled_refs 168404 # Sample count of references to valid blocks.
1196system.l2c.tags.avg_refs 1.448855 # Average number of references to valid blocks.
1197system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1198system.l2c.tags.occ_blocks::writebacks 48109.911781 # Average occupied blocks per requestor
1199system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010811 # Average occupied blocks per requestor
--- 17 unchanged lines hidden (view full) ---
1217system.l2c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
1218system.l2c.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id
1219system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id
1220system.l2c.tags.age_task_id_blocks_1024::4 45523 # Occupied blocks per task id
1221system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
1222system.l2c.tags.occ_task_id_percent::1024 0.925491 # Percentage of cache occupancy per task id
1223system.l2c.tags.tag_accesses 5181909 # Number of tag accesses
1224system.l2c.tags.data_accesses 5181909 # Number of data accesses
1225system.l2c.WritebackDirty_hits::writebacks 225821 # number of WritebackDirty hits
1226system.l2c.WritebackDirty_hits::total 225821 # number of WritebackDirty hits
1227system.l2c.UpgradeReq_hits::cpu0.data 557 # number of UpgradeReq hits
1228system.l2c.UpgradeReq_hits::cpu1.data 103 # number of UpgradeReq hits
1229system.l2c.UpgradeReq_hits::total 660 # number of UpgradeReq hits
1230system.l2c.SCUpgradeReq_hits::cpu0.data 84 # number of SCUpgradeReq hits
1231system.l2c.SCUpgradeReq_hits::cpu1.data 42 # number of SCUpgradeReq hits
1232system.l2c.SCUpgradeReq_hits::total 126 # number of SCUpgradeReq hits
--- 134 unchanged lines hidden (view full) ---
1367system.l2c.writebacks::writebacks 96240 # number of writebacks
1368system.l2c.writebacks::total 96240 # number of writebacks
1369system.membus.snoop_filter.tot_requests 462691 # Total number of requests made to the snoop filter.
1370system.membus.snoop_filter.hit_single_requests 248163 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1371system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1372system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1373system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1374system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1375system.membus.trans_dist::ReadReq 43996 # Transaction distribution
1376system.membus.trans_dist::ReadResp 75748 # Transaction distribution
1377system.membus.trans_dist::WriteReq 30846 # Transaction distribution
1378system.membus.trans_dist::WriteResp 30846 # Transaction distribution
1379system.membus.trans_dist::WritebackDirty 132430 # Transaction distribution
1380system.membus.trans_dist::CleanEvict 8725 # Transaction distribution
1381system.membus.trans_dist::UpgradeReq 60386 # Transaction distribution
1382system.membus.trans_dist::SCUpgradeReq 40885 # Transaction distribution
--- 26 unchanged lines hidden (view full) ---
1409system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1410system.membus.snoop_fanout::0 531950 98.96% 98.96% # Request fanout histogram
1411system.membus.snoop_fanout::1 5571 1.04% 100.00% # Request fanout histogram
1412system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1413system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1414system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1415system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1416system.membus.snoop_fanout::total 537521 # Request fanout histogram
1417system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
1418system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
1419system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
1420system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
1421system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
1422system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
1423system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1424system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1425system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1426system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1427system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1428system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1429system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
1430system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
--- 15 unchanged lines hidden (view full) ---
1446system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1447system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1448system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1449system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1450system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1451system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1452system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
1453system.realview.ethernet.droppedPackets 0 # number of packets dropped
1454system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
1455system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
1456system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
1457system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
1458system.toL2Bus.snoop_filter.tot_requests 863181 # Total number of requests made to the snoop filter.
1459system.toL2Bus.snoop_filter.hit_single_requests 444499 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1460system.toL2Bus.snoop_filter.hit_multi_requests 128781 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1461system.toL2Bus.snoop_filter.tot_snoops 9832 # Total number of snoops made to the snoop filter.
1462system.toL2Bus.snoop_filter.hit_single_snoops 9332 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1463system.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1464system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution
1465system.toL2Bus.trans_dist::ReadResp 301660 # Transaction distribution
1466system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution
1467system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution
1468system.toL2Bus.trans_dist::WritebackDirty 225821 # Transaction distribution
1469system.toL2Bus.trans_dist::CleanEvict 64447 # Transaction distribution
1470system.toL2Bus.trans_dist::UpgradeReq 60576 # Transaction distribution
1471system.toL2Bus.trans_dist::SCUpgradeReq 41011 # Transaction distribution
--- 24 unchanged lines hidden ---