| config.ini (10636:9ac724889705) | config.ini (10736:4433fb00fa7d) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 24 unchanged lines hidden (view full) --- 33kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM 38mem_mode=atomic 39mem_ranges=2147483648:2415919103 40memories=system.physmem system.realview.nvmem system.realview.vram | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 24 unchanged lines hidden (view full) --- 33kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM 38mem_mode=atomic 39mem_ranges=2147483648:2415919103 40memories=system.physmem system.realview.nvmem system.realview.vram |
| 41mmap_using_noreserve=false |
|
| 41multi_proc=true 42num_work_ids=16 43panic_on_oops=true 44panic_on_panic=true 45phys_addr_range_64=40 46readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh 47reset_addr_64=0 48symbolfile= --- 123 unchanged lines hidden (view full) --- 172sequential_access=false 173size=32768 174 175[system.cpu0.dstage2_mmu] 176type=ArmStage2MMU 177children=stage2_tlb 178eventq_index=0 179stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb | 42multi_proc=true 43num_work_ids=16 44panic_on_oops=true 45panic_on_panic=true 46phys_addr_range_64=40 47readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh 48reset_addr_64=0 49symbolfile= --- 123 unchanged lines hidden (view full) --- 173sequential_access=false 174size=32768 175 176[system.cpu0.dstage2_mmu] 177type=ArmStage2MMU 178children=stage2_tlb 179eventq_index=0 180stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb |
| 181sys=system |
|
| 180tlb=system.cpu0.dtb 181 182[system.cpu0.dstage2_mmu.stage2_tlb] 183type=ArmTLB 184children=walker 185eventq_index=0 186is_stage2=true 187size=32 188walker=system.cpu0.dstage2_mmu.stage2_tlb.walker 189 190[system.cpu0.dstage2_mmu.stage2_tlb.walker] 191type=ArmTableWalker 192clk_domain=system.cpu_clk_domain 193eventq_index=0 194is_stage2=true 195num_squash_per_cycle=2 196sys=system | 182tlb=system.cpu0.dtb 183 184[system.cpu0.dstage2_mmu.stage2_tlb] 185type=ArmTLB 186children=walker 187eventq_index=0 188is_stage2=true 189size=32 190walker=system.cpu0.dstage2_mmu.stage2_tlb.walker 191 192[system.cpu0.dstage2_mmu.stage2_tlb.walker] 193type=ArmTableWalker 194clk_domain=system.cpu_clk_domain 195eventq_index=0 196is_stage2=true 197num_squash_per_cycle=2 198sys=system |
| 197port=system.cpu0.toL2Bus.slave[5] | |
| 198 199[system.cpu0.dtb] 200type=ArmTLB 201children=walker 202eventq_index=0 203is_stage2=false 204size=64 205walker=system.cpu0.dtb.walker --- 77 unchanged lines hidden (view full) --- 283pmu=Null 284system=system 285 286[system.cpu0.istage2_mmu] 287type=ArmStage2MMU 288children=stage2_tlb 289eventq_index=0 290stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb | 199 200[system.cpu0.dtb] 201type=ArmTLB 202children=walker 203eventq_index=0 204is_stage2=false 205size=64 206walker=system.cpu0.dtb.walker --- 77 unchanged lines hidden (view full) --- 284pmu=Null 285system=system 286 287[system.cpu0.istage2_mmu] 288type=ArmStage2MMU 289children=stage2_tlb 290eventq_index=0 291stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb |
| 292sys=system |
|
| 291tlb=system.cpu0.itb 292 293[system.cpu0.istage2_mmu.stage2_tlb] 294type=ArmTLB 295children=walker 296eventq_index=0 297is_stage2=true 298size=32 299walker=system.cpu0.istage2_mmu.stage2_tlb.walker 300 301[system.cpu0.istage2_mmu.stage2_tlb.walker] 302type=ArmTableWalker 303clk_domain=system.cpu_clk_domain 304eventq_index=0 305is_stage2=true 306num_squash_per_cycle=2 307sys=system | 293tlb=system.cpu0.itb 294 295[system.cpu0.istage2_mmu.stage2_tlb] 296type=ArmTLB 297children=walker 298eventq_index=0 299is_stage2=true 300size=32 301walker=system.cpu0.istage2_mmu.stage2_tlb.walker 302 303[system.cpu0.istage2_mmu.stage2_tlb.walker] 304type=ArmTableWalker 305clk_domain=system.cpu_clk_domain 306eventq_index=0 307is_stage2=true 308num_squash_per_cycle=2 309sys=system |
| 308port=system.cpu0.toL2Bus.slave[4] | |
| 309 310[system.cpu0.itb] 311type=ArmTLB 312children=walker 313eventq_index=0 314is_stage2=false 315size=64 316walker=system.cpu0.itb.walker --- 67 unchanged lines hidden (view full) --- 384hit_latency=12 385sequential_access=false 386size=1048576 387 388[system.cpu0.toL2Bus] 389type=CoherentXBar 390clk_domain=system.cpu_clk_domain 391eventq_index=0 | 310 311[system.cpu0.itb] 312type=ArmTLB 313children=walker 314eventq_index=0 315is_stage2=false 316size=64 317walker=system.cpu0.itb.walker --- 67 unchanged lines hidden (view full) --- 385hit_latency=12 386sequential_access=false 387size=1048576 388 389[system.cpu0.toL2Bus] 390type=CoherentXBar 391clk_domain=system.cpu_clk_domain 392eventq_index=0 |
| 392header_cycles=1 | 393forward_latency=0 394frontend_latency=1 395response_latency=1 |
| 393snoop_filter=Null | 396snoop_filter=Null |
| 397snoop_response_latency=1 |
|
| 394system=system 395use_default_range=false 396width=32 397master=system.cpu0.l2cache.cpu_side | 398system=system 399use_default_range=false 400width=32 401master=system.cpu0.l2cache.cpu_side |
| 398slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port | 402slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port |
| 399 400[system.cpu0.tracer] 401type=ExeTracer 402eventq_index=0 403 404[system.cpu1] 405type=AtomicSimpleCPU 406children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer --- 69 unchanged lines hidden (view full) --- 476sequential_access=false 477size=32768 478 479[system.cpu1.dstage2_mmu] 480type=ArmStage2MMU 481children=stage2_tlb 482eventq_index=0 483stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb | 403 404[system.cpu0.tracer] 405type=ExeTracer 406eventq_index=0 407 408[system.cpu1] 409type=AtomicSimpleCPU 410children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer --- 69 unchanged lines hidden (view full) --- 480sequential_access=false 481size=32768 482 483[system.cpu1.dstage2_mmu] 484type=ArmStage2MMU 485children=stage2_tlb 486eventq_index=0 487stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb |
| 488sys=system |
|
| 484tlb=system.cpu1.dtb 485 486[system.cpu1.dstage2_mmu.stage2_tlb] 487type=ArmTLB 488children=walker 489eventq_index=0 490is_stage2=true 491size=32 492walker=system.cpu1.dstage2_mmu.stage2_tlb.walker 493 494[system.cpu1.dstage2_mmu.stage2_tlb.walker] 495type=ArmTableWalker 496clk_domain=system.cpu_clk_domain 497eventq_index=0 498is_stage2=true 499num_squash_per_cycle=2 500sys=system | 489tlb=system.cpu1.dtb 490 491[system.cpu1.dstage2_mmu.stage2_tlb] 492type=ArmTLB 493children=walker 494eventq_index=0 495is_stage2=true 496size=32 497walker=system.cpu1.dstage2_mmu.stage2_tlb.walker 498 499[system.cpu1.dstage2_mmu.stage2_tlb.walker] 500type=ArmTableWalker 501clk_domain=system.cpu_clk_domain 502eventq_index=0 503is_stage2=true 504num_squash_per_cycle=2 505sys=system |
| 501port=system.cpu1.toL2Bus.slave[5] | |
| 502 503[system.cpu1.dtb] 504type=ArmTLB 505children=walker 506eventq_index=0 507is_stage2=false 508size=64 509walker=system.cpu1.dtb.walker --- 77 unchanged lines hidden (view full) --- 587pmu=Null 588system=system 589 590[system.cpu1.istage2_mmu] 591type=ArmStage2MMU 592children=stage2_tlb 593eventq_index=0 594stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb | 506 507[system.cpu1.dtb] 508type=ArmTLB 509children=walker 510eventq_index=0 511is_stage2=false 512size=64 513walker=system.cpu1.dtb.walker --- 77 unchanged lines hidden (view full) --- 591pmu=Null 592system=system 593 594[system.cpu1.istage2_mmu] 595type=ArmStage2MMU 596children=stage2_tlb 597eventq_index=0 598stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb |
| 599sys=system |
|
| 595tlb=system.cpu1.itb 596 597[system.cpu1.istage2_mmu.stage2_tlb] 598type=ArmTLB 599children=walker 600eventq_index=0 601is_stage2=true 602size=32 603walker=system.cpu1.istage2_mmu.stage2_tlb.walker 604 605[system.cpu1.istage2_mmu.stage2_tlb.walker] 606type=ArmTableWalker 607clk_domain=system.cpu_clk_domain 608eventq_index=0 609is_stage2=true 610num_squash_per_cycle=2 611sys=system | 600tlb=system.cpu1.itb 601 602[system.cpu1.istage2_mmu.stage2_tlb] 603type=ArmTLB 604children=walker 605eventq_index=0 606is_stage2=true 607size=32 608walker=system.cpu1.istage2_mmu.stage2_tlb.walker 609 610[system.cpu1.istage2_mmu.stage2_tlb.walker] 611type=ArmTableWalker 612clk_domain=system.cpu_clk_domain 613eventq_index=0 614is_stage2=true 615num_squash_per_cycle=2 616sys=system |
| 612port=system.cpu1.toL2Bus.slave[4] | |
| 613 614[system.cpu1.itb] 615type=ArmTLB 616children=walker 617eventq_index=0 618is_stage2=false 619size=64 620walker=system.cpu1.itb.walker --- 67 unchanged lines hidden (view full) --- 688hit_latency=12 689sequential_access=false 690size=1048576 691 692[system.cpu1.toL2Bus] 693type=CoherentXBar 694clk_domain=system.cpu_clk_domain 695eventq_index=0 | 617 618[system.cpu1.itb] 619type=ArmTLB 620children=walker 621eventq_index=0 622is_stage2=false 623size=64 624walker=system.cpu1.itb.walker --- 67 unchanged lines hidden (view full) --- 692hit_latency=12 693sequential_access=false 694size=1048576 695 696[system.cpu1.toL2Bus] 697type=CoherentXBar 698clk_domain=system.cpu_clk_domain 699eventq_index=0 |
| 696header_cycles=1 | 700forward_latency=0 701frontend_latency=1 702response_latency=1 |
| 697snoop_filter=Null | 703snoop_filter=Null |
| 704snoop_response_latency=1 |
|
| 698system=system 699use_default_range=false 700width=32 701master=system.cpu1.l2cache.cpu_side | 705system=system 706use_default_range=false 707width=32 708master=system.cpu1.l2cache.cpu_side |
| 702slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port | 709slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port |
| 703 704[system.cpu1.tracer] 705type=ExeTracer 706eventq_index=0 707 708[system.cpu_clk_domain] 709type=SrcClockDomain 710clock=500 --- 14 unchanged lines hidden (view full) --- 725type=IntrControl 726eventq_index=0 727sys=system 728 729[system.iobus] 730type=NoncoherentXBar 731clk_domain=system.clk_domain 732eventq_index=0 | 710 711[system.cpu1.tracer] 712type=ExeTracer 713eventq_index=0 714 715[system.cpu_clk_domain] 716type=SrcClockDomain 717clock=500 --- 14 unchanged lines hidden (view full) --- 732type=IntrControl 733eventq_index=0 734sys=system 735 736[system.iobus] 737type=NoncoherentXBar 738clk_domain=system.clk_domain 739eventq_index=0 |
| 733header_cycles=1 | 740forward_latency=1 741frontend_latency=2 742response_latency=2 |
| 734use_default_range=true | 743use_default_range=true |
| 735width=8 | 744width=16 |
| 736default=system.realview.pciconfig.pio 737master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side 738slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 739 740[system.iocache] 741type=BaseCache 742children=tags 743addr_ranges=2147483648:2415919103 --- 65 unchanged lines hidden (view full) --- 809sequential_access=false 810size=4194304 811 812[system.membus] 813type=CoherentXBar 814children=badaddr_responder 815clk_domain=system.clk_domain 816eventq_index=0 | 745default=system.realview.pciconfig.pio 746master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side 747slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 748 749[system.iocache] 750type=BaseCache 751children=tags 752addr_ranges=2147483648:2415919103 --- 65 unchanged lines hidden (view full) --- 818sequential_access=false 819size=4194304 820 821[system.membus] 822type=CoherentXBar 823children=badaddr_responder 824clk_domain=system.clk_domain 825eventq_index=0 |
| 817header_cycles=1 | 826forward_latency=4 827frontend_latency=3 828response_latency=2 |
| 818snoop_filter=Null | 829snoop_filter=Null |
| 830snoop_response_latency=4 |
|
| 819system=system 820use_default_range=false | 831system=system 832use_default_range=false |
| 821width=8 | 833width=16 |
| 822default=system.membus.badaddr_responder.pio 823master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port 824slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side 825 826[system.membus.badaddr_responder] 827type=IsaFake 828clk_domain=system.clk_domain 829eventq_index=0 --- 680 unchanged lines hidden (view full) --- 1510number=0 1511output=true 1512port=3456 1513 1514[system.toL2Bus] 1515type=CoherentXBar 1516clk_domain=system.cpu_clk_domain 1517eventq_index=0 | 834default=system.membus.badaddr_responder.pio 835master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port 836slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side 837 838[system.membus.badaddr_responder] 839type=IsaFake 840clk_domain=system.clk_domain 841eventq_index=0 --- 680 unchanged lines hidden (view full) --- 1522number=0 1523output=true 1524port=3456 1525 1526[system.toL2Bus] 1527type=CoherentXBar 1528clk_domain=system.cpu_clk_domain 1529eventq_index=0 |
| 1518header_cycles=1 | 1530forward_latency=0 1531frontend_latency=1 1532response_latency=1 |
| 1519snoop_filter=Null | 1533snoop_filter=Null |
| 1534snoop_response_latency=1 |
|
| 1520system=system 1521use_default_range=false | 1535system=system 1536use_default_range=false |
| 1522width=8 | 1537width=32 |
| 1523master=system.l2c.cpu_side 1524slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side 1525 1526[system.vncserver] 1527type=VncServer 1528eventq_index=0 1529frame_capture=false 1530number=0 1531port=5900 1532 1533[system.voltage_domain] 1534type=VoltageDomain 1535eventq_index=0 1536voltage=1.000000 1537 | 1538master=system.l2c.cpu_side 1539slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side 1540 1541[system.vncserver] 1542type=VncServer 1543eventq_index=0 1544frame_capture=false 1545number=0 1546port=5900 1547 1548[system.voltage_domain] 1549type=VoltageDomain 1550eventq_index=0 1551voltage=1.000000 1552 |