40a41
> mmap_using_noreserve=false
179a181
> sys=system
197d198
< port=system.cpu0.toL2Bus.slave[5]
290a292
> sys=system
308d309
< port=system.cpu0.toL2Bus.slave[4]
392c393,395
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
393a397
> snoop_response_latency=1
398c402
< slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
483a488
> sys=system
501d505
< port=system.cpu1.toL2Bus.slave[5]
594a599
> sys=system
612d616
< port=system.cpu1.toL2Bus.slave[4]
696c700,702
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
697a704
> snoop_response_latency=1
702c709
< slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
733c740,742
< header_cycles=1
---
> forward_latency=1
> frontend_latency=2
> response_latency=2
735c744
< width=8
---
> width=16
817c826,828
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
818a830
> snoop_response_latency=4
821c833
< width=8
---
> width=16
1518c1530,1532
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
1519a1534
> snoop_response_latency=1
1522c1537
< width=8
---
> width=32