1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 24 unchanged lines hidden (view full) ---
33kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM
38mem_mode=atomic
39mem_ranges=2147483648:2415919103
40memories=system.physmem system.realview.nvmem system.realview.vram
41multi_proc=true
42num_work_ids=16
43panic_on_oops=true
44panic_on_panic=true
45phys_addr_range_64=40
46readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
47reset_addr_64=0
48symbolfile=
--- 123 unchanged lines hidden (view full) ---
172sequential_access=false
173size=32768
174
175[system.cpu0.dstage2_mmu]
176type=ArmStage2MMU
177children=stage2_tlb
178eventq_index=0
179stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
180tlb=system.cpu0.dtb
181
182[system.cpu0.dstage2_mmu.stage2_tlb]
183type=ArmTLB
184children=walker
185eventq_index=0
186is_stage2=true
187size=32
188walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
189
190[system.cpu0.dstage2_mmu.stage2_tlb.walker]
191type=ArmTableWalker
192clk_domain=system.cpu_clk_domain
193eventq_index=0
194is_stage2=true
195num_squash_per_cycle=2
196sys=system
197port=system.cpu0.toL2Bus.slave[5]
198
199[system.cpu0.dtb]
200type=ArmTLB
201children=walker
202eventq_index=0
203is_stage2=false
204size=64
205walker=system.cpu0.dtb.walker
--- 77 unchanged lines hidden (view full) ---
283pmu=Null
284system=system
285
286[system.cpu0.istage2_mmu]
287type=ArmStage2MMU
288children=stage2_tlb
289eventq_index=0
290stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
291tlb=system.cpu0.itb
292
293[system.cpu0.istage2_mmu.stage2_tlb]
294type=ArmTLB
295children=walker
296eventq_index=0
297is_stage2=true
298size=32
299walker=system.cpu0.istage2_mmu.stage2_tlb.walker
300
301[system.cpu0.istage2_mmu.stage2_tlb.walker]
302type=ArmTableWalker
303clk_domain=system.cpu_clk_domain
304eventq_index=0
305is_stage2=true
306num_squash_per_cycle=2
307sys=system
308port=system.cpu0.toL2Bus.slave[4]
309
310[system.cpu0.itb]
311type=ArmTLB
312children=walker
313eventq_index=0
314is_stage2=false
315size=64
316walker=system.cpu0.itb.walker
--- 67 unchanged lines hidden (view full) ---
384hit_latency=12
385sequential_access=false
386size=1048576
387
388[system.cpu0.toL2Bus]
389type=CoherentXBar
390clk_domain=system.cpu_clk_domain
391eventq_index=0
392header_cycles=1
393snoop_filter=Null
394system=system
395use_default_range=false
396width=32
397master=system.cpu0.l2cache.cpu_side
398slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
399
400[system.cpu0.tracer]
401type=ExeTracer
402eventq_index=0
403
404[system.cpu1]
405type=AtomicSimpleCPU
406children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
--- 69 unchanged lines hidden (view full) ---
476sequential_access=false
477size=32768
478
479[system.cpu1.dstage2_mmu]
480type=ArmStage2MMU
481children=stage2_tlb
482eventq_index=0
483stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
484tlb=system.cpu1.dtb
485
486[system.cpu1.dstage2_mmu.stage2_tlb]
487type=ArmTLB
488children=walker
489eventq_index=0
490is_stage2=true
491size=32
492walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
493
494[system.cpu1.dstage2_mmu.stage2_tlb.walker]
495type=ArmTableWalker
496clk_domain=system.cpu_clk_domain
497eventq_index=0
498is_stage2=true
499num_squash_per_cycle=2
500sys=system
501port=system.cpu1.toL2Bus.slave[5]
502
503[system.cpu1.dtb]
504type=ArmTLB
505children=walker
506eventq_index=0
507is_stage2=false
508size=64
509walker=system.cpu1.dtb.walker
--- 77 unchanged lines hidden (view full) ---
587pmu=Null
588system=system
589
590[system.cpu1.istage2_mmu]
591type=ArmStage2MMU
592children=stage2_tlb
593eventq_index=0
594stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
595tlb=system.cpu1.itb
596
597[system.cpu1.istage2_mmu.stage2_tlb]
598type=ArmTLB
599children=walker
600eventq_index=0
601is_stage2=true
602size=32
603walker=system.cpu1.istage2_mmu.stage2_tlb.walker
604
605[system.cpu1.istage2_mmu.stage2_tlb.walker]
606type=ArmTableWalker
607clk_domain=system.cpu_clk_domain
608eventq_index=0
609is_stage2=true
610num_squash_per_cycle=2
611sys=system
612port=system.cpu1.toL2Bus.slave[4]
613
614[system.cpu1.itb]
615type=ArmTLB
616children=walker
617eventq_index=0
618is_stage2=false
619size=64
620walker=system.cpu1.itb.walker
--- 67 unchanged lines hidden (view full) ---
688hit_latency=12
689sequential_access=false
690size=1048576
691
692[system.cpu1.toL2Bus]
693type=CoherentXBar
694clk_domain=system.cpu_clk_domain
695eventq_index=0
696header_cycles=1
697snoop_filter=Null
698system=system
699use_default_range=false
700width=32
701master=system.cpu1.l2cache.cpu_side
702slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
703
704[system.cpu1.tracer]
705type=ExeTracer
706eventq_index=0
707
708[system.cpu_clk_domain]
709type=SrcClockDomain
710clock=500
--- 14 unchanged lines hidden (view full) ---
725type=IntrControl
726eventq_index=0
727sys=system
728
729[system.iobus]
730type=NoncoherentXBar
731clk_domain=system.clk_domain
732eventq_index=0
733header_cycles=1
734use_default_range=true
735width=8
736default=system.realview.pciconfig.pio
737master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
738slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
739
740[system.iocache]
741type=BaseCache
742children=tags
743addr_ranges=2147483648:2415919103
--- 65 unchanged lines hidden (view full) ---
809sequential_access=false
810size=4194304
811
812[system.membus]
813type=CoherentXBar
814children=badaddr_responder
815clk_domain=system.clk_domain
816eventq_index=0
817header_cycles=1
818snoop_filter=Null
819system=system
820use_default_range=false
821width=8
822default=system.membus.badaddr_responder.pio
823master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
824slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
825
826[system.membus.badaddr_responder]
827type=IsaFake
828clk_domain=system.clk_domain
829eventq_index=0
--- 680 unchanged lines hidden (view full) ---
1510number=0
1511output=true
1512port=3456
1513
1514[system.toL2Bus]
1515type=CoherentXBar
1516clk_domain=system.cpu_clk_domain
1517eventq_index=0
1518header_cycles=1
1519snoop_filter=Null
1520system=system
1521use_default_range=false
1522width=8
1523master=system.l2c.cpu_side
1524slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
1525
1526[system.vncserver]
1527type=VncServer
1528eventq_index=0
1529frame_capture=false
1530number=0
1531port=5900
1532
1533[system.voltage_domain]
1534type=VoltageDomain
1535eventq_index=0
1536voltage=1.000000
1537
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 24 unchanged lines hidden (view full) ---
33kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM
38mem_mode=atomic
39mem_ranges=2147483648:2415919103
40memories=system.physmem system.realview.nvmem system.realview.vram
41multi_proc=true
42num_work_ids=16
43panic_on_oops=true
44panic_on_panic=true
45phys_addr_range_64=40
46readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
47reset_addr_64=0
48symbolfile=
--- 123 unchanged lines hidden (view full) ---
172sequential_access=false
173size=32768
174
175[system.cpu0.dstage2_mmu]
176type=ArmStage2MMU
177children=stage2_tlb
178eventq_index=0
179stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
180tlb=system.cpu0.dtb
181
182[system.cpu0.dstage2_mmu.stage2_tlb]
183type=ArmTLB
184children=walker
185eventq_index=0
186is_stage2=true
187size=32
188walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
189
190[system.cpu0.dstage2_mmu.stage2_tlb.walker]
191type=ArmTableWalker
192clk_domain=system.cpu_clk_domain
193eventq_index=0
194is_stage2=true
195num_squash_per_cycle=2
196sys=system
197port=system.cpu0.toL2Bus.slave[5]
198
199[system.cpu0.dtb]
200type=ArmTLB
201children=walker
202eventq_index=0
203is_stage2=false
204size=64
205walker=system.cpu0.dtb.walker
--- 77 unchanged lines hidden (view full) ---
283pmu=Null
284system=system
285
286[system.cpu0.istage2_mmu]
287type=ArmStage2MMU
288children=stage2_tlb
289eventq_index=0
290stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
291tlb=system.cpu0.itb
292
293[system.cpu0.istage2_mmu.stage2_tlb]
294type=ArmTLB
295children=walker
296eventq_index=0
297is_stage2=true
298size=32
299walker=system.cpu0.istage2_mmu.stage2_tlb.walker
300
301[system.cpu0.istage2_mmu.stage2_tlb.walker]
302type=ArmTableWalker
303clk_domain=system.cpu_clk_domain
304eventq_index=0
305is_stage2=true
306num_squash_per_cycle=2
307sys=system
308port=system.cpu0.toL2Bus.slave[4]
309
310[system.cpu0.itb]
311type=ArmTLB
312children=walker
313eventq_index=0
314is_stage2=false
315size=64
316walker=system.cpu0.itb.walker
--- 67 unchanged lines hidden (view full) ---
384hit_latency=12
385sequential_access=false
386size=1048576
387
388[system.cpu0.toL2Bus]
389type=CoherentXBar
390clk_domain=system.cpu_clk_domain
391eventq_index=0
392header_cycles=1
393snoop_filter=Null
394system=system
395use_default_range=false
396width=32
397master=system.cpu0.l2cache.cpu_side
398slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
399
400[system.cpu0.tracer]
401type=ExeTracer
402eventq_index=0
403
404[system.cpu1]
405type=AtomicSimpleCPU
406children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
--- 69 unchanged lines hidden (view full) ---
476sequential_access=false
477size=32768
478
479[system.cpu1.dstage2_mmu]
480type=ArmStage2MMU
481children=stage2_tlb
482eventq_index=0
483stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
484tlb=system.cpu1.dtb
485
486[system.cpu1.dstage2_mmu.stage2_tlb]
487type=ArmTLB
488children=walker
489eventq_index=0
490is_stage2=true
491size=32
492walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
493
494[system.cpu1.dstage2_mmu.stage2_tlb.walker]
495type=ArmTableWalker
496clk_domain=system.cpu_clk_domain
497eventq_index=0
498is_stage2=true
499num_squash_per_cycle=2
500sys=system
501port=system.cpu1.toL2Bus.slave[5]
502
503[system.cpu1.dtb]
504type=ArmTLB
505children=walker
506eventq_index=0
507is_stage2=false
508size=64
509walker=system.cpu1.dtb.walker
--- 77 unchanged lines hidden (view full) ---
587pmu=Null
588system=system
589
590[system.cpu1.istage2_mmu]
591type=ArmStage2MMU
592children=stage2_tlb
593eventq_index=0
594stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
595tlb=system.cpu1.itb
596
597[system.cpu1.istage2_mmu.stage2_tlb]
598type=ArmTLB
599children=walker
600eventq_index=0
601is_stage2=true
602size=32
603walker=system.cpu1.istage2_mmu.stage2_tlb.walker
604
605[system.cpu1.istage2_mmu.stage2_tlb.walker]
606type=ArmTableWalker
607clk_domain=system.cpu_clk_domain
608eventq_index=0
609is_stage2=true
610num_squash_per_cycle=2
611sys=system
612port=system.cpu1.toL2Bus.slave[4]
613
614[system.cpu1.itb]
615type=ArmTLB
616children=walker
617eventq_index=0
618is_stage2=false
619size=64
620walker=system.cpu1.itb.walker
--- 67 unchanged lines hidden (view full) ---
688hit_latency=12
689sequential_access=false
690size=1048576
691
692[system.cpu1.toL2Bus]
693type=CoherentXBar
694clk_domain=system.cpu_clk_domain
695eventq_index=0
696header_cycles=1
697snoop_filter=Null
698system=system
699use_default_range=false
700width=32
701master=system.cpu1.l2cache.cpu_side
702slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
703
704[system.cpu1.tracer]
705type=ExeTracer
706eventq_index=0
707
708[system.cpu_clk_domain]
709type=SrcClockDomain
710clock=500
--- 14 unchanged lines hidden (view full) ---
725type=IntrControl
726eventq_index=0
727sys=system
728
729[system.iobus]
730type=NoncoherentXBar
731clk_domain=system.clk_domain
732eventq_index=0
733header_cycles=1
734use_default_range=true
735width=8
736default=system.realview.pciconfig.pio
737master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
738slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
739
740[system.iocache]
741type=BaseCache
742children=tags
743addr_ranges=2147483648:2415919103
--- 65 unchanged lines hidden (view full) ---
809sequential_access=false
810size=4194304
811
812[system.membus]
813type=CoherentXBar
814children=badaddr_responder
815clk_domain=system.clk_domain
816eventq_index=0
817header_cycles=1
818snoop_filter=Null
819system=system
820use_default_range=false
821width=8
822default=system.membus.badaddr_responder.pio
823master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
824slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
825
826[system.membus.badaddr_responder]
827type=IsaFake
828clk_domain=system.clk_domain
829eventq_index=0
--- 680 unchanged lines hidden (view full) ---
1510number=0
1511output=true
1512port=3456
1513
1514[system.toL2Bus]
1515type=CoherentXBar
1516clk_domain=system.cpu_clk_domain
1517eventq_index=0
1518header_cycles=1
1519snoop_filter=Null
1520system=system
1521use_default_range=false
1522width=8
1523master=system.l2c.cpu_side
1524slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
1525
1526[system.vncserver]
1527type=VncServer
1528eventq_index=0
1529frame_capture=false
1530number=0
1531port=5900
1532
1533[system.voltage_domain]
1534type=VoltageDomain
1535eventq_index=0
1536voltage=1.000000
1537