| stats.txt (9838:43d22d746e7a) | stats.txt (9978:81d7551dd3be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.918473 # Number of seconds simulated 4sim_ticks 1918473094000 # Number of ticks simulated 5final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.920428 # Number of seconds simulated 4sim_ticks 1920428041000 # Number of ticks simulated 5final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 948634 # Simulator instruction rate (inst/s) 8host_op_rate 948634 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32389976926 # Simulator tick rate (ticks/s) 10host_mem_usage 304780 # Number of bytes of host memory used 11host_seconds 59.23 # Real time elapsed on the host 12sim_insts 56188014 # Number of instructions simulated 13sim_ops 56188014 # Number of ops (including micro ops) simulated | 7host_inst_rate 1218375 # Simulator instruction rate (inst/s) 8host_op_rate 1218374 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41646226437 # Simulator tick rate (ticks/s) 10host_mem_usage 305884 # Number of bytes of host memory used 11host_seconds 46.11 # Real time elapsed on the host 12sim_insts 56182750 # Number of instructions simulated 13sim_ops 56182750 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory | 14system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory | 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::total 28350528 # Number of bytes read from this memory | 17system.physmem.bytes_read::total 28349952 # Number of bytes read from this memory |
| 18system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory | 18system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory |
| 20system.physmem.bytes_written::writebacks 7389888 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7389888 # Number of bytes written to this memory | 20system.physmem.bytes_written::writebacks 7389824 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7389824 # Number of bytes written to this memory |
| 22system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory | 22system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory | 23system.physmem.num_reads::cpu.data 388233 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory | 24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::total 442977 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115467 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115467 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 443419 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12951700 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1382533 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14777652 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 443419 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 443419 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3851963 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3851963 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3851963 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 443419 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.readReqs 442977 # Total number of read requests accepted by DRAM controller 42system.physmem.writeReqs 115467 # Total number of write requests accepted by DRAM controller 43system.physmem.readBursts 442977 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 44system.physmem.writeBursts 115467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 45system.physmem.bytesRead 28350528 # Total number of bytes read from memory 46system.physmem.bytesWritten 7389888 # Total number of bytes written to memory 47system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize() 48system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize() 49system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q 50system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed 51system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::2 28297 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::3 28045 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::4 27408 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::5 27547 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::6 26911 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::7 26768 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::8 27805 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::9 27257 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::10 27713 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::11 27329 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::12 27431 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::13 28072 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::14 28025 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::15 28266 # Track reads on a per bank basis 67system.physmem.perBankWrReqs::0 7723 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::1 7594 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::2 7833 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::3 7543 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::4 7011 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::5 6984 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::6 6467 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::7 6223 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::8 7221 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::9 6661 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::10 7097 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::11 6780 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::12 7013 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::13 7721 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::14 7774 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::15 7822 # Track writes on a per bank basis 83system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 84system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 85system.physmem.totGap 1918461222000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Categorize read packet sizes 87system.physmem.readPktSize::1 0 # Categorize read packet sizes 88system.physmem.readPktSize::2 0 # Categorize read packet sizes 89system.physmem.readPktSize::3 0 # Categorize read packet sizes 90system.physmem.readPktSize::4 0 # Categorize read packet sizes 91system.physmem.readPktSize::5 0 # Categorize read packet sizes 92system.physmem.readPktSize::6 442977 # Categorize read packet sizes 93system.physmem.writePktSize::0 0 # Categorize write packet sizes 94system.physmem.writePktSize::1 0 # Categorize write packet sizes 95system.physmem.writePktSize::2 0 # Categorize write packet sizes 96system.physmem.writePktSize::3 0 # Categorize write packet sizes 97system.physmem.writePktSize::4 0 # Categorize write packet sizes 98system.physmem.writePktSize::5 0 # Categorize write packet sizes 99system.physmem.writePktSize::6 115467 # Categorize write packet sizes 100system.physmem.rdQLenPdf::0 402244 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 7043 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 5311 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 3263 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 3253 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 3011 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 1562 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 1513 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 1478 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 1450 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 1424 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 1426 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 1399 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 2029 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 2311 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 2193 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 1221 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 460 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see | 25system.physmem.num_reads::total 442968 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115466 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115466 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 442968 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12938216 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1381125 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14762309 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 442968 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 442968 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3848009 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3848009 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3848009 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 442968 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12938216 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1381125 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18610318 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.readReqs 442968 # Number of read requests accepted 42system.physmem.writeReqs 115466 # Number of write requests accepted 43system.physmem.readBursts 442968 # Number of DRAM read bursts, including those serviced by the write queue 44system.physmem.writeBursts 115466 # Number of DRAM write bursts, including those merged in the write queue 45system.physmem.bytesReadDRAM 28346688 # Total number of bytes read from DRAM 46system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue 47system.physmem.bytesWritten 7389440 # Total number of bytes written to DRAM 48system.physmem.bytesReadSys 28349952 # Total read bytes from the system interface side 49system.physmem.bytesWrittenSys 7389824 # Total written bytes from the system interface side 50system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue 51system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 52system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write 53system.physmem.perBankRdBursts::0 27966 # Per bank write bursts 54system.physmem.perBankRdBursts::1 28089 # Per bank write bursts 55system.physmem.perBankRdBursts::2 28297 # Per bank write bursts 56system.physmem.perBankRdBursts::3 28053 # Per bank write bursts 57system.physmem.perBankRdBursts::4 27407 # Per bank write bursts 58system.physmem.perBankRdBursts::5 27545 # Per bank write bursts 59system.physmem.perBankRdBursts::6 26911 # Per bank write bursts 60system.physmem.perBankRdBursts::7 26762 # Per bank write bursts 61system.physmem.perBankRdBursts::8 27807 # Per bank write bursts 62system.physmem.perBankRdBursts::9 27255 # Per bank write bursts 63system.physmem.perBankRdBursts::10 27714 # Per bank write bursts 64system.physmem.perBankRdBursts::11 27327 # Per bank write bursts 65system.physmem.perBankRdBursts::12 27431 # Per bank write bursts 66system.physmem.perBankRdBursts::13 28073 # Per bank write bursts 67system.physmem.perBankRdBursts::14 28024 # Per bank write bursts 68system.physmem.perBankRdBursts::15 28256 # Per bank write bursts 69system.physmem.perBankWrBursts::0 7722 # Per bank write bursts 70system.physmem.perBankWrBursts::1 7593 # Per bank write bursts 71system.physmem.perBankWrBursts::2 7833 # Per bank write bursts 72system.physmem.perBankWrBursts::3 7543 # Per bank write bursts 73system.physmem.perBankWrBursts::4 7010 # Per bank write bursts 74system.physmem.perBankWrBursts::5 6982 # Per bank write bursts 75system.physmem.perBankWrBursts::6 6469 # Per bank write bursts 76system.physmem.perBankWrBursts::7 6223 # Per bank write bursts 77system.physmem.perBankWrBursts::8 7224 # Per bank write bursts 78system.physmem.perBankWrBursts::9 6661 # Per bank write bursts 79system.physmem.perBankWrBursts::10 7099 # Per bank write bursts 80system.physmem.perBankWrBursts::11 6780 # Per bank write bursts 81system.physmem.perBankWrBursts::12 7009 # Per bank write bursts 82system.physmem.perBankWrBursts::13 7722 # Per bank write bursts 83system.physmem.perBankWrBursts::14 7773 # Per bank write bursts 84system.physmem.perBankWrBursts::15 7817 # Per bank write bursts 85system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 86system.physmem.numWrRetry 12 # Number of times write queue was full causing retry 87system.physmem.totGap 1920416169000 # Total gap between requests 88system.physmem.readPktSize::0 0 # Read request sizes (log2) 89system.physmem.readPktSize::1 0 # Read request sizes (log2) 90system.physmem.readPktSize::2 0 # Read request sizes (log2) 91system.physmem.readPktSize::3 0 # Read request sizes (log2) 92system.physmem.readPktSize::4 0 # Read request sizes (log2) 93system.physmem.readPktSize::5 0 # Read request sizes (log2) 94system.physmem.readPktSize::6 442968 # Read request sizes (log2) 95system.physmem.writePktSize::0 0 # Write request sizes (log2) 96system.physmem.writePktSize::1 0 # Write request sizes (log2) 97system.physmem.writePktSize::2 0 # Write request sizes (log2) 98system.physmem.writePktSize::3 0 # Write request sizes (log2) 99system.physmem.writePktSize::4 0 # Write request sizes (log2) 100system.physmem.writePktSize::5 0 # Write request sizes (log2) 101system.physmem.writePktSize::6 115466 # Write request sizes (log2) 102system.physmem.rdQLenPdf::0 403787 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::1 10503 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::2 5396 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::3 2702 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::4 2330 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::5 2324 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::6 1381 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::7 1352 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::10 1304 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::11 1247 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::13 967 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::16 958 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::17 953 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::19 963 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see |
| 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 123system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 132system.physmem.wrQLenPdf::0 3591 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 3696 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 4739 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 5019 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 5020 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 5020 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 5021 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 5020 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 5020 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 5020 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 5020 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 5020 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 5020 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 5020 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 5020 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 5020 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 5020 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 5020 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5020 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5020 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5020 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5020 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5020 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 1430 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 1325 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 282 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 164system.physmem.bytesPerActivate::samples 37132 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::mean 962.378541 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::gmean 229.718891 # Bytes accessed per row activation 167system.physmem.bytesPerActivate::stdev 2449.750918 # Bytes accessed per row activation 168system.physmem.bytesPerActivate::64-67 13161 35.44% 35.44% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::128-131 5591 15.06% 50.50% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::192-195 3357 9.04% 59.54% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::256-259 2263 6.09% 65.64% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::320-323 1589 4.28% 69.92% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::384-387 1303 3.51% 73.42% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::448-451 971 2.61% 76.04% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::512-515 731 1.97% 78.01% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::576-579 647 1.74% 79.75% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::640-643 569 1.53% 81.28% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::704-707 543 1.46% 82.75% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::768-771 425 1.14% 83.89% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::832-835 308 0.83% 84.72% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::896-899 237 0.64% 85.36% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::960-963 163 0.44% 85.80% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1024-1027 235 0.63% 86.43% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1088-1091 101 0.27% 86.70% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1152-1155 93 0.25% 86.95% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1216-1219 98 0.26% 87.22% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1280-1283 98 0.26% 87.48% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1344-1347 85 0.23% 87.71% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1408-1411 107 0.29% 88.00% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1472-1475 1046 2.82% 90.81% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1536-1539 157 0.42% 91.24% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1600-1603 87 0.23% 91.47% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1664-1667 55 0.15% 91.62% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1728-1731 46 0.12% 91.74% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1792-1795 40 0.11% 91.85% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1856-1859 31 0.08% 91.93% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1920-1923 18 0.05% 91.98% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1984-1987 16 0.04% 92.03% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2048-2051 26 0.07% 92.10% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.15% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2176-2179 8 0.02% 92.17% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2240-2243 8 0.02% 92.19% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2304-2307 15 0.04% 92.23% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2368-2371 14 0.04% 92.27% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.28% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.28% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.30% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.31% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.32% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.32% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.33% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2880-2883 2 0.01% 92.34% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2944-2947 4 0.01% 92.35% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.35% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.36% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3136-3139 3 0.01% 92.37% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3200-3203 4 0.01% 92.38% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.38% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.39% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.40% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.40% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.41% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.42% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.42% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.43% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.43% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.43% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.44% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.44% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.44% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.45% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.45% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.45% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4416-4419 3 0.01% 92.46% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.46% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.47% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.48% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.48% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::5056-5059 2 0.01% 92.49% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.49% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.50% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::5440-5443 2 0.01% 92.50% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.51% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5760-5763 1 0.00% 92.51% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.51% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.51% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.52% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.52% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.52% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::7168-7171 3 0.01% 92.53% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.53% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.54% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.54% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.55% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.55% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.55% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.55% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::7936-7939 3 0.01% 92.56% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.57% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.58% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::8192-8195 2437 6.56% 99.14% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.15% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.15% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.15% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.15% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.16% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.16% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.16% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.17% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.17% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.17% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.17% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.18% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.18% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.18% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.19% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.19% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.19% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.19% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.24% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.24% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.24% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.25% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.25% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::16384-16387 242 0.65% 99.90% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.92% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::16512-16515 9 0.02% 99.95% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.96% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::16704-16707 2 0.01% 99.97% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.97% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::16832-16835 4 0.01% 99.98% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::17024-17027 3 0.01% 99.99% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::17344-17347 2 0.01% 100.00% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::total 37132 # Bytes accessed per row activation 297system.physmem.totQLat 3659130000 # Total cycles spent in queuing delays 298system.physmem.totMemAccLat 11798708750 # Sum of mem lat for all requests 299system.physmem.totBusLat 2214635000 # Total cycles spent in databus access 300system.physmem.totBankLat 5924943750 # Total cycles spent in bank access 301system.physmem.avgQLat 8261.25 # Average queueing delay per request 302system.physmem.avgBankLat 13376.80 # Average bank access latency per request 303system.physmem.avgBusLat 5000.00 # Average bus latency per request 304system.physmem.avgMemAccLat 26638.04 # Average memory access latency 305system.physmem.avgRdBW 14.78 # Average achieved read bandwidth in MB/s 306system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MB/s 307system.physmem.avgConsumedRdBW 14.78 # Average consumed read bandwidth in MB/s 308system.physmem.avgConsumedWrBW 3.85 # Average consumed write bandwidth in MB/s 309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 134system.physmem.wrQLenPdf::0 4636 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::2 4672 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::3 5362 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::4 6093 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::5 5438 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::6 5429 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::7 5533 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::8 5593 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::9 4916 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::10 4913 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::11 4899 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::12 5734 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::13 5836 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::14 5819 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::15 5861 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::16 5900 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::17 4775 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::18 4734 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::20 4698 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::21 4676 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::22 213 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::23 175 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::25 26 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see 166system.physmem.bytesPerActivate::samples 46254 # Bytes accessed per row activation 167system.physmem.bytesPerActivate::mean 772.575777 # Bytes accessed per row activation 168system.physmem.bytesPerActivate::gmean 229.901205 # Bytes accessed per row activation 169system.physmem.bytesPerActivate::stdev 1785.674907 # Bytes accessed per row activation 170system.physmem.bytesPerActivate::64-67 16351 35.35% 35.35% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::128-131 6669 14.42% 49.77% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::192-195 4598 9.94% 59.71% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::256-259 2705 5.85% 65.56% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::320-323 1760 3.81% 69.36% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::384-387 1480 3.20% 72.56% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::448-451 1070 2.31% 74.88% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::512-515 848 1.83% 76.71% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::576-579 733 1.58% 78.29% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::640-643 614 1.33% 79.62% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::704-707 629 1.36% 80.98% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::768-771 417 0.90% 81.88% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::832-835 327 0.71% 82.59% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::896-899 305 0.66% 83.25% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::960-963 281 0.61% 83.86% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1024-1027 335 0.72% 84.58% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1088-1091 208 0.45% 85.03% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1152-1155 173 0.37% 85.40% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1216-1219 157 0.34% 85.74% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1280-1283 138 0.30% 86.04% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1344-1347 163 0.35% 86.39% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1408-1411 903 1.95% 88.35% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1472-1475 167 0.36% 88.71% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1536-1539 98 0.21% 88.92% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1600-1603 103 0.22% 89.14% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1664-1667 86 0.19% 89.33% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1728-1731 86 0.19% 89.51% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1792-1795 55 0.12% 89.63% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1856-1859 76 0.16% 89.80% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1920-1923 70 0.15% 89.95% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1984-1987 69 0.15% 90.10% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2048-2051 49 0.11% 90.20% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2112-2115 76 0.16% 90.37% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2176-2179 62 0.13% 90.50% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2240-2243 63 0.14% 90.64% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2304-2307 35 0.08% 90.71% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2368-2371 62 0.13% 90.85% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2432-2435 58 0.13% 90.97% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2496-2499 65 0.14% 91.11% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2560-2563 35 0.08% 91.19% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2624-2627 74 0.16% 91.35% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2688-2691 59 0.13% 91.48% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2752-2755 59 0.13% 91.61% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2816-2819 26 0.06% 91.66% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2880-2883 59 0.13% 91.79% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2944-2947 60 0.13% 91.92% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3008-3011 63 0.14% 92.05% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3072-3075 34 0.07% 92.13% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3136-3139 64 0.14% 92.27% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3200-3203 58 0.13% 92.39% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3264-3267 54 0.12% 92.51% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3328-3331 33 0.07% 92.58% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3392-3395 54 0.12% 92.70% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3456-3459 58 0.13% 92.82% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3520-3523 64 0.14% 92.96% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3584-3587 34 0.07% 93.03% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3648-3651 65 0.14% 93.17% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3712-3715 57 0.12% 93.30% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3776-3779 56 0.12% 93.42% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3840-3843 28 0.06% 93.48% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3904-3907 54 0.12% 93.60% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3968-3971 53 0.11% 93.71% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4032-4035 65 0.14% 93.85% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.92% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4160-4163 67 0.14% 94.06% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4224-4227 53 0.11% 94.18% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4288-4291 55 0.12% 94.30% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4352-4355 27 0.06% 94.36% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4416-4419 54 0.12% 94.47% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4480-4483 56 0.12% 94.59% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4544-4547 66 0.14% 94.74% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4608-4611 372 0.80% 95.54% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4672-4675 49 0.11% 95.65% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4736-4739 28 0.06% 95.71% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4800-4803 48 0.10% 95.81% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4864-4867 28 0.06% 95.87% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4928-4931 51 0.11% 95.98% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4992-4995 28 0.06% 96.04% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5056-5059 52 0.11% 96.15% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5120-5123 28 0.06% 96.21% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5184-5187 51 0.11% 96.32% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5248-5251 40 0.09% 96.41% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5312-5315 53 0.11% 96.53% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5376-5379 25 0.05% 96.58% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5440-5443 51 0.11% 96.69% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5504-5507 26 0.06% 96.75% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5568-5571 51 0.11% 96.86% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5632-5635 24 0.05% 96.91% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5696-5699 50 0.11% 97.02% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5760-5763 28 0.06% 97.08% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5824-5827 50 0.11% 97.19% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5888-5891 26 0.06% 97.24% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5952-5955 50 0.11% 97.35% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6016-6019 27 0.06% 97.41% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6080-6083 51 0.11% 97.52% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6144-6147 28 0.06% 97.58% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6208-6211 50 0.11% 97.69% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6272-6275 26 0.06% 97.74% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6336-6339 49 0.11% 97.85% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6400-6403 26 0.06% 97.91% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6464-6467 52 0.11% 98.02% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6528-6531 25 0.05% 98.07% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6592-6595 52 0.11% 98.18% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6656-6659 25 0.05% 98.24% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6720-6723 52 0.11% 98.35% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6784-6787 425 0.92% 99.27% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.27% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::7168-7171 13 0.03% 99.30% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.30% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.30% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.31% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7680-7683 4 0.01% 99.31% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.32% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.32% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.32% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.33% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.34% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.34% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.35% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.35% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.35% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.36% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.36% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.38% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.38% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.38% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.38% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.39% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.39% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.39% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.39% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.40% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.40% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.40% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.40% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.41% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::10880-10883 2 0.00% 99.41% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.42% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.43% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.43% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.44% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.44% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.44% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.45% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.45% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.46% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.46% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.46% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.46% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.46% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::13504-13507 3 0.01% 99.47% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.47% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.48% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.48% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.49% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.49% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.49% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.50% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::14336-14339 2 0.00% 99.50% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.50% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.51% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::14848-14851 2 0.00% 99.51% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.51% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.52% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.52% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.52% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::15360-15363 35 0.08% 99.60% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.60% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.60% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.60% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.61% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.61% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.61% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::16384-16387 180 0.39% 100.00% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::total 46254 # Bytes accessed per row activation 351system.physmem.totQLat 6257775000 # Total ticks spent queuing 352system.physmem.totMemAccLat 14505282500 # Total ticks spent from burst creation until serviced by the DRAM 353system.physmem.totBusLat 2214585000 # Total ticks spent in databus transfers 354system.physmem.totBankLat 6032922500 # Total ticks spent accessing banks 355system.physmem.avgQLat 14128.55 # Average queueing delay per DRAM burst 356system.physmem.avgBankLat 13620.89 # Average bank access latency per DRAM burst 357system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 358system.physmem.avgMemAccLat 32749.44 # Average memory access latency per DRAM burst 359system.physmem.avgRdBW 14.76 # Average DRAM read bandwidth in MiByte/s 360system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s 361system.physmem.avgRdBWSys 14.76 # Average system read bandwidth in MiByte/s 362system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s 363system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 310system.physmem.busUtil 0.15 # Data bus utilization in percentage | 364system.physmem.busUtil 0.15 # Data bus utilization in percentage |
| 311system.physmem.avgRdQLen 0.01 # Average read queue length over time 312system.physmem.avgWrQLen 13.19 # Average write queue length over time 313system.physmem.readRowHits 427838 # Number of row buffer hits during reads 314system.physmem.writeRowHits 93417 # Number of row buffer hits during writes 315system.physmem.readRowHitRate 96.59 # Row buffer hit rate for reads 316system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes 317system.physmem.avgGap 3435369.03 # Average gap between requests 318system.membus.throughput 18671288 # Throughput (bytes/s) 319system.membus.trans_dist::ReadReq 292313 # Transaction distribution 320system.membus.trans_dist::ReadResp 292313 # Transaction distribution 321system.membus.trans_dist::WriteReq 9649 # Transaction distribution 322system.membus.trans_dist::WriteResp 9649 # Transaction distribution 323system.membus.trans_dist::Writeback 115467 # Transaction distribution | 365system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 366system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 367system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing 368system.physmem.avgWrQLen 14.25 # Average write queue length when enqueuing 369system.physmem.readRowHits 419360 # Number of row buffer hits during reads 370system.physmem.writeRowHits 92763 # Number of row buffer hits during writes 371system.physmem.readRowHitRate 94.68 # Row buffer hit rate for reads 372system.physmem.writeRowHitRate 80.34 # Row buffer hit rate for writes 373system.physmem.avgGap 3438931.31 # Average gap between requests 374system.physmem.pageHitRate 91.72 # Row buffer hit rate, read and write combined 375system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state 376system.membus.throughput 18651952 # Throughput (bytes/s) 377system.membus.trans_dist::ReadReq 292310 # Transaction distribution 378system.membus.trans_dist::ReadResp 292310 # Transaction distribution 379system.membus.trans_dist::WriteReq 9650 # Transaction distribution 380system.membus.trans_dist::WriteResp 9650 # Transaction distribution 381system.membus.trans_dist::Writeback 115466 # Transaction distribution |
| 324system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 325system.membus.trans_dist::UpgradeResp 132 # Transaction distribution | 382system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 383system.membus.trans_dist::UpgradeResp 132 # Transaction distribution |
| 326system.membus.trans_dist::ReadExReq 158147 # Transaction distribution 327system.membus.trans_dist::ReadExResp 158147 # Transaction distribution 328system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) 329system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877556 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes) | 384system.membus.trans_dist::ReadExReq 158141 # Transaction distribution 385system.membus.trans_dist::ReadExResp 158141 # Transaction distribution 386system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) 387system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877537 # Packet count per connected master and slave (bytes) 388system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910697 # Packet count per connected master and slave (bytes) |
| 331system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) 332system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) | 389system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) 390system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) |
| 333system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes) 334system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) 335system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes) 336system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes) | 391system.membus.pkt_count::total 1035377 # Packet count per connected master and slave (bytes) 392system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) 393system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30430656 # Cumulative packet size per connected master and slave (bytes) 394system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475220 # Cumulative packet size per connected master and slave (bytes) |
| 337system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) 338system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) | 395system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) 396system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) |
| 339system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes) 340system.membus.data_through_bus 35784972 # Total data (bytes) | 397system.membus.tot_pkt_size::total 35784340 # Cumulative packet size per connected master and slave (bytes) 398system.membus.data_through_bus 35784340 # Total data (bytes) |
| 341system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) | 399system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) |
| 342system.membus.reqLayer0.occupancy 32373000 # Layer occupancy (ticks) | 400system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) |
| 343system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 401system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 344system.membus.reqLayer1.occupancy 1487941500 # Layer occupancy (ticks) | 402system.membus.reqLayer1.occupancy 1489694250 # Layer occupancy (ticks) |
| 345system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 403system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 346system.membus.respLayer1.occupancy 3745756604 # Layer occupancy (ticks) | 404system.membus.respLayer1.occupancy 3746415596 # Layer occupancy (ticks) |
| 347system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 405system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 348system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks) | 406system.membus.respLayer2.occupancy 376299750 # Layer occupancy (ticks) |
| 349system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 350system.iocache.tags.replacements 41685 # number of replacements | 407system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 408system.iocache.tags.replacements 41685 # number of replacements |
| 351system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use | 409system.iocache.tags.tagsinuse 1.352288 # Cycle average of tags in use |
| 352system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 353system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 354system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 410system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 411system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 412system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 355system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. 356system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor 357system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy 358system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy | 413system.iocache.tags.warmup_cycle 1753529489000 # Cycle when the warmup percentage was hit. 414system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor 415system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy 416system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy |
| 359system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 360system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 361system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 362system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 363system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 364system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 365system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 366system.iocache.overall_misses::total 41725 # number of overall misses | 417system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 418system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 419system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 420system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 421system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 422system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 423system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 424system.iocache.overall_misses::total 41725 # number of overall misses |
| 367system.iocache.ReadReq_miss_latency::tsunami.ide 21343633 # number of ReadReq miss cycles 368system.iocache.ReadReq_miss_latency::total 21343633 # number of ReadReq miss cycles 369system.iocache.WriteReq_miss_latency::tsunami.ide 10434225282 # number of WriteReq miss cycles 370system.iocache.WriteReq_miss_latency::total 10434225282 # number of WriteReq miss cycles 371system.iocache.demand_miss_latency::tsunami.ide 10455568915 # number of demand (read+write) miss cycles 372system.iocache.demand_miss_latency::total 10455568915 # number of demand (read+write) miss cycles 373system.iocache.overall_miss_latency::tsunami.ide 10455568915 # number of overall miss cycles 374system.iocache.overall_miss_latency::total 10455568915 # number of overall miss cycles | 425system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles 426system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles 427system.iocache.WriteReq_miss_latency::tsunami.ide 12989922573 # number of WriteReq miss cycles 428system.iocache.WriteReq_miss_latency::total 12989922573 # number of WriteReq miss cycles 429system.iocache.demand_miss_latency::tsunami.ide 13011056956 # number of demand (read+write) miss cycles 430system.iocache.demand_miss_latency::total 13011056956 # number of demand (read+write) miss cycles 431system.iocache.overall_miss_latency::tsunami.ide 13011056956 # number of overall miss cycles 432system.iocache.overall_miss_latency::total 13011056956 # number of overall miss cycles |
| 375system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 376system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 377system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 378system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 379system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 380system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 381system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 382system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 383system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 384system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 385system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 386system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 387system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 388system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 389system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 390system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 433system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 434system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 435system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 436system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 437system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 438system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 439system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 440system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 441system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 442system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 443system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 444system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 445system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 446system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 447system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 448system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 391system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123373.601156 # average ReadReq miss latency 392system.iocache.ReadReq_avg_miss_latency::total 123373.601156 # average ReadReq miss latency 393system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251112.468281 # average WriteReq miss latency 394system.iocache.WriteReq_avg_miss_latency::total 251112.468281 # average WriteReq miss latency 395system.iocache.demand_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency 396system.iocache.demand_avg_miss_latency::total 250582.837987 # average overall miss latency 397system.iocache.overall_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency 398system.iocache.overall_avg_miss_latency::total 250582.837987 # average overall miss latency 399system.iocache.blocked_cycles::no_mshrs 272640 # number of cycles access was blocked | 449system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency 450system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency 451system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775 # average WriteReq miss latency 452system.iocache.WriteReq_avg_miss_latency::total 312618.467775 # average WriteReq miss latency 453system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency 454system.iocache.demand_avg_miss_latency::total 311828.806615 # average overall miss latency 455system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency 456system.iocache.overall_avg_miss_latency::total 311828.806615 # average overall miss latency 457system.iocache.blocked_cycles::no_mshrs 403484 # number of cycles access was blocked |
| 400system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 458system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 401system.iocache.blocked::no_mshrs 27184 # number of cycles access was blocked | 459system.iocache.blocked::no_mshrs 29141 # number of cycles access was blocked |
| 402system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 460system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 403system.iocache.avg_blocked_cycles::no_mshrs 10.029429 # average number of cycles each access was blocked | 461system.iocache.avg_blocked_cycles::no_mshrs 13.845922 # average number of cycles each access was blocked |
| 404system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 405system.iocache.fast_writes 0 # number of fast writes performed 406system.iocache.cache_copies 0 # number of cache copies performed 407system.iocache.writebacks::writebacks 41512 # number of writebacks 408system.iocache.writebacks::total 41512 # number of writebacks 409system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 410system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 411system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 412system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 413system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 414system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 415system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 416system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 462system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 463system.iocache.fast_writes 0 # number of fast writes performed 464system.iocache.cache_copies 0 # number of cache copies performed 465system.iocache.writebacks::writebacks 41512 # number of writebacks 466system.iocache.writebacks::total 41512 # number of writebacks 467system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 468system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 469system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 470system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 471system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 472system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 473system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 474system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 417system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles 418system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles 419system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8272160782 # number of WriteReq MSHR miss cycles 420system.iocache.WriteReq_mshr_miss_latency::total 8272160782 # number of WriteReq MSHR miss cycles 421system.iocache.demand_mshr_miss_latency::tsunami.ide 8284506915 # number of demand (read+write) MSHR miss cycles 422system.iocache.demand_mshr_miss_latency::total 8284506915 # number of demand (read+write) MSHR miss cycles 423system.iocache.overall_mshr_miss_latency::tsunami.ide 8284506915 # number of overall MSHR miss cycles 424system.iocache.overall_mshr_miss_latency::total 8284506915 # number of overall MSHR miss cycles | 475system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles 476system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles 477system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10827670073 # number of WriteReq MSHR miss cycles 478system.iocache.WriteReq_mshr_miss_latency::total 10827670073 # number of WriteReq MSHR miss cycles 479system.iocache.demand_mshr_miss_latency::tsunami.ide 10839807456 # number of demand (read+write) MSHR miss cycles 480system.iocache.demand_mshr_miss_latency::total 10839807456 # number of demand (read+write) MSHR miss cycles 481system.iocache.overall_mshr_miss_latency::tsunami.ide 10839807456 # number of overall MSHR miss cycles 482system.iocache.overall_mshr_miss_latency::total 10839807456 # number of overall MSHR miss cycles |
| 425system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 426system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 427system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 428system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 429system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 431system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 483system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 484system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 485system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 486system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 487system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 488system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 489system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 490system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 433system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency 434system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency 435system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199079.726174 # average WriteReq mshr miss latency 436system.iocache.WriteReq_avg_mshr_miss_latency::total 199079.726174 # average WriteReq mshr miss latency 437system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency 438system.iocache.demand_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency 439system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency 440system.iocache.overall_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency | 491system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency 492system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency 493system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218 # average WriteReq mshr miss latency 494system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218 # average WriteReq mshr miss latency 495system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency 496system.iocache.demand_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency 497system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency 498system.iocache.overall_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency |
| 441system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 444system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 445system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 446system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 447system.disk0.dma_write_txs 395 # Number of DMA write transactions. 448system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 449system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 450system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 451system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 452system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 453system.disk2.dma_write_txs 1 # Number of DMA write transactions. 454system.cpu.dtb.fetch_hits 0 # ITB hits 455system.cpu.dtb.fetch_misses 0 # ITB misses 456system.cpu.dtb.fetch_acv 0 # ITB acv 457system.cpu.dtb.fetch_accesses 0 # ITB accesses | 499system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 500system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 501system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 502system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 503system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 504system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 505system.disk0.dma_write_txs 395 # Number of DMA write transactions. 506system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 507system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 508system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 509system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 510system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 511system.disk2.dma_write_txs 1 # Number of DMA write transactions. 512system.cpu.dtb.fetch_hits 0 # ITB hits 513system.cpu.dtb.fetch_misses 0 # ITB misses 514system.cpu.dtb.fetch_acv 0 # ITB acv 515system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 458system.cpu.dtb.read_hits 9065600 # DTB read hits 459system.cpu.dtb.read_misses 10324 # DTB read misses | 516system.cpu.dtb.read_hits 9064966 # DTB read hits 517system.cpu.dtb.read_misses 10312 # DTB read misses |
| 460system.cpu.dtb.read_acv 210 # DTB read access violations | 518system.cpu.dtb.read_acv 210 # DTB read access violations |
| 461system.cpu.dtb.read_accesses 728853 # DTB read accesses 462system.cpu.dtb.write_hits 6356756 # DTB write hits 463system.cpu.dtb.write_misses 1142 # DTB write misses | 519system.cpu.dtb.read_accesses 728817 # DTB read accesses 520system.cpu.dtb.write_hits 6356267 # DTB write hits 521system.cpu.dtb.write_misses 1140 # DTB write misses |
| 464system.cpu.dtb.write_acv 157 # DTB write access violations | 522system.cpu.dtb.write_acv 157 # DTB write access violations |
| 465system.cpu.dtb.write_accesses 291931 # DTB write accesses 466system.cpu.dtb.data_hits 15422356 # DTB hits 467system.cpu.dtb.data_misses 11466 # DTB misses | 523system.cpu.dtb.write_accesses 291929 # DTB write accesses 524system.cpu.dtb.data_hits 15421233 # DTB hits 525system.cpu.dtb.data_misses 11452 # DTB misses |
| 468system.cpu.dtb.data_acv 367 # DTB access violations | 526system.cpu.dtb.data_acv 367 # DTB access violations |
| 469system.cpu.dtb.data_accesses 1020784 # DTB accesses 470system.cpu.itb.fetch_hits 4974352 # ITB hits 471system.cpu.itb.fetch_misses 5010 # ITB misses | 527system.cpu.dtb.data_accesses 1020746 # DTB accesses 528system.cpu.itb.fetch_hits 4973920 # ITB hits 529system.cpu.itb.fetch_misses 4997 # ITB misses |
| 472system.cpu.itb.fetch_acv 184 # ITB acv | 530system.cpu.itb.fetch_acv 184 # ITB acv |
| 473system.cpu.itb.fetch_accesses 4979362 # ITB accesses | 531system.cpu.itb.fetch_accesses 4978917 # ITB accesses |
| 474system.cpu.itb.read_hits 0 # DTB read hits 475system.cpu.itb.read_misses 0 # DTB read misses 476system.cpu.itb.read_acv 0 # DTB read access violations 477system.cpu.itb.read_accesses 0 # DTB read accesses 478system.cpu.itb.write_hits 0 # DTB write hits 479system.cpu.itb.write_misses 0 # DTB write misses 480system.cpu.itb.write_acv 0 # DTB write access violations 481system.cpu.itb.write_accesses 0 # DTB write accesses 482system.cpu.itb.data_hits 0 # DTB hits 483system.cpu.itb.data_misses 0 # DTB misses 484system.cpu.itb.data_acv 0 # DTB access violations 485system.cpu.itb.data_accesses 0 # DTB accesses | 532system.cpu.itb.read_hits 0 # DTB read hits 533system.cpu.itb.read_misses 0 # DTB read misses 534system.cpu.itb.read_acv 0 # DTB read access violations 535system.cpu.itb.read_accesses 0 # DTB read accesses 536system.cpu.itb.write_hits 0 # DTB write hits 537system.cpu.itb.write_misses 0 # DTB write misses 538system.cpu.itb.write_acv 0 # DTB write access violations 539system.cpu.itb.write_accesses 0 # DTB write accesses 540system.cpu.itb.data_hits 0 # DTB hits 541system.cpu.itb.data_misses 0 # DTB misses 542system.cpu.itb.data_acv 0 # DTB access violations 543system.cpu.itb.data_accesses 0 # DTB accesses |
| 486system.cpu.numCycles 3836946188 # number of cpu cycles simulated | 544system.cpu.numCycles 3840856082 # number of cpu cycles simulated |
| 487system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 488system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 545system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 546system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 489system.cpu.committedInsts 56188014 # Number of instructions committed 490system.cpu.committedOps 56188014 # Number of ops (including micro ops) committed 491system.cpu.num_int_alu_accesses 52059797 # Number of integer alu accesses 492system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses 493system.cpu.num_func_calls 1483456 # number of times a function call or return occured 494system.cpu.num_conditional_control_insts 6468822 # number of instructions that are conditional controls 495system.cpu.num_int_insts 52059797 # number of integer instructions 496system.cpu.num_fp_insts 324527 # number of float instructions 497system.cpu.num_int_register_reads 71330046 # number of times the integer registers were read 498system.cpu.num_int_register_writes 38525190 # number of times the integer registers were written 499system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read 500system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written 501system.cpu.num_mem_refs 15474978 # number of memory refs 502system.cpu.num_load_insts 9102456 # Number of load instructions 503system.cpu.num_store_insts 6372522 # Number of store instructions 504system.cpu.num_idle_cycles 3586988416.498130 # Number of idle cycles 505system.cpu.num_busy_cycles 249957771.501870 # Number of busy cycles 506system.cpu.not_idle_fraction 0.065145 # Percentage of non-idle cycles 507system.cpu.idle_fraction 0.934855 # Percentage of idle cycles | 547system.cpu.committedInsts 56182750 # Number of instructions committed 548system.cpu.committedOps 56182750 # Number of ops (including micro ops) committed 549system.cpu.num_int_alu_accesses 52054772 # Number of integer alu accesses 550system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses 551system.cpu.num_func_calls 1483342 # number of times a function call or return occured 552system.cpu.num_conditional_control_insts 6468084 # number of instructions that are conditional controls 553system.cpu.num_int_insts 52054772 # number of integer instructions 554system.cpu.num_fp_insts 324326 # number of float instructions 555system.cpu.num_int_register_reads 71321847 # number of times the integer registers were read 556system.cpu.num_int_register_writes 38521555 # number of times the integer registers were written 557system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read 558system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written 559system.cpu.num_mem_refs 15473812 # number of memory refs 560system.cpu.num_load_insts 9101789 # Number of load instructions 561system.cpu.num_store_insts 6372023 # Number of store instructions 562system.cpu.num_idle_cycles 3588896828.998131 # Number of idle cycles 563system.cpu.num_busy_cycles 251959253.001869 # Number of busy cycles 564system.cpu.not_idle_fraction 0.065600 # Percentage of non-idle cycles 565system.cpu.idle_fraction 0.934400 # Percentage of idle cycles |
| 508system.cpu.kern.inst.arm 0 # number of arm instructions executed | 566system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 509system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 510system.cpu.kern.inst.hwrei 211982 # number of hwrei instructions executed 511system.cpu.kern.ipl_count::0 74893 40.89% 40.89% # number of times we switched to this ipl | 567system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed 568system.cpu.kern.inst.hwrei 211963 # number of hwrei instructions executed 569system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl |
| 512system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl | 570system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl |
| 513system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl 514system.cpu.kern.ipl_count::31 106209 57.99% 100.00% # number of times we switched to this ipl 515system.cpu.kern.ipl_count::total 183164 # number of times we switched to this ipl 516system.cpu.kern.ipl_good::0 73526 49.31% 49.31% # number of times we switched to this ipl from a different ipl | 571system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl 572system.cpu.kern.ipl_count::31 106216 57.99% 100.00% # number of times we switched to this ipl 573system.cpu.kern.ipl_count::total 183174 # number of times we switched to this ipl 574system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl |
| 517system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl | 575system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl |
| 518system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl 519system.cpu.kern.ipl_good::31 73526 49.31% 100.00% # number of times we switched to this ipl from a different ipl 520system.cpu.kern.ipl_good::total 149114 # number of times we switched to this ipl from a different ipl 521system.cpu.kern.ipl_ticks::0 1857159489000 96.80% 96.80% # number of cycles we spent at this ipl 522system.cpu.kern.ipl_ticks::21 91367000 0.00% 96.81% # number of cycles we spent at this ipl 523system.cpu.kern.ipl_ticks::22 736929000 0.04% 96.85% # number of cycles we spent at this ipl 524system.cpu.kern.ipl_ticks::31 60484575000 3.15% 100.00% # number of cycles we spent at this ipl 525system.cpu.kern.ipl_ticks::total 1918472360000 # number of cycles we spent at this ipl 526system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl | 576system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl 577system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl 578system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl 579system.cpu.kern.ipl_ticks::0 1858257404500 96.76% 96.76% # number of cycles we spent at this ipl 580system.cpu.kern.ipl_ticks::21 91623500 0.00% 96.77% # number of cycles we spent at this ipl 581system.cpu.kern.ipl_ticks::22 737068500 0.04% 96.81% # number of cycles we spent at this ipl 582system.cpu.kern.ipl_ticks::31 61341210500 3.19% 100.00% # number of cycles we spent at this ipl 583system.cpu.kern.ipl_ticks::total 1920427307000 # number of cycles we spent at this ipl 584system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl |
| 527system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 528system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 585system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 586system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 529system.cpu.kern.ipl_used::31 0.692277 # fraction of swpipl calls that actually changed the ipl 530system.cpu.kern.ipl_used::total 0.814101 # fraction of swpipl calls that actually changed the ipl | 587system.cpu.kern.ipl_used::31 0.692250 # fraction of swpipl calls that actually changed the ipl 588system.cpu.kern.ipl_used::total 0.814084 # fraction of swpipl calls that actually changed the ipl |
| 531system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 532system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 533system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 534system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 535system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 536system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 537system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 538system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 558system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 559system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 560system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 561system.cpu.kern.syscall::total 326 # number of syscalls executed 562system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 563system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 564system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 565system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 589system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 590system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 591system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 592system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 593system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 594system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 595system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 596system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 616system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 617system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 618system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 619system.cpu.kern.syscall::total 326 # number of syscalls executed 620system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 621system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 622system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 623system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 566system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed 567system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed | 624system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed 625system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed |
| 568system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 626system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 569system.cpu.kern.callpal::swpipl 175945 91.21% 93.41% # number of callpals executed 570system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed | 627system.cpu.kern.callpal::swpipl 175953 91.22% 93.41% # number of callpals executed 628system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed |
| 571system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 572system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed | 629system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 630system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed |
| 573system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed | 631system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed |
| 574system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed | 632system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed |
| 575system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed | 633system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed |
| 576system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 577system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 634system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 635system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 578system.cpu.kern.callpal::total 192891 # number of callpals executed | 636system.cpu.kern.callpal::total 192898 # number of callpals executed |
| 579system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches | 637system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches |
| 580system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 581system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 582system.cpu.kern.mode_good::kernel 1911 583system.cpu.kern.mode_good::user 1740 584system.cpu.kern.mode_good::idle 171 585system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches | 638system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 639system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches 640system.cpu.kern.mode_good::kernel 1908 641system.cpu.kern.mode_good::user 1739 642system.cpu.kern.mode_good::idle 169 643system.cpu.kern.mode_switch_good::kernel 0.323225 # fraction of useful protection mode switches |
| 586system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 644system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 587system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 588system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches 589system.cpu.kern.mode_ticks::kernel 46124802000 2.40% 2.40% # number of ticks spent at the given mode 590system.cpu.kern.mode_ticks::user 5245072500 0.27% 2.68% # number of ticks spent at the given mode 591system.cpu.kern.mode_ticks::idle 1867102483500 97.32% 100.00% # number of ticks spent at the given mode 592system.cpu.kern.swap_context 4179 # number of times the context was actually changed | 645system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches 646system.cpu.kern.mode_switch_good::total 0.391907 # fraction of useful protection mode switches 647system.cpu.kern.mode_ticks::kernel 46222890000 2.41% 2.41% # number of ticks spent at the given mode 648system.cpu.kern.mode_ticks::user 5212630500 0.27% 2.68% # number of ticks spent at the given mode 649system.cpu.kern.mode_ticks::idle 1868991784500 97.32% 100.00% # number of ticks spent at the given mode 650system.cpu.kern.swap_context 4176 # number of times the context was actually changed |
| 593system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 594system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 595system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 596system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 597system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 598system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 599system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 600system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 616system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 617system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 618system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 619system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 620system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 621system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 622system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 623system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 651system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 652system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 653system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 654system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 655system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 656system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 657system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 658system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 674system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 675system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 676system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 677system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 678system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 679system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 680system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 681system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 624system.iobus.throughput 1410582 # Throughput (bytes/s) | 682system.iobus.throughput 1409150 # Throughput (bytes/s) |
| 625system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 626system.iobus.trans_dist::ReadResp 7103 # Transaction distribution | 683system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 684system.iobus.trans_dist::ReadResp 7103 # Transaction distribution |
| 627system.iobus.trans_dist::WriteReq 51201 # Transaction distribution 628system.iobus.trans_dist::WriteResp 51201 # Transaction distribution 629system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) | 685system.iobus.trans_dist::WriteReq 51202 # Transaction distribution 686system.iobus.trans_dist::WriteResp 51202 # Transaction distribution 687system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) |
| 630system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 631system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 632system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 633system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 634system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 635system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 636system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 637system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 638system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 639system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 640system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 688system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 689system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 690system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 691system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 692system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 693system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 694system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 695system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 696system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 697system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 698system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 641system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) | 699system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) |
| 642system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 643system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) | 700system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 701system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) |
| 644system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) 645system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) | 702system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) 703system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) |
| 646system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 647system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 648system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 649system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 650system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 651system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 652system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 653system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 654system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 655system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 656system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 704system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 705system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 706system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 707system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 708system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 709system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 710system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 711system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 712system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 713system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 714system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 657system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) | 715system.iobus.tot_pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) |
| 658system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 659system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) | 716system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 717system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) |
| 660system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) 661system.iobus.data_through_bus 2706164 # Total data (bytes) 662system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) | 718system.iobus.tot_pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) 719system.iobus.data_through_bus 2706172 # Total data (bytes) 720system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) |
| 663system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 664system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 665system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 666system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 667system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 668system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 669system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 670system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 676system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 677system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 678system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 679system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 680system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 681system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 682system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 683system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 721system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 722system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 723system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 724system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 725system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 726system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 727system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 728system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 734system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 735system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 736system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 737system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 738system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 739system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 740system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 741system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 684system.iobus.reqLayer29.occupancy 378268915 # Layer occupancy (ticks) | 742system.iobus.reqLayer29.occupancy 377727206 # Layer occupancy (ticks) |
| 685system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 686system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 687system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | 743system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 744system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 745system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) |
| 688system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) | 746system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) |
| 689system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 747system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 690system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks) | 748system.iobus.respLayer1.occupancy 42674250 # Layer occupancy (ticks) |
| 691system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 749system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 692system.cpu.icache.tags.replacements 928665 # number of replacements 693system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use 694system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. 695system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. 696system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. 697system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. 698system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor 699system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy 700system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy 701system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits 702system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits 703system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits 704system.cpu.icache.demand_hits::total 55270512 # number of demand (read+write) hits 705system.cpu.icache.overall_hits::cpu.inst 55270512 # number of overall hits 706system.cpu.icache.overall_hits::total 55270512 # number of overall hits 707system.cpu.icache.ReadReq_misses::cpu.inst 929336 # number of ReadReq misses 708system.cpu.icache.ReadReq_misses::total 929336 # number of ReadReq misses 709system.cpu.icache.demand_misses::cpu.inst 929336 # number of demand (read+write) misses 710system.cpu.icache.demand_misses::total 929336 # number of demand (read+write) misses 711system.cpu.icache.overall_misses::cpu.inst 929336 # number of overall misses 712system.cpu.icache.overall_misses::total 929336 # number of overall misses 713system.cpu.icache.ReadReq_miss_latency::cpu.inst 13015346257 # number of ReadReq miss cycles 714system.cpu.icache.ReadReq_miss_latency::total 13015346257 # number of ReadReq miss cycles 715system.cpu.icache.demand_miss_latency::cpu.inst 13015346257 # number of demand (read+write) miss cycles 716system.cpu.icache.demand_miss_latency::total 13015346257 # number of demand (read+write) miss cycles 717system.cpu.icache.overall_miss_latency::cpu.inst 13015346257 # number of overall miss cycles 718system.cpu.icache.overall_miss_latency::total 13015346257 # number of overall miss cycles 719system.cpu.icache.ReadReq_accesses::cpu.inst 56199848 # number of ReadReq accesses(hits+misses) 720system.cpu.icache.ReadReq_accesses::total 56199848 # number of ReadReq accesses(hits+misses) 721system.cpu.icache.demand_accesses::cpu.inst 56199848 # number of demand (read+write) accesses 722system.cpu.icache.demand_accesses::total 56199848 # number of demand (read+write) accesses 723system.cpu.icache.overall_accesses::cpu.inst 56199848 # number of overall (read+write) accesses 724system.cpu.icache.overall_accesses::total 56199848 # number of overall (read+write) accesses 725system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016536 # miss rate for ReadReq accesses 726system.cpu.icache.ReadReq_miss_rate::total 0.016536 # miss rate for ReadReq accesses 727system.cpu.icache.demand_miss_rate::cpu.inst 0.016536 # miss rate for demand accesses 728system.cpu.icache.demand_miss_rate::total 0.016536 # miss rate for demand accesses 729system.cpu.icache.overall_miss_rate::cpu.inst 0.016536 # miss rate for overall accesses 730system.cpu.icache.overall_miss_rate::total 0.016536 # miss rate for overall accesses 731system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14004.995241 # average ReadReq miss latency 732system.cpu.icache.ReadReq_avg_miss_latency::total 14004.995241 # average ReadReq miss latency 733system.cpu.icache.demand_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency 734system.cpu.icache.demand_avg_miss_latency::total 14004.995241 # average overall miss latency 735system.cpu.icache.overall_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency 736system.cpu.icache.overall_avg_miss_latency::total 14004.995241 # average overall miss latency | 750system.cpu.icache.tags.replacements 928358 # number of replacements 751system.cpu.icache.tags.tagsinuse 508.321671 # Cycle average of tags in use 752system.cpu.icache.tags.total_refs 55265541 # Total number of references to valid blocks. 753system.cpu.icache.tags.sampled_refs 928869 # Sample count of references to valid blocks. 754system.cpu.icache.tags.avg_refs 59.497670 # Average number of references to valid blocks. 755system.cpu.icache.tags.warmup_cycle 39723654250 # Cycle when the warmup percentage was hit. 756system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor 757system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy 758system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy 759system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits 760system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits 761system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits 762system.cpu.icache.demand_hits::total 55265541 # number of demand (read+write) hits 763system.cpu.icache.overall_hits::cpu.inst 55265541 # number of overall hits 764system.cpu.icache.overall_hits::total 55265541 # number of overall hits 765system.cpu.icache.ReadReq_misses::cpu.inst 929029 # number of ReadReq misses 766system.cpu.icache.ReadReq_misses::total 929029 # number of ReadReq misses 767system.cpu.icache.demand_misses::cpu.inst 929029 # number of demand (read+write) misses 768system.cpu.icache.demand_misses::total 929029 # number of demand (read+write) misses 769system.cpu.icache.overall_misses::cpu.inst 929029 # number of overall misses 770system.cpu.icache.overall_misses::total 929029 # number of overall misses 771system.cpu.icache.ReadReq_miss_latency::cpu.inst 12961853258 # number of ReadReq miss cycles 772system.cpu.icache.ReadReq_miss_latency::total 12961853258 # number of ReadReq miss cycles 773system.cpu.icache.demand_miss_latency::cpu.inst 12961853258 # number of demand (read+write) miss cycles 774system.cpu.icache.demand_miss_latency::total 12961853258 # number of demand (read+write) miss cycles 775system.cpu.icache.overall_miss_latency::cpu.inst 12961853258 # number of overall miss cycles 776system.cpu.icache.overall_miss_latency::total 12961853258 # number of overall miss cycles 777system.cpu.icache.ReadReq_accesses::cpu.inst 56194570 # number of ReadReq accesses(hits+misses) 778system.cpu.icache.ReadReq_accesses::total 56194570 # number of ReadReq accesses(hits+misses) 779system.cpu.icache.demand_accesses::cpu.inst 56194570 # number of demand (read+write) accesses 780system.cpu.icache.demand_accesses::total 56194570 # number of demand (read+write) accesses 781system.cpu.icache.overall_accesses::cpu.inst 56194570 # number of overall (read+write) accesses 782system.cpu.icache.overall_accesses::total 56194570 # number of overall (read+write) accesses 783system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses 784system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses 785system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses 786system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses 787system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses 788system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses 789system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13952.043755 # average ReadReq miss latency 790system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755 # average ReadReq miss latency 791system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency 792system.cpu.icache.demand_avg_miss_latency::total 13952.043755 # average overall miss latency 793system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency 794system.cpu.icache.overall_avg_miss_latency::total 13952.043755 # average overall miss latency |
| 737system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 738system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 739system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 740system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 741system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 742system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 743system.cpu.icache.fast_writes 0 # number of fast writes performed 744system.cpu.icache.cache_copies 0 # number of cache copies performed | 795system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 796system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 797system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 798system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 799system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 800system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 801system.cpu.icache.fast_writes 0 # number of fast writes performed 802system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 745system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929336 # number of ReadReq MSHR misses 746system.cpu.icache.ReadReq_mshr_misses::total 929336 # number of ReadReq MSHR misses 747system.cpu.icache.demand_mshr_misses::cpu.inst 929336 # number of demand (read+write) MSHR misses 748system.cpu.icache.demand_mshr_misses::total 929336 # number of demand (read+write) MSHR misses 749system.cpu.icache.overall_mshr_misses::cpu.inst 929336 # number of overall MSHR misses 750system.cpu.icache.overall_mshr_misses::total 929336 # number of overall MSHR misses 751system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11150220743 # number of ReadReq MSHR miss cycles 752system.cpu.icache.ReadReq_mshr_miss_latency::total 11150220743 # number of ReadReq MSHR miss cycles 753system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11150220743 # number of demand (read+write) MSHR miss cycles 754system.cpu.icache.demand_mshr_miss_latency::total 11150220743 # number of demand (read+write) MSHR miss cycles 755system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11150220743 # number of overall MSHR miss cycles 756system.cpu.icache.overall_mshr_miss_latency::total 11150220743 # number of overall MSHR miss cycles 757system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for ReadReq accesses 758system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016536 # mshr miss rate for ReadReq accesses 759system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for demand accesses 760system.cpu.icache.demand_mshr_miss_rate::total 0.016536 # mshr miss rate for demand accesses 761system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for overall accesses 762system.cpu.icache.overall_mshr_miss_rate::total 0.016536 # mshr miss rate for overall accesses 763system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.051020 # average ReadReq mshr miss latency 764system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.051020 # average ReadReq mshr miss latency 765system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency 766system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency 767system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency 768system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency | 803system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929029 # number of ReadReq MSHR misses 804system.cpu.icache.ReadReq_mshr_misses::total 929029 # number of ReadReq MSHR misses 805system.cpu.icache.demand_mshr_misses::cpu.inst 929029 # number of demand (read+write) MSHR misses 806system.cpu.icache.demand_mshr_misses::total 929029 # number of demand (read+write) MSHR misses 807system.cpu.icache.overall_mshr_misses::cpu.inst 929029 # number of overall MSHR misses 808system.cpu.icache.overall_mshr_misses::total 929029 # number of overall MSHR misses 809system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11098555742 # number of ReadReq MSHR miss cycles 810system.cpu.icache.ReadReq_mshr_miss_latency::total 11098555742 # number of ReadReq MSHR miss cycles 811system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11098555742 # number of demand (read+write) MSHR miss cycles 812system.cpu.icache.demand_mshr_miss_latency::total 11098555742 # number of demand (read+write) MSHR miss cycles 813system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11098555742 # number of overall MSHR miss cycles 814system.cpu.icache.overall_mshr_miss_latency::total 11098555742 # number of overall MSHR miss cycles 815system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses 816system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses 817system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses 818system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses 819system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses 820system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses 821system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11946.403979 # average ReadReq mshr miss latency 822system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11946.403979 # average ReadReq mshr miss latency 823system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency 824system.cpu.icache.demand_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency 825system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency 826system.cpu.icache.overall_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency |
| 769system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 827system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 770system.cpu.l2cache.tags.replacements 336065 # number of replacements 771system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use 772system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks. 773system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks. 774system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks. 775system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit. 776system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753 # Average occupied blocks per requestor 777system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor 778system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor 779system.cpu.l2cache.tags.occ_percent::writebacks 0.848589 # Average percentage of cache occupancy 780system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072620 # Average percentage of cache occupancy 781system.cpu.l2cache.tags.occ_percent::cpu.data 0.075203 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy 783system.cpu.l2cache.ReadReq_hits::cpu.inst 916024 # number of ReadReq hits 784system.cpu.l2cache.ReadReq_hits::cpu.data 814969 # number of ReadReq hits 785system.cpu.l2cache.ReadReq_hits::total 1730993 # number of ReadReq hits 786system.cpu.l2cache.Writeback_hits::writebacks 835407 # number of Writeback hits 787system.cpu.l2cache.Writeback_hits::total 835407 # number of Writeback hits | 828system.cpu.l2cache.tags.replacements 336056 # number of replacements 829system.cpu.l2cache.tags.tagsinuse 65296.863719 # Cycle average of tags in use 830system.cpu.l2cache.tags.total_refs 2447536 # Total number of references to valid blocks. 831system.cpu.l2cache.tags.sampled_refs 401218 # Sample count of references to valid blocks. 832system.cpu.l2cache.tags.avg_refs 6.100265 # Average number of references to valid blocks. 833system.cpu.l2cache.tags.warmup_cycle 6747777750 # Cycle when the warmup percentage was hit. 834system.cpu.l2cache.tags.occ_blocks::writebacks 55582.845445 # Average occupied blocks per requestor 835system.cpu.l2cache.tags.occ_blocks::cpu.inst 4758.900638 # Average occupied blocks per requestor 836system.cpu.l2cache.tags.occ_blocks::cpu.data 4955.117636 # Average occupied blocks per requestor 837system.cpu.l2cache.tags.occ_percent::writebacks 0.848127 # Average percentage of cache occupancy 838system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072615 # Average percentage of cache occupancy 839system.cpu.l2cache.tags.occ_percent::cpu.data 0.075609 # Average percentage of cache occupancy 840system.cpu.l2cache.tags.occ_percent::total 0.996351 # Average percentage of cache occupancy 841system.cpu.l2cache.ReadReq_hits::cpu.inst 915717 # number of ReadReq hits 842system.cpu.l2cache.ReadReq_hits::cpu.data 814814 # number of ReadReq hits 843system.cpu.l2cache.ReadReq_hits::total 1730531 # number of ReadReq hits 844system.cpu.l2cache.Writeback_hits::writebacks 835114 # number of Writeback hits 845system.cpu.l2cache.Writeback_hits::total 835114 # number of Writeback hits |
| 788system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 789system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 846system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 847system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 790system.cpu.l2cache.ReadExReq_hits::cpu.data 187779 # number of ReadExReq hits 791system.cpu.l2cache.ReadExReq_hits::total 187779 # number of ReadExReq hits 792system.cpu.l2cache.demand_hits::cpu.inst 916024 # number of demand (read+write) hits 793system.cpu.l2cache.demand_hits::cpu.data 1002748 # number of demand (read+write) hits 794system.cpu.l2cache.demand_hits::total 1918772 # number of demand (read+write) hits 795system.cpu.l2cache.overall_hits::cpu.inst 916024 # number of overall hits 796system.cpu.l2cache.overall_hits::cpu.data 1002748 # number of overall hits 797system.cpu.l2cache.overall_hits::total 1918772 # number of overall hits | 848system.cpu.l2cache.ReadExReq_hits::cpu.data 187645 # number of ReadExReq hits 849system.cpu.l2cache.ReadExReq_hits::total 187645 # number of ReadExReq hits 850system.cpu.l2cache.demand_hits::cpu.inst 915717 # number of demand (read+write) hits 851system.cpu.l2cache.demand_hits::cpu.data 1002459 # number of demand (read+write) hits 852system.cpu.l2cache.demand_hits::total 1918176 # number of demand (read+write) hits 853system.cpu.l2cache.overall_hits::cpu.inst 915717 # number of overall hits 854system.cpu.l2cache.overall_hits::cpu.data 1002459 # number of overall hits 855system.cpu.l2cache.overall_hits::total 1918176 # number of overall hits |
| 798system.cpu.l2cache.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses | 856system.cpu.l2cache.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses |
| 799system.cpu.l2cache.ReadReq_misses::cpu.data 271918 # number of ReadReq misses 800system.cpu.l2cache.ReadReq_misses::total 285210 # number of ReadReq misses | 857system.cpu.l2cache.ReadReq_misses::cpu.data 271915 # number of ReadReq misses 858system.cpu.l2cache.ReadReq_misses::total 285207 # number of ReadReq misses |
| 801system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 802system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses | 859system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 860system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses |
| 803system.cpu.l2cache.ReadExReq_misses::cpu.data 116714 # number of ReadExReq misses 804system.cpu.l2cache.ReadExReq_misses::total 116714 # number of ReadExReq misses | 861system.cpu.l2cache.ReadExReq_misses::cpu.data 116708 # number of ReadExReq misses 862system.cpu.l2cache.ReadExReq_misses::total 116708 # number of ReadExReq misses |
| 805system.cpu.l2cache.demand_misses::cpu.inst 13292 # number of demand (read+write) misses | 863system.cpu.l2cache.demand_misses::cpu.inst 13292 # number of demand (read+write) misses |
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| 808system.cpu.l2cache.overall_misses::cpu.inst 13292 # number of overall misses | 866system.cpu.l2cache.overall_misses::cpu.inst 13292 # number of overall misses |
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| 816system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7757662128 # number of ReadExReq miss cycles 817system.cpu.l2cache.ReadExReq_miss_latency::total 7757662128 # number of ReadExReq miss cycles 818system.cpu.l2cache.demand_miss_latency::cpu.inst 1060624743 # number of demand (read+write) miss cycles 819system.cpu.l2cache.demand_miss_latency::cpu.data 24683218372 # number of demand (read+write) miss cycles 820system.cpu.l2cache.demand_miss_latency::total 25743843115 # number of demand (read+write) miss cycles 821system.cpu.l2cache.overall_miss_latency::cpu.inst 1060624743 # number of overall miss cycles 822system.cpu.l2cache.overall_miss_latency::cpu.data 24683218372 # number of overall miss cycles 823system.cpu.l2cache.overall_miss_latency::total 25743843115 # number of overall miss cycles 824system.cpu.l2cache.ReadReq_accesses::cpu.inst 929316 # number of ReadReq accesses(hits+misses) 825system.cpu.l2cache.ReadReq_accesses::cpu.data 1086887 # number of ReadReq accesses(hits+misses) 826system.cpu.l2cache.ReadReq_accesses::total 2016203 # number of ReadReq accesses(hits+misses) 827system.cpu.l2cache.Writeback_accesses::writebacks 835407 # number of Writeback accesses(hits+misses) 828system.cpu.l2cache.Writeback_accesses::total 835407 # number of Writeback accesses(hits+misses) | 874system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8190852374 # number of ReadExReq miss cycles 875system.cpu.l2cache.ReadExReq_miss_latency::total 8190852374 # number of ReadExReq miss cycles 876system.cpu.l2cache.demand_miss_latency::cpu.inst 1012336742 # number of demand (read+write) miss cycles 877system.cpu.l2cache.demand_miss_latency::cpu.data 25755182365 # number of demand (read+write) miss cycles 878system.cpu.l2cache.demand_miss_latency::total 26767519107 # number of demand (read+write) miss cycles 879system.cpu.l2cache.overall_miss_latency::cpu.inst 1012336742 # number of overall miss cycles 880system.cpu.l2cache.overall_miss_latency::cpu.data 25755182365 # number of overall miss cycles 881system.cpu.l2cache.overall_miss_latency::total 26767519107 # number of overall miss cycles 882system.cpu.l2cache.ReadReq_accesses::cpu.inst 929009 # number of ReadReq accesses(hits+misses) 883system.cpu.l2cache.ReadReq_accesses::cpu.data 1086729 # number of ReadReq accesses(hits+misses) 884system.cpu.l2cache.ReadReq_accesses::total 2015738 # number of ReadReq accesses(hits+misses) 885system.cpu.l2cache.Writeback_accesses::writebacks 835114 # number of Writeback accesses(hits+misses) 886system.cpu.l2cache.Writeback_accesses::total 835114 # number of Writeback accesses(hits+misses) |
| 829system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 830system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) | 887system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 888system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) |
| 831system.cpu.l2cache.ReadExReq_accesses::cpu.data 304493 # number of ReadExReq accesses(hits+misses) 832system.cpu.l2cache.ReadExReq_accesses::total 304493 # number of ReadExReq accesses(hits+misses) 833system.cpu.l2cache.demand_accesses::cpu.inst 929316 # number of demand (read+write) accesses 834system.cpu.l2cache.demand_accesses::cpu.data 1391380 # number of demand (read+write) accesses 835system.cpu.l2cache.demand_accesses::total 2320696 # number of demand (read+write) accesses 836system.cpu.l2cache.overall_accesses::cpu.inst 929316 # number of overall (read+write) accesses 837system.cpu.l2cache.overall_accesses::cpu.data 1391380 # number of overall (read+write) accesses 838system.cpu.l2cache.overall_accesses::total 2320696 # number of overall (read+write) accesses 839system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014303 # miss rate for ReadReq accesses 840system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250181 # miss rate for ReadReq accesses 841system.cpu.l2cache.ReadReq_miss_rate::total 0.141459 # miss rate for ReadReq accesses | 889system.cpu.l2cache.ReadExReq_accesses::cpu.data 304353 # number of ReadExReq accesses(hits+misses) 890system.cpu.l2cache.ReadExReq_accesses::total 304353 # number of ReadExReq accesses(hits+misses) 891system.cpu.l2cache.demand_accesses::cpu.inst 929009 # number of demand (read+write) accesses 892system.cpu.l2cache.demand_accesses::cpu.data 1391082 # number of demand (read+write) accesses 893system.cpu.l2cache.demand_accesses::total 2320091 # number of demand (read+write) accesses 894system.cpu.l2cache.overall_accesses::cpu.inst 929009 # number of overall (read+write) accesses 895system.cpu.l2cache.overall_accesses::cpu.data 1391082 # number of overall (read+write) accesses 896system.cpu.l2cache.overall_accesses::total 2320091 # number of overall (read+write) accesses 897system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014308 # miss rate for ReadReq accesses 898system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250214 # miss rate for ReadReq accesses 899system.cpu.l2cache.ReadReq_miss_rate::total 0.141490 # miss rate for ReadReq accesses |
| 842system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 843system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses | 900system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 901system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses |
| 844system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383306 # miss rate for ReadExReq accesses 845system.cpu.l2cache.ReadExReq_miss_rate::total 0.383306 # miss rate for ReadExReq accesses 846system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014303 # miss rate for demand accesses 847system.cpu.l2cache.demand_miss_rate::cpu.data 0.279314 # miss rate for demand accesses 848system.cpu.l2cache.demand_miss_rate::total 0.173191 # miss rate for demand accesses 849system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014303 # miss rate for overall accesses 850system.cpu.l2cache.overall_miss_rate::cpu.data 0.279314 # miss rate for overall accesses 851system.cpu.l2cache.overall_miss_rate::total 0.173191 # miss rate for overall accesses 852system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79794.217800 # average ReadReq miss latency 853system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62245.074780 # average ReadReq miss latency 854system.cpu.l2cache.ReadReq_avg_miss_latency::total 63062.939543 # average ReadReq miss latency | 902system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses 903system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses 904system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014308 # miss rate for demand accesses 905system.cpu.l2cache.demand_miss_rate::cpu.data 0.279367 # miss rate for demand accesses 906system.cpu.l2cache.demand_miss_rate::total 0.173232 # miss rate for demand accesses 907system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014308 # miss rate for overall accesses 908system.cpu.l2cache.overall_miss_rate::cpu.data 0.279367 # miss rate for overall accesses 909system.cpu.l2cache.overall_miss_rate::total 0.173232 # miss rate for overall accesses 910system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76161.355853 # average ReadReq miss latency 911system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64594.928529 # average ReadReq miss latency 912system.cpu.l2cache.ReadReq_avg_miss_latency::total 65133.978945 # average ReadReq miss latency |
| 855system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency 856system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency | 913system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency 914system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency |
| 857system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66467.280086 # average ReadExReq miss latency 858system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66467.280086 # average ReadExReq miss latency 859system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency 860system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency 861system.cpu.l2cache.demand_avg_miss_latency::total 64051.519976 # average overall miss latency 862system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency 863system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::total 64051.519976 # average overall miss latency | 915system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70182.441426 # average ReadExReq miss latency 916system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70182.441426 # average ReadExReq miss latency 917system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency 918system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency 919system.cpu.l2cache.demand_avg_miss_latency::total 66599.950504 # average overall miss latency 920system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency 921system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency 922system.cpu.l2cache.overall_avg_miss_latency::total 66599.950504 # average overall miss latency |
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| 875system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses | 933system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses |
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| 910system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 911system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses | 968system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 969system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses |
| 912system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383306 # mshr miss rate for ReadExReq accesses 913system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383306 # mshr miss rate for ReadExReq accesses 914system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for demand accesses 915system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for demand accesses 916system.cpu.l2cache.demand_mshr_miss_rate::total 0.173191 # mshr miss rate for demand accesses 917system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for overall accesses 918system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for overall accesses 919system.cpu.l2cache.overall_mshr_miss_rate::total 0.173191 # mshr miss rate for overall accesses 920system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67190.284156 # average ReadReq mshr miss latency 921system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49740.362006 # average ReadReq mshr miss latency 922system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50553.602654 # average ReadReq mshr miss latency | 970system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses 971system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses 972system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for demand accesses 973system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for demand accesses 974system.cpu.l2cache.demand_mshr_miss_rate::total 0.173232 # mshr miss rate for demand accesses 975system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for overall accesses 976system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for overall accesses 977system.cpu.l2cache.overall_mshr_miss_rate::total 0.173232 # mshr miss rate for overall accesses 978system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63625.207493 # average ReadReq mshr miss latency 979system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52092.839707 # average ReadReq mshr miss latency 980system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52630.302787 # average ReadReq mshr miss latency |
| 923system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency 924system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency | 981system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency 982system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency |
| 925system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53955.835392 # average ReadExReq mshr miss latency 926system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53955.835392 # average ReadExReq mshr miss latency 927system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency 928system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency 929system.cpu.l2cache.demand_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency 930system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency 931system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency 932system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency | 983system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57678.065137 # average ReadExReq mshr miss latency 984system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57678.065137 # average ReadExReq mshr miss latency 985system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency 986system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency 987system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency 988system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency 989system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency 990system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency |
| 933system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 934system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 935system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 936system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 937system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 938system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 939system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 991system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 992system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 993system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 994system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 995system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 996system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 997system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 940system.cpu.dcache.tags.replacements 1390866 # number of replacements 941system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use 942system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks. 943system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks. 944system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks. 945system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit. 946system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor | 998system.cpu.dcache.tags.replacements 1390568 # number of replacements 999system.cpu.dcache.tags.tagsinuse 511.978915 # Cycle average of tags in use 1000system.cpu.dcache.tags.total_refs 14049173 # Total number of references to valid blocks. 1001system.cpu.dcache.tags.sampled_refs 1391080 # Sample count of references to valid blocks. 1002system.cpu.dcache.tags.avg_refs 10.099472 # Average number of references to valid blocks. 1003system.cpu.dcache.tags.warmup_cycle 107298250 # Cycle when the warmup percentage was hit. 1004system.cpu.dcache.tags.occ_blocks::cpu.data 511.978915 # Average occupied blocks per requestor |
| 947system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy 948system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy | 1005system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy 1006system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy |
| 949system.cpu.dcache.ReadReq_hits::cpu.data 7815067 # number of ReadReq hits 950system.cpu.dcache.ReadReq_hits::total 7815067 # number of ReadReq hits 951system.cpu.dcache.WriteReq_hits::cpu.data 5852671 # number of WriteReq hits 952system.cpu.dcache.WriteReq_hits::total 5852671 # number of WriteReq hits 953system.cpu.dcache.LoadLockedReq_hits::cpu.data 183038 # number of LoadLockedReq hits 954system.cpu.dcache.LoadLockedReq_hits::total 183038 # number of LoadLockedReq hits 955system.cpu.dcache.StoreCondReq_hits::cpu.data 199236 # number of StoreCondReq hits 956system.cpu.dcache.StoreCondReq_hits::total 199236 # number of StoreCondReq hits 957system.cpu.dcache.demand_hits::cpu.data 13667738 # number of demand (read+write) hits 958system.cpu.dcache.demand_hits::total 13667738 # number of demand (read+write) hits 959system.cpu.dcache.overall_hits::cpu.data 13667738 # number of overall hits 960system.cpu.dcache.overall_hits::total 13667738 # number of overall hits 961system.cpu.dcache.ReadReq_misses::cpu.data 1069668 # number of ReadReq misses 962system.cpu.dcache.ReadReq_misses::total 1069668 # number of ReadReq misses 963system.cpu.dcache.WriteReq_misses::cpu.data 304510 # number of WriteReq misses 964system.cpu.dcache.WriteReq_misses::total 304510 # number of WriteReq misses 965system.cpu.dcache.LoadLockedReq_misses::cpu.data 17219 # number of LoadLockedReq misses 966system.cpu.dcache.LoadLockedReq_misses::total 17219 # number of LoadLockedReq misses 967system.cpu.dcache.demand_misses::cpu.data 1374178 # number of demand (read+write) misses 968system.cpu.dcache.demand_misses::total 1374178 # number of demand (read+write) misses 969system.cpu.dcache.overall_misses::cpu.data 1374178 # number of overall misses 970system.cpu.dcache.overall_misses::total 1374178 # number of overall misses 971system.cpu.dcache.ReadReq_miss_latency::cpu.data 28240934256 # number of ReadReq miss cycles 972system.cpu.dcache.ReadReq_miss_latency::total 28240934256 # number of ReadReq miss cycles 973system.cpu.dcache.WriteReq_miss_latency::cpu.data 10606589383 # number of WriteReq miss cycles 974system.cpu.dcache.WriteReq_miss_latency::total 10606589383 # number of WriteReq miss cycles 975system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229410500 # number of LoadLockedReq miss cycles 976system.cpu.dcache.LoadLockedReq_miss_latency::total 229410500 # number of LoadLockedReq miss cycles 977system.cpu.dcache.demand_miss_latency::cpu.data 38847523639 # number of demand (read+write) miss cycles 978system.cpu.dcache.demand_miss_latency::total 38847523639 # number of demand (read+write) miss cycles 979system.cpu.dcache.overall_miss_latency::cpu.data 38847523639 # number of overall miss cycles 980system.cpu.dcache.overall_miss_latency::total 38847523639 # number of overall miss cycles 981system.cpu.dcache.ReadReq_accesses::cpu.data 8884735 # number of ReadReq accesses(hits+misses) 982system.cpu.dcache.ReadReq_accesses::total 8884735 # number of ReadReq accesses(hits+misses) 983system.cpu.dcache.WriteReq_accesses::cpu.data 6157181 # number of WriteReq accesses(hits+misses) 984system.cpu.dcache.WriteReq_accesses::total 6157181 # number of WriteReq accesses(hits+misses) 985system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200257 # number of LoadLockedReq accesses(hits+misses) 986system.cpu.dcache.LoadLockedReq_accesses::total 200257 # number of LoadLockedReq accesses(hits+misses) 987system.cpu.dcache.StoreCondReq_accesses::cpu.data 199236 # number of StoreCondReq accesses(hits+misses) 988system.cpu.dcache.StoreCondReq_accesses::total 199236 # number of StoreCondReq accesses(hits+misses) 989system.cpu.dcache.demand_accesses::cpu.data 15041916 # number of demand (read+write) accesses 990system.cpu.dcache.demand_accesses::total 15041916 # number of demand (read+write) accesses 991system.cpu.dcache.overall_accesses::cpu.data 15041916 # number of overall (read+write) accesses 992system.cpu.dcache.overall_accesses::total 15041916 # number of overall (read+write) accesses 993system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120394 # miss rate for ReadReq accesses 994system.cpu.dcache.ReadReq_miss_rate::total 0.120394 # miss rate for ReadReq accesses 995system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049456 # miss rate for WriteReq accesses 996system.cpu.dcache.WriteReq_miss_rate::total 0.049456 # miss rate for WriteReq accesses 997system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085985 # miss rate for LoadLockedReq accesses 998system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085985 # miss rate for LoadLockedReq accesses 999system.cpu.dcache.demand_miss_rate::cpu.data 0.091357 # miss rate for demand accesses 1000system.cpu.dcache.demand_miss_rate::total 0.091357 # miss rate for demand accesses 1001system.cpu.dcache.overall_miss_rate::cpu.data 0.091357 # miss rate for overall accesses 1002system.cpu.dcache.overall_miss_rate::total 0.091357 # miss rate for overall accesses 1003system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26401.588396 # average ReadReq miss latency 1004system.cpu.dcache.ReadReq_avg_miss_latency::total 26401.588396 # average ReadReq miss latency 1005system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34831.661959 # average WriteReq miss latency 1006system.cpu.dcache.WriteReq_avg_miss_latency::total 34831.661959 # average WriteReq miss latency 1007system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13323.102387 # average LoadLockedReq miss latency 1008system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13323.102387 # average LoadLockedReq miss latency 1009system.cpu.dcache.demand_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency 1010system.cpu.dcache.demand_avg_miss_latency::total 28269.644572 # average overall miss latency 1011system.cpu.dcache.overall_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency 1012system.cpu.dcache.overall_avg_miss_latency::total 28269.644572 # average overall miss latency | 1007system.cpu.dcache.ReadReq_hits::cpu.data 7814622 # number of ReadReq hits 1008system.cpu.dcache.ReadReq_hits::total 7814622 # number of ReadReq hits 1009system.cpu.dcache.WriteReq_hits::cpu.data 5852326 # number of WriteReq hits 1010system.cpu.dcache.WriteReq_hits::total 5852326 # number of WriteReq hits 1011system.cpu.dcache.LoadLockedReq_hits::cpu.data 182986 # number of LoadLockedReq hits 1012system.cpu.dcache.LoadLockedReq_hits::total 182986 # number of LoadLockedReq hits 1013system.cpu.dcache.StoreCondReq_hits::cpu.data 199222 # number of StoreCondReq hits 1014system.cpu.dcache.StoreCondReq_hits::total 199222 # number of StoreCondReq hits 1015system.cpu.dcache.demand_hits::cpu.data 13666948 # number of demand (read+write) hits 1016system.cpu.dcache.demand_hits::total 13666948 # number of demand (read+write) hits 1017system.cpu.dcache.overall_hits::cpu.data 13666948 # number of overall hits 1018system.cpu.dcache.overall_hits::total 13666948 # number of overall hits 1019system.cpu.dcache.ReadReq_misses::cpu.data 1069470 # number of ReadReq misses 1020system.cpu.dcache.ReadReq_misses::total 1069470 # number of ReadReq misses 1021system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses 1022system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses 1023system.cpu.dcache.LoadLockedReq_misses::cpu.data 17259 # number of LoadLockedReq misses 1024system.cpu.dcache.LoadLockedReq_misses::total 17259 # number of LoadLockedReq misses 1025system.cpu.dcache.demand_misses::cpu.data 1373840 # number of demand (read+write) misses 1026system.cpu.dcache.demand_misses::total 1373840 # number of demand (read+write) misses 1027system.cpu.dcache.overall_misses::cpu.data 1373840 # number of overall misses 1028system.cpu.dcache.overall_misses::total 1373840 # number of overall misses 1029system.cpu.dcache.ReadReq_miss_latency::cpu.data 28875755759 # number of ReadReq miss cycles 1030system.cpu.dcache.ReadReq_miss_latency::total 28875755759 # number of ReadReq miss cycles 1031system.cpu.dcache.WriteReq_miss_latency::cpu.data 11035273137 # number of WriteReq miss cycles 1032system.cpu.dcache.WriteReq_miss_latency::total 11035273137 # number of WriteReq miss cycles 1033system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228925250 # number of LoadLockedReq miss cycles 1034system.cpu.dcache.LoadLockedReq_miss_latency::total 228925250 # number of LoadLockedReq miss cycles 1035system.cpu.dcache.demand_miss_latency::cpu.data 39911028896 # number of demand (read+write) miss cycles 1036system.cpu.dcache.demand_miss_latency::total 39911028896 # number of demand (read+write) miss cycles 1037system.cpu.dcache.overall_miss_latency::cpu.data 39911028896 # number of overall miss cycles 1038system.cpu.dcache.overall_miss_latency::total 39911028896 # number of overall miss cycles 1039system.cpu.dcache.ReadReq_accesses::cpu.data 8884092 # number of ReadReq accesses(hits+misses) 1040system.cpu.dcache.ReadReq_accesses::total 8884092 # number of ReadReq accesses(hits+misses) 1041system.cpu.dcache.WriteReq_accesses::cpu.data 6156696 # number of WriteReq accesses(hits+misses) 1042system.cpu.dcache.WriteReq_accesses::total 6156696 # number of WriteReq accesses(hits+misses) 1043system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses) 1044system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses) 1045system.cpu.dcache.StoreCondReq_accesses::cpu.data 199222 # number of StoreCondReq accesses(hits+misses) 1046system.cpu.dcache.StoreCondReq_accesses::total 199222 # number of StoreCondReq accesses(hits+misses) 1047system.cpu.dcache.demand_accesses::cpu.data 15040788 # number of demand (read+write) accesses 1048system.cpu.dcache.demand_accesses::total 15040788 # number of demand (read+write) accesses 1049system.cpu.dcache.overall_accesses::cpu.data 15040788 # number of overall (read+write) accesses 1050system.cpu.dcache.overall_accesses::total 15040788 # number of overall (read+write) accesses 1051system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120380 # miss rate for ReadReq accesses 1052system.cpu.dcache.ReadReq_miss_rate::total 0.120380 # miss rate for ReadReq accesses 1053system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049437 # miss rate for WriteReq accesses 1054system.cpu.dcache.WriteReq_miss_rate::total 0.049437 # miss rate for WriteReq accesses 1055system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086189 # miss rate for LoadLockedReq accesses 1056system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086189 # miss rate for LoadLockedReq accesses 1057system.cpu.dcache.demand_miss_rate::cpu.data 0.091341 # miss rate for demand accesses 1058system.cpu.dcache.demand_miss_rate::total 0.091341 # miss rate for demand accesses 1059system.cpu.dcache.overall_miss_rate::cpu.data 0.091341 # miss rate for overall accesses 1060system.cpu.dcache.overall_miss_rate::total 0.091341 # miss rate for overall accesses 1061system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27000.061487 # average ReadReq miss latency 1062system.cpu.dcache.ReadReq_avg_miss_latency::total 27000.061487 # average ReadReq miss latency 1063system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36256.113076 # average WriteReq miss latency 1064system.cpu.dcache.WriteReq_avg_miss_latency::total 36256.113076 # average WriteReq miss latency 1065system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13264.108581 # average LoadLockedReq miss latency 1066system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13264.108581 # average LoadLockedReq miss latency 1067system.cpu.dcache.demand_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency 1068system.cpu.dcache.demand_avg_miss_latency::total 29050.711070 # average overall miss latency 1069system.cpu.dcache.overall_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency 1070system.cpu.dcache.overall_avg_miss_latency::total 29050.711070 # average overall miss latency |
| 1013system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1014system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1015system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1016system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1017system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1018system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1019system.cpu.dcache.fast_writes 0 # number of fast writes performed 1020system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1071system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1072system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1073system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1074system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1075system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1076system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1077system.cpu.dcache.fast_writes 0 # number of fast writes performed 1078system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1021system.cpu.dcache.writebacks::writebacks 835407 # number of writebacks 1022system.cpu.dcache.writebacks::total 835407 # number of writebacks 1023system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069668 # number of ReadReq MSHR misses 1024system.cpu.dcache.ReadReq_mshr_misses::total 1069668 # number of ReadReq MSHR misses 1025system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304510 # number of WriteReq MSHR misses 1026system.cpu.dcache.WriteReq_mshr_misses::total 304510 # number of WriteReq MSHR misses 1027system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses 1028system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses 1029system.cpu.dcache.demand_mshr_misses::cpu.data 1374178 # number of demand (read+write) MSHR misses 1030system.cpu.dcache.demand_mshr_misses::total 1374178 # number of demand (read+write) MSHR misses 1031system.cpu.dcache.overall_mshr_misses::cpu.data 1374178 # number of overall MSHR misses 1032system.cpu.dcache.overall_mshr_misses::total 1374178 # number of overall MSHR misses 1033system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25967193744 # number of ReadReq MSHR miss cycles 1034system.cpu.dcache.ReadReq_mshr_miss_latency::total 25967193744 # number of ReadReq MSHR miss cycles 1035system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9940394617 # number of WriteReq MSHR miss cycles 1036system.cpu.dcache.WriteReq_mshr_miss_latency::total 9940394617 # number of WriteReq MSHR miss cycles 1037system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194939500 # number of LoadLockedReq MSHR miss cycles 1038system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194939500 # number of LoadLockedReq MSHR miss cycles 1039system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35907588361 # number of demand (read+write) MSHR miss cycles 1040system.cpu.dcache.demand_mshr_miss_latency::total 35907588361 # number of demand (read+write) MSHR miss cycles 1041system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35907588361 # number of overall MSHR miss cycles 1042system.cpu.dcache.overall_mshr_miss_latency::total 35907588361 # number of overall MSHR miss cycles 1043system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424233500 # number of ReadReq MSHR uncacheable cycles 1044system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424233500 # number of ReadReq MSHR uncacheable cycles 1045system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles 1046system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles 1047system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435453000 # number of overall MSHR uncacheable cycles 1048system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435453000 # number of overall MSHR uncacheable cycles 1049system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120394 # mshr miss rate for ReadReq accesses 1050system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120394 # mshr miss rate for ReadReq accesses 1051system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses 1052system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses 1053system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085985 # mshr miss rate for LoadLockedReq accesses 1054system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085985 # mshr miss rate for LoadLockedReq accesses 1055system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for demand accesses 1056system.cpu.dcache.demand_mshr_miss_rate::total 0.091357 # mshr miss rate for demand accesses 1057system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for overall accesses 1058system.cpu.dcache.overall_mshr_miss_rate::total 0.091357 # mshr miss rate for overall accesses 1059system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24275.937715 # average ReadReq mshr miss latency 1060system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24275.937715 # average ReadReq mshr miss latency 1061system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32643.902062 # average WriteReq mshr miss latency 1062system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32643.902062 # average WriteReq mshr miss latency 1063system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.185899 # average LoadLockedReq mshr miss latency 1064system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.185899 # average LoadLockedReq mshr miss latency 1065system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency 1066system.cpu.dcache.demand_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency 1067system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency 1068system.cpu.dcache.overall_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency | 1079system.cpu.dcache.writebacks::writebacks 835114 # number of writebacks 1080system.cpu.dcache.writebacks::total 835114 # number of writebacks 1081system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069470 # number of ReadReq MSHR misses 1082system.cpu.dcache.ReadReq_mshr_misses::total 1069470 # number of ReadReq MSHR misses 1083system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304370 # number of WriteReq MSHR misses 1084system.cpu.dcache.WriteReq_mshr_misses::total 304370 # number of WriteReq MSHR misses 1085system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17259 # number of LoadLockedReq MSHR misses 1086system.cpu.dcache.LoadLockedReq_mshr_misses::total 17259 # number of LoadLockedReq MSHR misses 1087system.cpu.dcache.demand_mshr_misses::cpu.data 1373840 # number of demand (read+write) MSHR misses 1088system.cpu.dcache.demand_mshr_misses::total 1373840 # number of demand (read+write) MSHR misses 1089system.cpu.dcache.overall_mshr_misses::cpu.data 1373840 # number of overall MSHR misses 1090system.cpu.dcache.overall_mshr_misses::total 1373840 # number of overall MSHR misses 1091system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26604805241 # number of ReadReq MSHR miss cycles 1092system.cpu.dcache.ReadReq_mshr_miss_latency::total 26604805241 # number of ReadReq MSHR miss cycles 1093system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10372104863 # number of WriteReq MSHR miss cycles 1094system.cpu.dcache.WriteReq_mshr_miss_latency::total 10372104863 # number of WriteReq MSHR miss cycles 1095system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194393750 # number of LoadLockedReq MSHR miss cycles 1096system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194393750 # number of LoadLockedReq MSHR miss cycles 1097system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36976910104 # number of demand (read+write) MSHR miss cycles 1098system.cpu.dcache.demand_mshr_miss_latency::total 36976910104 # number of demand (read+write) MSHR miss cycles 1099system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36976910104 # number of overall MSHR miss cycles 1100system.cpu.dcache.overall_mshr_miss_latency::total 36976910104 # number of overall MSHR miss cycles 1101system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles 1102system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles 1103system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011442000 # number of WriteReq MSHR uncacheable cycles 1104system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011442000 # number of WriteReq MSHR uncacheable cycles 1105system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles 1106system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles 1107system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120380 # mshr miss rate for ReadReq accesses 1108system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120380 # mshr miss rate for ReadReq accesses 1109system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049437 # mshr miss rate for WriteReq accesses 1110system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049437 # mshr miss rate for WriteReq accesses 1111system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086189 # mshr miss rate for LoadLockedReq accesses 1112system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086189 # mshr miss rate for LoadLockedReq accesses 1113system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for demand accesses 1114system.cpu.dcache.demand_mshr_miss_rate::total 0.091341 # mshr miss rate for demand accesses 1115system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for overall accesses 1116system.cpu.dcache.overall_mshr_miss_rate::total 0.091341 # mshr miss rate for overall accesses 1117system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031 # average ReadReq mshr miss latency 1118system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031 # average ReadReq mshr miss latency 1119system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347 # average WriteReq mshr miss latency 1120system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347 # average WriteReq mshr miss latency 1121system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380 # average LoadLockedReq mshr miss latency 1122system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380 # average LoadLockedReq mshr miss latency 1123system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency 1124system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency 1125system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency 1126system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency |
| 1069system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1070system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1071system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1072system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1073system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1074system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1075system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1127system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1128system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1129system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1130system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1131system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1132system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1133system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1076system.cpu.toL2Bus.throughput 105316327 # Throughput (bytes/s) 1077system.cpu.toL2Bus.trans_dist::ReadReq 2023326 # Transaction distribution 1078system.cpu.toL2Bus.trans_dist::ReadResp 2023309 # Transaction distribution 1079system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution 1080system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution 1081system.cpu.toL2Bus.trans_dist::Writeback 835407 # Transaction distribution | 1134system.cpu.toL2Bus.throughput 105179195 # Throughput (bytes/s) 1135system.cpu.toL2Bus.trans_dist::ReadReq 2022861 # Transaction distribution 1136system.cpu.toL2Bus.trans_dist::ReadResp 2022844 # Transaction distribution 1137system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution 1138system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution 1139system.cpu.toL2Bus.trans_dist::Writeback 835114 # Transaction distribution |
| 1082system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1083system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution | 1140system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1141system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution |
| 1084system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution 1085system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution 1086system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858652 # Packet count per connected master and slave (bytes) 1087system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651517 # Packet count per connected master and slave (bytes) 1088system.cpu.toL2Bus.pkt_count::total 5510169 # Packet count per connected master and slave (bytes) 1089system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476224 # Cumulative packet size per connected master and slave (bytes) 1090system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142569036 # Cumulative packet size per connected master and slave (bytes) 1091system.cpu.toL2Bus.tot_pkt_size::total 202045260 # Cumulative packet size per connected master and slave (bytes) 1092system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes) | 1142system.cpu.toL2Bus.trans_dist::ReadExReq 345905 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::ReadExResp 304355 # Transaction distribution 1144system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858038 # Packet count per connected master and slave (bytes) 1145system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3650630 # Packet count per connected master and slave (bytes) 1146system.cpu.toL2Bus.pkt_count::total 5508668 # Packet count per connected master and slave (bytes) 1147system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59456576 # Cumulative packet size per connected master and slave (bytes) 1148system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142531220 # Cumulative packet size per connected master and slave (bytes) 1149system.cpu.toL2Bus.tot_pkt_size::total 201987796 # Cumulative packet size per connected master and slave (bytes) 1150system.cpu.toL2Bus.data_through_bus 201977684 # Total data (bytes) |
| 1093system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) | 1151system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) |
| 1094system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks) | 1152system.cpu.toL2Bus.reqLayer0.occupancy 2425850000 # Layer occupancy (ticks) |
| 1095system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1096system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) 1097system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1153system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1154system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) 1155system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1098system.cpu.toL2Bus.respLayer0.occupancy 1397230757 # Layer occupancy (ticks) | 1156system.cpu.toL2Bus.respLayer0.occupancy 1396163258 # Layer occupancy (ticks) |
| 1099system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1157system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1100system.cpu.toL2Bus.respLayer1.occupancy 2194639139 # Layer occupancy (ticks) | 1158system.cpu.toL2Bus.respLayer1.occupancy 2191612646 # Layer occupancy (ticks) |
| 1101system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1102 1103---------- End Simulation Statistics ---------- | 1159system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1160 1161---------- End Simulation Statistics ---------- |