| stats.txt (9312:e05e1b69ebf2) | stats.txt (9314:63e7cfff4188) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.910582 # Number of seconds simulated 4sim_ticks 1910582068000 # Number of ticks simulated 5final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.910582 # Number of seconds simulated 4sim_ticks 1910582068000 # Number of ticks simulated 5final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1092208 # Simulator instruction rate (inst/s) 8host_op_rate 1092208 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37180157619 # Simulator tick rate (ticks/s) 10host_mem_usage 321564 # Number of bytes of host memory used 11host_seconds 51.39 # Real time elapsed on the host | 7host_inst_rate 942466 # Simulator instruction rate (inst/s) 8host_op_rate 942466 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32082735017 # Simulator tick rate (ticks/s) 10host_mem_usage 321492 # Number of bytes of host memory used 11host_seconds 59.55 # Real time elapsed on the host |
| 12sim_insts 56125446 # Number of instructions simulated 13sim_ops 56125446 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory --- 790 unchanged lines hidden (view full) --- 810system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4294420630 # number of ReadExReq MSHR miss cycles 811system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4294420630 # number of ReadExReq MSHR miss cycles 812system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 561273079 # number of demand (read+write) MSHR miss cycles 813system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12299252211 # number of demand (read+write) MSHR miss cycles 814system.cpu.l2cache.demand_mshr_miss_latency::total 12860525290 # number of demand (read+write) MSHR miss cycles 815system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 561273079 # number of overall MSHR miss cycles 816system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12299252211 # number of overall MSHR miss cycles 817system.cpu.l2cache.overall_mshr_miss_latency::total 12860525290 # number of overall MSHR miss cycles | 12sim_insts 56125446 # Number of instructions simulated 13sim_ops 56125446 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory --- 790 unchanged lines hidden (view full) --- 810system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4294420630 # number of ReadExReq MSHR miss cycles 811system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4294420630 # number of ReadExReq MSHR miss cycles 812system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 561273079 # number of demand (read+write) MSHR miss cycles 813system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12299252211 # number of demand (read+write) MSHR miss cycles 814system.cpu.l2cache.demand_mshr_miss_latency::total 12860525290 # number of demand (read+write) MSHR miss cycles 815system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 561273079 # number of overall MSHR miss cycles 816system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12299252211 # number of overall MSHR miss cycles 817system.cpu.l2cache.overall_mshr_miss_latency::total 12860525290 # number of overall MSHR miss cycles |
| 818system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles 819system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles 820system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1891670000 # number of WriteReq MSHR uncacheable cycles 821system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1891670000 # number of WriteReq MSHR uncacheable cycles 822system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223220000 # number of overall MSHR uncacheable cycles 823system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223220000 # number of overall MSHR uncacheable cycles | 818system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles 819system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles 820system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221500 # number of WriteReq MSHR uncacheable cycles 821system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221500 # number of WriteReq MSHR uncacheable cycles 822system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229367500 # number of overall MSHR uncacheable cycles 823system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229367500 # number of overall MSHR uncacheable cycles |
| 824system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses 825system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses 826system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses 827system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 828system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 829system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383643 # mshr miss rate for ReadExReq accesses 830system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383643 # mshr miss rate for ReadExReq accesses 831system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for demand accesses --- 27 unchanged lines hidden --- | 824system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses 825system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses 826system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses 827system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 828system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 829system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383643 # mshr miss rate for ReadExReq accesses 830system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383643 # mshr miss rate for ReadExReq accesses 831system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for demand accesses --- 27 unchanged lines hidden --- |