| stats.txt (9289:a31a1243a3ed) | stats.txt (9312:e05e1b69ebf2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.914421 # Number of seconds simulated 4sim_ticks 1914420945000 # Number of ticks simulated 5final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.910582 # Number of seconds simulated 4sim_ticks 1910582068000 # Number of ticks simulated 5final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1299276 # Simulator instruction rate (inst/s) 8host_op_rate 1299275 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44286723014 # Simulator tick rate (ticks/s) 10host_mem_usage 288696 # Number of bytes of host memory used 11host_seconds 43.23 # Real time elapsed on the host 12sim_insts 56164879 # Number of instructions simulated 13sim_ops 56164879 # Number of ops (including micro ops) simulated | 7host_inst_rate 1092208 # Simulator instruction rate (inst/s) 8host_op_rate 1092208 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37180157619 # Simulator tick rate (ticks/s) 10host_mem_usage 321564 # Number of bytes of host memory used 11host_seconds 51.39 # Real time elapsed on the host 12sim_insts 56125446 # Number of instructions simulated 13sim_ops 56125446 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory | 14system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.data 24860096 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28362752 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory |
| 18system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory | 18system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory |
| 20system.physmem.bytes_written::writebacks 7404800 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7404800 # Number of bytes written to this memory | 20system.physmem.bytes_written::writebacks 7392192 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7392192 # Number of bytes written to this memory |
| 22system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory | 22system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::cpu.data 388439 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 443168 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115700 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115700 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 444291 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12985700 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1385325 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14815316 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 444291 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 444291 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3867906 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3867906 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3867906 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 444291 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12985700 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1385325 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18683222 # Total bandwidth to/from this memory (bytes/s) | 23system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 442975 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115503 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115503 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 445184 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13005193 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1388243 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14838619 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 445184 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 445184 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3869078 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3869078 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3869078 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 445184 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13005193 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1388243 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18707698 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.readReqs 442975 # Total number of read requests seen 42system.physmem.writeReqs 115503 # Total number of write requests seen 43system.physmem.cpureqs 559567 # Reqs generatd by CPU via cache - shady 44system.physmem.bytesRead 28350400 # Total number of bytes read from memory 45system.physmem.bytesWritten 7392192 # Total number of bytes written to memory 46system.physmem.bytesConsumedRd 28350400 # bytesRead derated as per pkt->getSize() 47system.physmem.bytesConsumedWr 7392192 # bytesWritten derated as per pkt->getSize() 48system.physmem.servicedByWrQ 51 # Number of read reqs serviced by write Q 49system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed 50system.physmem.perBankRdReqs::0 28021 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::1 27576 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::2 27724 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::3 27399 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::4 28096 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::5 27946 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::6 27736 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::7 27622 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::8 27577 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::9 27238 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::10 27723 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::11 27886 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::12 27600 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::13 27483 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::14 27641 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::15 27656 # Track reads on a per bank basis 66system.physmem.perBankWrReqs::0 7552 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::1 7244 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::2 7137 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::3 6901 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::4 7584 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::8 7184 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::9 6832 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::10 7257 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::11 7441 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::12 7265 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::13 7126 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::14 7165 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::15 7126 # Track writes on a per bank basis 82system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 83system.physmem.numWrRetry 404 # Number of times wr buffer was full causing retry 84system.physmem.totGap 1910570168000 # Total gap between requests 85system.physmem.readPktSize::0 0 # Categorize read packet sizes 86system.physmem.readPktSize::1 0 # Categorize read packet sizes 87system.physmem.readPktSize::2 0 # Categorize read packet sizes 88system.physmem.readPktSize::3 0 # Categorize read packet sizes 89system.physmem.readPktSize::4 0 # Categorize read packet sizes 90system.physmem.readPktSize::5 0 # Categorize read packet sizes 91system.physmem.readPktSize::6 442975 # Categorize read packet sizes 92system.physmem.readPktSize::7 0 # Categorize read packet sizes 93system.physmem.readPktSize::8 0 # Categorize read packet sizes 94system.physmem.writePktSize::0 0 # categorize write packet sizes 95system.physmem.writePktSize::1 0 # categorize write packet sizes 96system.physmem.writePktSize::2 0 # categorize write packet sizes 97system.physmem.writePktSize::3 0 # categorize write packet sizes 98system.physmem.writePktSize::4 0 # categorize write packet sizes 99system.physmem.writePktSize::5 0 # categorize write packet sizes 100system.physmem.writePktSize::6 115907 # categorize write packet sizes 101system.physmem.writePktSize::7 0 # categorize write packet sizes 102system.physmem.writePktSize::8 0 # categorize write packet sizes 103system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 106system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 108system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 109system.physmem.neitherpktsize::6 130 # categorize neither packet sizes 110system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 111system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 112system.physmem.rdQLenPdf::0 404639 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 7455 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 5269 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 2334 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 2835 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 2403 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 1793 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 2009 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 1658 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 1931 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 1592 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 1535 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 1623 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 1782 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 1204 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 1459 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 903 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 267 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 130 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 101 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 145system.physmem.wrQLenPdf::0 4142 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::1 4753 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::2 4845 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::3 4893 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::4 4973 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::5 4987 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::6 5015 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::9 5022 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::10 5022 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::11 5022 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::12 5022 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::13 5022 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::14 5022 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::15 5022 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::16 5022 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::17 5022 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::18 5022 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::19 5022 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::21 5021 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::22 5021 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::23 880 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::24 269 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::25 177 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::27 49 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 178system.physmem.totQLat 2804911869 # Total cycles spent in queuing delays 179system.physmem.totMemAccLat 10779125869 # Sum of mem lat for all requests 180system.physmem.totBusLat 1771696000 # Total cycles spent in databus access 181system.physmem.totBankLat 6202518000 # Total cycles spent in bank access 182system.physmem.avgQLat 6332.72 # Average queueing delay per request 183system.physmem.avgBankLat 14003.57 # Average bank access latency per request 184system.physmem.avgBusLat 4000.00 # Average bus latency per request 185system.physmem.avgMemAccLat 24336.29 # Average memory access latency 186system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s 187system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s 188system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s 189system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s 190system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 191system.physmem.busUtil 0.12 # Data bus utilization in percentage 192system.physmem.avgRdQLen 0.01 # Average read queue length over time 193system.physmem.avgWrQLen 14.48 # Average write queue length over time 194system.physmem.readRowHits 423327 # Number of row buffer hits during reads 195system.physmem.writeRowHits 74914 # Number of row buffer hits during writes 196system.physmem.readRowHitRate 95.58 # Row buffer hit rate for reads 197system.physmem.writeRowHitRate 64.86 # Row buffer hit rate for writes 198system.physmem.avgGap 3421030.31 # Average gap between requests |
| 41system.iocache.replacements 41685 # number of replacements | 199system.iocache.replacements 41685 # number of replacements |
| 42system.iocache.tagsinuse 1.347664 # Cycle average of tags in use | 200system.iocache.tagsinuse 1.342666 # Cycle average of tags in use |
| 43system.iocache.total_refs 0 # Total number of references to valid blocks. 44system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 45system.iocache.avg_refs 0 # Average number of references to valid blocks. | 201system.iocache.total_refs 0 # Total number of references to valid blocks. 202system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 203system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 46system.iocache.warmup_cycle 1748614160000 # Cycle when the warmup percentage was hit. 47system.iocache.occ_blocks::tsunami.ide 1.347664 # Average occupied blocks per requestor 48system.iocache.occ_percent::tsunami.ide 0.084229 # Average percentage of cache occupancy 49system.iocache.occ_percent::total 0.084229 # Average percentage of cache occupancy | 204system.iocache.warmup_cycle 1745691885000 # Cycle when the warmup percentage was hit. 205system.iocache.occ_blocks::tsunami.ide 1.342666 # Average occupied blocks per requestor 206system.iocache.occ_percent::tsunami.ide 0.083917 # Average percentage of cache occupancy 207system.iocache.occ_percent::total 0.083917 # Average percentage of cache occupancy |
| 50system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 51system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 52system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 53system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 54system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 55system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 56system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 57system.iocache.overall_misses::total 41725 # number of overall misses | 208system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 209system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 210system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 211system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 212system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 213system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 214system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 215system.iocache.overall_misses::total 41725 # number of overall misses |
| 58system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 59system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles 60system.iocache.WriteReq_miss_latency::tsunami.ide 11444054806 # number of WriteReq miss cycles 61system.iocache.WriteReq_miss_latency::total 11444054806 # number of WriteReq miss cycles 62system.iocache.demand_miss_latency::tsunami.ide 11464727804 # number of demand (read+write) miss cycles 63system.iocache.demand_miss_latency::total 11464727804 # number of demand (read+write) miss cycles 64system.iocache.overall_miss_latency::tsunami.ide 11464727804 # number of overall miss cycles 65system.iocache.overall_miss_latency::total 11464727804 # number of overall miss cycles | 216system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles 217system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles 218system.iocache.WriteReq_miss_latency::tsunami.ide 9475235806 # number of WriteReq miss cycles 219system.iocache.WriteReq_miss_latency::total 9475235806 # number of WriteReq miss cycles 220system.iocache.demand_miss_latency::tsunami.ide 9496163804 # number of demand (read+write) miss cycles 221system.iocache.demand_miss_latency::total 9496163804 # number of demand (read+write) miss cycles 222system.iocache.overall_miss_latency::tsunami.ide 9496163804 # number of overall miss cycles 223system.iocache.overall_miss_latency::total 9496163804 # number of overall miss cycles |
| 66system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 67system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 68system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 69system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 70system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 71system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 72system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 73system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 74system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 75system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 76system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 77system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 78system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 79system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 80system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 81system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 224system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 225system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 226system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 227system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 228system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 229system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 230system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 231system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 232system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 233system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 234system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 235system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 236system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 237system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 238system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 239system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 82system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 83system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency 84system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275415.258134 # average WriteReq miss latency 85system.iocache.WriteReq_avg_miss_latency::total 275415.258134 # average WriteReq miss latency 86system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency 87system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency 88system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency 89system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency 90system.iocache.blocked_cycles::no_mshrs 199052 # number of cycles access was blocked | 240system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency 241system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency 242system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228033.206729 # average WriteReq miss latency 243system.iocache.WriteReq_avg_miss_latency::total 228033.206729 # average WriteReq miss latency 244system.iocache.demand_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency 245system.iocache.demand_avg_miss_latency::total 227589.306267 # average overall miss latency 246system.iocache.overall_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency 247system.iocache.overall_avg_miss_latency::total 227589.306267 # average overall miss latency 248system.iocache.blocked_cycles::no_mshrs 189601 # number of cycles access was blocked |
| 91system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 249system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 92system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked | 250system.iocache.blocked::no_mshrs 23064 # number of cycles access was blocked |
| 93system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 251system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 94system.iocache.avg_blocked_cycles::no_mshrs 8.086942 # average number of cycles each access was blocked | 252system.iocache.avg_blocked_cycles::no_mshrs 8.220647 # average number of cycles each access was blocked |
| 95system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 96system.iocache.fast_writes 0 # number of fast writes performed 97system.iocache.cache_copies 0 # number of cache copies performed 98system.iocache.writebacks::writebacks 41512 # number of writebacks 99system.iocache.writebacks::total 41512 # number of writebacks 100system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 101system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 102system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 103system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 104system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 105system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 106system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 107system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 253system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 254system.iocache.fast_writes 0 # number of fast writes performed 255system.iocache.cache_copies 0 # number of cache copies performed 256system.iocache.writebacks::writebacks 41512 # number of writebacks 257system.iocache.writebacks::total 41512 # number of writebacks 258system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 259system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 260system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 261system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 262system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 263system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 264system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 265system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 108system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles 109system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles 110system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283350806 # number of WriteReq MSHR miss cycles 111system.iocache.WriteReq_mshr_miss_latency::total 9283350806 # number of WriteReq MSHR miss cycles 112system.iocache.demand_mshr_miss_latency::tsunami.ide 9295027804 # number of demand (read+write) MSHR miss cycles 113system.iocache.demand_mshr_miss_latency::total 9295027804 # number of demand (read+write) MSHR miss cycles 114system.iocache.overall_mshr_miss_latency::tsunami.ide 9295027804 # number of overall MSHR miss cycles 115system.iocache.overall_mshr_miss_latency::total 9295027804 # number of overall MSHR miss cycles | 266system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles 267system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles 268system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7312468500 # number of WriteReq MSHR miss cycles 269system.iocache.WriteReq_mshr_miss_latency::total 7312468500 # number of WriteReq MSHR miss cycles 270system.iocache.demand_mshr_miss_latency::tsunami.ide 7324399500 # number of demand (read+write) MSHR miss cycles 271system.iocache.demand_mshr_miss_latency::total 7324399500 # number of demand (read+write) MSHR miss cycles 272system.iocache.overall_mshr_miss_latency::tsunami.ide 7324399500 # number of overall MSHR miss cycles 273system.iocache.overall_mshr_miss_latency::total 7324399500 # number of overall MSHR miss cycles |
| 116system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 117system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 118system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 119system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 120system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 121system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 122system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 123system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 274system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 275system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 276system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 277system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 278system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 279system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 280system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 281system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 124system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency 125system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency 126system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223415.258134 # average WriteReq mshr miss latency 127system.iocache.WriteReq_avg_mshr_miss_latency::total 223415.258134 # average WriteReq mshr miss latency 128system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency 129system.iocache.demand_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency 130system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency 131system.iocache.overall_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency | 282system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency 283system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency 284system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175983.550732 # average WriteReq mshr miss latency 285system.iocache.WriteReq_avg_mshr_miss_latency::total 175983.550732 # average WriteReq mshr miss latency 286system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency 287system.iocache.demand_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency 288system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency 289system.iocache.overall_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency |
| 132system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 133system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 134system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 135system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 136system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 137system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 138system.disk0.dma_write_txs 395 # Number of DMA write transactions. 139system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 140system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 141system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 142system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 143system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 144system.disk2.dma_write_txs 1 # Number of DMA write transactions. 145system.cpu.dtb.fetch_hits 0 # ITB hits 146system.cpu.dtb.fetch_misses 0 # ITB misses 147system.cpu.dtb.fetch_acv 0 # ITB acv 148system.cpu.dtb.fetch_accesses 0 # ITB accesses | 290system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 291system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 292system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 293system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 294system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 295system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 296system.disk0.dma_write_txs 395 # Number of DMA write transactions. 297system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 298system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 299system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 300system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 301system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 302system.disk2.dma_write_txs 1 # Number of DMA write transactions. 303system.cpu.dtb.fetch_hits 0 # ITB hits 304system.cpu.dtb.fetch_misses 0 # ITB misses 305system.cpu.dtb.fetch_acv 0 # ITB acv 306system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 149system.cpu.dtb.read_hits 9062432 # DTB read hits | 307system.cpu.dtb.read_hits 9055970 # DTB read hits |
| 150system.cpu.dtb.read_misses 10329 # DTB read misses 151system.cpu.dtb.read_acv 210 # DTB read access violations 152system.cpu.dtb.read_accesses 728856 # DTB read accesses | 308system.cpu.dtb.read_misses 10329 # DTB read misses 309system.cpu.dtb.read_acv 210 # DTB read access violations 310system.cpu.dtb.read_accesses 728856 # DTB read accesses |
| 153system.cpu.dtb.write_hits 6354530 # DTB write hits | 311system.cpu.dtb.write_hits 6351685 # DTB write hits |
| 154system.cpu.dtb.write_misses 1142 # DTB write misses 155system.cpu.dtb.write_acv 157 # DTB write access violations 156system.cpu.dtb.write_accesses 291931 # DTB write accesses | 312system.cpu.dtb.write_misses 1142 # DTB write misses 313system.cpu.dtb.write_acv 157 # DTB write access violations 314system.cpu.dtb.write_accesses 291931 # DTB write accesses |
| 157system.cpu.dtb.data_hits 15416962 # DTB hits | 315system.cpu.dtb.data_hits 15407655 # DTB hits |
| 158system.cpu.dtb.data_misses 11471 # DTB misses 159system.cpu.dtb.data_acv 367 # DTB access violations 160system.cpu.dtb.data_accesses 1020787 # DTB accesses | 316system.cpu.dtb.data_misses 11471 # DTB misses 317system.cpu.dtb.data_acv 367 # DTB access violations 318system.cpu.dtb.data_accesses 1020787 # DTB accesses |
| 161system.cpu.itb.fetch_hits 4974475 # ITB hits | 319system.cpu.itb.fetch_hits 4974178 # ITB hits |
| 162system.cpu.itb.fetch_misses 5006 # ITB misses 163system.cpu.itb.fetch_acv 184 # ITB acv | 320system.cpu.itb.fetch_misses 5006 # ITB misses 321system.cpu.itb.fetch_acv 184 # ITB acv |
| 164system.cpu.itb.fetch_accesses 4979481 # ITB accesses | 322system.cpu.itb.fetch_accesses 4979184 # ITB accesses |
| 165system.cpu.itb.read_hits 0 # DTB read hits 166system.cpu.itb.read_misses 0 # DTB read misses 167system.cpu.itb.read_acv 0 # DTB read access violations 168system.cpu.itb.read_accesses 0 # DTB read accesses 169system.cpu.itb.write_hits 0 # DTB write hits 170system.cpu.itb.write_misses 0 # DTB write misses 171system.cpu.itb.write_acv 0 # DTB write access violations 172system.cpu.itb.write_accesses 0 # DTB write accesses 173system.cpu.itb.data_hits 0 # DTB hits 174system.cpu.itb.data_misses 0 # DTB misses 175system.cpu.itb.data_acv 0 # DTB access violations 176system.cpu.itb.data_accesses 0 # DTB accesses | 323system.cpu.itb.read_hits 0 # DTB read hits 324system.cpu.itb.read_misses 0 # DTB read misses 325system.cpu.itb.read_acv 0 # DTB read access violations 326system.cpu.itb.read_accesses 0 # DTB read accesses 327system.cpu.itb.write_hits 0 # DTB write hits 328system.cpu.itb.write_misses 0 # DTB write misses 329system.cpu.itb.write_acv 0 # DTB write access violations 330system.cpu.itb.write_accesses 0 # DTB write accesses 331system.cpu.itb.data_hits 0 # DTB hits 332system.cpu.itb.data_misses 0 # DTB misses 333system.cpu.itb.data_acv 0 # DTB access violations 334system.cpu.itb.data_accesses 0 # DTB accesses |
| 177system.cpu.numCycles 3828841890 # number of cpu cycles simulated | 335system.cpu.numCycles 3821164136 # number of cpu cycles simulated |
| 178system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 179system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 336system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 337system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 180system.cpu.committedInsts 56164879 # Number of instructions committed 181system.cpu.committedOps 56164879 # Number of ops (including micro ops) committed 182system.cpu.num_int_alu_accesses 52037464 # Number of integer alu accesses | 338system.cpu.committedInsts 56125446 # Number of instructions committed 339system.cpu.committedOps 56125446 # Number of ops (including micro ops) committed 340system.cpu.num_int_alu_accesses 51999916 # Number of integer alu accesses |
| 183system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses | 341system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses |
| 184system.cpu.num_func_calls 1482804 # number of times a function call or return occured 185system.cpu.num_conditional_control_insts 6466141 # number of instructions that are conditional controls 186system.cpu.num_int_insts 52037464 # number of integer instructions | 342system.cpu.num_func_calls 1482010 # number of times a function call or return occured 343system.cpu.num_conditional_control_insts 6463546 # number of instructions that are conditional controls 344system.cpu.num_int_insts 51999916 # number of integer instructions |
| 187system.cpu.num_fp_insts 324393 # number of float instructions | 345system.cpu.num_fp_insts 324393 # number of float instructions |
| 188system.cpu.num_int_register_reads 71294843 # number of times the integer registers were read 189system.cpu.num_int_register_writes 38508157 # number of times the integer registers were written | 346system.cpu.num_int_register_reads 71242345 # number of times the integer registers were read 347system.cpu.num_int_register_writes 38476410 # number of times the integer registers were written |
| 190system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read 191system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written | 348system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read 349system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written |
| 192system.cpu.num_mem_refs 15469580 # number of memory refs 193system.cpu.num_load_insts 9099291 # Number of load instructions 194system.cpu.num_store_insts 6370289 # Number of store instructions 195system.cpu.num_idle_cycles 3589214946.998125 # Number of idle cycles 196system.cpu.num_busy_cycles 239626943.001875 # Number of busy cycles 197system.cpu.not_idle_fraction 0.062585 # Percentage of non-idle cycles 198system.cpu.idle_fraction 0.937415 # Percentage of idle cycles | 350system.cpu.num_mem_refs 15460271 # number of memory refs 351system.cpu.num_load_insts 9092827 # Number of load instructions 352system.cpu.num_store_insts 6367444 # Number of store instructions 353system.cpu.num_idle_cycles 3587332264.998123 # Number of idle cycles 354system.cpu.num_busy_cycles 233831871.001878 # Number of busy cycles 355system.cpu.not_idle_fraction 0.061194 # Percentage of non-idle cycles 356system.cpu.idle_fraction 0.938806 # Percentage of idle cycles |
| 199system.cpu.kern.inst.arm 0 # number of arm instructions executed | 357system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 200system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 201system.cpu.kern.inst.hwrei 211993 # number of hwrei instructions executed 202system.cpu.kern.ipl_count::0 74900 40.89% 40.89% # number of times we switched to this ipl 203system.cpu.kern.ipl_count::21 133 0.07% 40.96% # number of times we switched to this ipl | 358system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed 359system.cpu.kern.inst.hwrei 211969 # number of hwrei instructions executed 360system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl 361system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl |
| 204system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl | 362system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl |
| 205system.cpu.kern.ipl_count::31 106213 57.98% 100.00% # number of times we switched to this ipl 206system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl 207system.cpu.kern.ipl_good::0 73533 49.31% 49.31% # number of times we switched to this ipl from a different ipl 208system.cpu.kern.ipl_good::21 133 0.09% 49.40% # number of times we switched to this ipl from a different ipl | 363system.cpu.kern.ipl_count::31 106200 57.98% 100.00% # number of times we switched to this ipl 364system.cpu.kern.ipl_count::total 183153 # number of times we switched to this ipl 365system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl 366system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl |
| 209system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl | 367system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl |
| 210system.cpu.kern.ipl_good::31 73534 49.31% 100.00% # number of times we switched to this ipl from a different ipl 211system.cpu.kern.ipl_good::total 149130 # number of times we switched to this ipl from a different ipl 212system.cpu.kern.ipl_ticks::0 1856400078000 96.97% 96.97% # number of cycles we spent at this ipl 213system.cpu.kern.ipl_ticks::21 92059500 0.00% 96.97% # number of cycles we spent at this ipl 214system.cpu.kern.ipl_ticks::22 736279500 0.04% 97.01% # number of cycles we spent at this ipl 215system.cpu.kern.ipl_ticks::31 57191794000 2.99% 100.00% # number of cycles we spent at this ipl 216system.cpu.kern.ipl_ticks::total 1914420211000 # number of cycles we spent at this ipl 217system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl | 368system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl 369system.cpu.kern.ipl_good::total 149111 # number of times we switched to this ipl from a different ipl 370system.cpu.kern.ipl_ticks::0 1855918085500 97.14% 97.14% # number of cycles we spent at this ipl 371system.cpu.kern.ipl_ticks::21 91164500 0.00% 97.14% # number of cycles we spent at this ipl 372system.cpu.kern.ipl_ticks::22 736454000 0.04% 97.18% # number of cycles we spent at this ipl 373system.cpu.kern.ipl_ticks::31 53835630000 2.82% 100.00% # number of cycles we spent at this ipl 374system.cpu.kern.ipl_ticks::total 1910581334000 # number of cycles we spent at this ipl 375system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl |
| 218system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 219system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 220system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl | 376system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 377system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 378system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl |
| 221system.cpu.kern.ipl_used::total 0.814135 # fraction of swpipl calls that actually changed the ipl | 379system.cpu.kern.ipl_used::total 0.814134 # fraction of swpipl calls that actually changed the ipl |
| 222system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 223system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 224system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 225system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 226system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 227system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 228system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 229system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 249system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 250system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 251system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 252system.cpu.kern.syscall::total 326 # number of syscalls executed 253system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 254system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 255system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 256system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 380system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 381system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 382system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 383system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 384system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 385system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 386system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 387system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 407system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 408system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 409system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 410system.cpu.kern.syscall::total 326 # number of syscalls executed 411system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 412system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 413system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 414system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 257system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed 258system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed | 415system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed 416system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed |
| 259system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 417system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 260system.cpu.kern.callpal::swpipl 175957 91.22% 93.41% # number of callpals executed 261system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed | 418system.cpu.kern.callpal::swpipl 175936 91.22% 93.42% # number of callpals executed 419system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed |
| 262system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 263system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 264system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 265system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed | 420system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 421system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 422system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 423system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed |
| 266system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed | 424system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed |
| 267system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 268system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 425system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 426system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 269system.cpu.kern.callpal::total 192901 # number of callpals executed | 427system.cpu.kern.callpal::total 192878 # number of callpals executed |
| 270system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches | 428system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches |
| 271system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 272system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 273system.cpu.kern.mode_good::kernel 1910 274system.cpu.kern.mode_good::user 1740 | 429system.cpu.kern.mode_switch::user 1741 # number of protection mode switches 430system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches 431system.cpu.kern.mode_good::kernel 1911 432system.cpu.kern.mode_good::user 1741 |
| 275system.cpu.kern.mode_good::idle 170 | 433system.cpu.kern.mode_good::idle 170 |
| 276system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches | 434system.cpu.kern.mode_switch_good::kernel 0.323843 # fraction of useful protection mode switches |
| 277system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 435system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 278system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 279system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches 280system.cpu.kern.mode_ticks::kernel 45169028500 2.36% 2.36% # number of ticks spent at the given mode 281system.cpu.kern.mode_ticks::user 5015931500 0.26% 2.62% # number of ticks spent at the given mode 282system.cpu.kern.mode_ticks::idle 1864235249000 97.38% 100.00% # number of ticks spent at the given mode | 436system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches 437system.cpu.kern.mode_switch_good::total 0.392483 # fraction of useful protection mode switches 438system.cpu.kern.mode_ticks::kernel 45587423000 2.39% 2.39% # number of ticks spent at the given mode 439system.cpu.kern.mode_ticks::user 5075517000 0.27% 2.65% # number of ticks spent at the given mode 440system.cpu.kern.mode_ticks::idle 1859918392000 97.35% 100.00% # number of ticks spent at the given mode |
| 283system.cpu.kern.swap_context 4177 # number of times the context was actually changed 284system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 285system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 286system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 287system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 288system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 289system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 290system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 307system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 308system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 309system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 310system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 311system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 312system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 313system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 314system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 441system.cpu.kern.swap_context 4177 # number of times the context was actually changed 442system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 443system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 444system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 445system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 446system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 447system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 448system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 465system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 466system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 467system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 468system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 469system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 470system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 471system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 472system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 315system.cpu.icache.replacements 927876 # number of replacements 316system.cpu.icache.tagsinuse 508.762321 # Cycle average of tags in use 317system.cpu.icache.total_refs 55248171 # Total number of references to valid blocks. 318system.cpu.icache.sampled_refs 928387 # Sample count of references to valid blocks. 319system.cpu.icache.avg_refs 59.509850 # Average number of references to valid blocks. 320system.cpu.icache.warmup_cycle 35489468000 # Cycle when the warmup percentage was hit. 321system.cpu.icache.occ_blocks::cpu.inst 508.762321 # Average occupied blocks per requestor 322system.cpu.icache.occ_percent::cpu.inst 0.993676 # Average percentage of cache occupancy 323system.cpu.icache.occ_percent::total 0.993676 # Average percentage of cache occupancy 324system.cpu.icache.ReadReq_hits::cpu.inst 55248171 # number of ReadReq hits 325system.cpu.icache.ReadReq_hits::total 55248171 # number of ReadReq hits 326system.cpu.icache.demand_hits::cpu.inst 55248171 # number of demand (read+write) hits 327system.cpu.icache.demand_hits::total 55248171 # number of demand (read+write) hits 328system.cpu.icache.overall_hits::cpu.inst 55248171 # number of overall hits 329system.cpu.icache.overall_hits::total 55248171 # number of overall hits 330system.cpu.icache.ReadReq_misses::cpu.inst 928547 # number of ReadReq misses 331system.cpu.icache.ReadReq_misses::total 928547 # number of ReadReq misses 332system.cpu.icache.demand_misses::cpu.inst 928547 # number of demand (read+write) misses 333system.cpu.icache.demand_misses::total 928547 # number of demand (read+write) misses 334system.cpu.icache.overall_misses::cpu.inst 928547 # number of overall misses 335system.cpu.icache.overall_misses::total 928547 # number of overall misses 336system.cpu.icache.ReadReq_miss_latency::cpu.inst 12629515000 # number of ReadReq miss cycles 337system.cpu.icache.ReadReq_miss_latency::total 12629515000 # number of ReadReq miss cycles 338system.cpu.icache.demand_miss_latency::cpu.inst 12629515000 # number of demand (read+write) miss cycles 339system.cpu.icache.demand_miss_latency::total 12629515000 # number of demand (read+write) miss cycles 340system.cpu.icache.overall_miss_latency::cpu.inst 12629515000 # number of overall miss cycles 341system.cpu.icache.overall_miss_latency::total 12629515000 # number of overall miss cycles 342system.cpu.icache.ReadReq_accesses::cpu.inst 56176718 # number of ReadReq accesses(hits+misses) 343system.cpu.icache.ReadReq_accesses::total 56176718 # number of ReadReq accesses(hits+misses) 344system.cpu.icache.demand_accesses::cpu.inst 56176718 # number of demand (read+write) accesses 345system.cpu.icache.demand_accesses::total 56176718 # number of demand (read+write) accesses 346system.cpu.icache.overall_accesses::cpu.inst 56176718 # number of overall (read+write) accesses 347system.cpu.icache.overall_accesses::total 56176718 # number of overall (read+write) accesses 348system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016529 # miss rate for ReadReq accesses 349system.cpu.icache.ReadReq_miss_rate::total 0.016529 # miss rate for ReadReq accesses 350system.cpu.icache.demand_miss_rate::cpu.inst 0.016529 # miss rate for demand accesses 351system.cpu.icache.demand_miss_rate::total 0.016529 # miss rate for demand accesses 352system.cpu.icache.overall_miss_rate::cpu.inst 0.016529 # miss rate for overall accesses 353system.cpu.icache.overall_miss_rate::total 0.016529 # miss rate for overall accesses 354system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13601.373975 # average ReadReq miss latency 355system.cpu.icache.ReadReq_avg_miss_latency::total 13601.373975 # average ReadReq miss latency 356system.cpu.icache.demand_avg_miss_latency::cpu.inst 13601.373975 # average overall miss latency 357system.cpu.icache.demand_avg_miss_latency::total 13601.373975 # average overall miss latency 358system.cpu.icache.overall_avg_miss_latency::cpu.inst 13601.373975 # average overall miss latency 359system.cpu.icache.overall_avg_miss_latency::total 13601.373975 # average overall miss latency | 473system.cpu.icache.replacements 927460 # number of replacements 474system.cpu.icache.tagsinuse 509.121498 # Cycle average of tags in use 475system.cpu.icache.total_refs 55209154 # Total number of references to valid blocks. 476system.cpu.icache.sampled_refs 927971 # Sample count of references to valid blocks. 477system.cpu.icache.avg_refs 59.494482 # Average number of references to valid blocks. 478system.cpu.icache.warmup_cycle 32120759000 # Cycle when the warmup percentage was hit. 479system.cpu.icache.occ_blocks::cpu.inst 509.121498 # Average occupied blocks per requestor 480system.cpu.icache.occ_percent::cpu.inst 0.994378 # Average percentage of cache occupancy 481system.cpu.icache.occ_percent::total 0.994378 # Average percentage of cache occupancy 482system.cpu.icache.ReadReq_hits::cpu.inst 55209154 # number of ReadReq hits 483system.cpu.icache.ReadReq_hits::total 55209154 # number of ReadReq hits 484system.cpu.icache.demand_hits::cpu.inst 55209154 # number of demand (read+write) hits 485system.cpu.icache.demand_hits::total 55209154 # number of demand (read+write) hits 486system.cpu.icache.overall_hits::cpu.inst 55209154 # number of overall hits 487system.cpu.icache.overall_hits::total 55209154 # number of overall hits 488system.cpu.icache.ReadReq_misses::cpu.inst 928131 # number of ReadReq misses 489system.cpu.icache.ReadReq_misses::total 928131 # number of ReadReq misses 490system.cpu.icache.demand_misses::cpu.inst 928131 # number of demand (read+write) misses 491system.cpu.icache.demand_misses::total 928131 # number of demand (read+write) misses 492system.cpu.icache.overall_misses::cpu.inst 928131 # number of overall misses 493system.cpu.icache.overall_misses::total 928131 # number of overall misses 494system.cpu.icache.ReadReq_miss_latency::cpu.inst 12666318500 # number of ReadReq miss cycles 495system.cpu.icache.ReadReq_miss_latency::total 12666318500 # number of ReadReq miss cycles 496system.cpu.icache.demand_miss_latency::cpu.inst 12666318500 # number of demand (read+write) miss cycles 497system.cpu.icache.demand_miss_latency::total 12666318500 # number of demand (read+write) miss cycles 498system.cpu.icache.overall_miss_latency::cpu.inst 12666318500 # number of overall miss cycles 499system.cpu.icache.overall_miss_latency::total 12666318500 # number of overall miss cycles 500system.cpu.icache.ReadReq_accesses::cpu.inst 56137285 # number of ReadReq accesses(hits+misses) 501system.cpu.icache.ReadReq_accesses::total 56137285 # number of ReadReq accesses(hits+misses) 502system.cpu.icache.demand_accesses::cpu.inst 56137285 # number of demand (read+write) accesses 503system.cpu.icache.demand_accesses::total 56137285 # number of demand (read+write) accesses 504system.cpu.icache.overall_accesses::cpu.inst 56137285 # number of overall (read+write) accesses 505system.cpu.icache.overall_accesses::total 56137285 # number of overall (read+write) accesses 506system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016533 # miss rate for ReadReq accesses 507system.cpu.icache.ReadReq_miss_rate::total 0.016533 # miss rate for ReadReq accesses 508system.cpu.icache.demand_miss_rate::cpu.inst 0.016533 # miss rate for demand accesses 509system.cpu.icache.demand_miss_rate::total 0.016533 # miss rate for demand accesses 510system.cpu.icache.overall_miss_rate::cpu.inst 0.016533 # miss rate for overall accesses 511system.cpu.icache.overall_miss_rate::total 0.016533 # miss rate for overall accesses 512system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13647.123628 # average ReadReq miss latency 513system.cpu.icache.ReadReq_avg_miss_latency::total 13647.123628 # average ReadReq miss latency 514system.cpu.icache.demand_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency 515system.cpu.icache.demand_avg_miss_latency::total 13647.123628 # average overall miss latency 516system.cpu.icache.overall_avg_miss_latency::cpu.inst 13647.123628 # average overall miss latency 517system.cpu.icache.overall_avg_miss_latency::total 13647.123628 # average overall miss latency |
| 360system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 361system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 362system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 363system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 364system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 365system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 366system.cpu.icache.fast_writes 0 # number of fast writes performed 367system.cpu.icache.cache_copies 0 # number of cache copies performed | 518system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 519system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 520system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 521system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 522system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 523system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 524system.cpu.icache.fast_writes 0 # number of fast writes performed 525system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 368system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928547 # number of ReadReq MSHR misses 369system.cpu.icache.ReadReq_mshr_misses::total 928547 # number of ReadReq MSHR misses 370system.cpu.icache.demand_mshr_misses::cpu.inst 928547 # number of demand (read+write) MSHR misses 371system.cpu.icache.demand_mshr_misses::total 928547 # number of demand (read+write) MSHR misses 372system.cpu.icache.overall_mshr_misses::cpu.inst 928547 # number of overall MSHR misses 373system.cpu.icache.overall_mshr_misses::total 928547 # number of overall MSHR misses 374system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10772421000 # number of ReadReq MSHR miss cycles 375system.cpu.icache.ReadReq_mshr_miss_latency::total 10772421000 # number of ReadReq MSHR miss cycles 376system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10772421000 # number of demand (read+write) MSHR miss cycles 377system.cpu.icache.demand_mshr_miss_latency::total 10772421000 # number of demand (read+write) MSHR miss cycles 378system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10772421000 # number of overall MSHR miss cycles 379system.cpu.icache.overall_mshr_miss_latency::total 10772421000 # number of overall MSHR miss cycles 380system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016529 # mshr miss rate for ReadReq accesses 381system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016529 # mshr miss rate for ReadReq accesses 382system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016529 # mshr miss rate for demand accesses 383system.cpu.icache.demand_mshr_miss_rate::total 0.016529 # mshr miss rate for demand accesses 384system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016529 # mshr miss rate for overall accesses 385system.cpu.icache.overall_mshr_miss_rate::total 0.016529 # mshr miss rate for overall accesses 386system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11601.373975 # average ReadReq mshr miss latency 387system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11601.373975 # average ReadReq mshr miss latency 388system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11601.373975 # average overall mshr miss latency 389system.cpu.icache.demand_avg_mshr_miss_latency::total 11601.373975 # average overall mshr miss latency 390system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11601.373975 # average overall mshr miss latency 391system.cpu.icache.overall_avg_mshr_miss_latency::total 11601.373975 # average overall mshr miss latency | 526system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928131 # number of ReadReq MSHR misses 527system.cpu.icache.ReadReq_mshr_misses::total 928131 # number of ReadReq MSHR misses 528system.cpu.icache.demand_mshr_misses::cpu.inst 928131 # number of demand (read+write) MSHR misses 529system.cpu.icache.demand_mshr_misses::total 928131 # number of demand (read+write) MSHR misses 530system.cpu.icache.overall_mshr_misses::cpu.inst 928131 # number of overall MSHR misses 531system.cpu.icache.overall_mshr_misses::total 928131 # number of overall MSHR misses 532system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10810056500 # number of ReadReq MSHR miss cycles 533system.cpu.icache.ReadReq_mshr_miss_latency::total 10810056500 # number of ReadReq MSHR miss cycles 534system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10810056500 # number of demand (read+write) MSHR miss cycles 535system.cpu.icache.demand_mshr_miss_latency::total 10810056500 # number of demand (read+write) MSHR miss cycles 536system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10810056500 # number of overall MSHR miss cycles 537system.cpu.icache.overall_mshr_miss_latency::total 10810056500 # number of overall MSHR miss cycles 538system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for ReadReq accesses 539system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016533 # mshr miss rate for ReadReq accesses 540system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for demand accesses 541system.cpu.icache.demand_mshr_miss_rate::total 0.016533 # mshr miss rate for demand accesses 542system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016533 # mshr miss rate for overall accesses 543system.cpu.icache.overall_mshr_miss_rate::total 0.016533 # mshr miss rate for overall accesses 544system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11647.123628 # average ReadReq mshr miss latency 545system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11647.123628 # average ReadReq mshr miss latency 546system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency 547system.cpu.icache.demand_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency 548system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency 549system.cpu.icache.overall_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency |
| 392system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 550system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 393system.cpu.dcache.replacements 1390620 # number of replacements 394system.cpu.dcache.tagsinuse 511.980059 # Cycle average of tags in use 395system.cpu.dcache.total_refs 14044869 # Total number of references to valid blocks. 396system.cpu.dcache.sampled_refs 1391132 # Sample count of references to valid blocks. 397system.cpu.dcache.avg_refs 10.096000 # Average number of references to valid blocks. 398system.cpu.dcache.warmup_cycle 99394000 # Cycle when the warmup percentage was hit. 399system.cpu.dcache.occ_blocks::cpu.data 511.980059 # Average occupied blocks per requestor 400system.cpu.dcache.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy 401system.cpu.dcache.occ_percent::total 0.999961 # Average percentage of cache occupancy 402system.cpu.dcache.ReadReq_hits::cpu.data 7812084 # number of ReadReq hits 403system.cpu.dcache.ReadReq_hits::total 7812084 # number of ReadReq hits 404system.cpu.dcache.WriteReq_hits::cpu.data 5850550 # number of WriteReq hits 405system.cpu.dcache.WriteReq_hits::total 5850550 # number of WriteReq hits 406system.cpu.dcache.LoadLockedReq_hits::cpu.data 182982 # number of LoadLockedReq hits 407system.cpu.dcache.LoadLockedReq_hits::total 182982 # number of LoadLockedReq hits 408system.cpu.dcache.StoreCondReq_hits::cpu.data 199236 # number of StoreCondReq hits 409system.cpu.dcache.StoreCondReq_hits::total 199236 # number of StoreCondReq hits 410system.cpu.dcache.demand_hits::cpu.data 13662634 # number of demand (read+write) hits 411system.cpu.dcache.demand_hits::total 13662634 # number of demand (read+write) hits 412system.cpu.dcache.overall_hits::cpu.data 13662634 # number of overall hits 413system.cpu.dcache.overall_hits::total 13662634 # number of overall hits 414system.cpu.dcache.ReadReq_misses::cpu.data 1069478 # number of ReadReq misses 415system.cpu.dcache.ReadReq_misses::total 1069478 # number of ReadReq misses 416system.cpu.dcache.WriteReq_misses::cpu.data 304397 # number of WriteReq misses 417system.cpu.dcache.WriteReq_misses::total 304397 # number of WriteReq misses 418system.cpu.dcache.LoadLockedReq_misses::cpu.data 17275 # number of LoadLockedReq misses 419system.cpu.dcache.LoadLockedReq_misses::total 17275 # number of LoadLockedReq misses 420system.cpu.dcache.demand_misses::cpu.data 1373875 # number of demand (read+write) misses 421system.cpu.dcache.demand_misses::total 1373875 # number of demand (read+write) misses 422system.cpu.dcache.overall_misses::cpu.data 1373875 # number of overall misses 423system.cpu.dcache.overall_misses::total 1373875 # number of overall misses 424system.cpu.dcache.ReadReq_miss_latency::cpu.data 25328737500 # number of ReadReq miss cycles 425system.cpu.dcache.ReadReq_miss_latency::total 25328737500 # number of ReadReq miss cycles 426system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866760500 # number of WriteReq miss cycles 427system.cpu.dcache.WriteReq_miss_latency::total 8866760500 # number of WriteReq miss cycles 428system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 227305000 # number of LoadLockedReq miss cycles 429system.cpu.dcache.LoadLockedReq_miss_latency::total 227305000 # number of LoadLockedReq miss cycles 430system.cpu.dcache.demand_miss_latency::cpu.data 34195498000 # number of demand (read+write) miss cycles 431system.cpu.dcache.demand_miss_latency::total 34195498000 # number of demand (read+write) miss cycles 432system.cpu.dcache.overall_miss_latency::cpu.data 34195498000 # number of overall miss cycles 433system.cpu.dcache.overall_miss_latency::total 34195498000 # number of overall miss cycles 434system.cpu.dcache.ReadReq_accesses::cpu.data 8881562 # number of ReadReq accesses(hits+misses) 435system.cpu.dcache.ReadReq_accesses::total 8881562 # number of ReadReq accesses(hits+misses) 436system.cpu.dcache.WriteReq_accesses::cpu.data 6154947 # number of WriteReq accesses(hits+misses) 437system.cpu.dcache.WriteReq_accesses::total 6154947 # number of WriteReq accesses(hits+misses) 438system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200257 # number of LoadLockedReq accesses(hits+misses) 439system.cpu.dcache.LoadLockedReq_accesses::total 200257 # number of LoadLockedReq accesses(hits+misses) 440system.cpu.dcache.StoreCondReq_accesses::cpu.data 199236 # number of StoreCondReq accesses(hits+misses) 441system.cpu.dcache.StoreCondReq_accesses::total 199236 # number of StoreCondReq accesses(hits+misses) 442system.cpu.dcache.demand_accesses::cpu.data 15036509 # number of demand (read+write) accesses 443system.cpu.dcache.demand_accesses::total 15036509 # number of demand (read+write) accesses 444system.cpu.dcache.overall_accesses::cpu.data 15036509 # number of overall (read+write) accesses 445system.cpu.dcache.overall_accesses::total 15036509 # number of overall (read+write) accesses 446system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120416 # miss rate for ReadReq accesses 447system.cpu.dcache.ReadReq_miss_rate::total 0.120416 # miss rate for ReadReq accesses 448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049456 # miss rate for WriteReq accesses 449system.cpu.dcache.WriteReq_miss_rate::total 0.049456 # miss rate for WriteReq accesses 450system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086264 # miss rate for LoadLockedReq accesses 451system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086264 # miss rate for LoadLockedReq accesses 452system.cpu.dcache.demand_miss_rate::cpu.data 0.091369 # miss rate for demand accesses 453system.cpu.dcache.demand_miss_rate::total 0.091369 # miss rate for demand accesses 454system.cpu.dcache.overall_miss_rate::cpu.data 0.091369 # miss rate for overall accesses 455system.cpu.dcache.overall_miss_rate::total 0.091369 # miss rate for overall accesses 456system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23683.271185 # average ReadReq miss latency 457system.cpu.dcache.ReadReq_avg_miss_latency::total 23683.271185 # average ReadReq miss latency 458system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29128.935239 # average WriteReq miss latency 459system.cpu.dcache.WriteReq_avg_miss_latency::total 29128.935239 # average WriteReq miss latency 460system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13158.031838 # average LoadLockedReq miss latency 461system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13158.031838 # average LoadLockedReq miss latency 462system.cpu.dcache.demand_avg_miss_latency::cpu.data 24889.817487 # average overall miss latency 463system.cpu.dcache.demand_avg_miss_latency::total 24889.817487 # average overall miss latency 464system.cpu.dcache.overall_avg_miss_latency::cpu.data 24889.817487 # average overall miss latency 465system.cpu.dcache.overall_avg_miss_latency::total 24889.817487 # average overall miss latency | 551system.cpu.dcache.replacements 1389800 # number of replacements 552system.cpu.dcache.tagsinuse 511.980808 # Cycle average of tags in use 553system.cpu.dcache.total_refs 14036386 # Total number of references to valid blocks. 554system.cpu.dcache.sampled_refs 1390312 # Sample count of references to valid blocks. 555system.cpu.dcache.avg_refs 10.095853 # Average number of references to valid blocks. 556system.cpu.dcache.warmup_cycle 93442000 # Cycle when the warmup percentage was hit. 557system.cpu.dcache.occ_blocks::cpu.data 511.980808 # Average occupied blocks per requestor 558system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy 559system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy 560system.cpu.dcache.ReadReq_hits::cpu.data 7806239 # number of ReadReq hits 561system.cpu.dcache.ReadReq_hits::total 7806239 # number of ReadReq hits 562system.cpu.dcache.WriteReq_hits::cpu.data 5847887 # number of WriteReq hits 563system.cpu.dcache.WriteReq_hits::total 5847887 # number of WriteReq hits 564system.cpu.dcache.LoadLockedReq_hits::cpu.data 183020 # number of LoadLockedReq hits 565system.cpu.dcache.LoadLockedReq_hits::total 183020 # number of LoadLockedReq hits 566system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits 567system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits 568system.cpu.dcache.demand_hits::cpu.data 13654126 # number of demand (read+write) hits 569system.cpu.dcache.demand_hits::total 13654126 # number of demand (read+write) hits 570system.cpu.dcache.overall_hits::cpu.data 13654126 # number of overall hits 571system.cpu.dcache.overall_hits::total 13654126 # number of overall hits 572system.cpu.dcache.ReadReq_misses::cpu.data 1068876 # number of ReadReq misses 573system.cpu.dcache.ReadReq_misses::total 1068876 # number of ReadReq misses 574system.cpu.dcache.WriteReq_misses::cpu.data 304232 # number of WriteReq misses 575system.cpu.dcache.WriteReq_misses::total 304232 # number of WriteReq misses 576system.cpu.dcache.LoadLockedReq_misses::cpu.data 17223 # number of LoadLockedReq misses 577system.cpu.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses 578system.cpu.dcache.demand_misses::cpu.data 1373108 # number of demand (read+write) misses 579system.cpu.dcache.demand_misses::total 1373108 # number of demand (read+write) misses 580system.cpu.dcache.overall_misses::cpu.data 1373108 # number of overall misses 581system.cpu.dcache.overall_misses::total 1373108 # number of overall misses 582system.cpu.dcache.ReadReq_miss_latency::cpu.data 22711107000 # number of ReadReq miss cycles 583system.cpu.dcache.ReadReq_miss_latency::total 22711107000 # number of ReadReq miss cycles 584system.cpu.dcache.WriteReq_miss_latency::cpu.data 8598536500 # number of WriteReq miss cycles 585system.cpu.dcache.WriteReq_miss_latency::total 8598536500 # number of WriteReq miss cycles 586system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 227697000 # number of LoadLockedReq miss cycles 587system.cpu.dcache.LoadLockedReq_miss_latency::total 227697000 # number of LoadLockedReq miss cycles 588system.cpu.dcache.demand_miss_latency::cpu.data 31309643500 # number of demand (read+write) miss cycles 589system.cpu.dcache.demand_miss_latency::total 31309643500 # number of demand (read+write) miss cycles 590system.cpu.dcache.overall_miss_latency::cpu.data 31309643500 # number of overall miss cycles 591system.cpu.dcache.overall_miss_latency::total 31309643500 # number of overall miss cycles 592system.cpu.dcache.ReadReq_accesses::cpu.data 8875115 # number of ReadReq accesses(hits+misses) 593system.cpu.dcache.ReadReq_accesses::total 8875115 # number of ReadReq accesses(hits+misses) 594system.cpu.dcache.WriteReq_accesses::cpu.data 6152119 # number of WriteReq accesses(hits+misses) 595system.cpu.dcache.WriteReq_accesses::total 6152119 # number of WriteReq accesses(hits+misses) 596system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) 597system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) 598system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) 599system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) 600system.cpu.dcache.demand_accesses::cpu.data 15027234 # number of demand (read+write) accesses 601system.cpu.dcache.demand_accesses::total 15027234 # number of demand (read+write) accesses 602system.cpu.dcache.overall_accesses::cpu.data 15027234 # number of overall (read+write) accesses 603system.cpu.dcache.overall_accesses::total 15027234 # number of overall (read+write) accesses 604system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120435 # miss rate for ReadReq accesses 605system.cpu.dcache.ReadReq_miss_rate::total 0.120435 # miss rate for ReadReq accesses 606system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049452 # miss rate for WriteReq accesses 607system.cpu.dcache.WriteReq_miss_rate::total 0.049452 # miss rate for WriteReq accesses 608system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086010 # miss rate for LoadLockedReq accesses 609system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086010 # miss rate for LoadLockedReq accesses 610system.cpu.dcache.demand_miss_rate::cpu.data 0.091375 # miss rate for demand accesses 611system.cpu.dcache.demand_miss_rate::total 0.091375 # miss rate for demand accesses 612system.cpu.dcache.overall_miss_rate::cpu.data 0.091375 # miss rate for overall accesses 613system.cpu.dcache.overall_miss_rate::total 0.091375 # miss rate for overall accesses 614system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21247.653610 # average ReadReq miss latency 615system.cpu.dcache.ReadReq_avg_miss_latency::total 21247.653610 # average ReadReq miss latency 616system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28263.090339 # average WriteReq miss latency 617system.cpu.dcache.WriteReq_avg_miss_latency::total 28263.090339 # average WriteReq miss latency 618system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13220.519073 # average LoadLockedReq miss latency 619system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13220.519073 # average LoadLockedReq miss latency 620system.cpu.dcache.demand_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency 621system.cpu.dcache.demand_avg_miss_latency::total 22802.025405 # average overall miss latency 622system.cpu.dcache.overall_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency 623system.cpu.dcache.overall_avg_miss_latency::total 22802.025405 # average overall miss latency |
| 466system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 467system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 468system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 469system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 470system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 471system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 472system.cpu.dcache.fast_writes 0 # number of fast writes performed 473system.cpu.dcache.cache_copies 0 # number of cache copies performed | 624system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 625system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 626system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 627system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 628system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 629system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 630system.cpu.dcache.fast_writes 0 # number of fast writes performed 631system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 474system.cpu.dcache.writebacks::writebacks 835360 # number of writebacks 475system.cpu.dcache.writebacks::total 835360 # number of writebacks 476system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069478 # number of ReadReq MSHR misses 477system.cpu.dcache.ReadReq_mshr_misses::total 1069478 # number of ReadReq MSHR misses 478system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304397 # number of WriteReq MSHR misses 479system.cpu.dcache.WriteReq_mshr_misses::total 304397 # number of WriteReq MSHR misses 480system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17275 # number of LoadLockedReq MSHR misses 481system.cpu.dcache.LoadLockedReq_mshr_misses::total 17275 # number of LoadLockedReq MSHR misses 482system.cpu.dcache.demand_mshr_misses::cpu.data 1373875 # number of demand (read+write) MSHR misses 483system.cpu.dcache.demand_mshr_misses::total 1373875 # number of demand (read+write) MSHR misses 484system.cpu.dcache.overall_mshr_misses::cpu.data 1373875 # number of overall MSHR misses 485system.cpu.dcache.overall_mshr_misses::total 1373875 # number of overall MSHR misses 486system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23189781500 # number of ReadReq MSHR miss cycles 487system.cpu.dcache.ReadReq_mshr_miss_latency::total 23189781500 # number of ReadReq MSHR miss cycles 488system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257966500 # number of WriteReq MSHR miss cycles 489system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257966500 # number of WriteReq MSHR miss cycles 490system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 192755000 # number of LoadLockedReq MSHR miss cycles 491system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 192755000 # number of LoadLockedReq MSHR miss cycles 492system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31447748000 # number of demand (read+write) MSHR miss cycles 493system.cpu.dcache.demand_mshr_miss_latency::total 31447748000 # number of demand (read+write) MSHR miss cycles 494system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31447748000 # number of overall MSHR miss cycles 495system.cpu.dcache.overall_mshr_miss_latency::total 31447748000 # number of overall MSHR miss cycles 496system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424905500 # number of ReadReq MSHR uncacheable cycles 497system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424905500 # number of ReadReq MSHR uncacheable cycles 498system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011694000 # number of WriteReq MSHR uncacheable cycles 499system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011694000 # number of WriteReq MSHR uncacheable cycles 500system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3436599500 # number of overall MSHR uncacheable cycles 501system.cpu.dcache.overall_mshr_uncacheable_latency::total 3436599500 # number of overall MSHR uncacheable cycles 502system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120416 # mshr miss rate for ReadReq accesses 503system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120416 # mshr miss rate for ReadReq accesses 504system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses 505system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses 506system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086264 # mshr miss rate for LoadLockedReq accesses 507system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086264 # mshr miss rate for LoadLockedReq accesses 508system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091369 # mshr miss rate for demand accesses 509system.cpu.dcache.demand_mshr_miss_rate::total 0.091369 # mshr miss rate for demand accesses 510system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091369 # mshr miss rate for overall accesses 511system.cpu.dcache.overall_mshr_miss_rate::total 0.091369 # mshr miss rate for overall accesses 512system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21683.271185 # average ReadReq mshr miss latency 513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21683.271185 # average ReadReq mshr miss latency 514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27128.935239 # average WriteReq mshr miss latency 515system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27128.935239 # average WriteReq mshr miss latency 516system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11158.031838 # average LoadLockedReq mshr miss latency 517system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11158.031838 # average LoadLockedReq mshr miss latency 518system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22889.817487 # average overall mshr miss latency 519system.cpu.dcache.demand_avg_mshr_miss_latency::total 22889.817487 # average overall mshr miss latency 520system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22889.817487 # average overall mshr miss latency 521system.cpu.dcache.overall_avg_mshr_miss_latency::total 22889.817487 # average overall mshr miss latency | 632system.cpu.dcache.writebacks::writebacks 834403 # number of writebacks 633system.cpu.dcache.writebacks::total 834403 # number of writebacks 634system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068876 # number of ReadReq MSHR misses 635system.cpu.dcache.ReadReq_mshr_misses::total 1068876 # number of ReadReq MSHR misses 636system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304232 # number of WriteReq MSHR misses 637system.cpu.dcache.WriteReq_mshr_misses::total 304232 # number of WriteReq MSHR misses 638system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17223 # number of LoadLockedReq MSHR misses 639system.cpu.dcache.LoadLockedReq_mshr_misses::total 17223 # number of LoadLockedReq MSHR misses 640system.cpu.dcache.demand_mshr_misses::cpu.data 1373108 # number of demand (read+write) MSHR misses 641system.cpu.dcache.demand_mshr_misses::total 1373108 # number of demand (read+write) MSHR misses 642system.cpu.dcache.overall_mshr_misses::cpu.data 1373108 # number of overall MSHR misses 643system.cpu.dcache.overall_mshr_misses::total 1373108 # number of overall MSHR misses 644system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20573355000 # number of ReadReq MSHR miss cycles 645system.cpu.dcache.ReadReq_mshr_miss_latency::total 20573355000 # number of ReadReq MSHR miss cycles 646system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7990072500 # number of WriteReq MSHR miss cycles 647system.cpu.dcache.WriteReq_mshr_miss_latency::total 7990072500 # number of WriteReq MSHR miss cycles 648system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193251000 # number of LoadLockedReq MSHR miss cycles 649system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193251000 # number of LoadLockedReq MSHR miss cycles 650system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28563427500 # number of demand (read+write) MSHR miss cycles 651system.cpu.dcache.demand_mshr_miss_latency::total 28563427500 # number of demand (read+write) MSHR miss cycles 652system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28563427500 # number of overall MSHR miss cycles 653system.cpu.dcache.overall_mshr_miss_latency::total 28563427500 # number of overall MSHR miss cycles 654system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles 655system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles 656system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997500 # number of WriteReq MSHR uncacheable cycles 657system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997500 # number of WriteReq MSHR uncacheable cycles 658system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435233500 # number of overall MSHR uncacheable cycles 659system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435233500 # number of overall MSHR uncacheable cycles 660system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120435 # mshr miss rate for ReadReq accesses 661system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120435 # mshr miss rate for ReadReq accesses 662system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049452 # mshr miss rate for WriteReq accesses 663system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049452 # mshr miss rate for WriteReq accesses 664system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086010 # mshr miss rate for LoadLockedReq accesses 665system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086010 # mshr miss rate for LoadLockedReq accesses 666system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for demand accesses 667system.cpu.dcache.demand_mshr_miss_rate::total 0.091375 # mshr miss rate for demand accesses 668system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for overall accesses 669system.cpu.dcache.overall_mshr_miss_rate::total 0.091375 # mshr miss rate for overall accesses 670system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19247.653610 # average ReadReq mshr miss latency 671system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19247.653610 # average ReadReq mshr miss latency 672system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26263.090339 # average WriteReq mshr miss latency 673system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26263.090339 # average WriteReq mshr miss latency 674system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11220.519073 # average LoadLockedReq mshr miss latency 675system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11220.519073 # average LoadLockedReq mshr miss latency 676system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency 677system.cpu.dcache.demand_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency 678system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency 679system.cpu.dcache.overall_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency |
| 522system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 523system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 524system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 525system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 526system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 527system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 528system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 680system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 681system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 682system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 683system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 684system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 685system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 686system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 529system.cpu.l2cache.replacements 336256 # number of replacements 530system.cpu.l2cache.tagsinuse 65309.148086 # Cycle average of tags in use 531system.cpu.l2cache.total_refs 2447127 # Total number of references to valid blocks. 532system.cpu.l2cache.sampled_refs 401418 # Sample count of references to valid blocks. 533system.cpu.l2cache.avg_refs 6.096206 # Average number of references to valid blocks. 534system.cpu.l2cache.warmup_cycle 5907030000 # Cycle when the warmup percentage was hit. 535system.cpu.l2cache.occ_blocks::writebacks 55687.812663 # Average occupied blocks per requestor 536system.cpu.l2cache.occ_blocks::cpu.inst 4769.025398 # Average occupied blocks per requestor 537system.cpu.l2cache.occ_blocks::cpu.data 4852.310026 # Average occupied blocks per requestor 538system.cpu.l2cache.occ_percent::writebacks 0.849729 # Average percentage of cache occupancy 539system.cpu.l2cache.occ_percent::cpu.inst 0.072770 # Average percentage of cache occupancy 540system.cpu.l2cache.occ_percent::cpu.data 0.074040 # Average percentage of cache occupancy 541system.cpu.l2cache.occ_percent::total 0.996539 # Average percentage of cache occupancy 542system.cpu.l2cache.ReadReq_hits::cpu.inst 915237 # number of ReadReq hits 543system.cpu.l2cache.ReadReq_hits::cpu.data 814783 # number of ReadReq hits 544system.cpu.l2cache.ReadReq_hits::total 1730020 # number of ReadReq hits 545system.cpu.l2cache.Writeback_hits::writebacks 835360 # number of Writeback hits 546system.cpu.l2cache.Writeback_hits::total 835360 # number of Writeback hits | 687system.cpu.l2cache.replacements 336061 # number of replacements 688system.cpu.l2cache.tagsinuse 65323.847661 # Cycle average of tags in use 689system.cpu.l2cache.total_refs 2445310 # Total number of references to valid blocks. 690system.cpu.l2cache.sampled_refs 401224 # Sample count of references to valid blocks. 691system.cpu.l2cache.avg_refs 6.094625 # Average number of references to valid blocks. 692system.cpu.l2cache.warmup_cycle 5214408002 # Cycle when the warmup percentage was hit. 693system.cpu.l2cache.occ_blocks::writebacks 55704.521339 # Average occupied blocks per requestor 694system.cpu.l2cache.occ_blocks::cpu.inst 4784.646064 # Average occupied blocks per requestor 695system.cpu.l2cache.occ_blocks::cpu.data 4834.680258 # Average occupied blocks per requestor 696system.cpu.l2cache.occ_percent::writebacks 0.849984 # Average percentage of cache occupancy 697system.cpu.l2cache.occ_percent::cpu.inst 0.073008 # Average percentage of cache occupancy 698system.cpu.l2cache.occ_percent::cpu.data 0.073771 # Average percentage of cache occupancy 699system.cpu.l2cache.occ_percent::total 0.996763 # Average percentage of cache occupancy 700system.cpu.l2cache.ReadReq_hits::cpu.inst 914821 # number of ReadReq hits 701system.cpu.l2cache.ReadReq_hits::cpu.data 814177 # number of ReadReq hits 702system.cpu.l2cache.ReadReq_hits::total 1728998 # number of ReadReq hits 703system.cpu.l2cache.Writeback_hits::writebacks 834403 # number of Writeback hits 704system.cpu.l2cache.Writeback_hits::total 834403 # number of Writeback hits |
| 547system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 548system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 705system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 706system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 549system.cpu.l2cache.ReadExReq_hits::cpu.data 187521 # number of ReadExReq hits 550system.cpu.l2cache.ReadExReq_hits::total 187521 # number of ReadExReq hits 551system.cpu.l2cache.demand_hits::cpu.inst 915237 # number of demand (read+write) hits 552system.cpu.l2cache.demand_hits::cpu.data 1002304 # number of demand (read+write) hits 553system.cpu.l2cache.demand_hits::total 1917541 # number of demand (read+write) hits 554system.cpu.l2cache.overall_hits::cpu.inst 915237 # number of overall hits 555system.cpu.l2cache.overall_hits::cpu.data 1002304 # number of overall hits 556system.cpu.l2cache.overall_hits::total 1917541 # number of overall hits | 707system.cpu.l2cache.ReadExReq_hits::cpu.data 187505 # number of ReadExReq hits 708system.cpu.l2cache.ReadExReq_hits::total 187505 # number of ReadExReq hits 709system.cpu.l2cache.demand_hits::cpu.inst 914821 # number of demand (read+write) hits 710system.cpu.l2cache.demand_hits::cpu.data 1001682 # number of demand (read+write) hits 711system.cpu.l2cache.demand_hits::total 1916503 # number of demand (read+write) hits 712system.cpu.l2cache.overall_hits::cpu.inst 914821 # number of overall hits 713system.cpu.l2cache.overall_hits::cpu.data 1001682 # number of overall hits 714system.cpu.l2cache.overall_hits::total 1916503 # number of overall hits |
| 557system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses | 715system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses |
| 558system.cpu.l2cache.ReadReq_misses::cpu.data 271970 # number of ReadReq misses 559system.cpu.l2cache.ReadReq_misses::total 285260 # number of ReadReq misses | 716system.cpu.l2cache.ReadReq_misses::cpu.data 271922 # number of ReadReq misses 717system.cpu.l2cache.ReadReq_misses::total 285212 # number of ReadReq misses |
| 560system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 561system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses | 718system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 719system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses |
| 562system.cpu.l2cache.ReadExReq_misses::cpu.data 116859 # number of ReadExReq misses 563system.cpu.l2cache.ReadExReq_misses::total 116859 # number of ReadExReq misses | 720system.cpu.l2cache.ReadExReq_misses::cpu.data 116710 # number of ReadExReq misses 721system.cpu.l2cache.ReadExReq_misses::total 116710 # number of ReadExReq misses |
| 564system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses | 722system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses |
| 565system.cpu.l2cache.demand_misses::cpu.data 388829 # number of demand (read+write) misses 566system.cpu.l2cache.demand_misses::total 402119 # number of demand (read+write) misses | 723system.cpu.l2cache.demand_misses::cpu.data 388632 # number of demand (read+write) misses 724system.cpu.l2cache.demand_misses::total 401922 # number of demand (read+write) misses |
| 567system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses | 725system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses |
| 568system.cpu.l2cache.overall_misses::cpu.data 388829 # number of overall misses 569system.cpu.l2cache.overall_misses::total 402119 # number of overall misses 570system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 691484000 # number of ReadReq miss cycles 571system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14147953500 # number of ReadReq miss cycles 572system.cpu.l2cache.ReadReq_miss_latency::total 14839437500 # number of ReadReq miss cycles 573system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 248500 # number of UpgradeReq miss cycles 574system.cpu.l2cache.UpgradeReq_miss_latency::total 248500 # number of UpgradeReq miss cycles 575system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6077611500 # number of ReadExReq miss cycles 576system.cpu.l2cache.ReadExReq_miss_latency::total 6077611500 # number of ReadExReq miss cycles 577system.cpu.l2cache.demand_miss_latency::cpu.inst 691484000 # number of demand (read+write) miss cycles 578system.cpu.l2cache.demand_miss_latency::cpu.data 20225565000 # number of demand (read+write) miss cycles 579system.cpu.l2cache.demand_miss_latency::total 20917049000 # number of demand (read+write) miss cycles 580system.cpu.l2cache.overall_miss_latency::cpu.inst 691484000 # number of overall miss cycles 581system.cpu.l2cache.overall_miss_latency::cpu.data 20225565000 # number of overall miss cycles 582system.cpu.l2cache.overall_miss_latency::total 20917049000 # number of overall miss cycles 583system.cpu.l2cache.ReadReq_accesses::cpu.inst 928527 # number of ReadReq accesses(hits+misses) 584system.cpu.l2cache.ReadReq_accesses::cpu.data 1086753 # number of ReadReq accesses(hits+misses) 585system.cpu.l2cache.ReadReq_accesses::total 2015280 # number of ReadReq accesses(hits+misses) 586system.cpu.l2cache.Writeback_accesses::writebacks 835360 # number of Writeback accesses(hits+misses) 587system.cpu.l2cache.Writeback_accesses::total 835360 # number of Writeback accesses(hits+misses) | 726system.cpu.l2cache.overall_misses::cpu.data 388632 # number of overall misses 727system.cpu.l2cache.overall_misses::total 401922 # number of overall misses 728system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 733695500 # number of ReadReq miss cycles 729system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11538737000 # number of ReadReq miss cycles 730system.cpu.l2cache.ReadReq_miss_latency::total 12272432500 # number of ReadReq miss cycles 731system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 189500 # number of UpgradeReq miss cycles 732system.cpu.l2cache.UpgradeReq_miss_latency::total 189500 # number of UpgradeReq miss cycles 733system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5810363500 # number of ReadExReq miss cycles 734system.cpu.l2cache.ReadExReq_miss_latency::total 5810363500 # number of ReadExReq miss cycles 735system.cpu.l2cache.demand_miss_latency::cpu.inst 733695500 # number of demand (read+write) miss cycles 736system.cpu.l2cache.demand_miss_latency::cpu.data 17349100500 # number of demand (read+write) miss cycles 737system.cpu.l2cache.demand_miss_latency::total 18082796000 # number of demand (read+write) miss cycles 738system.cpu.l2cache.overall_miss_latency::cpu.inst 733695500 # number of overall miss cycles 739system.cpu.l2cache.overall_miss_latency::cpu.data 17349100500 # number of overall miss cycles 740system.cpu.l2cache.overall_miss_latency::total 18082796000 # number of overall miss cycles 741system.cpu.l2cache.ReadReq_accesses::cpu.inst 928111 # number of ReadReq accesses(hits+misses) 742system.cpu.l2cache.ReadReq_accesses::cpu.data 1086099 # number of ReadReq accesses(hits+misses) 743system.cpu.l2cache.ReadReq_accesses::total 2014210 # number of ReadReq accesses(hits+misses) 744system.cpu.l2cache.Writeback_accesses::writebacks 834403 # number of Writeback accesses(hits+misses) 745system.cpu.l2cache.Writeback_accesses::total 834403 # number of Writeback accesses(hits+misses) |
| 588system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 589system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) | 746system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 747system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) |
| 590system.cpu.l2cache.ReadExReq_accesses::cpu.data 304380 # number of ReadExReq accesses(hits+misses) 591system.cpu.l2cache.ReadExReq_accesses::total 304380 # number of ReadExReq accesses(hits+misses) 592system.cpu.l2cache.demand_accesses::cpu.inst 928527 # number of demand (read+write) accesses 593system.cpu.l2cache.demand_accesses::cpu.data 1391133 # number of demand (read+write) accesses 594system.cpu.l2cache.demand_accesses::total 2319660 # number of demand (read+write) accesses 595system.cpu.l2cache.overall_accesses::cpu.inst 928527 # number of overall (read+write) accesses 596system.cpu.l2cache.overall_accesses::cpu.data 1391133 # number of overall (read+write) accesses 597system.cpu.l2cache.overall_accesses::total 2319660 # number of overall (read+write) accesses 598system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014313 # miss rate for ReadReq accesses 599system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250259 # miss rate for ReadReq accesses 600system.cpu.l2cache.ReadReq_miss_rate::total 0.141549 # miss rate for ReadReq accesses | 748system.cpu.l2cache.ReadExReq_accesses::cpu.data 304215 # number of ReadExReq accesses(hits+misses) 749system.cpu.l2cache.ReadExReq_accesses::total 304215 # number of ReadExReq accesses(hits+misses) 750system.cpu.l2cache.demand_accesses::cpu.inst 928111 # number of demand (read+write) accesses 751system.cpu.l2cache.demand_accesses::cpu.data 1390314 # number of demand (read+write) accesses 752system.cpu.l2cache.demand_accesses::total 2318425 # number of demand (read+write) accesses 753system.cpu.l2cache.overall_accesses::cpu.inst 928111 # number of overall (read+write) accesses 754system.cpu.l2cache.overall_accesses::cpu.data 1390314 # number of overall (read+write) accesses 755system.cpu.l2cache.overall_accesses::total 2318425 # number of overall (read+write) accesses 756system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014319 # miss rate for ReadReq accesses 757system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250366 # miss rate for ReadReq accesses 758system.cpu.l2cache.ReadReq_miss_rate::total 0.141600 # miss rate for ReadReq accesses |
| 601system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 602system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses | 759system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 760system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses |
| 603system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383925 # miss rate for ReadExReq accesses 604system.cpu.l2cache.ReadExReq_miss_rate::total 0.383925 # miss rate for ReadExReq accesses 605system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014313 # miss rate for demand accesses 606system.cpu.l2cache.demand_miss_rate::cpu.data 0.279505 # miss rate for demand accesses 607system.cpu.l2cache.demand_miss_rate::total 0.173353 # miss rate for demand accesses 608system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014313 # miss rate for overall accesses 609system.cpu.l2cache.overall_miss_rate::cpu.data 0.279505 # miss rate for overall accesses 610system.cpu.l2cache.overall_miss_rate::total 0.173353 # miss rate for overall accesses 611system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52030.398796 # average ReadReq miss latency 612system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52020.272457 # average ReadReq miss latency 613system.cpu.l2cache.ReadReq_avg_miss_latency::total 52020.744233 # average ReadReq miss latency 614system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19115.384615 # average UpgradeReq miss latency 615system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19115.384615 # average UpgradeReq miss latency 616system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52008.073833 # average ReadExReq miss latency 617system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52008.073833 # average ReadExReq miss latency 618system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52030.398796 # average overall miss latency 619system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52016.606272 # average overall miss latency 620system.cpu.l2cache.demand_avg_miss_latency::total 52017.062113 # average overall miss latency 621system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52030.398796 # average overall miss latency 622system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52016.606272 # average overall miss latency 623system.cpu.l2cache.overall_avg_miss_latency::total 52017.062113 # average overall miss latency | 761system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383643 # miss rate for ReadExReq accesses 762system.cpu.l2cache.ReadExReq_miss_rate::total 0.383643 # miss rate for ReadExReq accesses 763system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014319 # miss rate for demand accesses 764system.cpu.l2cache.demand_miss_rate::cpu.data 0.279528 # miss rate for demand accesses 765system.cpu.l2cache.demand_miss_rate::total 0.173360 # miss rate for demand accesses 766system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014319 # miss rate for overall accesses 767system.cpu.l2cache.overall_miss_rate::cpu.data 0.279528 # miss rate for overall accesses 768system.cpu.l2cache.overall_miss_rate::total 0.173360 # miss rate for overall accesses 769system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55206.583898 # average ReadReq miss latency 770system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 42433.995778 # average ReadReq miss latency 771system.cpu.l2cache.ReadReq_avg_miss_latency::total 43029.159012 # average ReadReq miss latency 772system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14576.923077 # average UpgradeReq miss latency 773system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14576.923077 # average UpgradeReq miss latency 774system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49784.624282 # average ReadExReq miss latency 775system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49784.624282 # average ReadExReq miss latency 776system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55206.583898 # average overall miss latency 777system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44641.461588 # average overall miss latency 778system.cpu.l2cache.demand_avg_miss_latency::total 44990.809162 # average overall miss latency 779system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55206.583898 # average overall miss latency 780system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44641.461588 # average overall miss latency 781system.cpu.l2cache.overall_avg_miss_latency::total 44990.809162 # average overall miss latency |
| 624system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 625system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 626system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 627system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 628system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 629system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 630system.cpu.l2cache.fast_writes 0 # number of fast writes performed 631system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 782system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 783system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 784system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 785system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 786system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 787system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 788system.cpu.l2cache.fast_writes 0 # number of fast writes performed 789system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 632system.cpu.l2cache.writebacks::writebacks 74188 # number of writebacks 633system.cpu.l2cache.writebacks::total 74188 # number of writebacks | 790system.cpu.l2cache.writebacks::writebacks 73991 # number of writebacks 791system.cpu.l2cache.writebacks::total 73991 # number of writebacks |
| 634system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses | 792system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses |
| 635system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271970 # number of ReadReq MSHR misses 636system.cpu.l2cache.ReadReq_mshr_misses::total 285260 # number of ReadReq MSHR misses | 793system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271922 # number of ReadReq MSHR misses 794system.cpu.l2cache.ReadReq_mshr_misses::total 285212 # number of ReadReq MSHR misses |
| 637system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 638system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses | 795system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 796system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses |
| 639system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116859 # number of ReadExReq MSHR misses 640system.cpu.l2cache.ReadExReq_mshr_misses::total 116859 # number of ReadExReq MSHR misses | 797system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116710 # number of ReadExReq MSHR misses 798system.cpu.l2cache.ReadExReq_mshr_misses::total 116710 # number of ReadExReq MSHR misses |
| 641system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses | 799system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses |
| 642system.cpu.l2cache.demand_mshr_misses::cpu.data 388829 # number of demand (read+write) MSHR misses 643system.cpu.l2cache.demand_mshr_misses::total 402119 # number of demand (read+write) MSHR misses | 800system.cpu.l2cache.demand_mshr_misses::cpu.data 388632 # number of demand (read+write) MSHR misses 801system.cpu.l2cache.demand_mshr_misses::total 401922 # number of demand (read+write) MSHR misses |
| 644system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses | 802system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses |
| 645system.cpu.l2cache.overall_mshr_misses::cpu.data 388829 # number of overall MSHR misses 646system.cpu.l2cache.overall_mshr_misses::total 402119 # number of overall MSHR misses 647system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531884000 # number of ReadReq MSHR miss cycles 648system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884274000 # number of ReadReq MSHR miss cycles 649system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles 650system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles 651system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles 652system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219500 # number of ReadExReq MSHR miss cycles 653system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219500 # number of ReadExReq MSHR miss cycles 654system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles 655system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493500 # number of demand (read+write) MSHR miss cycles 656system.cpu.l2cache.demand_mshr_miss_latency::total 16091377500 # number of demand (read+write) MSHR miss cycles 657system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles 658system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493500 # number of overall MSHR miss cycles 659system.cpu.l2cache.overall_mshr_miss_latency::total 16091377500 # number of overall MSHR miss cycles 660system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles 661system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles 662system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles 663system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892328500 # number of WriteReq MSHR uncacheable cycles 664system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508500 # number of overall MSHR uncacheable cycles 665system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508500 # number of overall MSHR uncacheable cycles 666system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for ReadReq accesses 667system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses 668system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141549 # mshr miss rate for ReadReq accesses | 803system.cpu.l2cache.overall_mshr_misses::cpu.data 388632 # number of overall MSHR misses 804system.cpu.l2cache.overall_mshr_misses::total 401922 # number of overall MSHR misses 805system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 561273079 # number of ReadReq MSHR miss cycles 806system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8004831581 # number of ReadReq MSHR miss cycles 807system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8566104660 # number of ReadReq MSHR miss cycles 808system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles 809system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles 810system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4294420630 # number of ReadExReq MSHR miss cycles 811system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4294420630 # number of ReadExReq MSHR miss cycles 812system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 561273079 # number of demand (read+write) MSHR miss cycles 813system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12299252211 # number of demand (read+write) MSHR miss cycles 814system.cpu.l2cache.demand_mshr_miss_latency::total 12860525290 # number of demand (read+write) MSHR miss cycles 815system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 561273079 # number of overall MSHR miss cycles 816system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12299252211 # number of overall MSHR miss cycles 817system.cpu.l2cache.overall_mshr_miss_latency::total 12860525290 # number of overall MSHR miss cycles 818system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles 819system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles 820system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1891670000 # number of WriteReq MSHR uncacheable cycles 821system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1891670000 # number of WriteReq MSHR uncacheable cycles 822system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223220000 # number of overall MSHR uncacheable cycles 823system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223220000 # number of overall MSHR uncacheable cycles 824system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for ReadReq accesses 825system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250366 # mshr miss rate for ReadReq accesses 826system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141600 # mshr miss rate for ReadReq accesses |
| 669system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 670system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses | 827system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 828system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses |
| 671system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383925 # mshr miss rate for ReadExReq accesses 672system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383925 # mshr miss rate for ReadExReq accesses 673system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for demand accesses 674system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for demand accesses 675system.cpu.l2cache.demand_mshr_miss_rate::total 0.173353 # mshr miss rate for demand accesses 676system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for overall accesses 677system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for overall accesses 678system.cpu.l2cache.overall_mshr_miss_rate::total 0.173353 # mshr miss rate for overall accesses 679system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40021.369451 # average ReadReq mshr miss latency 680system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 # average ReadReq mshr miss latency 681system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency 682system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency 683system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency 684system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.355018 # average ReadExReq mshr miss latency 685system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.355018 # average ReadExReq mshr miss latency 686system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency 687system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency 688system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency 689system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency 690system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency 691system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency | 829system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383643 # mshr miss rate for ReadExReq accesses 830system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383643 # mshr miss rate for ReadExReq accesses 831system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for demand accesses 832system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279528 # mshr miss rate for demand accesses 833system.cpu.l2cache.demand_mshr_miss_rate::total 0.173360 # mshr miss rate for demand accesses 834system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014319 # mshr miss rate for overall accesses 835system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279528 # mshr miss rate for overall accesses 836system.cpu.l2cache.overall_mshr_miss_rate::total 0.173360 # mshr miss rate for overall accesses 837system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42232.737321 # average ReadReq mshr miss latency 838system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 29437.969642 # average ReadReq mshr miss latency 839system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30034.166374 # average ReadReq mshr miss latency 840system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency 841system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency 842system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36795.652729 # average ReadExReq mshr miss latency 843system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36795.652729 # average ReadExReq mshr miss latency 844system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42232.737321 # average overall mshr miss latency 845system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31647.554013 # average overall mshr miss latency 846system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31997.564926 # average overall mshr miss latency 847system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42232.737321 # average overall mshr miss latency 848system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31647.554013 # average overall mshr miss latency 849system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31997.564926 # average overall mshr miss latency |
| 692system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 693system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 694system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 695system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 696system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 697system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 698system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 699 700---------- End Simulation Statistics ---------- | 850system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 851system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 852system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 853system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 854system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 855system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 856system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 857 858---------- End Simulation Statistics ---------- |