| stats.txt (9285:9901180cd573) | stats.txt (9289:a31a1243a3ed) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.914421 # Number of seconds simulated 4sim_ticks 1914420945000 # Number of ticks simulated 5final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.914421 # Number of seconds simulated 4sim_ticks 1914420945000 # Number of ticks simulated 5final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1284205 # Simulator instruction rate (inst/s) 8host_op_rate 1284205 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43773036105 # Simulator tick rate (ticks/s) 10host_mem_usage 295308 # Number of bytes of host memory used 11host_seconds 43.74 # Real time elapsed on the host | 7host_inst_rate 1299276 # Simulator instruction rate (inst/s) 8host_op_rate 1299275 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44286723014 # Simulator tick rate (ticks/s) 10host_mem_usage 288696 # Number of bytes of host memory used 11host_seconds 43.23 # Real time elapsed on the host |
| 12sim_insts 56164879 # Number of instructions simulated 13sim_ops 56164879 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24860096 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28362752 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory --- 62 unchanged lines hidden (view full) --- 82system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 83system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency 84system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275415.258134 # average WriteReq miss latency 85system.iocache.WriteReq_avg_miss_latency::total 275415.258134 # average WriteReq miss latency 86system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency 87system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency 88system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency 89system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency | 12sim_insts 56164879 # Number of instructions simulated 13sim_ops 56164879 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24860096 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28362752 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory --- 62 unchanged lines hidden (view full) --- 82system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 83system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency 84system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275415.258134 # average WriteReq miss latency 85system.iocache.WriteReq_avg_miss_latency::total 275415.258134 # average WriteReq miss latency 86system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency 87system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency 88system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency 89system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency |
| 90system.iocache.blocked_cycles::no_mshrs 199052000 # number of cycles access was blocked | 90system.iocache.blocked_cycles::no_mshrs 199052 # number of cycles access was blocked |
| 91system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked 93system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 91system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked 93system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 94system.iocache.avg_blocked_cycles::no_mshrs 8086.942391 # average number of cycles each access was blocked | 94system.iocache.avg_blocked_cycles::no_mshrs 8.086942 # average number of cycles each access was blocked |
| 95system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 96system.iocache.fast_writes 0 # number of fast writes performed 97system.iocache.cache_copies 0 # number of cache copies performed 98system.iocache.writebacks::writebacks 41512 # number of writebacks 99system.iocache.writebacks::total 41512 # number of writebacks 100system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 101system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 102system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 103system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 104system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 105system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 106system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 107system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 95system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 96system.iocache.fast_writes 0 # number of fast writes performed 97system.iocache.cache_copies 0 # number of cache copies performed 98system.iocache.writebacks::writebacks 41512 # number of writebacks 99system.iocache.writebacks::total 41512 # number of writebacks 100system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 101system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 102system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 103system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 104system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 105system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 106system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 107system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 108system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 109system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles 110system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283200000 # number of WriteReq MSHR miss cycles 111system.iocache.WriteReq_mshr_miss_latency::total 9283200000 # number of WriteReq MSHR miss cycles 112system.iocache.demand_mshr_miss_latency::tsunami.ide 9294876000 # number of demand (read+write) MSHR miss cycles 113system.iocache.demand_mshr_miss_latency::total 9294876000 # number of demand (read+write) MSHR miss cycles 114system.iocache.overall_mshr_miss_latency::tsunami.ide 9294876000 # number of overall MSHR miss cycles 115system.iocache.overall_mshr_miss_latency::total 9294876000 # number of overall MSHR miss cycles | 108system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles 109system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles 110system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283350806 # number of WriteReq MSHR miss cycles 111system.iocache.WriteReq_mshr_miss_latency::total 9283350806 # number of WriteReq MSHR miss cycles 112system.iocache.demand_mshr_miss_latency::tsunami.ide 9295027804 # number of demand (read+write) MSHR miss cycles 113system.iocache.demand_mshr_miss_latency::total 9295027804 # number of demand (read+write) MSHR miss cycles 114system.iocache.overall_mshr_miss_latency::tsunami.ide 9295027804 # number of overall MSHR miss cycles 115system.iocache.overall_mshr_miss_latency::total 9295027804 # number of overall MSHR miss cycles |
| 116system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 117system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 118system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 119system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 120system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 121system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 122system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 123system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 116system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 117system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 118system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 119system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 120system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 121system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 122system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 123system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 124system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 125system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency 126system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223411.628802 # average WriteReq mshr miss latency 127system.iocache.WriteReq_avg_mshr_miss_latency::total 223411.628802 # average WriteReq mshr miss latency 128system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency 129system.iocache.demand_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency 130system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency 131system.iocache.overall_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency | 124system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency 125system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency 126system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223415.258134 # average WriteReq mshr miss latency 127system.iocache.WriteReq_avg_mshr_miss_latency::total 223415.258134 # average WriteReq mshr miss latency 128system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency 129system.iocache.demand_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency 130system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency 131system.iocache.overall_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency |
| 132system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 133system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 134system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 135system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 136system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 137system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 138system.disk0.dma_write_txs 395 # Number of DMA write transactions. 139system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 504 unchanged lines hidden (view full) --- 644system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses 645system.cpu.l2cache.overall_mshr_misses::cpu.data 388829 # number of overall MSHR misses 646system.cpu.l2cache.overall_mshr_misses::total 402119 # number of overall MSHR misses 647system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531884000 # number of ReadReq MSHR miss cycles 648system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884274000 # number of ReadReq MSHR miss cycles 649system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles 650system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles 651system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles | 132system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 133system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 134system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 135system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 136system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 137system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 138system.disk0.dma_write_txs 395 # Number of DMA write transactions. 139system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 504 unchanged lines hidden (view full) --- 644system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses 645system.cpu.l2cache.overall_mshr_misses::cpu.data 388829 # number of overall MSHR misses 646system.cpu.l2cache.overall_mshr_misses::total 402119 # number of overall MSHR misses 647system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531884000 # number of ReadReq MSHR miss cycles 648system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884274000 # number of ReadReq MSHR miss cycles 649system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles 650system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles 651system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles |
| 652system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219000 # number of ReadExReq MSHR miss cycles 653system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219000 # number of ReadExReq MSHR miss cycles | 652system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219500 # number of ReadExReq MSHR miss cycles 653system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219500 # number of ReadExReq MSHR miss cycles |
| 654system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles | 654system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles |
| 655system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493000 # number of demand (read+write) MSHR miss cycles 656system.cpu.l2cache.demand_mshr_miss_latency::total 16091377000 # number of demand (read+write) MSHR miss cycles | 655system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493500 # number of demand (read+write) MSHR miss cycles 656system.cpu.l2cache.demand_mshr_miss_latency::total 16091377500 # number of demand (read+write) MSHR miss cycles |
| 657system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles | 657system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles |
| 658system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493000 # number of overall MSHR miss cycles 659system.cpu.l2cache.overall_mshr_miss_latency::total 16091377000 # number of overall MSHR miss cycles | 658system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493500 # number of overall MSHR miss cycles 659system.cpu.l2cache.overall_mshr_miss_latency::total 16091377500 # number of overall MSHR miss cycles |
| 660system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles 661system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles 662system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles 663system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892328500 # number of WriteReq MSHR uncacheable cycles 664system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508500 # number of overall MSHR uncacheable cycles 665system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508500 # number of overall MSHR uncacheable cycles 666system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for ReadReq accesses 667system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses --- 8 unchanged lines hidden (view full) --- 676system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for overall accesses 677system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for overall accesses 678system.cpu.l2cache.overall_mshr_miss_rate::total 0.173353 # mshr miss rate for overall accesses 679system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40021.369451 # average ReadReq mshr miss latency 680system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 # average ReadReq mshr miss latency 681system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency 682system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency 683system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency | 660system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles 661system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles 662system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles 663system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892328500 # number of WriteReq MSHR uncacheable cycles 664system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508500 # number of overall MSHR uncacheable cycles 665system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508500 # number of overall MSHR uncacheable cycles 666system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for ReadReq accesses 667system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses --- 8 unchanged lines hidden (view full) --- 676system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for overall accesses 677system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for overall accesses 678system.cpu.l2cache.overall_mshr_miss_rate::total 0.173353 # mshr miss rate for overall accesses 679system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40021.369451 # average ReadReq mshr miss latency 680system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 # average ReadReq mshr miss latency 681system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency 682system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency 683system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency |
| 684system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.350739 # average ReadExReq mshr miss latency 685system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.350739 # average ReadExReq mshr miss latency | 684system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.355018 # average ReadExReq mshr miss latency 685system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.355018 # average ReadExReq mshr miss latency |
| 686system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency | 686system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency |
| 687system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency 688system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency | 687system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency 688system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency |
| 689system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency | 689system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency |
| 690system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency 691system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency | 690system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency 691system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency |
| 692system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 693system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 694system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 695system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 696system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 697system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 698system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 699 700---------- End Simulation Statistics ---------- | 692system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 693system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 694system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 695system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 696system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 697system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 698system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 699 700---------- End Simulation Statistics ---------- |