| stats.txt (9283:490958b032d6) | stats.txt (9285:9901180cd573) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.920895 # Number of seconds simulated 4sim_ticks 1920895294000 # Number of ticks simulated 5final_tick 1920895294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.914421 # Number of seconds simulated 4sim_ticks 1914420945000 # Number of ticks simulated 5final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1271848 # Simulator instruction rate (inst/s) 8host_op_rate 1271848 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43474553061 # Simulator tick rate (ticks/s) 10host_mem_usage 295012 # Number of bytes of host memory used 11host_seconds 44.18 # Real time elapsed on the host 12sim_insts 56195754 # Number of instructions simulated 13sim_ops 56195754 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24859968 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28362816 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7404288 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7404288 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388437 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 443169 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115692 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115692 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 442760 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12941865 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1380789 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14765415 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 442760 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 442760 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3854603 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3854603 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3854603 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 442760 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s) 41system.cpu.l2cache.replacements 336257 # number of replacements 42system.cpu.l2cache.tagsinuse 65308.063316 # Cycle average of tags in use 43system.cpu.l2cache.total_refs 2448454 # Total number of references to valid blocks. 44system.cpu.l2cache.sampled_refs 401419 # Sample count of references to valid blocks. 45system.cpu.l2cache.avg_refs 6.099497 # Average number of references to valid blocks. 46system.cpu.l2cache.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. 47system.cpu.l2cache.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor 48system.cpu.l2cache.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor 49system.cpu.l2cache.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor 50system.cpu.l2cache.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy 51system.cpu.l2cache.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy 52system.cpu.l2cache.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy 53system.cpu.l2cache.occ_percent::total 0.996522 # Average percentage of cache occupancy 54system.cpu.l2cache.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits 55system.cpu.l2cache.ReadReq_hits::cpu.data 814985 # number of ReadReq hits 56system.cpu.l2cache.ReadReq_hits::total 1731448 # number of ReadReq hits 57system.cpu.l2cache.Writeback_hits::writebacks 835257 # number of Writeback hits 58system.cpu.l2cache.Writeback_hits::total 835257 # number of Writeback hits 59system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 60system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 61system.cpu.l2cache.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits 62system.cpu.l2cache.ReadExReq_hits::total 187565 # number of ReadExReq hits 63system.cpu.l2cache.demand_hits::cpu.inst 916463 # number of demand (read+write) hits 64system.cpu.l2cache.demand_hits::cpu.data 1002550 # number of demand (read+write) hits 65system.cpu.l2cache.demand_hits::total 1919013 # number of demand (read+write) hits 66system.cpu.l2cache.overall_hits::cpu.inst 916463 # number of overall hits 67system.cpu.l2cache.overall_hits::cpu.data 1002550 # number of overall hits 68system.cpu.l2cache.overall_hits::total 1919013 # number of overall hits 69system.cpu.l2cache.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses 70system.cpu.l2cache.ReadReq_misses::cpu.data 271966 # number of ReadReq misses 71system.cpu.l2cache.ReadReq_misses::total 285255 # number of ReadReq misses 72system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 73system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses 74system.cpu.l2cache.ReadExReq_misses::cpu.data 116861 # number of ReadExReq misses 75system.cpu.l2cache.ReadExReq_misses::total 116861 # number of ReadExReq misses 76system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses 77system.cpu.l2cache.demand_misses::cpu.data 388827 # number of demand (read+write) misses 78system.cpu.l2cache.demand_misses::total 402116 # number of demand (read+write) misses 79system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses 80system.cpu.l2cache.overall_misses::cpu.data 388827 # number of overall misses 81system.cpu.l2cache.overall_misses::total 402116 # number of overall misses 82system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 691205000 # number of ReadReq miss cycles 83system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14147611000 # number of ReadReq miss cycles 84system.cpu.l2cache.ReadReq_miss_latency::total 14838816000 # number of ReadReq miss cycles 85system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles 86system.cpu.l2cache.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles 87system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6077413000 # number of ReadExReq miss cycles 88system.cpu.l2cache.ReadExReq_miss_latency::total 6077413000 # number of ReadExReq miss cycles 89system.cpu.l2cache.demand_miss_latency::cpu.inst 691205000 # number of demand (read+write) miss cycles 90system.cpu.l2cache.demand_miss_latency::cpu.data 20225024000 # number of demand (read+write) miss cycles 91system.cpu.l2cache.demand_miss_latency::total 20916229000 # number of demand (read+write) miss cycles 92system.cpu.l2cache.overall_miss_latency::cpu.inst 691205000 # number of overall miss cycles 93system.cpu.l2cache.overall_miss_latency::cpu.data 20225024000 # number of overall miss cycles 94system.cpu.l2cache.overall_miss_latency::total 20916229000 # number of overall miss cycles 95system.cpu.l2cache.ReadReq_accesses::cpu.inst 929752 # number of ReadReq accesses(hits+misses) 96system.cpu.l2cache.ReadReq_accesses::cpu.data 1086951 # number of ReadReq accesses(hits+misses) 97system.cpu.l2cache.ReadReq_accesses::total 2016703 # number of ReadReq accesses(hits+misses) 98system.cpu.l2cache.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses) 99system.cpu.l2cache.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses) 100system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 101system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 102system.cpu.l2cache.ReadExReq_accesses::cpu.data 304426 # number of ReadExReq accesses(hits+misses) 103system.cpu.l2cache.ReadExReq_accesses::total 304426 # number of ReadExReq accesses(hits+misses) 104system.cpu.l2cache.demand_accesses::cpu.inst 929752 # number of demand (read+write) accesses 105system.cpu.l2cache.demand_accesses::cpu.data 1391377 # number of demand (read+write) accesses 106system.cpu.l2cache.demand_accesses::total 2321129 # number of demand (read+write) accesses 107system.cpu.l2cache.overall_accesses::cpu.inst 929752 # number of overall (read+write) accesses 108system.cpu.l2cache.overall_accesses::cpu.data 1391377 # number of overall (read+write) accesses 109system.cpu.l2cache.overall_accesses::total 2321129 # number of overall (read+write) accesses 110system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014293 # miss rate for ReadReq accesses 111system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250210 # miss rate for ReadReq accesses 112system.cpu.l2cache.ReadReq_miss_rate::total 0.141446 # miss rate for ReadReq accesses 113system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 114system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses 115system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383873 # miss rate for ReadExReq accesses 116system.cpu.l2cache.ReadExReq_miss_rate::total 0.383873 # miss rate for ReadExReq accesses 117system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014293 # miss rate for demand accesses 118system.cpu.l2cache.demand_miss_rate::cpu.data 0.279455 # miss rate for demand accesses 119system.cpu.l2cache.demand_miss_rate::total 0.173242 # miss rate for demand accesses 120system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014293 # miss rate for overall accesses 121system.cpu.l2cache.overall_miss_rate::cpu.data 0.279455 # miss rate for overall accesses 122system.cpu.l2cache.overall_miss_rate::total 0.173242 # miss rate for overall accesses 123system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52013.319287 # average ReadReq miss latency 124system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52019.778208 # average ReadReq miss latency 125system.cpu.l2cache.ReadReq_avg_miss_latency::total 52019.477310 # average ReadReq miss latency 126system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19076.923077 # average UpgradeReq miss latency 127system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19076.923077 # average UpgradeReq miss latency 128system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52005.485149 # average ReadExReq miss latency 129system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52005.485149 # average ReadExReq miss latency 130system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency 131system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency 132system.cpu.l2cache.demand_avg_miss_latency::total 52015.410976 # average overall miss latency 133system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency 134system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency 135system.cpu.l2cache.overall_avg_miss_latency::total 52015.410976 # average overall miss latency 136system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 137system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 138system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 139system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 140system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 141system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 142system.cpu.l2cache.fast_writes 0 # number of fast writes performed 143system.cpu.l2cache.cache_copies 0 # number of cache copies performed 144system.cpu.l2cache.writebacks::writebacks 74180 # number of writebacks 145system.cpu.l2cache.writebacks::total 74180 # number of writebacks 146system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13289 # number of ReadReq MSHR misses 147system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271966 # number of ReadReq MSHR misses 148system.cpu.l2cache.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses 149system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 150system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 151system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116861 # number of ReadExReq MSHR misses 152system.cpu.l2cache.ReadExReq_mshr_misses::total 116861 # number of ReadExReq MSHR misses 153system.cpu.l2cache.demand_mshr_misses::cpu.inst 13289 # number of demand (read+write) MSHR misses 154system.cpu.l2cache.demand_mshr_misses::cpu.data 388827 # number of demand (read+write) MSHR misses 155system.cpu.l2cache.demand_mshr_misses::total 402116 # number of demand (read+write) MSHR misses 156system.cpu.l2cache.overall_mshr_misses::cpu.inst 13289 # number of overall MSHR misses 157system.cpu.l2cache.overall_mshr_misses::cpu.data 388827 # number of overall MSHR misses 158system.cpu.l2cache.overall_mshr_misses::total 402116 # number of overall MSHR misses 159system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531734000 # number of ReadReq MSHR miss cycles 160system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884019000 # number of ReadReq MSHR miss cycles 161system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11415753000 # number of ReadReq MSHR miss cycles 162system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles 163system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles 164system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675081000 # number of ReadExReq MSHR miss cycles 165system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675081000 # number of ReadExReq MSHR miss cycles 166system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531734000 # number of demand (read+write) MSHR miss cycles 167system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559100000 # number of demand (read+write) MSHR miss cycles 168system.cpu.l2cache.demand_mshr_miss_latency::total 16090834000 # number of demand (read+write) MSHR miss cycles 169system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531734000 # number of overall MSHR miss cycles 170system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559100000 # number of overall MSHR miss cycles 171system.cpu.l2cache.overall_mshr_miss_latency::total 16090834000 # number of overall MSHR miss cycles 172system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles 173system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles 174system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892958000 # number of WriteReq MSHR uncacheable cycles 175system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892958000 # number of WriteReq MSHR uncacheable cycles 176system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508000 # number of overall MSHR uncacheable cycles 177system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles 178system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses 179system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses 180system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses 181system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 182system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 183system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses 184system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses 185system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses 186system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses 187system.cpu.l2cache.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses 188system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses 189system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses 190system.cpu.l2cache.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses 191system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency 192system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency 193system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency 194system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency 195system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency 196system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency 197system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency 198system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency 199system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency 200system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency 201system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency 202system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency 203system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency 204system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 205system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 206system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 207system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 208system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 209system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 210system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 7host_inst_rate 1284205 # Simulator instruction rate (inst/s) 8host_op_rate 1284205 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43773036105 # Simulator tick rate (ticks/s) 10host_mem_usage 295308 # Number of bytes of host memory used 11host_seconds 43.74 # Real time elapsed on the host 12sim_insts 56164879 # Number of instructions simulated 13sim_ops 56164879 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24860096 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28362752 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7404800 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7404800 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388439 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 443168 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115700 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115700 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 444291 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12985700 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1385325 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14815316 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 444291 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 444291 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3867906 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3867906 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3867906 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 444291 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12985700 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1385325 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18683222 # Total bandwidth to/from this memory (bytes/s) |
| 211system.iocache.replacements 41685 # number of replacements | 41system.iocache.replacements 41685 # number of replacements |
| 212system.iocache.tagsinuse 1.347775 # Cycle average of tags in use | 42system.iocache.tagsinuse 1.347664 # Cycle average of tags in use |
| 213system.iocache.total_refs 0 # Total number of references to valid blocks. 214system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 215system.iocache.avg_refs 0 # Average number of references to valid blocks. | 43system.iocache.total_refs 0 # Total number of references to valid blocks. 44system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 45system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 216system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. 217system.iocache.occ_blocks::tsunami.ide 1.347775 # Average occupied blocks per requestor 218system.iocache.occ_percent::tsunami.ide 0.084236 # Average percentage of cache occupancy 219system.iocache.occ_percent::total 0.084236 # Average percentage of cache occupancy | 46system.iocache.warmup_cycle 1748614160000 # Cycle when the warmup percentage was hit. 47system.iocache.occ_blocks::tsunami.ide 1.347664 # Average occupied blocks per requestor 48system.iocache.occ_percent::tsunami.ide 0.084229 # Average percentage of cache occupancy 49system.iocache.occ_percent::total 0.084229 # Average percentage of cache occupancy |
| 220system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 221system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 222system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 223system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 224system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 225system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 226system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 227system.iocache.overall_misses::total 41725 # number of overall misses 228system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 229system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles | 50system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 51system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 52system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 53system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 54system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 55system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 56system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 57system.iocache.overall_misses::total 41725 # number of overall misses 58system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 59system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles |
| 230system.iocache.WriteReq_miss_latency::tsunami.ide 11448538806 # number of WriteReq miss cycles 231system.iocache.WriteReq_miss_latency::total 11448538806 # number of WriteReq miss cycles 232system.iocache.demand_miss_latency::tsunami.ide 11469211804 # number of demand (read+write) miss cycles 233system.iocache.demand_miss_latency::total 11469211804 # number of demand (read+write) miss cycles 234system.iocache.overall_miss_latency::tsunami.ide 11469211804 # number of overall miss cycles 235system.iocache.overall_miss_latency::total 11469211804 # number of overall miss cycles | 60system.iocache.WriteReq_miss_latency::tsunami.ide 11444054806 # number of WriteReq miss cycles 61system.iocache.WriteReq_miss_latency::total 11444054806 # number of WriteReq miss cycles 62system.iocache.demand_miss_latency::tsunami.ide 11464727804 # number of demand (read+write) miss cycles 63system.iocache.demand_miss_latency::total 11464727804 # number of demand (read+write) miss cycles 64system.iocache.overall_miss_latency::tsunami.ide 11464727804 # number of overall miss cycles 65system.iocache.overall_miss_latency::total 11464727804 # number of overall miss cycles |
| 236system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 237system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 238system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 239system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 240system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 241system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 242system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 243system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 244system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 245system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 246system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 247system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 248system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 249system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 250system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 251system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 252system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 253system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency | 66system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 67system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 68system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 69system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 70system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 71system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 72system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 73system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 74system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 75system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 76system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 77system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 78system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 79system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 80system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 81system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 82system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 83system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency |
| 254system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275523.171111 # average WriteReq miss latency 255system.iocache.WriteReq_avg_miss_latency::total 275523.171111 # average WriteReq miss latency 256system.iocache.demand_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency 257system.iocache.demand_avg_miss_latency::total 274876.256537 # average overall miss latency 258system.iocache.overall_avg_miss_latency::tsunami.ide 274876.256537 # average overall miss latency 259system.iocache.overall_avg_miss_latency::total 274876.256537 # average overall miss latency 260system.iocache.blocked_cycles::no_mshrs 199147000 # number of cycles access was blocked | 84system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275415.258134 # average WriteReq miss latency 85system.iocache.WriteReq_avg_miss_latency::total 275415.258134 # average WriteReq miss latency 86system.iocache.demand_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency 87system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency 88system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency 89system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency 90system.iocache.blocked_cycles::no_mshrs 199052000 # number of cycles access was blocked |
| 261system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 91system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 262system.iocache.blocked::no_mshrs 24626 # number of cycles access was blocked | 92system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked |
| 263system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 93system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 264system.iocache.avg_blocked_cycles::no_mshrs 8086.859417 # average number of cycles each access was blocked | 94system.iocache.avg_blocked_cycles::no_mshrs 8086.942391 # average number of cycles each access was blocked |
| 265system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 266system.iocache.fast_writes 0 # number of fast writes performed 267system.iocache.cache_copies 0 # number of cache copies performed 268system.iocache.writebacks::writebacks 41512 # number of writebacks 269system.iocache.writebacks::total 41512 # number of writebacks 270system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 271system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 272system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 273system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 274system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 275system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 276system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 277system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 278system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 279system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles | 95system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 96system.iocache.fast_writes 0 # number of fast writes performed 97system.iocache.cache_copies 0 # number of cache copies performed 98system.iocache.writebacks::writebacks 41512 # number of writebacks 99system.iocache.writebacks::total 41512 # number of writebacks 100system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 101system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 102system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 103system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 104system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 105system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 106system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 107system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 108system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 109system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles |
| 280system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287684000 # number of WriteReq MSHR miss cycles 281system.iocache.WriteReq_mshr_miss_latency::total 9287684000 # number of WriteReq MSHR miss cycles 282system.iocache.demand_mshr_miss_latency::tsunami.ide 9299360000 # number of demand (read+write) MSHR miss cycles 283system.iocache.demand_mshr_miss_latency::total 9299360000 # number of demand (read+write) MSHR miss cycles 284system.iocache.overall_mshr_miss_latency::tsunami.ide 9299360000 # number of overall MSHR miss cycles 285system.iocache.overall_mshr_miss_latency::total 9299360000 # number of overall MSHR miss cycles | 110system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283200000 # number of WriteReq MSHR miss cycles 111system.iocache.WriteReq_mshr_miss_latency::total 9283200000 # number of WriteReq MSHR miss cycles 112system.iocache.demand_mshr_miss_latency::tsunami.ide 9294876000 # number of demand (read+write) MSHR miss cycles 113system.iocache.demand_mshr_miss_latency::total 9294876000 # number of demand (read+write) MSHR miss cycles 114system.iocache.overall_mshr_miss_latency::tsunami.ide 9294876000 # number of overall MSHR miss cycles 115system.iocache.overall_mshr_miss_latency::total 9294876000 # number of overall MSHR miss cycles |
| 286system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 287system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 288system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 289system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 290system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 291system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 292system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 293system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 294system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 295system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency | 116system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 117system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 118system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 119system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 120system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 121system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 122system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 123system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 124system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 125system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency |
| 296system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223519.541779 # average WriteReq mshr miss latency 297system.iocache.WriteReq_avg_mshr_miss_latency::total 223519.541779 # average WriteReq mshr miss latency 298system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency 299system.iocache.demand_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency 300system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222872.618334 # average overall mshr miss latency 301system.iocache.overall_avg_mshr_miss_latency::total 222872.618334 # average overall mshr miss latency | 126system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223411.628802 # average WriteReq mshr miss latency 127system.iocache.WriteReq_avg_mshr_miss_latency::total 223411.628802 # average WriteReq mshr miss latency 128system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency 129system.iocache.demand_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency 130system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency 131system.iocache.overall_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency |
| 302system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 303system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 304system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 305system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 306system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 307system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 308system.disk0.dma_write_txs 395 # Number of DMA write transactions. 309system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 310system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 311system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 312system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 313system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 314system.disk2.dma_write_txs 1 # Number of DMA write transactions. 315system.cpu.dtb.fetch_hits 0 # ITB hits 316system.cpu.dtb.fetch_misses 0 # ITB misses 317system.cpu.dtb.fetch_acv 0 # ITB acv 318system.cpu.dtb.fetch_accesses 0 # ITB accesses | 132system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 133system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 134system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 135system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 136system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 137system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 138system.disk0.dma_write_txs 395 # Number of DMA write transactions. 139system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 140system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 141system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 142system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 143system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 144system.disk2.dma_write_txs 1 # Number of DMA write transactions. 145system.cpu.dtb.fetch_hits 0 # ITB hits 146system.cpu.dtb.fetch_misses 0 # ITB misses 147system.cpu.dtb.fetch_acv 0 # ITB acv 148system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 319system.cpu.dtb.read_hits 9066995 # DTB read hits | 149system.cpu.dtb.read_hits 9062432 # DTB read hits |
| 320system.cpu.dtb.read_misses 10329 # DTB read misses 321system.cpu.dtb.read_acv 210 # DTB read access violations 322system.cpu.dtb.read_accesses 728856 # DTB read accesses | 150system.cpu.dtb.read_misses 10329 # DTB read misses 151system.cpu.dtb.read_acv 210 # DTB read access violations 152system.cpu.dtb.read_accesses 728856 # DTB read accesses |
| 323system.cpu.dtb.write_hits 6357563 # DTB write hits | 153system.cpu.dtb.write_hits 6354530 # DTB write hits |
| 324system.cpu.dtb.write_misses 1142 # DTB write misses 325system.cpu.dtb.write_acv 157 # DTB write access violations 326system.cpu.dtb.write_accesses 291931 # DTB write accesses | 154system.cpu.dtb.write_misses 1142 # DTB write misses 155system.cpu.dtb.write_acv 157 # DTB write access violations 156system.cpu.dtb.write_accesses 291931 # DTB write accesses |
| 327system.cpu.dtb.data_hits 15424558 # DTB hits | 157system.cpu.dtb.data_hits 15416962 # DTB hits |
| 328system.cpu.dtb.data_misses 11471 # DTB misses 329system.cpu.dtb.data_acv 367 # DTB access violations 330system.cpu.dtb.data_accesses 1020787 # DTB accesses | 158system.cpu.dtb.data_misses 11471 # DTB misses 159system.cpu.dtb.data_acv 367 # DTB access violations 160system.cpu.dtb.data_accesses 1020787 # DTB accesses |
| 331system.cpu.itb.fetch_hits 4975749 # ITB hits | 161system.cpu.itb.fetch_hits 4974475 # ITB hits |
| 332system.cpu.itb.fetch_misses 5006 # ITB misses 333system.cpu.itb.fetch_acv 184 # ITB acv | 162system.cpu.itb.fetch_misses 5006 # ITB misses 163system.cpu.itb.fetch_acv 184 # ITB acv |
| 334system.cpu.itb.fetch_accesses 4980755 # ITB accesses | 164system.cpu.itb.fetch_accesses 4979481 # ITB accesses |
| 335system.cpu.itb.read_hits 0 # DTB read hits 336system.cpu.itb.read_misses 0 # DTB read misses 337system.cpu.itb.read_acv 0 # DTB read access violations 338system.cpu.itb.read_accesses 0 # DTB read accesses 339system.cpu.itb.write_hits 0 # DTB write hits 340system.cpu.itb.write_misses 0 # DTB write misses 341system.cpu.itb.write_acv 0 # DTB write access violations 342system.cpu.itb.write_accesses 0 # DTB write accesses 343system.cpu.itb.data_hits 0 # DTB hits 344system.cpu.itb.data_misses 0 # DTB misses 345system.cpu.itb.data_acv 0 # DTB access violations 346system.cpu.itb.data_accesses 0 # DTB accesses | 165system.cpu.itb.read_hits 0 # DTB read hits 166system.cpu.itb.read_misses 0 # DTB read misses 167system.cpu.itb.read_acv 0 # DTB read access violations 168system.cpu.itb.read_accesses 0 # DTB read accesses 169system.cpu.itb.write_hits 0 # DTB write hits 170system.cpu.itb.write_misses 0 # DTB write misses 171system.cpu.itb.write_acv 0 # DTB write access violations 172system.cpu.itb.write_accesses 0 # DTB write accesses 173system.cpu.itb.data_hits 0 # DTB hits 174system.cpu.itb.data_misses 0 # DTB misses 175system.cpu.itb.data_acv 0 # DTB access violations 176system.cpu.itb.data_accesses 0 # DTB accesses |
| 347system.cpu.numCycles 3841790588 # number of cpu cycles simulated | 177system.cpu.numCycles 3828841890 # number of cpu cycles simulated |
| 348system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 349system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 178system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 179system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 350system.cpu.committedInsts 56195754 # Number of instructions committed 351system.cpu.committedOps 56195754 # Number of ops (including micro ops) committed 352system.cpu.num_int_alu_accesses 52066962 # Number of integer alu accesses | 180system.cpu.committedInsts 56164879 # Number of instructions committed 181system.cpu.committedOps 56164879 # Number of ops (including micro ops) committed 182system.cpu.num_int_alu_accesses 52037464 # Number of integer alu accesses |
| 353system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses | 183system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses |
| 354system.cpu.num_func_calls 1483816 # number of times a function call or return occured 355system.cpu.num_conditional_control_insts 6469707 # number of instructions that are conditional controls 356system.cpu.num_int_insts 52066962 # number of integer instructions | 184system.cpu.num_func_calls 1482804 # number of times a function call or return occured 185system.cpu.num_conditional_control_insts 6466141 # number of instructions that are conditional controls 186system.cpu.num_int_insts 52037464 # number of integer instructions |
| 357system.cpu.num_fp_insts 324393 # number of float instructions | 187system.cpu.num_fp_insts 324393 # number of float instructions |
| 358system.cpu.num_int_register_reads 71340235 # number of times the integer registers were read 359system.cpu.num_int_register_writes 38530699 # number of times the integer registers were written | 188system.cpu.num_int_register_reads 71294843 # number of times the integer registers were read 189system.cpu.num_int_register_writes 38508157 # number of times the integer registers were written |
| 360system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read 361system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written | 190system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read 191system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written |
| 362system.cpu.num_mem_refs 15477180 # number of memory refs 363system.cpu.num_load_insts 9103852 # Number of load instructions 364system.cpu.num_store_insts 6373328 # Number of store instructions 365system.cpu.num_idle_cycles 3586858626.998133 # Number of idle cycles 366system.cpu.num_busy_cycles 254931961.001867 # Number of busy cycles 367system.cpu.not_idle_fraction 0.066358 # Percentage of non-idle cycles 368system.cpu.idle_fraction 0.933642 # Percentage of idle cycles | 192system.cpu.num_mem_refs 15469580 # number of memory refs 193system.cpu.num_load_insts 9099291 # Number of load instructions 194system.cpu.num_store_insts 6370289 # Number of store instructions 195system.cpu.num_idle_cycles 3589214946.998125 # Number of idle cycles 196system.cpu.num_busy_cycles 239626943.001875 # Number of busy cycles 197system.cpu.not_idle_fraction 0.062585 # Percentage of non-idle cycles 198system.cpu.idle_fraction 0.937415 # Percentage of idle cycles |
| 369system.cpu.kern.inst.arm 0 # number of arm instructions executed | 199system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 370system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed 371system.cpu.kern.inst.hwrei 212106 # number of hwrei instructions executed 372system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl 373system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl 374system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl 375system.cpu.kern.ipl_count::31 106288 57.99% 100.00% # number of times we switched to this ipl 376system.cpu.kern.ipl_count::total 183284 # number of times we switched to this ipl 377system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl 378system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 379system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl 380system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl 381system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl 382system.cpu.kern.ipl_ticks::0 1860148981000 96.84% 96.84% # number of cycles we spent at this ipl 383system.cpu.kern.ipl_ticks::21 104328000 0.01% 96.84% # number of cycles we spent at this ipl 384system.cpu.kern.ipl_ticks::22 779009000 0.04% 96.88% # number of cycles we spent at this ipl 385system.cpu.kern.ipl_ticks::31 59862143000 3.12% 100.00% # number of cycles we spent at this ipl 386system.cpu.kern.ipl_ticks::total 1920894461000 # number of cycles we spent at this ipl 387system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl | 200system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 201system.cpu.kern.inst.hwrei 211993 # number of hwrei instructions executed 202system.cpu.kern.ipl_count::0 74900 40.89% 40.89% # number of times we switched to this ipl 203system.cpu.kern.ipl_count::21 133 0.07% 40.96% # number of times we switched to this ipl 204system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl 205system.cpu.kern.ipl_count::31 106213 57.98% 100.00% # number of times we switched to this ipl 206system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl 207system.cpu.kern.ipl_good::0 73533 49.31% 49.31% # number of times we switched to this ipl from a different ipl 208system.cpu.kern.ipl_good::21 133 0.09% 49.40% # number of times we switched to this ipl from a different ipl 209system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl 210system.cpu.kern.ipl_good::31 73534 49.31% 100.00% # number of times we switched to this ipl from a different ipl 211system.cpu.kern.ipl_good::total 149130 # number of times we switched to this ipl from a different ipl 212system.cpu.kern.ipl_ticks::0 1856400078000 96.97% 96.97% # number of cycles we spent at this ipl 213system.cpu.kern.ipl_ticks::21 92059500 0.00% 96.97% # number of cycles we spent at this ipl 214system.cpu.kern.ipl_ticks::22 736279500 0.04% 97.01% # number of cycles we spent at this ipl 215system.cpu.kern.ipl_ticks::31 57191794000 2.99% 100.00% # number of cycles we spent at this ipl 216system.cpu.kern.ipl_ticks::total 1914420211000 # number of cycles we spent at this ipl 217system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl |
| 388system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 389system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 218system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 219system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 390system.cpu.kern.ipl_used::31 0.692101 # fraction of swpipl calls that actually changed the ipl 391system.cpu.kern.ipl_used::total 0.813988 # fraction of swpipl calls that actually changed the ipl | 220system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl 221system.cpu.kern.ipl_used::total 0.814135 # fraction of swpipl calls that actually changed the ipl |
| 392system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 393system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 394system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 395system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 396system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 397system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 398system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 399system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 422system.cpu.kern.syscall::total 326 # number of syscalls executed 423system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 424system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 425system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 426system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 427system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed 428system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 429system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 222system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 223system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 224system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 225system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 226system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 227system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 228system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 229system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 252system.cpu.kern.syscall::total 326 # number of syscalls executed 253system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 254system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 255system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 256system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 257system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed 258system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 259system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 430system.cpu.kern.callpal::swpipl 176055 91.22% 93.41% # number of callpals executed 431system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed | 260system.cpu.kern.callpal::swpipl 175957 91.22% 93.41% # number of callpals executed 261system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed |
| 432system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 433system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed | 262system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 263system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed |
| 434system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed | 264system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed |
| 435system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed | 265system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed |
| 436system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed | 266system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed |
| 437system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 438system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 267system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 268system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 439system.cpu.kern.callpal::total 193009 # number of callpals executed 440system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches 441system.cpu.kern.mode_switch::user 1739 # number of protection mode switches | 269system.cpu.kern.callpal::total 192901 # number of callpals executed 270system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches 271system.cpu.kern.mode_switch::user 1740 # number of protection mode switches |
| 442system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches | 272system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches |
| 443system.cpu.kern.mode_good::kernel 1909 444system.cpu.kern.mode_good::user 1739 | 273system.cpu.kern.mode_good::kernel 1910 274system.cpu.kern.mode_good::user 1740 |
| 445system.cpu.kern.mode_good::idle 170 | 275system.cpu.kern.mode_good::idle 170 |
| 446system.cpu.kern.mode_switch_good::kernel 0.323231 # fraction of useful protection mode switches | 276system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches |
| 447system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 448system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches | 277system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 278system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches |
| 449system.cpu.kern.mode_switch_good::total 0.391911 # fraction of useful protection mode switches 450system.cpu.kern.mode_ticks::kernel 46683787000 2.43% 2.43% # number of ticks spent at the given mode 451system.cpu.kern.mode_ticks::user 5260006000 0.27% 2.70% # number of ticks spent at the given mode 452system.cpu.kern.mode_ticks::idle 1868950661000 97.30% 100.00% # number of ticks spent at the given mode | 279system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches 280system.cpu.kern.mode_ticks::kernel 45169028500 2.36% 2.36% # number of ticks spent at the given mode 281system.cpu.kern.mode_ticks::user 5015931500 0.26% 2.62% # number of ticks spent at the given mode 282system.cpu.kern.mode_ticks::idle 1864235249000 97.38% 100.00% # number of ticks spent at the given mode |
| 453system.cpu.kern.swap_context 4177 # number of times the context was actually changed 454system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 455system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 456system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 457system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 458system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 459system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 460system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 477system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 478system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 479system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 480system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 481system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 482system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 483system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 484system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 283system.cpu.kern.swap_context 4177 # number of times the context was actually changed 284system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 285system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 286system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 287system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 288system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 289system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 290system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 307system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 308system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 309system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 310system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 311system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 312system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 313system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 314system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 485system.cpu.icache.replacements 929101 # number of replacements 486system.cpu.icache.tagsinuse 508.704776 # Cycle average of tags in use 487system.cpu.icache.total_refs 55277821 # Total number of references to valid blocks. 488system.cpu.icache.sampled_refs 929612 # Sample count of references to valid blocks. 489system.cpu.icache.avg_refs 59.463326 # Average number of references to valid blocks. 490system.cpu.icache.warmup_cycle 36213864000 # Cycle when the warmup percentage was hit. 491system.cpu.icache.occ_blocks::cpu.inst 508.704776 # Average occupied blocks per requestor 492system.cpu.icache.occ_percent::cpu.inst 0.993564 # Average percentage of cache occupancy 493system.cpu.icache.occ_percent::total 0.993564 # Average percentage of cache occupancy 494system.cpu.icache.ReadReq_hits::cpu.inst 55277821 # number of ReadReq hits 495system.cpu.icache.ReadReq_hits::total 55277821 # number of ReadReq hits 496system.cpu.icache.demand_hits::cpu.inst 55277821 # number of demand (read+write) hits 497system.cpu.icache.demand_hits::total 55277821 # number of demand (read+write) hits 498system.cpu.icache.overall_hits::cpu.inst 55277821 # number of overall hits 499system.cpu.icache.overall_hits::total 55277821 # number of overall hits 500system.cpu.icache.ReadReq_misses::cpu.inst 929772 # number of ReadReq misses 501system.cpu.icache.ReadReq_misses::total 929772 # number of ReadReq misses 502system.cpu.icache.demand_misses::cpu.inst 929772 # number of demand (read+write) misses 503system.cpu.icache.demand_misses::total 929772 # number of demand (read+write) misses 504system.cpu.icache.overall_misses::cpu.inst 929772 # number of overall misses 505system.cpu.icache.overall_misses::total 929772 # number of overall misses 506system.cpu.icache.ReadReq_miss_latency::cpu.inst 13856924500 # number of ReadReq miss cycles 507system.cpu.icache.ReadReq_miss_latency::total 13856924500 # number of ReadReq miss cycles 508system.cpu.icache.demand_miss_latency::cpu.inst 13856924500 # number of demand (read+write) miss cycles 509system.cpu.icache.demand_miss_latency::total 13856924500 # number of demand (read+write) miss cycles 510system.cpu.icache.overall_miss_latency::cpu.inst 13856924500 # number of overall miss cycles 511system.cpu.icache.overall_miss_latency::total 13856924500 # number of overall miss cycles 512system.cpu.icache.ReadReq_accesses::cpu.inst 56207593 # number of ReadReq accesses(hits+misses) 513system.cpu.icache.ReadReq_accesses::total 56207593 # number of ReadReq accesses(hits+misses) 514system.cpu.icache.demand_accesses::cpu.inst 56207593 # number of demand (read+write) accesses 515system.cpu.icache.demand_accesses::total 56207593 # number of demand (read+write) accesses 516system.cpu.icache.overall_accesses::cpu.inst 56207593 # number of overall (read+write) accesses 517system.cpu.icache.overall_accesses::total 56207593 # number of overall (read+write) accesses 518system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses 519system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses 520system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses 521system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses 522system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses 523system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses 524system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.572596 # average ReadReq miss latency 525system.cpu.icache.ReadReq_avg_miss_latency::total 14903.572596 # average ReadReq miss latency 526system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.572596 # average overall miss latency 527system.cpu.icache.demand_avg_miss_latency::total 14903.572596 # average overall miss latency 528system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.572596 # average overall miss latency 529system.cpu.icache.overall_avg_miss_latency::total 14903.572596 # average overall miss latency | 315system.cpu.icache.replacements 927876 # number of replacements 316system.cpu.icache.tagsinuse 508.762321 # Cycle average of tags in use 317system.cpu.icache.total_refs 55248171 # Total number of references to valid blocks. 318system.cpu.icache.sampled_refs 928387 # Sample count of references to valid blocks. 319system.cpu.icache.avg_refs 59.509850 # Average number of references to valid blocks. 320system.cpu.icache.warmup_cycle 35489468000 # Cycle when the warmup percentage was hit. 321system.cpu.icache.occ_blocks::cpu.inst 508.762321 # Average occupied blocks per requestor 322system.cpu.icache.occ_percent::cpu.inst 0.993676 # Average percentage of cache occupancy 323system.cpu.icache.occ_percent::total 0.993676 # Average percentage of cache occupancy 324system.cpu.icache.ReadReq_hits::cpu.inst 55248171 # number of ReadReq hits 325system.cpu.icache.ReadReq_hits::total 55248171 # number of ReadReq hits 326system.cpu.icache.demand_hits::cpu.inst 55248171 # number of demand (read+write) hits 327system.cpu.icache.demand_hits::total 55248171 # number of demand (read+write) hits 328system.cpu.icache.overall_hits::cpu.inst 55248171 # number of overall hits 329system.cpu.icache.overall_hits::total 55248171 # number of overall hits 330system.cpu.icache.ReadReq_misses::cpu.inst 928547 # number of ReadReq misses 331system.cpu.icache.ReadReq_misses::total 928547 # number of ReadReq misses 332system.cpu.icache.demand_misses::cpu.inst 928547 # number of demand (read+write) misses 333system.cpu.icache.demand_misses::total 928547 # number of demand (read+write) misses 334system.cpu.icache.overall_misses::cpu.inst 928547 # number of overall misses 335system.cpu.icache.overall_misses::total 928547 # number of overall misses 336system.cpu.icache.ReadReq_miss_latency::cpu.inst 12629515000 # number of ReadReq miss cycles 337system.cpu.icache.ReadReq_miss_latency::total 12629515000 # number of ReadReq miss cycles 338system.cpu.icache.demand_miss_latency::cpu.inst 12629515000 # number of demand (read+write) miss cycles 339system.cpu.icache.demand_miss_latency::total 12629515000 # number of demand (read+write) miss cycles 340system.cpu.icache.overall_miss_latency::cpu.inst 12629515000 # number of overall miss cycles 341system.cpu.icache.overall_miss_latency::total 12629515000 # number of overall miss cycles 342system.cpu.icache.ReadReq_accesses::cpu.inst 56176718 # number of ReadReq accesses(hits+misses) 343system.cpu.icache.ReadReq_accesses::total 56176718 # number of ReadReq accesses(hits+misses) 344system.cpu.icache.demand_accesses::cpu.inst 56176718 # number of demand (read+write) accesses 345system.cpu.icache.demand_accesses::total 56176718 # number of demand (read+write) accesses 346system.cpu.icache.overall_accesses::cpu.inst 56176718 # number of overall (read+write) accesses 347system.cpu.icache.overall_accesses::total 56176718 # number of overall (read+write) accesses 348system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016529 # miss rate for ReadReq accesses 349system.cpu.icache.ReadReq_miss_rate::total 0.016529 # miss rate for ReadReq accesses 350system.cpu.icache.demand_miss_rate::cpu.inst 0.016529 # miss rate for demand accesses 351system.cpu.icache.demand_miss_rate::total 0.016529 # miss rate for demand accesses 352system.cpu.icache.overall_miss_rate::cpu.inst 0.016529 # miss rate for overall accesses 353system.cpu.icache.overall_miss_rate::total 0.016529 # miss rate for overall accesses 354system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13601.373975 # average ReadReq miss latency 355system.cpu.icache.ReadReq_avg_miss_latency::total 13601.373975 # average ReadReq miss latency 356system.cpu.icache.demand_avg_miss_latency::cpu.inst 13601.373975 # average overall miss latency 357system.cpu.icache.demand_avg_miss_latency::total 13601.373975 # average overall miss latency 358system.cpu.icache.overall_avg_miss_latency::cpu.inst 13601.373975 # average overall miss latency 359system.cpu.icache.overall_avg_miss_latency::total 13601.373975 # average overall miss latency |
| 530system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 531system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 532system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 533system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 534system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 535system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 536system.cpu.icache.fast_writes 0 # number of fast writes performed 537system.cpu.icache.cache_copies 0 # number of cache copies performed | 360system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 361system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 362system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 363system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 364system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 365system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 366system.cpu.icache.fast_writes 0 # number of fast writes performed 367system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 538system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929772 # number of ReadReq MSHR misses 539system.cpu.icache.ReadReq_mshr_misses::total 929772 # number of ReadReq MSHR misses 540system.cpu.icache.demand_mshr_misses::cpu.inst 929772 # number of demand (read+write) MSHR misses 541system.cpu.icache.demand_mshr_misses::total 929772 # number of demand (read+write) MSHR misses 542system.cpu.icache.overall_mshr_misses::cpu.inst 929772 # number of overall MSHR misses 543system.cpu.icache.overall_mshr_misses::total 929772 # number of overall MSHR misses 544system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11066921000 # number of ReadReq MSHR miss cycles 545system.cpu.icache.ReadReq_mshr_miss_latency::total 11066921000 # number of ReadReq MSHR miss cycles 546system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11066921000 # number of demand (read+write) MSHR miss cycles 547system.cpu.icache.demand_mshr_miss_latency::total 11066921000 # number of demand (read+write) MSHR miss cycles 548system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11066921000 # number of overall MSHR miss cycles 549system.cpu.icache.overall_mshr_miss_latency::total 11066921000 # number of overall MSHR miss cycles 550system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses 552system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses 553system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses 554system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses 555system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses 556system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11902.833168 # average ReadReq mshr miss latency 557system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11902.833168 # average ReadReq mshr miss latency 558system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11902.833168 # average overall mshr miss latency 559system.cpu.icache.demand_avg_mshr_miss_latency::total 11902.833168 # average overall mshr miss latency 560system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11902.833168 # average overall mshr miss latency 561system.cpu.icache.overall_avg_mshr_miss_latency::total 11902.833168 # average overall mshr miss latency | 368system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928547 # number of ReadReq MSHR misses 369system.cpu.icache.ReadReq_mshr_misses::total 928547 # number of ReadReq MSHR misses 370system.cpu.icache.demand_mshr_misses::cpu.inst 928547 # number of demand (read+write) MSHR misses 371system.cpu.icache.demand_mshr_misses::total 928547 # number of demand (read+write) MSHR misses 372system.cpu.icache.overall_mshr_misses::cpu.inst 928547 # number of overall MSHR misses 373system.cpu.icache.overall_mshr_misses::total 928547 # number of overall MSHR misses 374system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10772421000 # number of ReadReq MSHR miss cycles 375system.cpu.icache.ReadReq_mshr_miss_latency::total 10772421000 # number of ReadReq MSHR miss cycles 376system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10772421000 # number of demand (read+write) MSHR miss cycles 377system.cpu.icache.demand_mshr_miss_latency::total 10772421000 # number of demand (read+write) MSHR miss cycles 378system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10772421000 # number of overall MSHR miss cycles 379system.cpu.icache.overall_mshr_miss_latency::total 10772421000 # number of overall MSHR miss cycles 380system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016529 # mshr miss rate for ReadReq accesses 381system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016529 # mshr miss rate for ReadReq accesses 382system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016529 # mshr miss rate for demand accesses 383system.cpu.icache.demand_mshr_miss_rate::total 0.016529 # mshr miss rate for demand accesses 384system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016529 # mshr miss rate for overall accesses 385system.cpu.icache.overall_mshr_miss_rate::total 0.016529 # mshr miss rate for overall accesses 386system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11601.373975 # average ReadReq mshr miss latency 387system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11601.373975 # average ReadReq mshr miss latency 388system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11601.373975 # average overall mshr miss latency 389system.cpu.icache.demand_avg_mshr_miss_latency::total 11601.373975 # average overall mshr miss latency 390system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11601.373975 # average overall mshr miss latency 391system.cpu.icache.overall_avg_mshr_miss_latency::total 11601.373975 # average overall mshr miss latency |
| 562system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 392system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 563system.cpu.dcache.replacements 1390864 # number of replacements 564system.cpu.dcache.tagsinuse 511.979749 # Cycle average of tags in use 565system.cpu.dcache.total_refs 14052220 # Total number of references to valid blocks. 566system.cpu.dcache.sampled_refs 1391376 # Sample count of references to valid blocks. 567system.cpu.dcache.avg_refs 10.099513 # Average number of references to valid blocks. 568system.cpu.dcache.warmup_cycle 101905000 # Cycle when the warmup percentage was hit. 569system.cpu.dcache.occ_blocks::cpu.data 511.979749 # Average occupied blocks per requestor 570system.cpu.dcache.occ_percent::cpu.data 0.999960 # Average percentage of cache occupancy 571system.cpu.dcache.occ_percent::total 0.999960 # Average percentage of cache occupancy 572system.cpu.dcache.ReadReq_hits::cpu.data 7816402 # number of ReadReq hits 573system.cpu.dcache.ReadReq_hits::total 7816402 # number of ReadReq hits 574system.cpu.dcache.WriteReq_hits::cpu.data 5853491 # number of WriteReq hits 575system.cpu.dcache.WriteReq_hits::total 5853491 # number of WriteReq hits 576system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits 577system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits 578system.cpu.dcache.StoreCondReq_hits::cpu.data 199280 # number of StoreCondReq hits 579system.cpu.dcache.StoreCondReq_hits::total 199280 # number of StoreCondReq hits 580system.cpu.dcache.demand_hits::cpu.data 13669893 # number of demand (read+write) hits 581system.cpu.dcache.demand_hits::total 13669893 # number of demand (read+write) hits 582system.cpu.dcache.overall_hits::cpu.data 13669893 # number of overall hits 583system.cpu.dcache.overall_hits::total 13669893 # number of overall hits 584system.cpu.dcache.ReadReq_misses::cpu.data 1069678 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 1069678 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.data 304443 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 304443 # number of WriteReq misses 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 17273 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 17273 # number of LoadLockedReq misses 590system.cpu.dcache.demand_misses::cpu.data 1374121 # number of demand (read+write) misses 591system.cpu.dcache.demand_misses::total 1374121 # number of demand (read+write) misses 592system.cpu.dcache.overall_misses::cpu.data 1374121 # number of overall misses 593system.cpu.dcache.overall_misses::total 1374121 # number of overall misses 594system.cpu.dcache.ReadReq_miss_latency::cpu.data 26660570000 # number of ReadReq miss cycles 595system.cpu.dcache.ReadReq_miss_latency::total 26660570000 # number of ReadReq miss cycles 596system.cpu.dcache.WriteReq_miss_latency::cpu.data 9239957000 # number of WriteReq miss cycles 597system.cpu.dcache.WriteReq_miss_latency::total 9239957000 # number of WriteReq miss cycles 598system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247721000 # number of LoadLockedReq miss cycles 599system.cpu.dcache.LoadLockedReq_miss_latency::total 247721000 # number of LoadLockedReq miss cycles 600system.cpu.dcache.demand_miss_latency::cpu.data 35900527000 # number of demand (read+write) miss cycles 601system.cpu.dcache.demand_miss_latency::total 35900527000 # number of demand (read+write) miss cycles 602system.cpu.dcache.overall_miss_latency::cpu.data 35900527000 # number of overall miss cycles 603system.cpu.dcache.overall_miss_latency::total 35900527000 # number of overall miss cycles 604system.cpu.dcache.ReadReq_accesses::cpu.data 8886080 # number of ReadReq accesses(hits+misses) 605system.cpu.dcache.ReadReq_accesses::total 8886080 # number of ReadReq accesses(hits+misses) 606system.cpu.dcache.WriteReq_accesses::cpu.data 6157934 # number of WriteReq accesses(hits+misses) 607system.cpu.dcache.WriteReq_accesses::total 6157934 # number of WriteReq accesses(hits+misses) 608system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 609system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 610system.cpu.dcache.StoreCondReq_accesses::cpu.data 199280 # number of StoreCondReq accesses(hits+misses) 611system.cpu.dcache.StoreCondReq_accesses::total 199280 # number of StoreCondReq accesses(hits+misses) 612system.cpu.dcache.demand_accesses::cpu.data 15044014 # number of demand (read+write) accesses 613system.cpu.dcache.demand_accesses::total 15044014 # number of demand (read+write) accesses 614system.cpu.dcache.overall_accesses::cpu.data 15044014 # number of overall (read+write) accesses 615system.cpu.dcache.overall_accesses::total 15044014 # number of overall (read+write) accesses 616system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120377 # miss rate for ReadReq accesses 617system.cpu.dcache.ReadReq_miss_rate::total 0.120377 # miss rate for ReadReq accesses 618system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049439 # miss rate for WriteReq accesses 619system.cpu.dcache.WriteReq_miss_rate::total 0.049439 # miss rate for WriteReq accesses 620system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086234 # miss rate for LoadLockedReq accesses 621system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086234 # miss rate for LoadLockedReq accesses 622system.cpu.dcache.demand_miss_rate::cpu.data 0.091340 # miss rate for demand accesses 623system.cpu.dcache.demand_miss_rate::total 0.091340 # miss rate for demand accesses 624system.cpu.dcache.overall_miss_rate::cpu.data 0.091340 # miss rate for overall accesses 625system.cpu.dcache.overall_miss_rate::total 0.091340 # miss rate for overall accesses 626system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.921030 # average ReadReq miss latency 627system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.921030 # average ReadReq miss latency 628system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30350.367721 # average WriteReq miss latency 629system.cpu.dcache.WriteReq_avg_miss_latency::total 30350.367721 # average WriteReq miss latency 630system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14341.515660 # average LoadLockedReq miss latency 631system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14341.515660 # average LoadLockedReq miss latency 632system.cpu.dcache.demand_avg_miss_latency::cpu.data 26126.175934 # average overall miss latency 633system.cpu.dcache.demand_avg_miss_latency::total 26126.175934 # average overall miss latency 634system.cpu.dcache.overall_avg_miss_latency::cpu.data 26126.175934 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::total 26126.175934 # average overall miss latency | 393system.cpu.dcache.replacements 1390620 # number of replacements 394system.cpu.dcache.tagsinuse 511.980059 # Cycle average of tags in use 395system.cpu.dcache.total_refs 14044869 # Total number of references to valid blocks. 396system.cpu.dcache.sampled_refs 1391132 # Sample count of references to valid blocks. 397system.cpu.dcache.avg_refs 10.096000 # Average number of references to valid blocks. 398system.cpu.dcache.warmup_cycle 99394000 # Cycle when the warmup percentage was hit. 399system.cpu.dcache.occ_blocks::cpu.data 511.980059 # Average occupied blocks per requestor 400system.cpu.dcache.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy 401system.cpu.dcache.occ_percent::total 0.999961 # Average percentage of cache occupancy 402system.cpu.dcache.ReadReq_hits::cpu.data 7812084 # number of ReadReq hits 403system.cpu.dcache.ReadReq_hits::total 7812084 # number of ReadReq hits 404system.cpu.dcache.WriteReq_hits::cpu.data 5850550 # number of WriteReq hits 405system.cpu.dcache.WriteReq_hits::total 5850550 # number of WriteReq hits 406system.cpu.dcache.LoadLockedReq_hits::cpu.data 182982 # number of LoadLockedReq hits 407system.cpu.dcache.LoadLockedReq_hits::total 182982 # number of LoadLockedReq hits 408system.cpu.dcache.StoreCondReq_hits::cpu.data 199236 # number of StoreCondReq hits 409system.cpu.dcache.StoreCondReq_hits::total 199236 # number of StoreCondReq hits 410system.cpu.dcache.demand_hits::cpu.data 13662634 # number of demand (read+write) hits 411system.cpu.dcache.demand_hits::total 13662634 # number of demand (read+write) hits 412system.cpu.dcache.overall_hits::cpu.data 13662634 # number of overall hits 413system.cpu.dcache.overall_hits::total 13662634 # number of overall hits 414system.cpu.dcache.ReadReq_misses::cpu.data 1069478 # number of ReadReq misses 415system.cpu.dcache.ReadReq_misses::total 1069478 # number of ReadReq misses 416system.cpu.dcache.WriteReq_misses::cpu.data 304397 # number of WriteReq misses 417system.cpu.dcache.WriteReq_misses::total 304397 # number of WriteReq misses 418system.cpu.dcache.LoadLockedReq_misses::cpu.data 17275 # number of LoadLockedReq misses 419system.cpu.dcache.LoadLockedReq_misses::total 17275 # number of LoadLockedReq misses 420system.cpu.dcache.demand_misses::cpu.data 1373875 # number of demand (read+write) misses 421system.cpu.dcache.demand_misses::total 1373875 # number of demand (read+write) misses 422system.cpu.dcache.overall_misses::cpu.data 1373875 # number of overall misses 423system.cpu.dcache.overall_misses::total 1373875 # number of overall misses 424system.cpu.dcache.ReadReq_miss_latency::cpu.data 25328737500 # number of ReadReq miss cycles 425system.cpu.dcache.ReadReq_miss_latency::total 25328737500 # number of ReadReq miss cycles 426system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866760500 # number of WriteReq miss cycles 427system.cpu.dcache.WriteReq_miss_latency::total 8866760500 # number of WriteReq miss cycles 428system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 227305000 # number of LoadLockedReq miss cycles 429system.cpu.dcache.LoadLockedReq_miss_latency::total 227305000 # number of LoadLockedReq miss cycles 430system.cpu.dcache.demand_miss_latency::cpu.data 34195498000 # number of demand (read+write) miss cycles 431system.cpu.dcache.demand_miss_latency::total 34195498000 # number of demand (read+write) miss cycles 432system.cpu.dcache.overall_miss_latency::cpu.data 34195498000 # number of overall miss cycles 433system.cpu.dcache.overall_miss_latency::total 34195498000 # number of overall miss cycles 434system.cpu.dcache.ReadReq_accesses::cpu.data 8881562 # number of ReadReq accesses(hits+misses) 435system.cpu.dcache.ReadReq_accesses::total 8881562 # number of ReadReq accesses(hits+misses) 436system.cpu.dcache.WriteReq_accesses::cpu.data 6154947 # number of WriteReq accesses(hits+misses) 437system.cpu.dcache.WriteReq_accesses::total 6154947 # number of WriteReq accesses(hits+misses) 438system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200257 # number of LoadLockedReq accesses(hits+misses) 439system.cpu.dcache.LoadLockedReq_accesses::total 200257 # number of LoadLockedReq accesses(hits+misses) 440system.cpu.dcache.StoreCondReq_accesses::cpu.data 199236 # number of StoreCondReq accesses(hits+misses) 441system.cpu.dcache.StoreCondReq_accesses::total 199236 # number of StoreCondReq accesses(hits+misses) 442system.cpu.dcache.demand_accesses::cpu.data 15036509 # number of demand (read+write) accesses 443system.cpu.dcache.demand_accesses::total 15036509 # number of demand (read+write) accesses 444system.cpu.dcache.overall_accesses::cpu.data 15036509 # number of overall (read+write) accesses 445system.cpu.dcache.overall_accesses::total 15036509 # number of overall (read+write) accesses 446system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120416 # miss rate for ReadReq accesses 447system.cpu.dcache.ReadReq_miss_rate::total 0.120416 # miss rate for ReadReq accesses 448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049456 # miss rate for WriteReq accesses 449system.cpu.dcache.WriteReq_miss_rate::total 0.049456 # miss rate for WriteReq accesses 450system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086264 # miss rate for LoadLockedReq accesses 451system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086264 # miss rate for LoadLockedReq accesses 452system.cpu.dcache.demand_miss_rate::cpu.data 0.091369 # miss rate for demand accesses 453system.cpu.dcache.demand_miss_rate::total 0.091369 # miss rate for demand accesses 454system.cpu.dcache.overall_miss_rate::cpu.data 0.091369 # miss rate for overall accesses 455system.cpu.dcache.overall_miss_rate::total 0.091369 # miss rate for overall accesses 456system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23683.271185 # average ReadReq miss latency 457system.cpu.dcache.ReadReq_avg_miss_latency::total 23683.271185 # average ReadReq miss latency 458system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29128.935239 # average WriteReq miss latency 459system.cpu.dcache.WriteReq_avg_miss_latency::total 29128.935239 # average WriteReq miss latency 460system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13158.031838 # average LoadLockedReq miss latency 461system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13158.031838 # average LoadLockedReq miss latency 462system.cpu.dcache.demand_avg_miss_latency::cpu.data 24889.817487 # average overall miss latency 463system.cpu.dcache.demand_avg_miss_latency::total 24889.817487 # average overall miss latency 464system.cpu.dcache.overall_avg_miss_latency::cpu.data 24889.817487 # average overall miss latency 465system.cpu.dcache.overall_avg_miss_latency::total 24889.817487 # average overall miss latency |
| 636system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 637system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 641system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.dcache.fast_writes 0 # number of fast writes performed 643system.cpu.dcache.cache_copies 0 # number of cache copies performed | 466system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 467system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 468system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 469system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 470system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 471system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 472system.cpu.dcache.fast_writes 0 # number of fast writes performed 473system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 644system.cpu.dcache.writebacks::writebacks 835257 # number of writebacks 645system.cpu.dcache.writebacks::total 835257 # number of writebacks 646system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069678 # number of ReadReq MSHR misses 647system.cpu.dcache.ReadReq_mshr_misses::total 1069678 # number of ReadReq MSHR misses 648system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304443 # number of WriteReq MSHR misses 649system.cpu.dcache.WriteReq_mshr_misses::total 304443 # number of WriteReq MSHR misses 650system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17273 # number of LoadLockedReq MSHR misses 651system.cpu.dcache.LoadLockedReq_mshr_misses::total 17273 # number of LoadLockedReq MSHR misses 652system.cpu.dcache.demand_mshr_misses::cpu.data 1374121 # number of demand (read+write) MSHR misses 653system.cpu.dcache.demand_mshr_misses::total 1374121 # number of demand (read+write) MSHR misses 654system.cpu.dcache.overall_mshr_misses::cpu.data 1374121 # number of overall MSHR misses 655system.cpu.dcache.overall_mshr_misses::total 1374121 # number of overall MSHR misses 656system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23451491000 # number of ReadReq MSHR miss cycles 657system.cpu.dcache.ReadReq_mshr_miss_latency::total 23451491000 # number of ReadReq MSHR miss cycles 658system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8326628000 # number of WriteReq MSHR miss cycles 659system.cpu.dcache.WriteReq_mshr_miss_latency::total 8326628000 # number of WriteReq MSHR miss cycles 660system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195902000 # number of LoadLockedReq MSHR miss cycles 661system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195902000 # number of LoadLockedReq MSHR miss cycles 662system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31778119000 # number of demand (read+write) MSHR miss cycles 663system.cpu.dcache.demand_mshr_miss_latency::total 31778119000 # number of demand (read+write) MSHR miss cycles 664system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31778119000 # number of overall MSHR miss cycles 665system.cpu.dcache.overall_mshr_miss_latency::total 31778119000 # number of overall MSHR miss cycles 666system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1421708000 # number of ReadReq MSHR uncacheable cycles 667system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1421708000 # number of ReadReq MSHR uncacheable cycles 668system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010806000 # number of WriteReq MSHR uncacheable cycles 669system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010806000 # number of WriteReq MSHR uncacheable cycles 670system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3432514000 # number of overall MSHR uncacheable cycles 671system.cpu.dcache.overall_mshr_uncacheable_latency::total 3432514000 # number of overall MSHR uncacheable cycles 672system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120377 # mshr miss rate for ReadReq accesses 673system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120377 # mshr miss rate for ReadReq accesses 674system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049439 # mshr miss rate for WriteReq accesses 675system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049439 # mshr miss rate for WriteReq accesses 676system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086234 # mshr miss rate for LoadLockedReq accesses 677system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086234 # mshr miss rate for LoadLockedReq accesses 678system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091340 # mshr miss rate for demand accesses 679system.cpu.dcache.demand_mshr_miss_rate::total 0.091340 # mshr miss rate for demand accesses 680system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091340 # mshr miss rate for overall accesses 681system.cpu.dcache.overall_mshr_miss_rate::total 0.091340 # mshr miss rate for overall accesses 682system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.878962 # average ReadReq mshr miss latency 683system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.878962 # average ReadReq mshr miss latency 684system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.367721 # average WriteReq mshr miss latency 685system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.367721 # average WriteReq mshr miss latency 686system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.515660 # average LoadLockedReq mshr miss latency 687system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.515660 # average LoadLockedReq mshr miss latency 688system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23126.143185 # average overall mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::total 23126.143185 # average overall mshr miss latency 690system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23126.143185 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::total 23126.143185 # average overall mshr miss latency | 474system.cpu.dcache.writebacks::writebacks 835360 # number of writebacks 475system.cpu.dcache.writebacks::total 835360 # number of writebacks 476system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069478 # number of ReadReq MSHR misses 477system.cpu.dcache.ReadReq_mshr_misses::total 1069478 # number of ReadReq MSHR misses 478system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304397 # number of WriteReq MSHR misses 479system.cpu.dcache.WriteReq_mshr_misses::total 304397 # number of WriteReq MSHR misses 480system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17275 # number of LoadLockedReq MSHR misses 481system.cpu.dcache.LoadLockedReq_mshr_misses::total 17275 # number of LoadLockedReq MSHR misses 482system.cpu.dcache.demand_mshr_misses::cpu.data 1373875 # number of demand (read+write) MSHR misses 483system.cpu.dcache.demand_mshr_misses::total 1373875 # number of demand (read+write) MSHR misses 484system.cpu.dcache.overall_mshr_misses::cpu.data 1373875 # number of overall MSHR misses 485system.cpu.dcache.overall_mshr_misses::total 1373875 # number of overall MSHR misses 486system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23189781500 # number of ReadReq MSHR miss cycles 487system.cpu.dcache.ReadReq_mshr_miss_latency::total 23189781500 # number of ReadReq MSHR miss cycles 488system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257966500 # number of WriteReq MSHR miss cycles 489system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257966500 # number of WriteReq MSHR miss cycles 490system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 192755000 # number of LoadLockedReq MSHR miss cycles 491system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 192755000 # number of LoadLockedReq MSHR miss cycles 492system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31447748000 # number of demand (read+write) MSHR miss cycles 493system.cpu.dcache.demand_mshr_miss_latency::total 31447748000 # number of demand (read+write) MSHR miss cycles 494system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31447748000 # number of overall MSHR miss cycles 495system.cpu.dcache.overall_mshr_miss_latency::total 31447748000 # number of overall MSHR miss cycles 496system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424905500 # number of ReadReq MSHR uncacheable cycles 497system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424905500 # number of ReadReq MSHR uncacheable cycles 498system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011694000 # number of WriteReq MSHR uncacheable cycles 499system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011694000 # number of WriteReq MSHR uncacheable cycles 500system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3436599500 # number of overall MSHR uncacheable cycles 501system.cpu.dcache.overall_mshr_uncacheable_latency::total 3436599500 # number of overall MSHR uncacheable cycles 502system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120416 # mshr miss rate for ReadReq accesses 503system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120416 # mshr miss rate for ReadReq accesses 504system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses 505system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses 506system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086264 # mshr miss rate for LoadLockedReq accesses 507system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086264 # mshr miss rate for LoadLockedReq accesses 508system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091369 # mshr miss rate for demand accesses 509system.cpu.dcache.demand_mshr_miss_rate::total 0.091369 # mshr miss rate for demand accesses 510system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091369 # mshr miss rate for overall accesses 511system.cpu.dcache.overall_mshr_miss_rate::total 0.091369 # mshr miss rate for overall accesses 512system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21683.271185 # average ReadReq mshr miss latency 513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21683.271185 # average ReadReq mshr miss latency 514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27128.935239 # average WriteReq mshr miss latency 515system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27128.935239 # average WriteReq mshr miss latency 516system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11158.031838 # average LoadLockedReq mshr miss latency 517system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11158.031838 # average LoadLockedReq mshr miss latency 518system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22889.817487 # average overall mshr miss latency 519system.cpu.dcache.demand_avg_mshr_miss_latency::total 22889.817487 # average overall mshr miss latency 520system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22889.817487 # average overall mshr miss latency 521system.cpu.dcache.overall_avg_mshr_miss_latency::total 22889.817487 # average overall mshr miss latency |
| 692system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 693system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 694system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 695system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 696system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 697system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 698system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 522system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 523system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 524system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 525system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 526system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 527system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 528system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 529system.cpu.l2cache.replacements 336256 # number of replacements 530system.cpu.l2cache.tagsinuse 65309.148086 # Cycle average of tags in use 531system.cpu.l2cache.total_refs 2447127 # Total number of references to valid blocks. 532system.cpu.l2cache.sampled_refs 401418 # Sample count of references to valid blocks. 533system.cpu.l2cache.avg_refs 6.096206 # Average number of references to valid blocks. 534system.cpu.l2cache.warmup_cycle 5907030000 # Cycle when the warmup percentage was hit. 535system.cpu.l2cache.occ_blocks::writebacks 55687.812663 # Average occupied blocks per requestor 536system.cpu.l2cache.occ_blocks::cpu.inst 4769.025398 # Average occupied blocks per requestor 537system.cpu.l2cache.occ_blocks::cpu.data 4852.310026 # Average occupied blocks per requestor 538system.cpu.l2cache.occ_percent::writebacks 0.849729 # Average percentage of cache occupancy 539system.cpu.l2cache.occ_percent::cpu.inst 0.072770 # Average percentage of cache occupancy 540system.cpu.l2cache.occ_percent::cpu.data 0.074040 # Average percentage of cache occupancy 541system.cpu.l2cache.occ_percent::total 0.996539 # Average percentage of cache occupancy 542system.cpu.l2cache.ReadReq_hits::cpu.inst 915237 # number of ReadReq hits 543system.cpu.l2cache.ReadReq_hits::cpu.data 814783 # number of ReadReq hits 544system.cpu.l2cache.ReadReq_hits::total 1730020 # number of ReadReq hits 545system.cpu.l2cache.Writeback_hits::writebacks 835360 # number of Writeback hits 546system.cpu.l2cache.Writeback_hits::total 835360 # number of Writeback hits 547system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 548system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 549system.cpu.l2cache.ReadExReq_hits::cpu.data 187521 # number of ReadExReq hits 550system.cpu.l2cache.ReadExReq_hits::total 187521 # number of ReadExReq hits 551system.cpu.l2cache.demand_hits::cpu.inst 915237 # number of demand (read+write) hits 552system.cpu.l2cache.demand_hits::cpu.data 1002304 # number of demand (read+write) hits 553system.cpu.l2cache.demand_hits::total 1917541 # number of demand (read+write) hits 554system.cpu.l2cache.overall_hits::cpu.inst 915237 # number of overall hits 555system.cpu.l2cache.overall_hits::cpu.data 1002304 # number of overall hits 556system.cpu.l2cache.overall_hits::total 1917541 # number of overall hits 557system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses 558system.cpu.l2cache.ReadReq_misses::cpu.data 271970 # number of ReadReq misses 559system.cpu.l2cache.ReadReq_misses::total 285260 # number of ReadReq misses 560system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 561system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses 562system.cpu.l2cache.ReadExReq_misses::cpu.data 116859 # number of ReadExReq misses 563system.cpu.l2cache.ReadExReq_misses::total 116859 # number of ReadExReq misses 564system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses 565system.cpu.l2cache.demand_misses::cpu.data 388829 # number of demand (read+write) misses 566system.cpu.l2cache.demand_misses::total 402119 # number of demand (read+write) misses 567system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses 568system.cpu.l2cache.overall_misses::cpu.data 388829 # number of overall misses 569system.cpu.l2cache.overall_misses::total 402119 # number of overall misses 570system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 691484000 # number of ReadReq miss cycles 571system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14147953500 # number of ReadReq miss cycles 572system.cpu.l2cache.ReadReq_miss_latency::total 14839437500 # number of ReadReq miss cycles 573system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 248500 # number of UpgradeReq miss cycles 574system.cpu.l2cache.UpgradeReq_miss_latency::total 248500 # number of UpgradeReq miss cycles 575system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6077611500 # number of ReadExReq miss cycles 576system.cpu.l2cache.ReadExReq_miss_latency::total 6077611500 # number of ReadExReq miss cycles 577system.cpu.l2cache.demand_miss_latency::cpu.inst 691484000 # number of demand (read+write) miss cycles 578system.cpu.l2cache.demand_miss_latency::cpu.data 20225565000 # number of demand (read+write) miss cycles 579system.cpu.l2cache.demand_miss_latency::total 20917049000 # number of demand (read+write) miss cycles 580system.cpu.l2cache.overall_miss_latency::cpu.inst 691484000 # number of overall miss cycles 581system.cpu.l2cache.overall_miss_latency::cpu.data 20225565000 # number of overall miss cycles 582system.cpu.l2cache.overall_miss_latency::total 20917049000 # number of overall miss cycles 583system.cpu.l2cache.ReadReq_accesses::cpu.inst 928527 # number of ReadReq accesses(hits+misses) 584system.cpu.l2cache.ReadReq_accesses::cpu.data 1086753 # number of ReadReq accesses(hits+misses) 585system.cpu.l2cache.ReadReq_accesses::total 2015280 # number of ReadReq accesses(hits+misses) 586system.cpu.l2cache.Writeback_accesses::writebacks 835360 # number of Writeback accesses(hits+misses) 587system.cpu.l2cache.Writeback_accesses::total 835360 # number of Writeback accesses(hits+misses) 588system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 589system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 590system.cpu.l2cache.ReadExReq_accesses::cpu.data 304380 # number of ReadExReq accesses(hits+misses) 591system.cpu.l2cache.ReadExReq_accesses::total 304380 # number of ReadExReq accesses(hits+misses) 592system.cpu.l2cache.demand_accesses::cpu.inst 928527 # number of demand (read+write) accesses 593system.cpu.l2cache.demand_accesses::cpu.data 1391133 # number of demand (read+write) accesses 594system.cpu.l2cache.demand_accesses::total 2319660 # number of demand (read+write) accesses 595system.cpu.l2cache.overall_accesses::cpu.inst 928527 # number of overall (read+write) accesses 596system.cpu.l2cache.overall_accesses::cpu.data 1391133 # number of overall (read+write) accesses 597system.cpu.l2cache.overall_accesses::total 2319660 # number of overall (read+write) accesses 598system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014313 # miss rate for ReadReq accesses 599system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250259 # miss rate for ReadReq accesses 600system.cpu.l2cache.ReadReq_miss_rate::total 0.141549 # miss rate for ReadReq accesses 601system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 602system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses 603system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383925 # miss rate for ReadExReq accesses 604system.cpu.l2cache.ReadExReq_miss_rate::total 0.383925 # miss rate for ReadExReq accesses 605system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014313 # miss rate for demand accesses 606system.cpu.l2cache.demand_miss_rate::cpu.data 0.279505 # miss rate for demand accesses 607system.cpu.l2cache.demand_miss_rate::total 0.173353 # miss rate for demand accesses 608system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014313 # miss rate for overall accesses 609system.cpu.l2cache.overall_miss_rate::cpu.data 0.279505 # miss rate for overall accesses 610system.cpu.l2cache.overall_miss_rate::total 0.173353 # miss rate for overall accesses 611system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52030.398796 # average ReadReq miss latency 612system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52020.272457 # average ReadReq miss latency 613system.cpu.l2cache.ReadReq_avg_miss_latency::total 52020.744233 # average ReadReq miss latency 614system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19115.384615 # average UpgradeReq miss latency 615system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19115.384615 # average UpgradeReq miss latency 616system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52008.073833 # average ReadExReq miss latency 617system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52008.073833 # average ReadExReq miss latency 618system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52030.398796 # average overall miss latency 619system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52016.606272 # average overall miss latency 620system.cpu.l2cache.demand_avg_miss_latency::total 52017.062113 # average overall miss latency 621system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52030.398796 # average overall miss latency 622system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52016.606272 # average overall miss latency 623system.cpu.l2cache.overall_avg_miss_latency::total 52017.062113 # average overall miss latency 624system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 625system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 626system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 627system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 628system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 629system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 630system.cpu.l2cache.fast_writes 0 # number of fast writes performed 631system.cpu.l2cache.cache_copies 0 # number of cache copies performed 632system.cpu.l2cache.writebacks::writebacks 74188 # number of writebacks 633system.cpu.l2cache.writebacks::total 74188 # number of writebacks 634system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses 635system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271970 # number of ReadReq MSHR misses 636system.cpu.l2cache.ReadReq_mshr_misses::total 285260 # number of ReadReq MSHR misses 637system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 638system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 639system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116859 # number of ReadExReq MSHR misses 640system.cpu.l2cache.ReadExReq_mshr_misses::total 116859 # number of ReadExReq MSHR misses 641system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses 642system.cpu.l2cache.demand_mshr_misses::cpu.data 388829 # number of demand (read+write) MSHR misses 643system.cpu.l2cache.demand_mshr_misses::total 402119 # number of demand (read+write) MSHR misses 644system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses 645system.cpu.l2cache.overall_mshr_misses::cpu.data 388829 # number of overall MSHR misses 646system.cpu.l2cache.overall_mshr_misses::total 402119 # number of overall MSHR misses 647system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531884000 # number of ReadReq MSHR miss cycles 648system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884274000 # number of ReadReq MSHR miss cycles 649system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles 650system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles 651system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles 652system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219000 # number of ReadExReq MSHR miss cycles 653system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219000 # number of ReadExReq MSHR miss cycles 654system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles 655system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493000 # number of demand (read+write) MSHR miss cycles 656system.cpu.l2cache.demand_mshr_miss_latency::total 16091377000 # number of demand (read+write) MSHR miss cycles 657system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles 658system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493000 # number of overall MSHR miss cycles 659system.cpu.l2cache.overall_mshr_miss_latency::total 16091377000 # number of overall MSHR miss cycles 660system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles 661system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles 662system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles 663system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892328500 # number of WriteReq MSHR uncacheable cycles 664system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508500 # number of overall MSHR uncacheable cycles 665system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508500 # number of overall MSHR uncacheable cycles 666system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for ReadReq accesses 667system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses 668system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141549 # mshr miss rate for ReadReq accesses 669system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 670system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 671system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383925 # mshr miss rate for ReadExReq accesses 672system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383925 # mshr miss rate for ReadExReq accesses 673system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for demand accesses 674system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for demand accesses 675system.cpu.l2cache.demand_mshr_miss_rate::total 0.173353 # mshr miss rate for demand accesses 676system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014313 # mshr miss rate for overall accesses 677system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279505 # mshr miss rate for overall accesses 678system.cpu.l2cache.overall_mshr_miss_rate::total 0.173353 # mshr miss rate for overall accesses 679system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40021.369451 # average ReadReq mshr miss latency 680system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40020.127220 # average ReadReq mshr miss latency 681system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency 682system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency 683system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency 684system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.350739 # average ReadExReq mshr miss latency 685system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.350739 # average ReadExReq mshr miss latency 686system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency 687system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency 688system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency 689system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency 690system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency 691system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency 692system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 693system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 694system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 695system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 696system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 697system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 698system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
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| 699 700---------- End Simulation Statistics ---------- | 699 700---------- End Simulation Statistics ---------- |