| stats.txt (9229:65f927bda74d) | stats.txt (9283:490958b032d6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.920895 # Number of seconds simulated 4sim_ticks 1920895294000 # Number of ticks simulated 5final_tick 1920895294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1271848 # Simulator instruction rate (inst/s) 8host_op_rate 1271848 # Simulator op (including micro ops) rate (op/s) --- 24 unchanged lines hidden (view full) --- 33system.physmem.bw_inst_read::total 442760 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3854603 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3854603 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3854603 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 442760 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s) | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.920895 # Number of seconds simulated 4sim_ticks 1920895294000 # Number of ticks simulated 5final_tick 1920895294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1271848 # Simulator instruction rate (inst/s) 8host_op_rate 1271848 # Simulator op (including micro ops) rate (op/s) --- 24 unchanged lines hidden (view full) --- 33system.physmem.bw_inst_read::total 442760 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3854603 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3854603 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3854603 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 442760 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12941865 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1380789 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18620018 # Total bandwidth to/from this memory (bytes/s) |
| 41system.l2c.replacements 336257 # number of replacements 42system.l2c.tagsinuse 65308.063316 # Cycle average of tags in use 43system.l2c.total_refs 2448454 # Total number of references to valid blocks. 44system.l2c.sampled_refs 401419 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.099497 # Average number of references to valid blocks. 46system.l2c.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. 47system.l2c.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor 50system.l2c.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.996522 # Average percentage of cache occupancy 54system.l2c.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 814985 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1731448 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 835257 # number of Writeback hits 58system.l2c.Writeback_hits::total 835257 # number of Writeback hits 59system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits 61system.l2c.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits 62system.l2c.ReadExReq_hits::total 187565 # number of ReadExReq hits 63system.l2c.demand_hits::cpu.inst 916463 # number of demand (read+write) hits 64system.l2c.demand_hits::cpu.data 1002550 # number of demand (read+write) hits 65system.l2c.demand_hits::total 1919013 # number of demand (read+write) hits 66system.l2c.overall_hits::cpu.inst 916463 # number of overall hits 67system.l2c.overall_hits::cpu.data 1002550 # number of overall hits 68system.l2c.overall_hits::total 1919013 # number of overall hits 69system.l2c.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses 70system.l2c.ReadReq_misses::cpu.data 271966 # number of ReadReq misses 71system.l2c.ReadReq_misses::total 285255 # number of ReadReq misses 72system.l2c.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 73system.l2c.UpgradeReq_misses::total 13 # number of UpgradeReq misses 74system.l2c.ReadExReq_misses::cpu.data 116861 # number of ReadExReq misses 75system.l2c.ReadExReq_misses::total 116861 # number of ReadExReq misses 76system.l2c.demand_misses::cpu.inst 13289 # number of demand (read+write) misses 77system.l2c.demand_misses::cpu.data 388827 # number of demand (read+write) misses 78system.l2c.demand_misses::total 402116 # number of demand (read+write) misses 79system.l2c.overall_misses::cpu.inst 13289 # number of overall misses 80system.l2c.overall_misses::cpu.data 388827 # number of overall misses 81system.l2c.overall_misses::total 402116 # number of overall misses 82system.l2c.ReadReq_miss_latency::cpu.inst 691205000 # number of ReadReq miss cycles 83system.l2c.ReadReq_miss_latency::cpu.data 14147611000 # number of ReadReq miss cycles 84system.l2c.ReadReq_miss_latency::total 14838816000 # number of ReadReq miss cycles 85system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles 86system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles 87system.l2c.ReadExReq_miss_latency::cpu.data 6077413000 # number of ReadExReq miss cycles 88system.l2c.ReadExReq_miss_latency::total 6077413000 # number of ReadExReq miss cycles 89system.l2c.demand_miss_latency::cpu.inst 691205000 # number of demand (read+write) miss cycles 90system.l2c.demand_miss_latency::cpu.data 20225024000 # number of demand (read+write) miss cycles 91system.l2c.demand_miss_latency::total 20916229000 # number of demand (read+write) miss cycles 92system.l2c.overall_miss_latency::cpu.inst 691205000 # number of overall miss cycles 93system.l2c.overall_miss_latency::cpu.data 20225024000 # number of overall miss cycles 94system.l2c.overall_miss_latency::total 20916229000 # number of overall miss cycles 95system.l2c.ReadReq_accesses::cpu.inst 929752 # number of ReadReq accesses(hits+misses) 96system.l2c.ReadReq_accesses::cpu.data 1086951 # number of ReadReq accesses(hits+misses) 97system.l2c.ReadReq_accesses::total 2016703 # number of ReadReq accesses(hits+misses) 98system.l2c.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses) 99system.l2c.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses) 100system.l2c.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 101system.l2c.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 102system.l2c.ReadExReq_accesses::cpu.data 304426 # number of ReadExReq accesses(hits+misses) 103system.l2c.ReadExReq_accesses::total 304426 # number of ReadExReq accesses(hits+misses) 104system.l2c.demand_accesses::cpu.inst 929752 # number of demand (read+write) accesses 105system.l2c.demand_accesses::cpu.data 1391377 # number of demand (read+write) accesses 106system.l2c.demand_accesses::total 2321129 # number of demand (read+write) accesses 107system.l2c.overall_accesses::cpu.inst 929752 # number of overall (read+write) accesses 108system.l2c.overall_accesses::cpu.data 1391377 # number of overall (read+write) accesses 109system.l2c.overall_accesses::total 2321129 # number of overall (read+write) accesses 110system.l2c.ReadReq_miss_rate::cpu.inst 0.014293 # miss rate for ReadReq accesses 111system.l2c.ReadReq_miss_rate::cpu.data 0.250210 # miss rate for ReadReq accesses 112system.l2c.ReadReq_miss_rate::total 0.141446 # miss rate for ReadReq accesses 113system.l2c.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 114system.l2c.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses 115system.l2c.ReadExReq_miss_rate::cpu.data 0.383873 # miss rate for ReadExReq accesses 116system.l2c.ReadExReq_miss_rate::total 0.383873 # miss rate for ReadExReq accesses 117system.l2c.demand_miss_rate::cpu.inst 0.014293 # miss rate for demand accesses 118system.l2c.demand_miss_rate::cpu.data 0.279455 # miss rate for demand accesses 119system.l2c.demand_miss_rate::total 0.173242 # miss rate for demand accesses 120system.l2c.overall_miss_rate::cpu.inst 0.014293 # miss rate for overall accesses 121system.l2c.overall_miss_rate::cpu.data 0.279455 # miss rate for overall accesses 122system.l2c.overall_miss_rate::total 0.173242 # miss rate for overall accesses 123system.l2c.ReadReq_avg_miss_latency::cpu.inst 52013.319287 # average ReadReq miss latency 124system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.778208 # average ReadReq miss latency 125system.l2c.ReadReq_avg_miss_latency::total 52019.477310 # average ReadReq miss latency 126system.l2c.UpgradeReq_avg_miss_latency::cpu.data 19076.923077 # average UpgradeReq miss latency 127system.l2c.UpgradeReq_avg_miss_latency::total 19076.923077 # average UpgradeReq miss latency 128system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.485149 # average ReadExReq miss latency 129system.l2c.ReadExReq_avg_miss_latency::total 52005.485149 # average ReadExReq miss latency 130system.l2c.demand_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency 131system.l2c.demand_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency 132system.l2c.demand_avg_miss_latency::total 52015.410976 # average overall miss latency 133system.l2c.overall_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency 134system.l2c.overall_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency 135system.l2c.overall_avg_miss_latency::total 52015.410976 # average overall miss latency 136system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 137system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 138system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 139system.l2c.blocked::no_targets 0 # number of cycles access was blocked 140system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 141system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 142system.l2c.fast_writes 0 # number of fast writes performed 143system.l2c.cache_copies 0 # number of cache copies performed 144system.l2c.writebacks::writebacks 74180 # number of writebacks 145system.l2c.writebacks::total 74180 # number of writebacks 146system.l2c.ReadReq_mshr_misses::cpu.inst 13289 # number of ReadReq MSHR misses 147system.l2c.ReadReq_mshr_misses::cpu.data 271966 # number of ReadReq MSHR misses 148system.l2c.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses 149system.l2c.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 150system.l2c.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 151system.l2c.ReadExReq_mshr_misses::cpu.data 116861 # number of ReadExReq MSHR misses 152system.l2c.ReadExReq_mshr_misses::total 116861 # number of ReadExReq MSHR misses 153system.l2c.demand_mshr_misses::cpu.inst 13289 # number of demand (read+write) MSHR misses 154system.l2c.demand_mshr_misses::cpu.data 388827 # number of demand (read+write) MSHR misses 155system.l2c.demand_mshr_misses::total 402116 # number of demand (read+write) MSHR misses 156system.l2c.overall_mshr_misses::cpu.inst 13289 # number of overall MSHR misses 157system.l2c.overall_mshr_misses::cpu.data 388827 # number of overall MSHR misses 158system.l2c.overall_mshr_misses::total 402116 # number of overall MSHR misses 159system.l2c.ReadReq_mshr_miss_latency::cpu.inst 531734000 # number of ReadReq MSHR miss cycles 160system.l2c.ReadReq_mshr_miss_latency::cpu.data 10884019000 # number of ReadReq MSHR miss cycles 161system.l2c.ReadReq_mshr_miss_latency::total 11415753000 # number of ReadReq MSHR miss cycles 162system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles 163system.l2c.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles 164system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4675081000 # number of ReadExReq MSHR miss cycles 165system.l2c.ReadExReq_mshr_miss_latency::total 4675081000 # number of ReadExReq MSHR miss cycles 166system.l2c.demand_mshr_miss_latency::cpu.inst 531734000 # number of demand (read+write) MSHR miss cycles 167system.l2c.demand_mshr_miss_latency::cpu.data 15559100000 # number of demand (read+write) MSHR miss cycles 168system.l2c.demand_mshr_miss_latency::total 16090834000 # number of demand (read+write) MSHR miss cycles 169system.l2c.overall_mshr_miss_latency::cpu.inst 531734000 # number of overall MSHR miss cycles 170system.l2c.overall_mshr_miss_latency::cpu.data 15559100000 # number of overall MSHR miss cycles 171system.l2c.overall_mshr_miss_latency::total 16090834000 # number of overall MSHR miss cycles 172system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles 173system.l2c.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles 174system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1892958000 # number of WriteReq MSHR uncacheable cycles 175system.l2c.WriteReq_mshr_uncacheable_latency::total 1892958000 # number of WriteReq MSHR uncacheable cycles 176system.l2c.overall_mshr_uncacheable_latency::cpu.data 3224508000 # number of overall MSHR uncacheable cycles 177system.l2c.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles 178system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses 179system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses 180system.l2c.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses 181system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 182system.l2c.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 183system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses 184system.l2c.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses 185system.l2c.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses 186system.l2c.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses 187system.l2c.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses 188system.l2c.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses 189system.l2c.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses 190system.l2c.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses 191system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency 192system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency 193system.l2c.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency 194system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency 195system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency 196system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency 197system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency 198system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency 199system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency 200system.l2c.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency 201system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency 202system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency 203system.l2c.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency 204system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 205system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 206system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 207system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 208system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 209system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 210system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 41system.cpu.l2cache.replacements 336257 # number of replacements 42system.cpu.l2cache.tagsinuse 65308.063316 # Cycle average of tags in use 43system.cpu.l2cache.total_refs 2448454 # Total number of references to valid blocks. 44system.cpu.l2cache.sampled_refs 401419 # Sample count of references to valid blocks. 45system.cpu.l2cache.avg_refs 6.099497 # Average number of references to valid blocks. 46system.cpu.l2cache.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. 47system.cpu.l2cache.occ_blocks::writebacks 55656.590733 # Average occupied blocks per requestor 48system.cpu.l2cache.occ_blocks::cpu.inst 4765.137084 # Average occupied blocks per requestor 49system.cpu.l2cache.occ_blocks::cpu.data 4886.335499 # Average occupied blocks per requestor 50system.cpu.l2cache.occ_percent::writebacks 0.849252 # Average percentage of cache occupancy 51system.cpu.l2cache.occ_percent::cpu.inst 0.072710 # Average percentage of cache occupancy 52system.cpu.l2cache.occ_percent::cpu.data 0.074560 # Average percentage of cache occupancy 53system.cpu.l2cache.occ_percent::total 0.996522 # Average percentage of cache occupancy 54system.cpu.l2cache.ReadReq_hits::cpu.inst 916463 # number of ReadReq hits 55system.cpu.l2cache.ReadReq_hits::cpu.data 814985 # number of ReadReq hits 56system.cpu.l2cache.ReadReq_hits::total 1731448 # number of ReadReq hits 57system.cpu.l2cache.Writeback_hits::writebacks 835257 # number of Writeback hits 58system.cpu.l2cache.Writeback_hits::total 835257 # number of Writeback hits 59system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 60system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 61system.cpu.l2cache.ReadExReq_hits::cpu.data 187565 # number of ReadExReq hits 62system.cpu.l2cache.ReadExReq_hits::total 187565 # number of ReadExReq hits 63system.cpu.l2cache.demand_hits::cpu.inst 916463 # number of demand (read+write) hits 64system.cpu.l2cache.demand_hits::cpu.data 1002550 # number of demand (read+write) hits 65system.cpu.l2cache.demand_hits::total 1919013 # number of demand (read+write) hits 66system.cpu.l2cache.overall_hits::cpu.inst 916463 # number of overall hits 67system.cpu.l2cache.overall_hits::cpu.data 1002550 # number of overall hits 68system.cpu.l2cache.overall_hits::total 1919013 # number of overall hits 69system.cpu.l2cache.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses 70system.cpu.l2cache.ReadReq_misses::cpu.data 271966 # number of ReadReq misses 71system.cpu.l2cache.ReadReq_misses::total 285255 # number of ReadReq misses 72system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 73system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses 74system.cpu.l2cache.ReadExReq_misses::cpu.data 116861 # number of ReadExReq misses 75system.cpu.l2cache.ReadExReq_misses::total 116861 # number of ReadExReq misses 76system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses 77system.cpu.l2cache.demand_misses::cpu.data 388827 # number of demand (read+write) misses 78system.cpu.l2cache.demand_misses::total 402116 # number of demand (read+write) misses 79system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses 80system.cpu.l2cache.overall_misses::cpu.data 388827 # number of overall misses 81system.cpu.l2cache.overall_misses::total 402116 # number of overall misses 82system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 691205000 # number of ReadReq miss cycles 83system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14147611000 # number of ReadReq miss cycles 84system.cpu.l2cache.ReadReq_miss_latency::total 14838816000 # number of ReadReq miss cycles 85system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles 86system.cpu.l2cache.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles 87system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6077413000 # number of ReadExReq miss cycles 88system.cpu.l2cache.ReadExReq_miss_latency::total 6077413000 # number of ReadExReq miss cycles 89system.cpu.l2cache.demand_miss_latency::cpu.inst 691205000 # number of demand (read+write) miss cycles 90system.cpu.l2cache.demand_miss_latency::cpu.data 20225024000 # number of demand (read+write) miss cycles 91system.cpu.l2cache.demand_miss_latency::total 20916229000 # number of demand (read+write) miss cycles 92system.cpu.l2cache.overall_miss_latency::cpu.inst 691205000 # number of overall miss cycles 93system.cpu.l2cache.overall_miss_latency::cpu.data 20225024000 # number of overall miss cycles 94system.cpu.l2cache.overall_miss_latency::total 20916229000 # number of overall miss cycles 95system.cpu.l2cache.ReadReq_accesses::cpu.inst 929752 # number of ReadReq accesses(hits+misses) 96system.cpu.l2cache.ReadReq_accesses::cpu.data 1086951 # number of ReadReq accesses(hits+misses) 97system.cpu.l2cache.ReadReq_accesses::total 2016703 # number of ReadReq accesses(hits+misses) 98system.cpu.l2cache.Writeback_accesses::writebacks 835257 # number of Writeback accesses(hits+misses) 99system.cpu.l2cache.Writeback_accesses::total 835257 # number of Writeback accesses(hits+misses) 100system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 101system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) 102system.cpu.l2cache.ReadExReq_accesses::cpu.data 304426 # number of ReadExReq accesses(hits+misses) 103system.cpu.l2cache.ReadExReq_accesses::total 304426 # number of ReadExReq accesses(hits+misses) 104system.cpu.l2cache.demand_accesses::cpu.inst 929752 # number of demand (read+write) accesses 105system.cpu.l2cache.demand_accesses::cpu.data 1391377 # number of demand (read+write) accesses 106system.cpu.l2cache.demand_accesses::total 2321129 # number of demand (read+write) accesses 107system.cpu.l2cache.overall_accesses::cpu.inst 929752 # number of overall (read+write) accesses 108system.cpu.l2cache.overall_accesses::cpu.data 1391377 # number of overall (read+write) accesses 109system.cpu.l2cache.overall_accesses::total 2321129 # number of overall (read+write) accesses 110system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014293 # miss rate for ReadReq accesses 111system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250210 # miss rate for ReadReq accesses 112system.cpu.l2cache.ReadReq_miss_rate::total 0.141446 # miss rate for ReadReq accesses 113system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 114system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses 115system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383873 # miss rate for ReadExReq accesses 116system.cpu.l2cache.ReadExReq_miss_rate::total 0.383873 # miss rate for ReadExReq accesses 117system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014293 # miss rate for demand accesses 118system.cpu.l2cache.demand_miss_rate::cpu.data 0.279455 # miss rate for demand accesses 119system.cpu.l2cache.demand_miss_rate::total 0.173242 # miss rate for demand accesses 120system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014293 # miss rate for overall accesses 121system.cpu.l2cache.overall_miss_rate::cpu.data 0.279455 # miss rate for overall accesses 122system.cpu.l2cache.overall_miss_rate::total 0.173242 # miss rate for overall accesses 123system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52013.319287 # average ReadReq miss latency 124system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52019.778208 # average ReadReq miss latency 125system.cpu.l2cache.ReadReq_avg_miss_latency::total 52019.477310 # average ReadReq miss latency 126system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19076.923077 # average UpgradeReq miss latency 127system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19076.923077 # average UpgradeReq miss latency 128system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52005.485149 # average ReadExReq miss latency 129system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52005.485149 # average ReadExReq miss latency 130system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency 131system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency 132system.cpu.l2cache.demand_avg_miss_latency::total 52015.410976 # average overall miss latency 133system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52013.319287 # average overall miss latency 134system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52015.482464 # average overall miss latency 135system.cpu.l2cache.overall_avg_miss_latency::total 52015.410976 # average overall miss latency 136system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 137system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 138system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 139system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 140system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 141system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 142system.cpu.l2cache.fast_writes 0 # number of fast writes performed 143system.cpu.l2cache.cache_copies 0 # number of cache copies performed 144system.cpu.l2cache.writebacks::writebacks 74180 # number of writebacks 145system.cpu.l2cache.writebacks::total 74180 # number of writebacks 146system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13289 # number of ReadReq MSHR misses 147system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271966 # number of ReadReq MSHR misses 148system.cpu.l2cache.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses 149system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 150system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 151system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116861 # number of ReadExReq MSHR misses 152system.cpu.l2cache.ReadExReq_mshr_misses::total 116861 # number of ReadExReq MSHR misses 153system.cpu.l2cache.demand_mshr_misses::cpu.inst 13289 # number of demand (read+write) MSHR misses 154system.cpu.l2cache.demand_mshr_misses::cpu.data 388827 # number of demand (read+write) MSHR misses 155system.cpu.l2cache.demand_mshr_misses::total 402116 # number of demand (read+write) MSHR misses 156system.cpu.l2cache.overall_mshr_misses::cpu.inst 13289 # number of overall MSHR misses 157system.cpu.l2cache.overall_mshr_misses::cpu.data 388827 # number of overall MSHR misses 158system.cpu.l2cache.overall_mshr_misses::total 402116 # number of overall MSHR misses 159system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 531734000 # number of ReadReq MSHR miss cycles 160system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10884019000 # number of ReadReq MSHR miss cycles 161system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11415753000 # number of ReadReq MSHR miss cycles 162system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles 163system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles 164system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675081000 # number of ReadExReq MSHR miss cycles 165system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675081000 # number of ReadExReq MSHR miss cycles 166system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531734000 # number of demand (read+write) MSHR miss cycles 167system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559100000 # number of demand (read+write) MSHR miss cycles 168system.cpu.l2cache.demand_mshr_miss_latency::total 16090834000 # number of demand (read+write) MSHR miss cycles 169system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531734000 # number of overall MSHR miss cycles 170system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559100000 # number of overall MSHR miss cycles 171system.cpu.l2cache.overall_mshr_miss_latency::total 16090834000 # number of overall MSHR miss cycles 172system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles 173system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles 174system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892958000 # number of WriteReq MSHR uncacheable cycles 175system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892958000 # number of WriteReq MSHR uncacheable cycles 176system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3224508000 # number of overall MSHR uncacheable cycles 177system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3224508000 # number of overall MSHR uncacheable cycles 178system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for ReadReq accesses 179system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250210 # mshr miss rate for ReadReq accesses 180system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141446 # mshr miss rate for ReadReq accesses 181system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 182system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 183system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383873 # mshr miss rate for ReadExReq accesses 184system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383873 # mshr miss rate for ReadExReq accesses 185system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for demand accesses 186system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for demand accesses 187system.cpu.l2cache.demand_mshr_miss_rate::total 0.173242 # mshr miss rate for demand accesses 188system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014293 # mshr miss rate for overall accesses 189system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279455 # mshr miss rate for overall accesses 190system.cpu.l2cache.overall_mshr_miss_rate::total 0.173242 # mshr miss rate for overall accesses 191system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40013.093536 # average ReadReq mshr miss latency 192system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40019.778208 # average ReadReq mshr miss latency 193system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40019.466793 # average ReadReq mshr miss latency 194system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency 195system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency 196system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.485149 # average ReadExReq mshr miss latency 197system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40005.485149 # average ReadExReq mshr miss latency 198system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency 199system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency 200system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency 201system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40013.093536 # average overall mshr miss latency 202system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40015.482464 # average overall mshr miss latency 203system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40015.403515 # average overall mshr miss latency 204system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 205system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 206system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 207system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 208system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 209system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 210system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 211system.iocache.replacements 41685 # number of replacements 212system.iocache.tagsinuse 1.347775 # Cycle average of tags in use 213system.iocache.total_refs 0 # Total number of references to valid blocks. 214system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 215system.iocache.avg_refs 0 # Average number of references to valid blocks. 216system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. 217system.iocache.occ_blocks::tsunami.ide 1.347775 # Average occupied blocks per requestor 218system.iocache.occ_percent::tsunami.ide 0.084236 # Average percentage of cache occupancy --- 482 unchanged lines hidden --- | 211system.iocache.replacements 41685 # number of replacements 212system.iocache.tagsinuse 1.347775 # Cycle average of tags in use 213system.iocache.total_refs 0 # Total number of references to valid blocks. 214system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 215system.iocache.avg_refs 0 # Average number of references to valid blocks. 216system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. 217system.iocache.occ_blocks::tsunami.ide 1.347775 # Average occupied blocks per requestor 218system.iocache.occ_percent::tsunami.ide 0.084236 # Average percentage of cache occupancy --- 482 unchanged lines hidden --- |