stats.txt (9134:275232ad377d) | stats.txt (9199:2a5516167688) |
---|---|
1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 1.920853 # Number of seconds simulated 4sim_ticks 1920853042000 # Number of ticks simulated 5final_tick 1920853042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.921792 # Number of seconds simulated 4sim_ticks 1921792488000 # Number of ticks simulated 5final_tick 1921792488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 1381815 # Simulator instruction rate (inst/s) 8host_op_rate 1381815 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47239093914 # Simulator tick rate (ticks/s) 10host_mem_usage 299308 # Number of bytes of host memory used 11host_seconds 40.66 # Real time elapsed on the host 12sim_insts 56187824 # Number of instructions simulated 13sim_ops 56187824 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24847552 # Number of bytes read from this memory | 7host_inst_rate 1964765 # Simulator instruction rate (inst/s) 8host_op_rate 1964764 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 67191639126 # Simulator tick rate (ticks/s) 10host_mem_usage 295072 # Number of bytes of host memory used 11host_seconds 28.60 # Real time elapsed on the host 12sim_insts 56195476 # Number of instructions simulated 13sim_ops 56195476 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory |
16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory | 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory |
17system.physmem.bytes_read::total 28350592 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7389056 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7389056 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388243 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::total 28361728 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7403520 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7403520 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388418 # Number of read requests responded to by this memory |
24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory | 24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory |
25system.physmem.num_reads::total 442978 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115454 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115454 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 442870 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12935686 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1380820 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14759376 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 442870 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 442870 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3846758 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3846758 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3846758 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 442870 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12935686 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1380820 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18606133 # Total bandwidth to/from this memory (bytes/s) 41system.l2c.replacements 336066 # number of replacements 42system.l2c.tagsinuse 65311.806529 # Cycle average of tags in use 43system.l2c.total_refs 2448197 # Total number of references to valid blocks. 44system.l2c.sampled_refs 401228 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.101760 # Average number of references to valid blocks. 46system.l2c.warmup_cycle 5946056000 # Cycle when the warmup percentage was hit. 47system.l2c.occ_blocks::writebacks 55675.727094 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 4768.395922 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 4867.683513 # Average occupied blocks per requestor 50system.l2c.occ_percent::writebacks 0.849544 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.074275 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.996579 # Average percentage of cache occupancy 54system.l2c.ReadReq_hits::cpu.inst 916208 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 814933 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1731141 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 835149 # number of Writeback hits 58system.l2c.Writeback_hits::total 835149 # number of Writeback hits | 25system.physmem.num_reads::total 443152 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115680 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115680 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 442620 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12935191 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1380145 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 14757955 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 442620 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 442620 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 3852403 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3852403 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3852403 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 442620 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 12935191 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1380145 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 18610359 # Total bandwidth to/from this memory (bytes/s) 41system.l2c.replacements 336240 # number of replacements 42system.l2c.tagsinuse 65308.066862 # Cycle average of tags in use 43system.l2c.total_refs 2448422 # Total number of references to valid blocks. 44system.l2c.sampled_refs 401402 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.099676 # Average number of references to valid blocks. 46system.l2c.warmup_cycle 6040304000 # Cycle when the warmup percentage was hit. 47system.l2c.occ_blocks::writebacks 55651.693971 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 4767.859045 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 4888.513847 # Average occupied blocks per requestor 50system.l2c.occ_percent::writebacks 0.849177 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.072752 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.074593 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.996522 # Average percentage of cache occupancy 54system.l2c.ReadReq_hits::cpu.inst 916493 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 814973 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1731466 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 835196 # number of Writeback hits 58system.l2c.Writeback_hits::total 835196 # number of Writeback hits |
59system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 59system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
61system.l2c.ReadExReq_hits::cpu.data 187605 # number of ReadExReq hits 62system.l2c.ReadExReq_hits::total 187605 # number of ReadExReq hits 63system.l2c.demand_hits::cpu.inst 916208 # number of demand (read+write) hits 64system.l2c.demand_hits::cpu.data 1002538 # number of demand (read+write) hits 65system.l2c.demand_hits::total 1918746 # number of demand (read+write) hits 66system.l2c.overall_hits::cpu.inst 916208 # number of overall hits 67system.l2c.overall_hits::cpu.data 1002538 # number of overall hits 68system.l2c.overall_hits::total 1918746 # number of overall hits 69system.l2c.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses 70system.l2c.ReadReq_misses::cpu.data 271915 # number of ReadReq misses 71system.l2c.ReadReq_misses::total 285207 # number of ReadReq misses | 61system.l2c.ReadExReq_hits::cpu.data 187534 # number of ReadExReq hits 62system.l2c.ReadExReq_hits::total 187534 # number of ReadExReq hits 63system.l2c.demand_hits::cpu.inst 916493 # number of demand (read+write) hits 64system.l2c.demand_hits::cpu.data 1002507 # number of demand (read+write) hits 65system.l2c.demand_hits::total 1919000 # number of demand (read+write) hits 66system.l2c.overall_hits::cpu.inst 916493 # number of overall hits 67system.l2c.overall_hits::cpu.data 1002507 # number of overall hits 68system.l2c.overall_hits::total 1919000 # number of overall hits 69system.l2c.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses 70system.l2c.ReadReq_misses::cpu.data 271963 # number of ReadReq misses 71system.l2c.ReadReq_misses::total 285254 # number of ReadReq misses |
72system.l2c.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses 73system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses | 72system.l2c.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses 73system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses |
74system.l2c.ReadExReq_misses::cpu.data 116718 # number of ReadExReq misses 75system.l2c.ReadExReq_misses::total 116718 # number of ReadExReq misses 76system.l2c.demand_misses::cpu.inst 13292 # number of demand (read+write) misses 77system.l2c.demand_misses::cpu.data 388633 # number of demand (read+write) misses 78system.l2c.demand_misses::total 401925 # number of demand (read+write) misses 79system.l2c.overall_misses::cpu.inst 13292 # number of overall misses 80system.l2c.overall_misses::cpu.data 388633 # number of overall misses 81system.l2c.overall_misses::total 401925 # number of overall misses 82system.l2c.ReadReq_miss_latency::cpu.inst 691773000 # number of ReadReq miss cycles 83system.l2c.ReadReq_miss_latency::cpu.data 14144855000 # number of ReadReq miss cycles 84system.l2c.ReadReq_miss_latency::total 14836628000 # number of ReadReq miss cycles | 74system.l2c.ReadExReq_misses::cpu.data 116845 # number of ReadExReq misses 75system.l2c.ReadExReq_misses::total 116845 # number of ReadExReq misses 76system.l2c.demand_misses::cpu.inst 13291 # number of demand (read+write) misses 77system.l2c.demand_misses::cpu.data 388808 # number of demand (read+write) misses 78system.l2c.demand_misses::total 402099 # number of demand (read+write) misses 79system.l2c.overall_misses::cpu.inst 13291 # number of overall misses 80system.l2c.overall_misses::cpu.data 388808 # number of overall misses 81system.l2c.overall_misses::total 402099 # number of overall misses 82system.l2c.ReadReq_miss_latency::cpu.inst 691744000 # number of ReadReq miss cycles 83system.l2c.ReadReq_miss_latency::cpu.data 14147302000 # number of ReadReq miss cycles 84system.l2c.ReadReq_miss_latency::total 14839046000 # number of ReadReq miss cycles |
85system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles 86system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles | 85system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles 86system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles |
87system.l2c.ReadExReq_miss_latency::cpu.data 6070015000 # number of ReadExReq miss cycles 88system.l2c.ReadExReq_miss_latency::total 6070015000 # number of ReadExReq miss cycles 89system.l2c.demand_miss_latency::cpu.inst 691773000 # number of demand (read+write) miss cycles 90system.l2c.demand_miss_latency::cpu.data 20214870000 # number of demand (read+write) miss cycles 91system.l2c.demand_miss_latency::total 20906643000 # number of demand (read+write) miss cycles 92system.l2c.overall_miss_latency::cpu.inst 691773000 # number of overall miss cycles 93system.l2c.overall_miss_latency::cpu.data 20214870000 # number of overall miss cycles 94system.l2c.overall_miss_latency::total 20906643000 # number of overall miss cycles 95system.l2c.ReadReq_accesses::cpu.inst 929500 # number of ReadReq accesses(hits+misses) 96system.l2c.ReadReq_accesses::cpu.data 1086848 # number of ReadReq accesses(hits+misses) 97system.l2c.ReadReq_accesses::total 2016348 # number of ReadReq accesses(hits+misses) 98system.l2c.Writeback_accesses::writebacks 835149 # number of Writeback accesses(hits+misses) 99system.l2c.Writeback_accesses::total 835149 # number of Writeback accesses(hits+misses) | 87system.l2c.ReadExReq_miss_latency::cpu.data 6076563000 # number of ReadExReq miss cycles 88system.l2c.ReadExReq_miss_latency::total 6076563000 # number of ReadExReq miss cycles 89system.l2c.demand_miss_latency::cpu.inst 691744000 # number of demand (read+write) miss cycles 90system.l2c.demand_miss_latency::cpu.data 20223865000 # number of demand (read+write) miss cycles 91system.l2c.demand_miss_latency::total 20915609000 # number of demand (read+write) miss cycles 92system.l2c.overall_miss_latency::cpu.inst 691744000 # number of overall miss cycles 93system.l2c.overall_miss_latency::cpu.data 20223865000 # number of overall miss cycles 94system.l2c.overall_miss_latency::total 20915609000 # number of overall miss cycles 95system.l2c.ReadReq_accesses::cpu.inst 929784 # number of ReadReq accesses(hits+misses) 96system.l2c.ReadReq_accesses::cpu.data 1086936 # number of ReadReq accesses(hits+misses) 97system.l2c.ReadReq_accesses::total 2016720 # number of ReadReq accesses(hits+misses) 98system.l2c.Writeback_accesses::writebacks 835196 # number of Writeback accesses(hits+misses) 99system.l2c.Writeback_accesses::total 835196 # number of Writeback accesses(hits+misses) |
100system.l2c.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) 101system.l2c.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) | 100system.l2c.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) 101system.l2c.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) |
102system.l2c.ReadExReq_accesses::cpu.data 304323 # number of ReadExReq accesses(hits+misses) 103system.l2c.ReadExReq_accesses::total 304323 # number of ReadExReq accesses(hits+misses) 104system.l2c.demand_accesses::cpu.inst 929500 # number of demand (read+write) accesses 105system.l2c.demand_accesses::cpu.data 1391171 # number of demand (read+write) accesses 106system.l2c.demand_accesses::total 2320671 # number of demand (read+write) accesses 107system.l2c.overall_accesses::cpu.inst 929500 # number of overall (read+write) accesses 108system.l2c.overall_accesses::cpu.data 1391171 # number of overall (read+write) accesses 109system.l2c.overall_accesses::total 2320671 # number of overall (read+write) accesses 110system.l2c.ReadReq_miss_rate::cpu.inst 0.014300 # miss rate for ReadReq accesses 111system.l2c.ReadReq_miss_rate::cpu.data 0.250187 # miss rate for ReadReq accesses 112system.l2c.ReadReq_miss_rate::total 0.141447 # miss rate for ReadReq accesses | 102system.l2c.ReadExReq_accesses::cpu.data 304379 # number of ReadExReq accesses(hits+misses) 103system.l2c.ReadExReq_accesses::total 304379 # number of ReadExReq accesses(hits+misses) 104system.l2c.demand_accesses::cpu.inst 929784 # number of demand (read+write) accesses 105system.l2c.demand_accesses::cpu.data 1391315 # number of demand (read+write) accesses 106system.l2c.demand_accesses::total 2321099 # number of demand (read+write) accesses 107system.l2c.overall_accesses::cpu.inst 929784 # number of overall (read+write) accesses 108system.l2c.overall_accesses::cpu.data 1391315 # number of overall (read+write) accesses 109system.l2c.overall_accesses::total 2321099 # number of overall (read+write) accesses 110system.l2c.ReadReq_miss_rate::cpu.inst 0.014295 # miss rate for ReadReq accesses 111system.l2c.ReadReq_miss_rate::cpu.data 0.250211 # miss rate for ReadReq accesses 112system.l2c.ReadReq_miss_rate::total 0.141445 # miss rate for ReadReq accesses |
113system.l2c.UpgradeReq_miss_rate::cpu.data 0.777778 # miss rate for UpgradeReq accesses 114system.l2c.UpgradeReq_miss_rate::total 0.777778 # miss rate for UpgradeReq accesses | 113system.l2c.UpgradeReq_miss_rate::cpu.data 0.777778 # miss rate for UpgradeReq accesses 114system.l2c.UpgradeReq_miss_rate::total 0.777778 # miss rate for UpgradeReq accesses |
115system.l2c.ReadExReq_miss_rate::cpu.data 0.383533 # miss rate for ReadExReq accesses 116system.l2c.ReadExReq_miss_rate::total 0.383533 # miss rate for ReadExReq accesses 117system.l2c.demand_miss_rate::cpu.inst 0.014300 # miss rate for demand accesses 118system.l2c.demand_miss_rate::cpu.data 0.279357 # miss rate for demand accesses 119system.l2c.demand_miss_rate::total 0.173193 # miss rate for demand accesses 120system.l2c.overall_miss_rate::cpu.inst 0.014300 # miss rate for overall accesses 121system.l2c.overall_miss_rate::cpu.data 0.279357 # miss rate for overall accesses 122system.l2c.overall_miss_rate::total 0.173193 # miss rate for overall accesses 123system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368 # average ReadReq miss latency 124system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445 # average ReadReq miss latency 125system.l2c.ReadReq_avg_miss_latency::total 52020.560505 # average ReadReq miss latency | 115system.l2c.ReadExReq_miss_rate::cpu.data 0.383880 # miss rate for ReadExReq accesses 116system.l2c.ReadExReq_miss_rate::total 0.383880 # miss rate for ReadExReq accesses 117system.l2c.demand_miss_rate::cpu.inst 0.014295 # miss rate for demand accesses 118system.l2c.demand_miss_rate::cpu.data 0.279454 # miss rate for demand accesses 119system.l2c.demand_miss_rate::total 0.173236 # miss rate for demand accesses 120system.l2c.overall_miss_rate::cpu.inst 0.014295 # miss rate for overall accesses 121system.l2c.overall_miss_rate::cpu.data 0.279454 # miss rate for overall accesses 122system.l2c.overall_miss_rate::total 0.173236 # miss rate for overall accesses 123system.l2c.ReadReq_avg_miss_latency::cpu.inst 52046.046197 # average ReadReq miss latency 124system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.215849 # average ReadReq miss latency 125system.l2c.ReadReq_avg_miss_latency::total 52020.465971 # average ReadReq miss latency |
126system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857 # average UpgradeReq miss latency 127system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857 # average UpgradeReq miss latency | 126system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857 # average UpgradeReq miss latency 127system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857 # average UpgradeReq miss latency |
128system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817440 # average ReadExReq miss latency 129system.l2c.ReadExReq_avg_miss_latency::total 52005.817440 # average ReadExReq miss latency 130system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency 131system.l2c.demand_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency 132system.l2c.demand_avg_miss_latency::total 52016.279157 # average overall miss latency 133system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency 134system.l2c.overall_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency 135system.l2c.overall_avg_miss_latency::total 52016.279157 # average overall miss latency | 128system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.331850 # average ReadExReq miss latency 129system.l2c.ReadExReq_avg_miss_latency::total 52005.331850 # average ReadExReq miss latency 130system.l2c.demand_avg_miss_latency::cpu.inst 52046.046197 # average overall miss latency 131system.l2c.demand_avg_miss_latency::cpu.data 52015.043415 # average overall miss latency 132system.l2c.demand_avg_miss_latency::total 52016.068182 # average overall miss latency 133system.l2c.overall_avg_miss_latency::cpu.inst 52046.046197 # average overall miss latency 134system.l2c.overall_avg_miss_latency::cpu.data 52015.043415 # average overall miss latency 135system.l2c.overall_avg_miss_latency::total 52016.068182 # average overall miss latency |
136system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 137system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 138system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 139system.l2c.blocked::no_targets 0 # number of cycles access was blocked 140system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 141system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 142system.l2c.fast_writes 0 # number of fast writes performed 143system.l2c.cache_copies 0 # number of cache copies performed | 136system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 137system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 138system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 139system.l2c.blocked::no_targets 0 # number of cycles access was blocked 140system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 141system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 142system.l2c.fast_writes 0 # number of fast writes performed 143system.l2c.cache_copies 0 # number of cache copies performed |
144system.l2c.writebacks::writebacks 73942 # number of writebacks 145system.l2c.writebacks::total 73942 # number of writebacks 146system.l2c.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses 147system.l2c.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses 148system.l2c.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses | 144system.l2c.writebacks::writebacks 74168 # number of writebacks 145system.l2c.writebacks::total 74168 # number of writebacks 146system.l2c.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses 147system.l2c.ReadReq_mshr_misses::cpu.data 271963 # number of ReadReq MSHR misses 148system.l2c.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses |
149system.l2c.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses 150system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses | 149system.l2c.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses 150system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses |
151system.l2c.ReadExReq_mshr_misses::cpu.data 116718 # number of ReadExReq MSHR misses 152system.l2c.ReadExReq_mshr_misses::total 116718 # number of ReadExReq MSHR misses 153system.l2c.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses 154system.l2c.demand_mshr_misses::cpu.data 388633 # number of demand (read+write) MSHR misses 155system.l2c.demand_mshr_misses::total 401925 # number of demand (read+write) MSHR misses 156system.l2c.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses 157system.l2c.overall_mshr_misses::cpu.data 388633 # number of overall MSHR misses 158system.l2c.overall_mshr_misses::total 401925 # number of overall MSHR misses 159system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532266000 # number of ReadReq MSHR miss cycles 160system.l2c.ReadReq_mshr_miss_latency::cpu.data 10881875000 # number of ReadReq MSHR miss cycles 161system.l2c.ReadReq_mshr_miss_latency::total 11414141000 # number of ReadReq MSHR miss cycles | 151system.l2c.ReadExReq_mshr_misses::cpu.data 116845 # number of ReadExReq MSHR misses 152system.l2c.ReadExReq_mshr_misses::total 116845 # number of ReadExReq MSHR misses 153system.l2c.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses 154system.l2c.demand_mshr_misses::cpu.data 388808 # number of demand (read+write) MSHR misses 155system.l2c.demand_mshr_misses::total 402099 # number of demand (read+write) MSHR misses 156system.l2c.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses 157system.l2c.overall_mshr_misses::cpu.data 388808 # number of overall MSHR misses 158system.l2c.overall_mshr_misses::total 402099 # number of overall MSHR misses 159system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532249000 # number of ReadReq MSHR miss cycles 160system.l2c.ReadReq_mshr_miss_latency::cpu.data 10883746000 # number of ReadReq MSHR miss cycles 161system.l2c.ReadReq_mshr_miss_latency::total 11415995000 # number of ReadReq MSHR miss cycles |
162system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 620000 # number of UpgradeReq MSHR miss cycles 163system.l2c.UpgradeReq_mshr_miss_latency::total 620000 # number of UpgradeReq MSHR miss cycles | 162system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 620000 # number of UpgradeReq MSHR miss cycles 163system.l2c.UpgradeReq_mshr_miss_latency::total 620000 # number of UpgradeReq MSHR miss cycles |
164system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669399000 # number of ReadExReq MSHR miss cycles 165system.l2c.ReadExReq_mshr_miss_latency::total 4669399000 # number of ReadExReq MSHR miss cycles 166system.l2c.demand_mshr_miss_latency::cpu.inst 532266000 # number of demand (read+write) MSHR miss cycles 167system.l2c.demand_mshr_miss_latency::cpu.data 15551274000 # number of demand (read+write) MSHR miss cycles 168system.l2c.demand_mshr_miss_latency::total 16083540000 # number of demand (read+write) MSHR miss cycles 169system.l2c.overall_mshr_miss_latency::cpu.inst 532266000 # number of overall MSHR miss cycles 170system.l2c.overall_mshr_miss_latency::cpu.data 15551274000 # number of overall MSHR miss cycles 171system.l2c.overall_mshr_miss_latency::total 16083540000 # number of overall MSHR miss cycles 172system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772639030 # number of ReadReq MSHR uncacheable cycles 173system.l2c.ReadReq_mshr_uncacheable_latency::total 772639030 # number of ReadReq MSHR uncacheable cycles 174system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1072677000 # number of WriteReq MSHR uncacheable cycles 175system.l2c.WriteReq_mshr_uncacheable_latency::total 1072677000 # number of WriteReq MSHR uncacheable cycles 176system.l2c.overall_mshr_uncacheable_latency::cpu.data 1845316030 # number of overall MSHR uncacheable cycles 177system.l2c.overall_mshr_uncacheable_latency::total 1845316030 # number of overall MSHR uncacheable cycles 178system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for ReadReq accesses 179system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250187 # mshr miss rate for ReadReq accesses 180system.l2c.ReadReq_mshr_miss_rate::total 0.141447 # mshr miss rate for ReadReq accesses | 164system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4674423000 # number of ReadExReq MSHR miss cycles 165system.l2c.ReadExReq_mshr_miss_latency::total 4674423000 # number of ReadExReq MSHR miss cycles 166system.l2c.demand_mshr_miss_latency::cpu.inst 532249000 # number of demand (read+write) MSHR miss cycles 167system.l2c.demand_mshr_miss_latency::cpu.data 15558169000 # number of demand (read+write) MSHR miss cycles 168system.l2c.demand_mshr_miss_latency::total 16090418000 # number of demand (read+write) MSHR miss cycles 169system.l2c.overall_mshr_miss_latency::cpu.inst 532249000 # number of overall MSHR miss cycles 170system.l2c.overall_mshr_miss_latency::cpu.data 15558169000 # number of overall MSHR miss cycles 171system.l2c.overall_mshr_miss_latency::total 16090418000 # number of overall MSHR miss cycles 172system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 1331550000 # number of ReadReq MSHR uncacheable cycles 173system.l2c.ReadReq_mshr_uncacheable_latency::total 1331550000 # number of ReadReq MSHR uncacheable cycles 174system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1893145000 # number of WriteReq MSHR uncacheable cycles 175system.l2c.WriteReq_mshr_uncacheable_latency::total 1893145000 # number of WriteReq MSHR uncacheable cycles 176system.l2c.overall_mshr_uncacheable_latency::cpu.data 3224695000 # number of overall MSHR uncacheable cycles 177system.l2c.overall_mshr_uncacheable_latency::total 3224695000 # number of overall MSHR uncacheable cycles 178system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for ReadReq accesses 179system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250211 # mshr miss rate for ReadReq accesses 180system.l2c.ReadReq_mshr_miss_rate::total 0.141445 # mshr miss rate for ReadReq accesses |
181system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.777778 # mshr miss rate for UpgradeReq accesses 182system.l2c.UpgradeReq_mshr_miss_rate::total 0.777778 # mshr miss rate for UpgradeReq accesses | 181system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.777778 # mshr miss rate for UpgradeReq accesses 182system.l2c.UpgradeReq_mshr_miss_rate::total 0.777778 # mshr miss rate for UpgradeReq accesses |
183system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383533 # mshr miss rate for ReadExReq accesses 184system.l2c.ReadExReq_mshr_miss_rate::total 0.383533 # mshr miss rate for ReadExReq accesses 185system.l2c.demand_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for demand accesses 186system.l2c.demand_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for demand accesses 187system.l2c.demand_mshr_miss_rate::total 0.173193 # mshr miss rate for demand accesses 188system.l2c.overall_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for overall accesses 189system.l2c.overall_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for overall accesses 190system.l2c.overall_mshr_miss_rate::total 0.173193 # mshr miss rate for overall accesses 191system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669 # average ReadReq mshr miss latency 192system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445 # average ReadReq mshr miss latency 193system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987 # average ReadReq mshr miss latency | 183system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383880 # mshr miss rate for ReadExReq accesses 184system.l2c.ReadExReq_mshr_miss_rate::total 0.383880 # mshr miss rate for ReadExReq accesses 185system.l2c.demand_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for demand accesses 186system.l2c.demand_mshr_miss_rate::cpu.data 0.279454 # mshr miss rate for demand accesses 187system.l2c.demand_mshr_miss_rate::total 0.173236 # mshr miss rate for demand accesses 188system.l2c.overall_mshr_miss_rate::cpu.inst 0.014295 # mshr miss rate for overall accesses 189system.l2c.overall_mshr_miss_rate::cpu.data 0.279454 # mshr miss rate for overall accesses 190system.l2c.overall_mshr_miss_rate::total 0.173236 # mshr miss rate for overall accesses 191system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.820480 # average ReadReq mshr miss latency 192system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.215849 # average ReadReq mshr miss latency 193system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.455454 # average ReadReq mshr miss latency |
194system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286 # average UpgradeReq mshr miss latency 195system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286 # average UpgradeReq mshr miss latency | 194system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286 # average UpgradeReq mshr miss latency 195system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286 # average UpgradeReq mshr miss latency |
196system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817440 # average ReadExReq mshr miss latency 197system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817440 # average ReadExReq mshr miss latency 198system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency 199system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency 200system.l2c.demand_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency 201system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency 202system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency 203system.l2c.overall_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency | 196system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.331850 # average ReadExReq mshr miss latency 197system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.331850 # average ReadExReq mshr miss latency 198system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.820480 # average overall mshr miss latency 199system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.043415 # average overall mshr miss latency 200system.l2c.demand_avg_mshr_miss_latency::total 40016.060721 # average overall mshr miss latency 201system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.820480 # average overall mshr miss latency 202system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.043415 # average overall mshr miss latency 203system.l2c.overall_avg_mshr_miss_latency::total 40016.060721 # average overall mshr miss latency |
204system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 205system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 206system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 207system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 208system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 209system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 210system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 211system.iocache.replacements 41685 # number of replacements | 204system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 205system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 206system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 207system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 208system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 209system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 210system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 211system.iocache.replacements 41685 # number of replacements |
212system.iocache.tagsinuse 1.356968 # Cycle average of tags in use | 212system.iocache.tagsinuse 1.355427 # Cycle average of tags in use |
213system.iocache.total_refs 0 # Total number of references to valid blocks. 214system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 215system.iocache.avg_refs 0 # Average number of references to valid blocks. | 213system.iocache.total_refs 0 # Total number of references to valid blocks. 214system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 215system.iocache.avg_refs 0 # Average number of references to valid blocks. |
216system.iocache.warmup_cycle 1753491316000 # Cycle when the warmup percentage was hit. 217system.iocache.occ_blocks::tsunami.ide 1.356968 # Average occupied blocks per requestor 218system.iocache.occ_percent::tsunami.ide 0.084811 # Average percentage of cache occupancy 219system.iocache.occ_percent::total 0.084811 # Average percentage of cache occupancy | 216system.iocache.warmup_cycle 1754498131000 # Cycle when the warmup percentage was hit. 217system.iocache.occ_blocks::tsunami.ide 1.355427 # Average occupied blocks per requestor 218system.iocache.occ_percent::tsunami.ide 0.084714 # Average percentage of cache occupancy 219system.iocache.occ_percent::total 0.084714 # Average percentage of cache occupancy |
220system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 221system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 222system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 223system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 224system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 225system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 226system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 227system.iocache.overall_misses::total 41725 # number of overall misses 228system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 229system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles | 220system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 221system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 222system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 223system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 224system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 225system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 226system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 227system.iocache.overall_misses::total 41725 # number of overall misses 228system.iocache.ReadReq_miss_latency::tsunami.ide 20672998 # number of ReadReq miss cycles 229system.iocache.ReadReq_miss_latency::total 20672998 # number of ReadReq miss cycles |
230system.iocache.WriteReq_miss_latency::tsunami.ide 7638105806 # number of WriteReq miss cycles 231system.iocache.WriteReq_miss_latency::total 7638105806 # number of WriteReq miss cycles 232system.iocache.demand_miss_latency::tsunami.ide 7658778804 # number of demand (read+write) miss cycles 233system.iocache.demand_miss_latency::total 7658778804 # number of demand (read+write) miss cycles 234system.iocache.overall_miss_latency::tsunami.ide 7658778804 # number of overall miss cycles 235system.iocache.overall_miss_latency::total 7658778804 # number of overall miss cycles | 230system.iocache.WriteReq_miss_latency::tsunami.ide 7634106806 # number of WriteReq miss cycles 231system.iocache.WriteReq_miss_latency::total 7634106806 # number of WriteReq miss cycles 232system.iocache.demand_miss_latency::tsunami.ide 7654779804 # number of demand (read+write) miss cycles 233system.iocache.demand_miss_latency::total 7654779804 # number of demand (read+write) miss cycles 234system.iocache.overall_miss_latency::tsunami.ide 7654779804 # number of overall miss cycles 235system.iocache.overall_miss_latency::total 7654779804 # number of overall miss cycles |
236system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 237system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 238system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 239system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 240system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 241system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 242system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 243system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 244system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 245system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 246system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 247system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 248system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 249system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 250system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 251system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 252system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 253system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency | 236system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 237system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 238system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 239system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 240system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 241system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 242system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 243system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 244system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 245system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 246system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 247system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 248system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 249system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 250system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 251system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 252system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency 253system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency |
254system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183820.413121 # average WriteReq miss latency 255system.iocache.WriteReq_avg_miss_latency::total 183820.413121 # average WriteReq miss latency 256system.iocache.demand_avg_miss_latency::tsunami.ide 183553.716093 # average overall miss latency 257system.iocache.demand_avg_miss_latency::total 183553.716093 # average overall miss latency 258system.iocache.overall_avg_miss_latency::tsunami.ide 183553.716093 # average overall miss latency 259system.iocache.overall_avg_miss_latency::total 183553.716093 # average overall miss latency 260system.iocache.blocked_cycles::no_mshrs 7453000 # number of cycles access was blocked | 254system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183724.172266 # average WriteReq miss latency 255system.iocache.WriteReq_avg_miss_latency::total 183724.172266 # average WriteReq miss latency 256system.iocache.demand_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency 257system.iocache.demand_avg_miss_latency::total 183457.874272 # average overall miss latency 258system.iocache.overall_avg_miss_latency::tsunami.ide 183457.874272 # average overall miss latency 259system.iocache.overall_avg_miss_latency::total 183457.874272 # average overall miss latency 260system.iocache.blocked_cycles::no_mshrs 7454000 # number of cycles access was blocked |
261system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 261system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
262system.iocache.blocked::no_mshrs 7118 # number of cycles access was blocked | 262system.iocache.blocked::no_mshrs 7097 # number of cycles access was blocked |
263system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 263system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
264system.iocache.avg_blocked_cycles::no_mshrs 1047.063782 # average number of cycles each access was blocked | 264system.iocache.avg_blocked_cycles::no_mshrs 1050.302945 # average number of cycles each access was blocked |
265system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 266system.iocache.fast_writes 0 # number of fast writes performed 267system.iocache.cache_copies 0 # number of cache copies performed 268system.iocache.writebacks::writebacks 41512 # number of writebacks 269system.iocache.writebacks::total 41512 # number of writebacks 270system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 271system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 272system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 273system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 274system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 275system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 276system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 277system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 278system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 279system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles | 265system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 266system.iocache.fast_writes 0 # number of fast writes performed 267system.iocache.cache_copies 0 # number of cache copies performed 268system.iocache.writebacks::writebacks 41512 # number of writebacks 269system.iocache.writebacks::total 41512 # number of writebacks 270system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 271system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 272system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 273system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 274system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 275system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 276system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 277system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 278system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles 279system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles |
280system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5477251000 # number of WriteReq MSHR miss cycles 281system.iocache.WriteReq_mshr_miss_latency::total 5477251000 # number of WriteReq MSHR miss cycles 282system.iocache.demand_mshr_miss_latency::tsunami.ide 5488927000 # number of demand (read+write) MSHR miss cycles 283system.iocache.demand_mshr_miss_latency::total 5488927000 # number of demand (read+write) MSHR miss cycles 284system.iocache.overall_mshr_miss_latency::tsunami.ide 5488927000 # number of overall MSHR miss cycles 285system.iocache.overall_mshr_miss_latency::total 5488927000 # number of overall MSHR miss cycles | 280system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5473252000 # number of WriteReq MSHR miss cycles 281system.iocache.WriteReq_mshr_miss_latency::total 5473252000 # number of WriteReq MSHR miss cycles 282system.iocache.demand_mshr_miss_latency::tsunami.ide 5484928000 # number of demand (read+write) MSHR miss cycles 283system.iocache.demand_mshr_miss_latency::total 5484928000 # number of demand (read+write) MSHR miss cycles 284system.iocache.overall_mshr_miss_latency::tsunami.ide 5484928000 # number of overall MSHR miss cycles 285system.iocache.overall_mshr_miss_latency::total 5484928000 # number of overall MSHR miss cycles |
286system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 287system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 288system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 289system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 290system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 291system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 292system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 293system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 294system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 295system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency | 286system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 287system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 288system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 289system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 290system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 291system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 292system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 293system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 294system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency 295system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency |
296system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131816.783789 # average WriteReq mshr miss latency 297system.iocache.WriteReq_avg_mshr_miss_latency::total 131816.783789 # average WriteReq mshr miss latency 298system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131550.077891 # average overall mshr miss latency 299system.iocache.demand_avg_mshr_miss_latency::total 131550.077891 # average overall mshr miss latency 300system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131550.077891 # average overall mshr miss latency 301system.iocache.overall_avg_mshr_miss_latency::total 131550.077891 # average overall mshr miss latency | 296system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131720.542934 # average WriteReq mshr miss latency 297system.iocache.WriteReq_avg_mshr_miss_latency::total 131720.542934 # average WriteReq mshr miss latency 298system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency 299system.iocache.demand_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency 300system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131454.236070 # average overall mshr miss latency 301system.iocache.overall_avg_mshr_miss_latency::total 131454.236070 # average overall mshr miss latency |
302system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 303system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 304system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 305system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 306system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 307system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 308system.disk0.dma_write_txs 395 # Number of DMA write transactions. 309system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 310system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 311system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 312system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 313system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 314system.disk2.dma_write_txs 1 # Number of DMA write transactions. 315system.cpu.dtb.fetch_hits 0 # ITB hits 316system.cpu.dtb.fetch_misses 0 # ITB misses 317system.cpu.dtb.fetch_acv 0 # ITB acv 318system.cpu.dtb.fetch_accesses 0 # ITB accesses | 302system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 303system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 304system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 305system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 306system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 307system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 308system.disk0.dma_write_txs 395 # Number of DMA write transactions. 309system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 310system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 311system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 312system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 313system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 314system.disk2.dma_write_txs 1 # Number of DMA write transactions. 315system.cpu.dtb.fetch_hits 0 # ITB hits 316system.cpu.dtb.fetch_misses 0 # ITB misses 317system.cpu.dtb.fetch_acv 0 # ITB acv 318system.cpu.dtb.fetch_accesses 0 # ITB accesses |
319system.cpu.dtb.read_hits 9065773 # DTB read hits | 319system.cpu.dtb.read_hits 9066933 # DTB read hits |
320system.cpu.dtb.read_misses 10329 # DTB read misses 321system.cpu.dtb.read_acv 210 # DTB read access violations 322system.cpu.dtb.read_accesses 728856 # DTB read accesses | 320system.cpu.dtb.read_misses 10329 # DTB read misses 321system.cpu.dtb.read_acv 210 # DTB read access violations 322system.cpu.dtb.read_accesses 728856 # DTB read accesses |
323system.cpu.dtb.write_hits 6357048 # DTB write hits | 323system.cpu.dtb.write_hits 6357519 # DTB write hits |
324system.cpu.dtb.write_misses 1142 # DTB write misses 325system.cpu.dtb.write_acv 157 # DTB write access violations 326system.cpu.dtb.write_accesses 291931 # DTB write accesses | 324system.cpu.dtb.write_misses 1142 # DTB write misses 325system.cpu.dtb.write_acv 157 # DTB write access violations 326system.cpu.dtb.write_accesses 291931 # DTB write accesses |
327system.cpu.dtb.data_hits 15422821 # DTB hits | 327system.cpu.dtb.data_hits 15424452 # DTB hits |
328system.cpu.dtb.data_misses 11471 # DTB misses 329system.cpu.dtb.data_acv 367 # DTB access violations 330system.cpu.dtb.data_accesses 1020787 # DTB accesses | 328system.cpu.dtb.data_misses 11471 # DTB misses 329system.cpu.dtb.data_acv 367 # DTB access violations 330system.cpu.dtb.data_accesses 1020787 # DTB accesses |
331system.cpu.itb.fetch_hits 4975760 # ITB hits | 331system.cpu.itb.fetch_hits 4975863 # ITB hits |
332system.cpu.itb.fetch_misses 5006 # ITB misses 333system.cpu.itb.fetch_acv 184 # ITB acv | 332system.cpu.itb.fetch_misses 5006 # ITB misses 333system.cpu.itb.fetch_acv 184 # ITB acv |
334system.cpu.itb.fetch_accesses 4980766 # ITB accesses | 334system.cpu.itb.fetch_accesses 4980869 # ITB accesses |
335system.cpu.itb.read_hits 0 # DTB read hits 336system.cpu.itb.read_misses 0 # DTB read misses 337system.cpu.itb.read_acv 0 # DTB read access violations 338system.cpu.itb.read_accesses 0 # DTB read accesses 339system.cpu.itb.write_hits 0 # DTB write hits 340system.cpu.itb.write_misses 0 # DTB write misses 341system.cpu.itb.write_acv 0 # DTB write access violations 342system.cpu.itb.write_accesses 0 # DTB write accesses 343system.cpu.itb.data_hits 0 # DTB hits 344system.cpu.itb.data_misses 0 # DTB misses 345system.cpu.itb.data_acv 0 # DTB access violations 346system.cpu.itb.data_accesses 0 # DTB accesses | 335system.cpu.itb.read_hits 0 # DTB read hits 336system.cpu.itb.read_misses 0 # DTB read misses 337system.cpu.itb.read_acv 0 # DTB read access violations 338system.cpu.itb.read_accesses 0 # DTB read accesses 339system.cpu.itb.write_hits 0 # DTB write hits 340system.cpu.itb.write_misses 0 # DTB write misses 341system.cpu.itb.write_acv 0 # DTB write access violations 342system.cpu.itb.write_accesses 0 # DTB write accesses 343system.cpu.itb.data_hits 0 # DTB hits 344system.cpu.itb.data_misses 0 # DTB misses 345system.cpu.itb.data_acv 0 # DTB access violations 346system.cpu.itb.data_accesses 0 # DTB accesses |
347system.cpu.numCycles 3841706084 # number of cpu cycles simulated | 347system.cpu.numCycles 3843584976 # number of cpu cycles simulated |
348system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 349system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 348system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 349system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
350system.cpu.committedInsts 56187824 # Number of instructions committed 351system.cpu.committedOps 56187824 # Number of ops (including micro ops) committed 352system.cpu.num_int_alu_accesses 52059470 # Number of integer alu accesses 353system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 354system.cpu.num_func_calls 1483670 # number of times a function call or return occured 355system.cpu.num_conditional_control_insts 6469221 # number of instructions that are conditional controls 356system.cpu.num_int_insts 52059470 # number of integer instructions 357system.cpu.num_fp_insts 324460 # number of float instructions 358system.cpu.num_int_register_reads 71329755 # number of times the integer registers were read 359system.cpu.num_int_register_writes 38524240 # number of times the integer registers were written 360system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 361system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 362system.cpu.num_mem_refs 15475451 # number of memory refs 363system.cpu.num_load_insts 9102635 # Number of load instructions 364system.cpu.num_store_insts 6372816 # Number of store instructions 365system.cpu.num_idle_cycles 3589579952.998131 # Number of idle cycles 366system.cpu.num_busy_cycles 252126131.001869 # Number of busy cycles 367system.cpu.not_idle_fraction 0.065629 # Percentage of non-idle cycles 368system.cpu.idle_fraction 0.934371 # Percentage of idle cycles | 350system.cpu.committedInsts 56195476 # Number of instructions committed 351system.cpu.committedOps 56195476 # Number of ops (including micro ops) committed 352system.cpu.num_int_alu_accesses 52066692 # Number of integer alu accesses 353system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses 354system.cpu.num_func_calls 1483822 # number of times a function call or return occured 355system.cpu.num_conditional_control_insts 6469666 # number of instructions that are conditional controls 356system.cpu.num_int_insts 52066692 # number of integer instructions 357system.cpu.num_fp_insts 324259 # number of float instructions 358system.cpu.num_int_register_reads 71339619 # number of times the integer registers were read 359system.cpu.num_int_register_writes 38530592 # number of times the integer registers were written 360system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read 361system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written 362system.cpu.num_mem_refs 15477059 # number of memory refs 363system.cpu.num_load_insts 9103780 # Number of load instructions 364system.cpu.num_store_insts 6373279 # Number of store instructions 365system.cpu.num_idle_cycles 3588655153.998133 # Number of idle cycles 366system.cpu.num_busy_cycles 254929822.001867 # Number of busy cycles 367system.cpu.not_idle_fraction 0.066326 # Percentage of non-idle cycles 368system.cpu.idle_fraction 0.933674 # Percentage of idle cycles |
369system.cpu.kern.inst.arm 0 # number of arm instructions executed | 369system.cpu.kern.inst.arm 0 # number of arm instructions executed |
370system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 371system.cpu.kern.inst.hwrei 212104 # number of hwrei instructions executed 372system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl | 370system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed 371system.cpu.kern.inst.hwrei 212119 # number of hwrei instructions executed 372system.cpu.kern.ipl_count::0 74932 40.88% 40.88% # number of times we switched to this ipl |
373system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl | 373system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl |
374system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl 375system.cpu.kern.ipl_count::31 106285 57.99% 100.00% # number of times we switched to this ipl 376system.cpu.kern.ipl_count::total 183281 # number of times we switched to this ipl 377system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl 378system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 379system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl 380system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl 381system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl 382system.cpu.kern.ipl_ticks::0 1861395652500 96.90% 96.90% # number of cycles we spent at this ipl 383system.cpu.kern.ipl_ticks::21 90398000 0.00% 96.91% # number of cycles we spent at this ipl 384system.cpu.kern.ipl_ticks::22 587366500 0.03% 96.94% # number of cycles we spent at this ipl 385system.cpu.kern.ipl_ticks::31 58778792000 3.06% 100.00% # number of cycles we spent at this ipl 386system.cpu.kern.ipl_ticks::total 1920852209000 # number of cycles we spent at this ipl 387system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl | 374system.cpu.kern.ipl_count::22 1937 1.06% 42.01% # number of times we switched to this ipl 375system.cpu.kern.ipl_count::31 106298 57.99% 100.00% # number of times we switched to this ipl 376system.cpu.kern.ipl_count::total 183298 # number of times we switched to this ipl 377system.cpu.kern.ipl_good::0 73565 49.31% 49.31% # number of times we switched to this ipl from a different ipl 378system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl 379system.cpu.kern.ipl_good::22 1937 1.30% 50.69% # number of times we switched to this ipl from a different ipl 380system.cpu.kern.ipl_good::31 73565 49.31% 100.00% # number of times we switched to this ipl from a different ipl 381system.cpu.kern.ipl_good::total 149198 # number of times we switched to this ipl from a different ipl 382system.cpu.kern.ipl_ticks::0 1861046523500 96.84% 96.84% # number of cycles we spent at this ipl 383system.cpu.kern.ipl_ticks::21 104284500 0.01% 96.84% # number of cycles we spent at this ipl 384system.cpu.kern.ipl_ticks::22 779455000 0.04% 96.89% # number of cycles we spent at this ipl 385system.cpu.kern.ipl_ticks::31 59861392000 3.11% 100.00% # number of cycles we spent at this ipl 386system.cpu.kern.ipl_ticks::total 1921791655000 # number of cycles we spent at this ipl 387system.cpu.kern.ipl_used::0 0.981757 # fraction of swpipl calls that actually changed the ipl |
388system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 389system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 388system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 389system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
390system.cpu.kern.ipl_used::31 0.692120 # fraction of swpipl calls that actually changed the ipl 391system.cpu.kern.ipl_used::total 0.814001 # fraction of swpipl calls that actually changed the ipl | 390system.cpu.kern.ipl_used::31 0.692064 # fraction of swpipl calls that actually changed the ipl 391system.cpu.kern.ipl_used::total 0.813964 # fraction of swpipl calls that actually changed the ipl |
392system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 393system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 394system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 395system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 396system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 397system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 398system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 399system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 419system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 420system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 421system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 422system.cpu.kern.syscall::total 326 # number of syscalls executed 423system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 424system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 425system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 426system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 392system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 393system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 394system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 395system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 396system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 397system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 398system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 399system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 419system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 420system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 421system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 422system.cpu.kern.syscall::total 326 # number of syscalls executed 423system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 424system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 425system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 426system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
427system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed | 427system.cpu.kern.callpal::swpctx 4174 2.16% 2.16% # number of callpals executed |
428system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 429system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 428system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 429system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
430system.cpu.kern.callpal::swpipl 176052 91.22% 93.41% # number of callpals executed 431system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed | 430system.cpu.kern.callpal::swpipl 176067 91.22% 93.41% # number of callpals executed 431system.cpu.kern.callpal::rdps 6838 3.54% 96.96% # number of callpals executed |
432system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 433system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 434system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed 435system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed | 432system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 433system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 434system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed 435system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed |
436system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed | 436system.cpu.kern.callpal::rti 5162 2.67% 99.64% # number of callpals executed |
437system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 438system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 437system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 438system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
439system.cpu.kern.callpal::total 193007 # number of callpals executed 440system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches 441system.cpu.kern.mode_switch::user 1738 # number of protection mode switches 442system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches 443system.cpu.kern.mode_good::kernel 1908 444system.cpu.kern.mode_good::user 1738 445system.cpu.kern.mode_good::idle 170 446system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches | 439system.cpu.kern.callpal::total 193021 # number of callpals executed 440system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches 441system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 442system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 443system.cpu.kern.mode_good::kernel 1909 444system.cpu.kern.mode_good::user 1740 445system.cpu.kern.mode_good::idle 169 446system.cpu.kern.mode_switch_good::kernel 0.323285 # fraction of useful protection mode switches |
447system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 447system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
448system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches 449system.cpu.kern.mode_switch_good::total 0.391706 # fraction of useful protection mode switches 450system.cpu.kern.mode_ticks::kernel 46234707000 2.41% 2.41% # number of ticks spent at the given mode 451system.cpu.kern.mode_ticks::user 5259387000 0.27% 2.68% # number of ticks spent at the given mode 452system.cpu.kern.mode_ticks::idle 1869358108000 97.32% 100.00% # number of ticks spent at the given mode 453system.cpu.kern.swap_context 4178 # number of times the context was actually changed | 448system.cpu.kern.mode_switch_good::idle 0.080591 # fraction of useful protection mode switches 449system.cpu.kern.mode_switch_good::total 0.391911 # fraction of useful protection mode switches 450system.cpu.kern.mode_ticks::kernel 46687559000 2.43% 2.43% # number of ticks spent at the given mode 451system.cpu.kern.mode_ticks::user 5260775000 0.27% 2.70% # number of ticks spent at the given mode 452system.cpu.kern.mode_ticks::idle 1869843314000 97.30% 100.00% # number of ticks spent at the given mode 453system.cpu.kern.swap_context 4175 # number of times the context was actually changed |
454system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 455system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 456system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 457system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 458system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 459system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 460system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 461system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 477system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 478system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 479system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 480system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 481system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 482system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 483system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 484system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 454system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 455system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 456system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 457system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 458system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 459system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 460system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 461system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 477system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 478system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 479system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 480system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 481system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 482system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 483system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 484system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
485system.cpu.icache.replacements 928849 # number of replacements 486system.cpu.icache.tagsinuse 508.732123 # Cycle average of tags in use 487system.cpu.icache.total_refs 55270143 # Total number of references to valid blocks. 488system.cpu.icache.sampled_refs 929360 # Sample count of references to valid blocks. 489system.cpu.icache.avg_refs 59.471188 # Average number of references to valid blocks. 490system.cpu.icache.warmup_cycle 35877190000 # Cycle when the warmup percentage was hit. 491system.cpu.icache.occ_blocks::cpu.inst 508.732123 # Average occupied blocks per requestor 492system.cpu.icache.occ_percent::cpu.inst 0.993617 # Average percentage of cache occupancy 493system.cpu.icache.occ_percent::total 0.993617 # Average percentage of cache occupancy 494system.cpu.icache.ReadReq_hits::cpu.inst 55270143 # number of ReadReq hits 495system.cpu.icache.ReadReq_hits::total 55270143 # number of ReadReq hits 496system.cpu.icache.demand_hits::cpu.inst 55270143 # number of demand (read+write) hits 497system.cpu.icache.demand_hits::total 55270143 # number of demand (read+write) hits 498system.cpu.icache.overall_hits::cpu.inst 55270143 # number of overall hits 499system.cpu.icache.overall_hits::total 55270143 # number of overall hits 500system.cpu.icache.ReadReq_misses::cpu.inst 929520 # number of ReadReq misses 501system.cpu.icache.ReadReq_misses::total 929520 # number of ReadReq misses 502system.cpu.icache.demand_misses::cpu.inst 929520 # number of demand (read+write) misses 503system.cpu.icache.demand_misses::total 929520 # number of demand (read+write) misses 504system.cpu.icache.overall_misses::cpu.inst 929520 # number of overall misses 505system.cpu.icache.overall_misses::total 929520 # number of overall misses 506system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854449500 # number of ReadReq miss cycles 507system.cpu.icache.ReadReq_miss_latency::total 13854449500 # number of ReadReq miss cycles 508system.cpu.icache.demand_miss_latency::cpu.inst 13854449500 # number of demand (read+write) miss cycles 509system.cpu.icache.demand_miss_latency::total 13854449500 # number of demand (read+write) miss cycles 510system.cpu.icache.overall_miss_latency::cpu.inst 13854449500 # number of overall miss cycles 511system.cpu.icache.overall_miss_latency::total 13854449500 # number of overall miss cycles 512system.cpu.icache.ReadReq_accesses::cpu.inst 56199663 # number of ReadReq accesses(hits+misses) 513system.cpu.icache.ReadReq_accesses::total 56199663 # number of ReadReq accesses(hits+misses) 514system.cpu.icache.demand_accesses::cpu.inst 56199663 # number of demand (read+write) accesses 515system.cpu.icache.demand_accesses::total 56199663 # number of demand (read+write) accesses 516system.cpu.icache.overall_accesses::cpu.inst 56199663 # number of overall (read+write) accesses 517system.cpu.icache.overall_accesses::total 56199663 # number of overall (read+write) accesses 518system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses 519system.cpu.icache.ReadReq_miss_rate::total 0.016540 # miss rate for ReadReq accesses 520system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses 521system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses 522system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses 523system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses 524system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.950405 # average ReadReq miss latency 525system.cpu.icache.ReadReq_avg_miss_latency::total 14904.950405 # average ReadReq miss latency 526system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency 527system.cpu.icache.demand_avg_miss_latency::total 14904.950405 # average overall miss latency 528system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency 529system.cpu.icache.overall_avg_miss_latency::total 14904.950405 # average overall miss latency | 485system.cpu.icache.replacements 929133 # number of replacements 486system.cpu.icache.tagsinuse 508.706285 # Cycle average of tags in use 487system.cpu.icache.total_refs 55277511 # Total number of references to valid blocks. 488system.cpu.icache.sampled_refs 929644 # Sample count of references to valid blocks. 489system.cpu.icache.avg_refs 59.460945 # Average number of references to valid blocks. 490system.cpu.icache.warmup_cycle 36213864000 # Cycle when the warmup percentage was hit. 491system.cpu.icache.occ_blocks::cpu.inst 508.706285 # Average occupied blocks per requestor 492system.cpu.icache.occ_percent::cpu.inst 0.993567 # Average percentage of cache occupancy 493system.cpu.icache.occ_percent::total 0.993567 # Average percentage of cache occupancy 494system.cpu.icache.ReadReq_hits::cpu.inst 55277511 # number of ReadReq hits 495system.cpu.icache.ReadReq_hits::total 55277511 # number of ReadReq hits 496system.cpu.icache.demand_hits::cpu.inst 55277511 # number of demand (read+write) hits 497system.cpu.icache.demand_hits::total 55277511 # number of demand (read+write) hits 498system.cpu.icache.overall_hits::cpu.inst 55277511 # number of overall hits 499system.cpu.icache.overall_hits::total 55277511 # number of overall hits 500system.cpu.icache.ReadReq_misses::cpu.inst 929804 # number of ReadReq misses 501system.cpu.icache.ReadReq_misses::total 929804 # number of ReadReq misses 502system.cpu.icache.demand_misses::cpu.inst 929804 # number of demand (read+write) misses 503system.cpu.icache.demand_misses::total 929804 # number of demand (read+write) misses 504system.cpu.icache.overall_misses::cpu.inst 929804 # number of overall misses 505system.cpu.icache.overall_misses::total 929804 # number of overall misses 506system.cpu.icache.ReadReq_miss_latency::cpu.inst 13857748000 # number of ReadReq miss cycles 507system.cpu.icache.ReadReq_miss_latency::total 13857748000 # number of ReadReq miss cycles 508system.cpu.icache.demand_miss_latency::cpu.inst 13857748000 # number of demand (read+write) miss cycles 509system.cpu.icache.demand_miss_latency::total 13857748000 # number of demand (read+write) miss cycles 510system.cpu.icache.overall_miss_latency::cpu.inst 13857748000 # number of overall miss cycles 511system.cpu.icache.overall_miss_latency::total 13857748000 # number of overall miss cycles 512system.cpu.icache.ReadReq_accesses::cpu.inst 56207315 # number of ReadReq accesses(hits+misses) 513system.cpu.icache.ReadReq_accesses::total 56207315 # number of ReadReq accesses(hits+misses) 514system.cpu.icache.demand_accesses::cpu.inst 56207315 # number of demand (read+write) accesses 515system.cpu.icache.demand_accesses::total 56207315 # number of demand (read+write) accesses 516system.cpu.icache.overall_accesses::cpu.inst 56207315 # number of overall (read+write) accesses 517system.cpu.icache.overall_accesses::total 56207315 # number of overall (read+write) accesses 518system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses 519system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses 520system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses 521system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses 522system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses 523system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses 524system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.945348 # average ReadReq miss latency 525system.cpu.icache.ReadReq_avg_miss_latency::total 14903.945348 # average ReadReq miss latency 526system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.945348 # average overall miss latency 527system.cpu.icache.demand_avg_miss_latency::total 14903.945348 # average overall miss latency 528system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.945348 # average overall miss latency 529system.cpu.icache.overall_avg_miss_latency::total 14903.945348 # average overall miss latency |
530system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 531system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 532system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 533system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 534system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 535system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 536system.cpu.icache.fast_writes 0 # number of fast writes performed 537system.cpu.icache.cache_copies 0 # number of cache copies performed | 530system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 531system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 532system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 533system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 534system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 535system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 536system.cpu.icache.fast_writes 0 # number of fast writes performed 537system.cpu.icache.cache_copies 0 # number of cache copies performed |
538system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929520 # number of ReadReq MSHR misses 539system.cpu.icache.ReadReq_mshr_misses::total 929520 # number of ReadReq MSHR misses 540system.cpu.icache.demand_mshr_misses::cpu.inst 929520 # number of demand (read+write) MSHR misses 541system.cpu.icache.demand_mshr_misses::total 929520 # number of demand (read+write) MSHR misses 542system.cpu.icache.overall_mshr_misses::cpu.inst 929520 # number of overall MSHR misses 543system.cpu.icache.overall_mshr_misses::total 929520 # number of overall MSHR misses 544system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11065203000 # number of ReadReq MSHR miss cycles 545system.cpu.icache.ReadReq_mshr_miss_latency::total 11065203000 # number of ReadReq MSHR miss cycles 546system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11065203000 # number of demand (read+write) MSHR miss cycles 547system.cpu.icache.demand_mshr_miss_latency::total 11065203000 # number of demand (read+write) MSHR miss cycles 548system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11065203000 # number of overall MSHR miss cycles 549system.cpu.icache.overall_mshr_miss_latency::total 11065203000 # number of overall MSHR miss cycles 550system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses 552system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses 553system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses 554system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses 555system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses 556system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.211851 # average ReadReq mshr miss latency 557system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.211851 # average ReadReq mshr miss latency 558system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency 559system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency 560system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency 561system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency | 538system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929804 # number of ReadReq MSHR misses 539system.cpu.icache.ReadReq_mshr_misses::total 929804 # number of ReadReq MSHR misses 540system.cpu.icache.demand_mshr_misses::cpu.inst 929804 # number of demand (read+write) MSHR misses 541system.cpu.icache.demand_mshr_misses::total 929804 # number of demand (read+write) MSHR misses 542system.cpu.icache.overall_mshr_misses::cpu.inst 929804 # number of overall MSHR misses 543system.cpu.icache.overall_mshr_misses::total 929804 # number of overall MSHR misses 544system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11067649000 # number of ReadReq MSHR miss cycles 545system.cpu.icache.ReadReq_mshr_miss_latency::total 11067649000 # number of ReadReq MSHR miss cycles 546system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11067649000 # number of demand (read+write) MSHR miss cycles 547system.cpu.icache.demand_mshr_miss_latency::total 11067649000 # number of demand (read+write) MSHR miss cycles 548system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11067649000 # number of overall MSHR miss cycles 549system.cpu.icache.overall_mshr_miss_latency::total 11067649000 # number of overall MSHR miss cycles 550system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses 552system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses 553system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses 554system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses 555system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses 556system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.206482 # average ReadReq mshr miss latency 557system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.206482 # average ReadReq mshr miss latency 558system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.206482 # average overall mshr miss latency 559system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.206482 # average overall mshr miss latency 560system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.206482 # average overall mshr miss latency 561system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.206482 # average overall mshr miss latency |
562system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 562system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
563system.cpu.dcache.replacements 1390657 # number of replacements 564system.cpu.dcache.tagsinuse 511.983813 # Cycle average of tags in use 565system.cpu.dcache.total_refs 14050696 # Total number of references to valid blocks. 566system.cpu.dcache.sampled_refs 1391169 # Sample count of references to valid blocks. 567system.cpu.dcache.avg_refs 10.099920 # Average number of references to valid blocks. 568system.cpu.dcache.warmup_cycle 85768000 # Cycle when the warmup percentage was hit. 569system.cpu.dcache.occ_blocks::cpu.data 511.983813 # Average occupied blocks per requestor 570system.cpu.dcache.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy 571system.cpu.dcache.occ_percent::total 0.999968 # Average percentage of cache occupancy 572system.cpu.dcache.ReadReq_hits::cpu.data 7815339 # number of ReadReq hits 573system.cpu.dcache.ReadReq_hits::total 7815339 # number of ReadReq hits 574system.cpu.dcache.WriteReq_hits::cpu.data 5853076 # number of WriteReq hits 575system.cpu.dcache.WriteReq_hits::total 5853076 # number of WriteReq hits 576system.cpu.dcache.LoadLockedReq_hits::cpu.data 182979 # number of LoadLockedReq hits 577system.cpu.dcache.LoadLockedReq_hits::total 182979 # number of LoadLockedReq hits 578system.cpu.dcache.StoreCondReq_hits::cpu.data 199284 # number of StoreCondReq hits 579system.cpu.dcache.StoreCondReq_hits::total 199284 # number of StoreCondReq hits 580system.cpu.dcache.demand_hits::cpu.data 13668415 # number of demand (read+write) hits 581system.cpu.dcache.demand_hits::total 13668415 # number of demand (read+write) hits 582system.cpu.dcache.overall_hits::cpu.data 13668415 # number of overall hits 583system.cpu.dcache.overall_hits::total 13668415 # number of overall hits 584system.cpu.dcache.ReadReq_misses::cpu.data 1069522 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 1069522 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.data 304341 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 304341 # number of WriteReq misses 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 17326 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses 590system.cpu.dcache.demand_misses::cpu.data 1373863 # number of demand (read+write) misses 591system.cpu.dcache.demand_misses::total 1373863 # number of demand (read+write) misses 592system.cpu.dcache.overall_misses::cpu.data 1373863 # number of overall misses 593system.cpu.dcache.overall_misses::total 1373863 # number of overall misses 594system.cpu.dcache.ReadReq_miss_latency::cpu.data 26656014000 # number of ReadReq miss cycles 595system.cpu.dcache.ReadReq_miss_latency::total 26656014000 # number of ReadReq miss cycles 596system.cpu.dcache.WriteReq_miss_latency::cpu.data 9232792000 # number of WriteReq miss cycles 597system.cpu.dcache.WriteReq_miss_latency::total 9232792000 # number of WriteReq miss cycles 598system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 248493000 # number of LoadLockedReq miss cycles 599system.cpu.dcache.LoadLockedReq_miss_latency::total 248493000 # number of LoadLockedReq miss cycles 600system.cpu.dcache.demand_miss_latency::cpu.data 35888806000 # number of demand (read+write) miss cycles 601system.cpu.dcache.demand_miss_latency::total 35888806000 # number of demand (read+write) miss cycles 602system.cpu.dcache.overall_miss_latency::cpu.data 35888806000 # number of overall miss cycles 603system.cpu.dcache.overall_miss_latency::total 35888806000 # number of overall miss cycles 604system.cpu.dcache.ReadReq_accesses::cpu.data 8884861 # number of ReadReq accesses(hits+misses) 605system.cpu.dcache.ReadReq_accesses::total 8884861 # number of ReadReq accesses(hits+misses) 606system.cpu.dcache.WriteReq_accesses::cpu.data 6157417 # number of WriteReq accesses(hits+misses) 607system.cpu.dcache.WriteReq_accesses::total 6157417 # number of WriteReq accesses(hits+misses) 608system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200305 # number of LoadLockedReq accesses(hits+misses) 609system.cpu.dcache.LoadLockedReq_accesses::total 200305 # number of LoadLockedReq accesses(hits+misses) 610system.cpu.dcache.StoreCondReq_accesses::cpu.data 199284 # number of StoreCondReq accesses(hits+misses) 611system.cpu.dcache.StoreCondReq_accesses::total 199284 # number of StoreCondReq accesses(hits+misses) 612system.cpu.dcache.demand_accesses::cpu.data 15042278 # number of demand (read+write) accesses 613system.cpu.dcache.demand_accesses::total 15042278 # number of demand (read+write) accesses 614system.cpu.dcache.overall_accesses::cpu.data 15042278 # number of overall (read+write) accesses 615system.cpu.dcache.overall_accesses::total 15042278 # number of overall (read+write) accesses | 563system.cpu.dcache.replacements 1390802 # number of replacements 564system.cpu.dcache.tagsinuse 511.979761 # Cycle average of tags in use 565system.cpu.dcache.total_refs 14052158 # Total number of references to valid blocks. 566system.cpu.dcache.sampled_refs 1391314 # Sample count of references to valid blocks. 567system.cpu.dcache.avg_refs 10.099918 # Average number of references to valid blocks. 568system.cpu.dcache.warmup_cycle 101905000 # Cycle when the warmup percentage was hit. 569system.cpu.dcache.occ_blocks::cpu.data 511.979761 # Average occupied blocks per requestor 570system.cpu.dcache.occ_percent::cpu.data 0.999960 # Average percentage of cache occupancy 571system.cpu.dcache.occ_percent::total 0.999960 # Average percentage of cache occupancy 572system.cpu.dcache.ReadReq_hits::cpu.data 7816348 # number of ReadReq hits 573system.cpu.dcache.ReadReq_hits::total 7816348 # number of ReadReq hits 574system.cpu.dcache.WriteReq_hits::cpu.data 5853489 # number of WriteReq hits 575system.cpu.dcache.WriteReq_hits::total 5853489 # number of WriteReq hits 576system.cpu.dcache.LoadLockedReq_hits::cpu.data 183027 # number of LoadLockedReq hits 577system.cpu.dcache.LoadLockedReq_hits::total 183027 # number of LoadLockedReq hits 578system.cpu.dcache.StoreCondReq_hits::cpu.data 199276 # number of StoreCondReq hits 579system.cpu.dcache.StoreCondReq_hits::total 199276 # number of StoreCondReq hits 580system.cpu.dcache.demand_hits::cpu.data 13669837 # number of demand (read+write) hits 581system.cpu.dcache.demand_hits::total 13669837 # number of demand (read+write) hits 582system.cpu.dcache.overall_hits::cpu.data 13669837 # number of overall hits 583system.cpu.dcache.overall_hits::total 13669837 # number of overall hits 584system.cpu.dcache.ReadReq_misses::cpu.data 1069663 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 1069663 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.data 304397 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 304397 # number of WriteReq misses 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 17273 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 17273 # number of LoadLockedReq misses 590system.cpu.dcache.demand_misses::cpu.data 1374060 # number of demand (read+write) misses 591system.cpu.dcache.demand_misses::total 1374060 # number of demand (read+write) misses 592system.cpu.dcache.overall_misses::cpu.data 1374060 # number of overall misses 593system.cpu.dcache.overall_misses::total 1374060 # number of overall misses 594system.cpu.dcache.ReadReq_miss_latency::cpu.data 26660030000 # number of ReadReq miss cycles 595system.cpu.dcache.ReadReq_miss_latency::total 26660030000 # number of ReadReq miss cycles 596system.cpu.dcache.WriteReq_miss_latency::cpu.data 9238691000 # number of WriteReq miss cycles 597system.cpu.dcache.WriteReq_miss_latency::total 9238691000 # number of WriteReq miss cycles 598system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247715000 # number of LoadLockedReq miss cycles 599system.cpu.dcache.LoadLockedReq_miss_latency::total 247715000 # number of LoadLockedReq miss cycles 600system.cpu.dcache.demand_miss_latency::cpu.data 35898721000 # number of demand (read+write) miss cycles 601system.cpu.dcache.demand_miss_latency::total 35898721000 # number of demand (read+write) miss cycles 602system.cpu.dcache.overall_miss_latency::cpu.data 35898721000 # number of overall miss cycles 603system.cpu.dcache.overall_miss_latency::total 35898721000 # number of overall miss cycles 604system.cpu.dcache.ReadReq_accesses::cpu.data 8886011 # number of ReadReq accesses(hits+misses) 605system.cpu.dcache.ReadReq_accesses::total 8886011 # number of ReadReq accesses(hits+misses) 606system.cpu.dcache.WriteReq_accesses::cpu.data 6157886 # number of WriteReq accesses(hits+misses) 607system.cpu.dcache.WriteReq_accesses::total 6157886 # number of WriteReq accesses(hits+misses) 608system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200300 # number of LoadLockedReq accesses(hits+misses) 609system.cpu.dcache.LoadLockedReq_accesses::total 200300 # number of LoadLockedReq accesses(hits+misses) 610system.cpu.dcache.StoreCondReq_accesses::cpu.data 199276 # number of StoreCondReq accesses(hits+misses) 611system.cpu.dcache.StoreCondReq_accesses::total 199276 # number of StoreCondReq accesses(hits+misses) 612system.cpu.dcache.demand_accesses::cpu.data 15043897 # number of demand (read+write) accesses 613system.cpu.dcache.demand_accesses::total 15043897 # number of demand (read+write) accesses 614system.cpu.dcache.overall_accesses::cpu.data 15043897 # number of overall (read+write) accesses 615system.cpu.dcache.overall_accesses::total 15043897 # number of overall (read+write) accesses |
616system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120376 # miss rate for ReadReq accesses 617system.cpu.dcache.ReadReq_miss_rate::total 0.120376 # miss rate for ReadReq accesses | 616system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120376 # miss rate for ReadReq accesses 617system.cpu.dcache.ReadReq_miss_rate::total 0.120376 # miss rate for ReadReq accesses |
618system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049427 # miss rate for WriteReq accesses 619system.cpu.dcache.WriteReq_miss_rate::total 0.049427 # miss rate for WriteReq accesses 620system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086498 # miss rate for LoadLockedReq accesses 621system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086498 # miss rate for LoadLockedReq accesses 622system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses 623system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses 624system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses 625system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses 626system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.296575 # average ReadReq miss latency 627system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.296575 # average ReadReq miss latency 628system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30336.996987 # average WriteReq miss latency 629system.cpu.dcache.WriteReq_avg_miss_latency::total 30336.996987 # average WriteReq miss latency 630system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470 # average LoadLockedReq miss latency 631system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470 # average LoadLockedReq miss latency 632system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency 633system.cpu.dcache.demand_avg_miss_latency::total 26122.550793 # average overall miss latency 634system.cpu.dcache.overall_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::total 26122.550793 # average overall miss latency | 618system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049432 # miss rate for WriteReq accesses 619system.cpu.dcache.WriteReq_miss_rate::total 0.049432 # miss rate for WriteReq accesses 620system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086236 # miss rate for LoadLockedReq accesses 621system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086236 # miss rate for LoadLockedReq accesses 622system.cpu.dcache.demand_miss_rate::cpu.data 0.091337 # miss rate for demand accesses 623system.cpu.dcache.demand_miss_rate::total 0.091337 # miss rate for demand accesses 624system.cpu.dcache.overall_miss_rate::cpu.data 0.091337 # miss rate for overall accesses 625system.cpu.dcache.overall_miss_rate::total 0.091337 # miss rate for overall accesses 626system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.765709 # average ReadReq miss latency 627system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.765709 # average ReadReq miss latency 628system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30350.795179 # average WriteReq miss latency 629system.cpu.dcache.WriteReq_avg_miss_latency::total 30350.795179 # average WriteReq miss latency 630system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14341.168297 # average LoadLockedReq miss latency 631system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14341.168297 # average LoadLockedReq miss latency 632system.cpu.dcache.demand_avg_miss_latency::cpu.data 26126.021426 # average overall miss latency 633system.cpu.dcache.demand_avg_miss_latency::total 26126.021426 # average overall miss latency 634system.cpu.dcache.overall_avg_miss_latency::cpu.data 26126.021426 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::total 26126.021426 # average overall miss latency |
636system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 637system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 641system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.dcache.fast_writes 0 # number of fast writes performed 643system.cpu.dcache.cache_copies 0 # number of cache copies performed | 636system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 637system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 641system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.dcache.fast_writes 0 # number of fast writes performed 643system.cpu.dcache.cache_copies 0 # number of cache copies performed |
644system.cpu.dcache.writebacks::writebacks 835149 # number of writebacks 645system.cpu.dcache.writebacks::total 835149 # number of writebacks 646system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069522 # number of ReadReq MSHR misses 647system.cpu.dcache.ReadReq_mshr_misses::total 1069522 # number of ReadReq MSHR misses 648system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304341 # number of WriteReq MSHR misses 649system.cpu.dcache.WriteReq_mshr_misses::total 304341 # number of WriteReq MSHR misses 650system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17326 # number of LoadLockedReq MSHR misses 651system.cpu.dcache.LoadLockedReq_mshr_misses::total 17326 # number of LoadLockedReq MSHR misses 652system.cpu.dcache.demand_mshr_misses::cpu.data 1373863 # number of demand (read+write) MSHR misses 653system.cpu.dcache.demand_mshr_misses::total 1373863 # number of demand (read+write) MSHR misses 654system.cpu.dcache.overall_mshr_misses::cpu.data 1373863 # number of overall MSHR misses 655system.cpu.dcache.overall_mshr_misses::total 1373863 # number of overall MSHR misses 656system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23447403000 # number of ReadReq MSHR miss cycles 657system.cpu.dcache.ReadReq_mshr_miss_latency::total 23447403000 # number of ReadReq MSHR miss cycles 658system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8319769000 # number of WriteReq MSHR miss cycles 659system.cpu.dcache.WriteReq_mshr_miss_latency::total 8319769000 # number of WriteReq MSHR miss cycles 660system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196515000 # number of LoadLockedReq MSHR miss cycles 661system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196515000 # number of LoadLockedReq MSHR miss cycles 662system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31767172000 # number of demand (read+write) MSHR miss cycles 663system.cpu.dcache.demand_mshr_miss_latency::total 31767172000 # number of demand (read+write) MSHR miss cycles 664system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31767172000 # number of overall MSHR miss cycles 665system.cpu.dcache.overall_mshr_miss_latency::total 31767172000 # number of overall MSHR miss cycles 666system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862831000 # number of ReadReq MSHR uncacheable cycles 667system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862831000 # number of ReadReq MSHR uncacheable cycles 668system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1190523500 # number of WriteReq MSHR uncacheable cycles 669system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1190523500 # number of WriteReq MSHR uncacheable cycles 670system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2053354500 # number of overall MSHR uncacheable cycles 671system.cpu.dcache.overall_mshr_uncacheable_latency::total 2053354500 # number of overall MSHR uncacheable cycles | 644system.cpu.dcache.writebacks::writebacks 835196 # number of writebacks 645system.cpu.dcache.writebacks::total 835196 # number of writebacks 646system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069663 # number of ReadReq MSHR misses 647system.cpu.dcache.ReadReq_mshr_misses::total 1069663 # number of ReadReq MSHR misses 648system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304397 # number of WriteReq MSHR misses 649system.cpu.dcache.WriteReq_mshr_misses::total 304397 # number of WriteReq MSHR misses 650system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17273 # number of LoadLockedReq MSHR misses 651system.cpu.dcache.LoadLockedReq_mshr_misses::total 17273 # number of LoadLockedReq MSHR misses 652system.cpu.dcache.demand_mshr_misses::cpu.data 1374060 # number of demand (read+write) MSHR misses 653system.cpu.dcache.demand_mshr_misses::total 1374060 # number of demand (read+write) MSHR misses 654system.cpu.dcache.overall_mshr_misses::cpu.data 1374060 # number of overall MSHR misses 655system.cpu.dcache.overall_mshr_misses::total 1374060 # number of overall MSHR misses 656system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23450996000 # number of ReadReq MSHR miss cycles 657system.cpu.dcache.ReadReq_mshr_miss_latency::total 23450996000 # number of ReadReq MSHR miss cycles 658system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8325500000 # number of WriteReq MSHR miss cycles 659system.cpu.dcache.WriteReq_mshr_miss_latency::total 8325500000 # number of WriteReq MSHR miss cycles 660system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195896000 # number of LoadLockedReq MSHR miss cycles 661system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195896000 # number of LoadLockedReq MSHR miss cycles 662system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31776496000 # number of demand (read+write) MSHR miss cycles 663system.cpu.dcache.demand_mshr_miss_latency::total 31776496000 # number of demand (read+write) MSHR miss cycles 664system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31776496000 # number of overall MSHR miss cycles 665system.cpu.dcache.overall_mshr_miss_latency::total 31776496000 # number of overall MSHR miss cycles 666system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1421708000 # number of ReadReq MSHR uncacheable cycles 667system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1421708000 # number of ReadReq MSHR uncacheable cycles 668system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011005000 # number of WriteReq MSHR uncacheable cycles 669system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011005000 # number of WriteReq MSHR uncacheable cycles 670system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3432713000 # number of overall MSHR uncacheable cycles 671system.cpu.dcache.overall_mshr_uncacheable_latency::total 3432713000 # number of overall MSHR uncacheable cycles |
672system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120376 # mshr miss rate for ReadReq accesses 673system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120376 # mshr miss rate for ReadReq accesses | 672system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120376 # mshr miss rate for ReadReq accesses 673system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120376 # mshr miss rate for ReadReq accesses |
674system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049427 # mshr miss rate for WriteReq accesses 675system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049427 # mshr miss rate for WriteReq accesses 676system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086498 # mshr miss rate for LoadLockedReq accesses 677system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086498 # mshr miss rate for LoadLockedReq accesses 678system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses 679system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses 680system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses 681system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses 682system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.254501 # average ReadReq mshr miss latency 683system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.254501 # average ReadReq mshr miss latency 684system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27336.996987 # average WriteReq mshr miss latency 685system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27336.996987 # average WriteReq mshr miss latency 686system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470 # average LoadLockedReq mshr miss latency 687system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470 # average LoadLockedReq mshr miss latency 688system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency 690system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency | 674system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049432 # mshr miss rate for WriteReq accesses 675system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049432 # mshr miss rate for WriteReq accesses 676system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086236 # mshr miss rate for LoadLockedReq accesses 677system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086236 # mshr miss rate for LoadLockedReq accesses 678system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses 679system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses 680system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses 681system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses 682system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.723640 # average ReadReq mshr miss latency 683system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.723640 # average ReadReq mshr miss latency 684system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.795179 # average WriteReq mshr miss latency 685system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.795179 # average WriteReq mshr miss latency 686system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.168297 # average LoadLockedReq mshr miss latency 687system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.168297 # average LoadLockedReq mshr miss latency 688system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency 690system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23125.988676 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::total 23125.988676 # average overall mshr miss latency |
692system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 693system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 694system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 695system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 696system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 697system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 698system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 699 700---------- End Simulation Statistics ---------- | 692system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 693system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 694system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 695system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 696system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 697system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 698system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 699 700---------- End Simulation Statistics ---------- |