| stats.txt (9096:8971a998190a) | stats.txt (9134:275232ad377d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.920852 # Number of seconds simulated 4sim_ticks 1920852274000 # Number of ticks simulated 5final_tick 1920852274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.920853 # Number of seconds simulated 4sim_ticks 1920853042000 # Number of ticks simulated 5final_tick 1920853042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1904642 # Simulator instruction rate (inst/s) 8host_op_rate 1904641 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 65112526106 # Simulator tick rate (ticks/s) 10host_mem_usage 294856 # Number of bytes of host memory used 11host_seconds 29.50 # Real time elapsed on the host | 7host_inst_rate 1381815 # Simulator instruction rate (inst/s) 8host_op_rate 1381815 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47239093914 # Simulator tick rate (ticks/s) 10host_mem_usage 299308 # Number of bytes of host memory used 11host_seconds 40.66 # Real time elapsed on the host |
| 12sim_insts 56187824 # Number of instructions simulated 13sim_ops 56187824 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24847552 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28350592 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7389056 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7389056 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388243 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 442978 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115454 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115454 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 442870 # Total read bandwidth from this memory (bytes/s) | 12sim_insts 56187824 # Number of instructions simulated 13sim_ops 56187824 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24847552 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28350592 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7389056 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7389056 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388243 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 442978 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 115454 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 115454 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 442870 # Total read bandwidth from this memory (bytes/s) |
| 29system.physmem.bw_read::cpu.data 12935691 # Total read bandwidth from this memory (bytes/s) | 29system.physmem.bw_read::cpu.data 12935686 # Total read bandwidth from this memory (bytes/s) |
| 30system.physmem.bw_read::tsunami.ide 1380820 # Total read bandwidth from this memory (bytes/s) | 30system.physmem.bw_read::tsunami.ide 1380820 # Total read bandwidth from this memory (bytes/s) |
| 31system.physmem.bw_read::total 14759382 # Total read bandwidth from this memory (bytes/s) | 31system.physmem.bw_read::total 14759376 # Total read bandwidth from this memory (bytes/s) |
| 32system.physmem.bw_inst_read::cpu.inst 442870 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 442870 # Instruction read bandwidth from this memory (bytes/s) | 32system.physmem.bw_inst_read::cpu.inst 442870 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 442870 # Instruction read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_write::writebacks 3846759 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3846759 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3846759 # Total bandwidth to/from this memory (bytes/s) | 34system.physmem.bw_write::writebacks 3846758 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 3846758 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 3846758 # Total bandwidth to/from this memory (bytes/s) |
| 37system.physmem.bw_total::cpu.inst 442870 # Total bandwidth to/from this memory (bytes/s) | 37system.physmem.bw_total::cpu.inst 442870 # Total bandwidth to/from this memory (bytes/s) |
| 38system.physmem.bw_total::cpu.data 12935691 # Total bandwidth to/from this memory (bytes/s) | 38system.physmem.bw_total::cpu.data 12935686 # Total bandwidth to/from this memory (bytes/s) |
| 39system.physmem.bw_total::tsunami.ide 1380820 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_total::tsunami.ide 1380820 # Total bandwidth to/from this memory (bytes/s) |
| 40system.physmem.bw_total::total 18606141 # Total bandwidth to/from this memory (bytes/s) | 40system.physmem.bw_total::total 18606133 # Total bandwidth to/from this memory (bytes/s) |
| 41system.l2c.replacements 336066 # number of replacements | 41system.l2c.replacements 336066 # number of replacements |
| 42system.l2c.tagsinuse 65311.816256 # Cycle average of tags in use 43system.l2c.total_refs 2448229 # Total number of references to valid blocks. 44system.l2c.sampled_refs 401229 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.101825 # Average number of references to valid blocks. | 42system.l2c.tagsinuse 65311.806529 # Cycle average of tags in use 43system.l2c.total_refs 2448197 # Total number of references to valid blocks. 44system.l2c.sampled_refs 401228 # Sample count of references to valid blocks. 45system.l2c.avg_refs 6.101760 # Average number of references to valid blocks. |
| 46system.l2c.warmup_cycle 5946056000 # Cycle when the warmup percentage was hit. | 46system.l2c.warmup_cycle 5946056000 # Cycle when the warmup percentage was hit. |
| 47system.l2c.occ_blocks::writebacks 55675.740322 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 4768.394145 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 4867.681789 # Average occupied blocks per requestor | 47system.l2c.occ_blocks::writebacks 55675.727094 # Average occupied blocks per requestor 48system.l2c.occ_blocks::cpu.inst 4768.395922 # Average occupied blocks per requestor 49system.l2c.occ_blocks::cpu.data 4867.683513 # Average occupied blocks per requestor |
| 50system.l2c.occ_percent::writebacks 0.849544 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.074275 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.996579 # Average percentage of cache occupancy | 50system.l2c.occ_percent::writebacks 0.849544 # Average percentage of cache occupancy 51system.l2c.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy 52system.l2c.occ_percent::cpu.data 0.074275 # Average percentage of cache occupancy 53system.l2c.occ_percent::total 0.996579 # Average percentage of cache occupancy |
| 54system.l2c.ReadReq_hits::cpu.inst 916210 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 814879 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1731089 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 835223 # number of Writeback hits 58system.l2c.Writeback_hits::total 835223 # number of Writeback hits 59system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits 61system.l2c.ReadExReq_hits::cpu.data 187457 # number of ReadExReq hits 62system.l2c.ReadExReq_hits::total 187457 # number of ReadExReq hits 63system.l2c.demand_hits::cpu.inst 916210 # number of demand (read+write) hits 64system.l2c.demand_hits::cpu.data 1002336 # number of demand (read+write) hits 65system.l2c.demand_hits::total 1918546 # number of demand (read+write) hits 66system.l2c.overall_hits::cpu.inst 916210 # number of overall hits 67system.l2c.overall_hits::cpu.data 1002336 # number of overall hits 68system.l2c.overall_hits::total 1918546 # number of overall hits | 54system.l2c.ReadReq_hits::cpu.inst 916208 # number of ReadReq hits 55system.l2c.ReadReq_hits::cpu.data 814933 # number of ReadReq hits 56system.l2c.ReadReq_hits::total 1731141 # number of ReadReq hits 57system.l2c.Writeback_hits::writebacks 835149 # number of Writeback hits 58system.l2c.Writeback_hits::total 835149 # number of Writeback hits 59system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 60system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits 61system.l2c.ReadExReq_hits::cpu.data 187605 # number of ReadExReq hits 62system.l2c.ReadExReq_hits::total 187605 # number of ReadExReq hits 63system.l2c.demand_hits::cpu.inst 916208 # number of demand (read+write) hits 64system.l2c.demand_hits::cpu.data 1002538 # number of demand (read+write) hits 65system.l2c.demand_hits::total 1918746 # number of demand (read+write) hits 66system.l2c.overall_hits::cpu.inst 916208 # number of overall hits 67system.l2c.overall_hits::cpu.data 1002538 # number of overall hits 68system.l2c.overall_hits::total 1918746 # number of overall hits |
| 69system.l2c.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses 70system.l2c.ReadReq_misses::cpu.data 271915 # number of ReadReq misses 71system.l2c.ReadReq_misses::total 285207 # number of ReadReq misses | 69system.l2c.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses 70system.l2c.ReadReq_misses::cpu.data 271915 # number of ReadReq misses 71system.l2c.ReadReq_misses::total 285207 # number of ReadReq misses |
| 72system.l2c.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses 73system.l2c.UpgradeReq_misses::total 8 # number of UpgradeReq misses 74system.l2c.ReadExReq_misses::cpu.data 116714 # number of ReadExReq misses 75system.l2c.ReadExReq_misses::total 116714 # number of ReadExReq misses | 72system.l2c.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses 73system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses 74system.l2c.ReadExReq_misses::cpu.data 116718 # number of ReadExReq misses 75system.l2c.ReadExReq_misses::total 116718 # number of ReadExReq misses |
| 76system.l2c.demand_misses::cpu.inst 13292 # number of demand (read+write) misses | 76system.l2c.demand_misses::cpu.inst 13292 # number of demand (read+write) misses |
| 77system.l2c.demand_misses::cpu.data 388629 # number of demand (read+write) misses 78system.l2c.demand_misses::total 401921 # number of demand (read+write) misses | 77system.l2c.demand_misses::cpu.data 388633 # number of demand (read+write) misses 78system.l2c.demand_misses::total 401925 # number of demand (read+write) misses |
| 79system.l2c.overall_misses::cpu.inst 13292 # number of overall misses | 79system.l2c.overall_misses::cpu.inst 13292 # number of overall misses |
| 80system.l2c.overall_misses::cpu.data 388629 # number of overall misses 81system.l2c.overall_misses::total 401921 # number of overall misses | 80system.l2c.overall_misses::cpu.data 388633 # number of overall misses 81system.l2c.overall_misses::total 401925 # number of overall misses |
| 82system.l2c.ReadReq_miss_latency::cpu.inst 691773000 # number of ReadReq miss cycles 83system.l2c.ReadReq_miss_latency::cpu.data 14144855000 # number of ReadReq miss cycles 84system.l2c.ReadReq_miss_latency::total 14836628000 # number of ReadReq miss cycles 85system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles 86system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles | 82system.l2c.ReadReq_miss_latency::cpu.inst 691773000 # number of ReadReq miss cycles 83system.l2c.ReadReq_miss_latency::cpu.data 14144855000 # number of ReadReq miss cycles 84system.l2c.ReadReq_miss_latency::total 14836628000 # number of ReadReq miss cycles 85system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles 86system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles |
| 87system.l2c.ReadExReq_miss_latency::cpu.data 6069807000 # number of ReadExReq miss cycles 88system.l2c.ReadExReq_miss_latency::total 6069807000 # number of ReadExReq miss cycles | 87system.l2c.ReadExReq_miss_latency::cpu.data 6070015000 # number of ReadExReq miss cycles 88system.l2c.ReadExReq_miss_latency::total 6070015000 # number of ReadExReq miss cycles |
| 89system.l2c.demand_miss_latency::cpu.inst 691773000 # number of demand (read+write) miss cycles | 89system.l2c.demand_miss_latency::cpu.inst 691773000 # number of demand (read+write) miss cycles |
| 90system.l2c.demand_miss_latency::cpu.data 20214662000 # number of demand (read+write) miss cycles 91system.l2c.demand_miss_latency::total 20906435000 # number of demand (read+write) miss cycles | 90system.l2c.demand_miss_latency::cpu.data 20214870000 # number of demand (read+write) miss cycles 91system.l2c.demand_miss_latency::total 20906643000 # number of demand (read+write) miss cycles |
| 92system.l2c.overall_miss_latency::cpu.inst 691773000 # number of overall miss cycles | 92system.l2c.overall_miss_latency::cpu.inst 691773000 # number of overall miss cycles |
| 93system.l2c.overall_miss_latency::cpu.data 20214662000 # number of overall miss cycles 94system.l2c.overall_miss_latency::total 20906435000 # number of overall miss cycles 95system.l2c.ReadReq_accesses::cpu.inst 929502 # number of ReadReq accesses(hits+misses) 96system.l2c.ReadReq_accesses::cpu.data 1086794 # number of ReadReq accesses(hits+misses) 97system.l2c.ReadReq_accesses::total 2016296 # number of ReadReq accesses(hits+misses) 98system.l2c.Writeback_accesses::writebacks 835223 # number of Writeback accesses(hits+misses) 99system.l2c.Writeback_accesses::total 835223 # number of Writeback accesses(hits+misses) 100system.l2c.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) 101system.l2c.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) 102system.l2c.ReadExReq_accesses::cpu.data 304171 # number of ReadExReq accesses(hits+misses) 103system.l2c.ReadExReq_accesses::total 304171 # number of ReadExReq accesses(hits+misses) 104system.l2c.demand_accesses::cpu.inst 929502 # number of demand (read+write) accesses 105system.l2c.demand_accesses::cpu.data 1390965 # number of demand (read+write) accesses 106system.l2c.demand_accesses::total 2320467 # number of demand (read+write) accesses 107system.l2c.overall_accesses::cpu.inst 929502 # number of overall (read+write) accesses 108system.l2c.overall_accesses::cpu.data 1390965 # number of overall (read+write) accesses 109system.l2c.overall_accesses::total 2320467 # number of overall (read+write) accesses | 93system.l2c.overall_miss_latency::cpu.data 20214870000 # number of overall miss cycles 94system.l2c.overall_miss_latency::total 20906643000 # number of overall miss cycles 95system.l2c.ReadReq_accesses::cpu.inst 929500 # number of ReadReq accesses(hits+misses) 96system.l2c.ReadReq_accesses::cpu.data 1086848 # number of ReadReq accesses(hits+misses) 97system.l2c.ReadReq_accesses::total 2016348 # number of ReadReq accesses(hits+misses) 98system.l2c.Writeback_accesses::writebacks 835149 # number of Writeback accesses(hits+misses) 99system.l2c.Writeback_accesses::total 835149 # number of Writeback accesses(hits+misses) 100system.l2c.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) 101system.l2c.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) 102system.l2c.ReadExReq_accesses::cpu.data 304323 # number of ReadExReq accesses(hits+misses) 103system.l2c.ReadExReq_accesses::total 304323 # number of ReadExReq accesses(hits+misses) 104system.l2c.demand_accesses::cpu.inst 929500 # number of demand (read+write) accesses 105system.l2c.demand_accesses::cpu.data 1391171 # number of demand (read+write) accesses 106system.l2c.demand_accesses::total 2320671 # number of demand (read+write) accesses 107system.l2c.overall_accesses::cpu.inst 929500 # number of overall (read+write) accesses 108system.l2c.overall_accesses::cpu.data 1391171 # number of overall (read+write) accesses 109system.l2c.overall_accesses::total 2320671 # number of overall (read+write) accesses |
| 110system.l2c.ReadReq_miss_rate::cpu.inst 0.014300 # miss rate for ReadReq accesses | 110system.l2c.ReadReq_miss_rate::cpu.inst 0.014300 # miss rate for ReadReq accesses |
| 111system.l2c.ReadReq_miss_rate::cpu.data 0.250199 # miss rate for ReadReq accesses 112system.l2c.ReadReq_miss_rate::total 0.141451 # miss rate for ReadReq accesses 113system.l2c.UpgradeReq_miss_rate::cpu.data 0.571429 # miss rate for UpgradeReq accesses 114system.l2c.UpgradeReq_miss_rate::total 0.571429 # miss rate for UpgradeReq accesses 115system.l2c.ReadExReq_miss_rate::cpu.data 0.383712 # miss rate for ReadExReq accesses 116system.l2c.ReadExReq_miss_rate::total 0.383712 # miss rate for ReadExReq accesses | 111system.l2c.ReadReq_miss_rate::cpu.data 0.250187 # miss rate for ReadReq accesses 112system.l2c.ReadReq_miss_rate::total 0.141447 # miss rate for ReadReq accesses 113system.l2c.UpgradeReq_miss_rate::cpu.data 0.777778 # miss rate for UpgradeReq accesses 114system.l2c.UpgradeReq_miss_rate::total 0.777778 # miss rate for UpgradeReq accesses 115system.l2c.ReadExReq_miss_rate::cpu.data 0.383533 # miss rate for ReadExReq accesses 116system.l2c.ReadExReq_miss_rate::total 0.383533 # miss rate for ReadExReq accesses |
| 117system.l2c.demand_miss_rate::cpu.inst 0.014300 # miss rate for demand accesses | 117system.l2c.demand_miss_rate::cpu.inst 0.014300 # miss rate for demand accesses |
| 118system.l2c.demand_miss_rate::cpu.data 0.279395 # miss rate for demand accesses 119system.l2c.demand_miss_rate::total 0.173207 # miss rate for demand accesses | 118system.l2c.demand_miss_rate::cpu.data 0.279357 # miss rate for demand accesses 119system.l2c.demand_miss_rate::total 0.173193 # miss rate for demand accesses |
| 120system.l2c.overall_miss_rate::cpu.inst 0.014300 # miss rate for overall accesses | 120system.l2c.overall_miss_rate::cpu.inst 0.014300 # miss rate for overall accesses |
| 121system.l2c.overall_miss_rate::cpu.data 0.279395 # miss rate for overall accesses 122system.l2c.overall_miss_rate::total 0.173207 # miss rate for overall accesses | 121system.l2c.overall_miss_rate::cpu.data 0.279357 # miss rate for overall accesses 122system.l2c.overall_miss_rate::total 0.173193 # miss rate for overall accesses |
| 123system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368 # average ReadReq miss latency 124system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445 # average ReadReq miss latency 125system.l2c.ReadReq_avg_miss_latency::total 52020.560505 # average ReadReq miss latency | 123system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368 # average ReadReq miss latency 124system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445 # average ReadReq miss latency 125system.l2c.ReadReq_avg_miss_latency::total 52020.560505 # average ReadReq miss latency |
| 126system.l2c.UpgradeReq_avg_miss_latency::cpu.data 40000 # average UpgradeReq miss latency 127system.l2c.UpgradeReq_avg_miss_latency::total 40000 # average UpgradeReq miss latency 128system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817640 # average ReadExReq miss latency 129system.l2c.ReadExReq_avg_miss_latency::total 52005.817640 # average ReadExReq miss latency | 126system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857 # average UpgradeReq miss latency 127system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857 # average UpgradeReq miss latency 128system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817440 # average ReadExReq miss latency 129system.l2c.ReadExReq_avg_miss_latency::total 52005.817440 # average ReadExReq miss latency |
| 130system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency | 130system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency |
| 131system.l2c.demand_avg_miss_latency::cpu.data 52015.320524 # average overall miss latency 132system.l2c.demand_avg_miss_latency::total 52016.279319 # average overall miss latency | 131system.l2c.demand_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency 132system.l2c.demand_avg_miss_latency::total 52016.279157 # average overall miss latency |
| 133system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency | 133system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency |
| 134system.l2c.overall_avg_miss_latency::cpu.data 52015.320524 # average overall miss latency 135system.l2c.overall_avg_miss_latency::total 52016.279319 # average overall miss latency | 134system.l2c.overall_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency 135system.l2c.overall_avg_miss_latency::total 52016.279157 # average overall miss latency |
| 136system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 137system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 138system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 139system.l2c.blocked::no_targets 0 # number of cycles access was blocked 140system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 141system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 142system.l2c.fast_writes 0 # number of fast writes performed 143system.l2c.cache_copies 0 # number of cache copies performed 144system.l2c.writebacks::writebacks 73942 # number of writebacks 145system.l2c.writebacks::total 73942 # number of writebacks 146system.l2c.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses 147system.l2c.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses 148system.l2c.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses | 136system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 137system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 138system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 139system.l2c.blocked::no_targets 0 # number of cycles access was blocked 140system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 141system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 142system.l2c.fast_writes 0 # number of fast writes performed 143system.l2c.cache_copies 0 # number of cache copies performed 144system.l2c.writebacks::writebacks 73942 # number of writebacks 145system.l2c.writebacks::total 73942 # number of writebacks 146system.l2c.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses 147system.l2c.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses 148system.l2c.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses |
| 149system.l2c.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses 150system.l2c.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses 151system.l2c.ReadExReq_mshr_misses::cpu.data 116714 # number of ReadExReq MSHR misses 152system.l2c.ReadExReq_mshr_misses::total 116714 # number of ReadExReq MSHR misses | 149system.l2c.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses 150system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses 151system.l2c.ReadExReq_mshr_misses::cpu.data 116718 # number of ReadExReq MSHR misses 152system.l2c.ReadExReq_mshr_misses::total 116718 # number of ReadExReq MSHR misses |
| 153system.l2c.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses | 153system.l2c.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses |
| 154system.l2c.demand_mshr_misses::cpu.data 388629 # number of demand (read+write) MSHR misses 155system.l2c.demand_mshr_misses::total 401921 # number of demand (read+write) MSHR misses | 154system.l2c.demand_mshr_misses::cpu.data 388633 # number of demand (read+write) MSHR misses 155system.l2c.demand_mshr_misses::total 401925 # number of demand (read+write) MSHR misses |
| 156system.l2c.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses | 156system.l2c.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses |
| 157system.l2c.overall_mshr_misses::cpu.data 388629 # number of overall MSHR misses 158system.l2c.overall_mshr_misses::total 401921 # number of overall MSHR misses | 157system.l2c.overall_mshr_misses::cpu.data 388633 # number of overall MSHR misses 158system.l2c.overall_mshr_misses::total 401925 # number of overall MSHR misses |
| 159system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532266000 # number of ReadReq MSHR miss cycles 160system.l2c.ReadReq_mshr_miss_latency::cpu.data 10881875000 # number of ReadReq MSHR miss cycles 161system.l2c.ReadReq_mshr_miss_latency::total 11414141000 # number of ReadReq MSHR miss cycles | 159system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532266000 # number of ReadReq MSHR miss cycles 160system.l2c.ReadReq_mshr_miss_latency::cpu.data 10881875000 # number of ReadReq MSHR miss cycles 161system.l2c.ReadReq_mshr_miss_latency::total 11414141000 # number of ReadReq MSHR miss cycles |
| 162system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 380000 # number of UpgradeReq MSHR miss cycles 163system.l2c.UpgradeReq_mshr_miss_latency::total 380000 # number of UpgradeReq MSHR miss cycles 164system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669239000 # number of ReadExReq MSHR miss cycles 165system.l2c.ReadExReq_mshr_miss_latency::total 4669239000 # number of ReadExReq MSHR miss cycles | 162system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 620000 # number of UpgradeReq MSHR miss cycles 163system.l2c.UpgradeReq_mshr_miss_latency::total 620000 # number of UpgradeReq MSHR miss cycles 164system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669399000 # number of ReadExReq MSHR miss cycles 165system.l2c.ReadExReq_mshr_miss_latency::total 4669399000 # number of ReadExReq MSHR miss cycles |
| 166system.l2c.demand_mshr_miss_latency::cpu.inst 532266000 # number of demand (read+write) MSHR miss cycles | 166system.l2c.demand_mshr_miss_latency::cpu.inst 532266000 # number of demand (read+write) MSHR miss cycles |
| 167system.l2c.demand_mshr_miss_latency::cpu.data 15551114000 # number of demand (read+write) MSHR miss cycles 168system.l2c.demand_mshr_miss_latency::total 16083380000 # number of demand (read+write) MSHR miss cycles | 167system.l2c.demand_mshr_miss_latency::cpu.data 15551274000 # number of demand (read+write) MSHR miss cycles 168system.l2c.demand_mshr_miss_latency::total 16083540000 # number of demand (read+write) MSHR miss cycles |
| 169system.l2c.overall_mshr_miss_latency::cpu.inst 532266000 # number of overall MSHR miss cycles | 169system.l2c.overall_mshr_miss_latency::cpu.inst 532266000 # number of overall MSHR miss cycles |
| 170system.l2c.overall_mshr_miss_latency::cpu.data 15551114000 # number of overall MSHR miss cycles 171system.l2c.overall_mshr_miss_latency::total 16083380000 # number of overall MSHR miss cycles | 170system.l2c.overall_mshr_miss_latency::cpu.data 15551274000 # number of overall MSHR miss cycles 171system.l2c.overall_mshr_miss_latency::total 16083540000 # number of overall MSHR miss cycles |
| 172system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772639030 # number of ReadReq MSHR uncacheable cycles 173system.l2c.ReadReq_mshr_uncacheable_latency::total 772639030 # number of ReadReq MSHR uncacheable cycles 174system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1072677000 # number of WriteReq MSHR uncacheable cycles 175system.l2c.WriteReq_mshr_uncacheable_latency::total 1072677000 # number of WriteReq MSHR uncacheable cycles 176system.l2c.overall_mshr_uncacheable_latency::cpu.data 1845316030 # number of overall MSHR uncacheable cycles 177system.l2c.overall_mshr_uncacheable_latency::total 1845316030 # number of overall MSHR uncacheable cycles 178system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for ReadReq accesses | 172system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772639030 # number of ReadReq MSHR uncacheable cycles 173system.l2c.ReadReq_mshr_uncacheable_latency::total 772639030 # number of ReadReq MSHR uncacheable cycles 174system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1072677000 # number of WriteReq MSHR uncacheable cycles 175system.l2c.WriteReq_mshr_uncacheable_latency::total 1072677000 # number of WriteReq MSHR uncacheable cycles 176system.l2c.overall_mshr_uncacheable_latency::cpu.data 1845316030 # number of overall MSHR uncacheable cycles 177system.l2c.overall_mshr_uncacheable_latency::total 1845316030 # number of overall MSHR uncacheable cycles 178system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for ReadReq accesses |
| 179system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250199 # mshr miss rate for ReadReq accesses 180system.l2c.ReadReq_mshr_miss_rate::total 0.141451 # mshr miss rate for ReadReq accesses 181system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.571429 # mshr miss rate for UpgradeReq accesses 182system.l2c.UpgradeReq_mshr_miss_rate::total 0.571429 # mshr miss rate for UpgradeReq accesses 183system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383712 # mshr miss rate for ReadExReq accesses 184system.l2c.ReadExReq_mshr_miss_rate::total 0.383712 # mshr miss rate for ReadExReq accesses | 179system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250187 # mshr miss rate for ReadReq accesses 180system.l2c.ReadReq_mshr_miss_rate::total 0.141447 # mshr miss rate for ReadReq accesses 181system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.777778 # mshr miss rate for UpgradeReq accesses 182system.l2c.UpgradeReq_mshr_miss_rate::total 0.777778 # mshr miss rate for UpgradeReq accesses 183system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383533 # mshr miss rate for ReadExReq accesses 184system.l2c.ReadExReq_mshr_miss_rate::total 0.383533 # mshr miss rate for ReadExReq accesses |
| 185system.l2c.demand_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for demand accesses | 185system.l2c.demand_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for demand accesses |
| 186system.l2c.demand_mshr_miss_rate::cpu.data 0.279395 # mshr miss rate for demand accesses 187system.l2c.demand_mshr_miss_rate::total 0.173207 # mshr miss rate for demand accesses | 186system.l2c.demand_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for demand accesses 187system.l2c.demand_mshr_miss_rate::total 0.173193 # mshr miss rate for demand accesses |
| 188system.l2c.overall_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for overall accesses | 188system.l2c.overall_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for overall accesses |
| 189system.l2c.overall_mshr_miss_rate::cpu.data 0.279395 # mshr miss rate for overall accesses 190system.l2c.overall_mshr_miss_rate::total 0.173207 # mshr miss rate for overall accesses | 189system.l2c.overall_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for overall accesses 190system.l2c.overall_mshr_miss_rate::total 0.173193 # mshr miss rate for overall accesses |
| 191system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669 # average ReadReq mshr miss latency 192system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445 # average ReadReq mshr miss latency 193system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987 # average ReadReq mshr miss latency | 191system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669 # average ReadReq mshr miss latency 192system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445 # average ReadReq mshr miss latency 193system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987 # average ReadReq mshr miss latency |
| 194system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 47500 # average UpgradeReq mshr miss latency 195system.l2c.UpgradeReq_avg_mshr_miss_latency::total 47500 # average UpgradeReq mshr miss latency 196system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817640 # average ReadExReq mshr miss latency 197system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817640 # average ReadExReq mshr miss latency | 194system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286 # average UpgradeReq mshr miss latency 195system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286 # average UpgradeReq mshr miss latency 196system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817440 # average ReadExReq mshr miss latency 197system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817440 # average ReadExReq mshr miss latency |
| 198system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency | 198system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency |
| 199system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320524 # average overall mshr miss latency 200system.l2c.demand_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency | 199system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency 200system.l2c.demand_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency |
| 201system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency | 201system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency |
| 202system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320524 # average overall mshr miss latency 203system.l2c.overall_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency | 202system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency 203system.l2c.overall_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency |
| 204system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 205system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 206system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 207system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 208system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 209system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 210system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 211system.iocache.replacements 41685 # number of replacements | 204system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 205system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 206system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 207system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 208system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 209system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 210system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 211system.iocache.replacements 41685 # number of replacements |
| 212system.iocache.tagsinuse 1.356962 # Cycle average of tags in use | 212system.iocache.tagsinuse 1.356968 # Cycle average of tags in use |
| 213system.iocache.total_refs 0 # Total number of references to valid blocks. 214system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 215system.iocache.avg_refs 0 # Average number of references to valid blocks. 216system.iocache.warmup_cycle 1753491316000 # Cycle when the warmup percentage was hit. | 213system.iocache.total_refs 0 # Total number of references to valid blocks. 214system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. 215system.iocache.avg_refs 0 # Average number of references to valid blocks. 216system.iocache.warmup_cycle 1753491316000 # Cycle when the warmup percentage was hit. |
| 217system.iocache.occ_blocks::tsunami.ide 1.356962 # Average occupied blocks per requestor 218system.iocache.occ_percent::tsunami.ide 0.084810 # Average percentage of cache occupancy 219system.iocache.occ_percent::total 0.084810 # Average percentage of cache occupancy | 217system.iocache.occ_blocks::tsunami.ide 1.356968 # Average occupied blocks per requestor 218system.iocache.occ_percent::tsunami.ide 0.084811 # Average percentage of cache occupancy 219system.iocache.occ_percent::total 0.084811 # Average percentage of cache occupancy |
| 220system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 221system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 222system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 223system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 224system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 225system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 226system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 227system.iocache.overall_misses::total 41725 # number of overall misses --- 111 unchanged lines hidden (view full) --- 339system.cpu.itb.write_hits 0 # DTB write hits 340system.cpu.itb.write_misses 0 # DTB write misses 341system.cpu.itb.write_acv 0 # DTB write access violations 342system.cpu.itb.write_accesses 0 # DTB write accesses 343system.cpu.itb.data_hits 0 # DTB hits 344system.cpu.itb.data_misses 0 # DTB misses 345system.cpu.itb.data_acv 0 # DTB access violations 346system.cpu.itb.data_accesses 0 # DTB accesses | 220system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 221system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 222system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 223system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 224system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 225system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 226system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 227system.iocache.overall_misses::total 41725 # number of overall misses --- 111 unchanged lines hidden (view full) --- 339system.cpu.itb.write_hits 0 # DTB write hits 340system.cpu.itb.write_misses 0 # DTB write misses 341system.cpu.itb.write_acv 0 # DTB write access violations 342system.cpu.itb.write_accesses 0 # DTB write accesses 343system.cpu.itb.data_hits 0 # DTB hits 344system.cpu.itb.data_misses 0 # DTB misses 345system.cpu.itb.data_acv 0 # DTB access violations 346system.cpu.itb.data_accesses 0 # DTB accesses |
| 347system.cpu.numCycles 3841704548 # number of cpu cycles simulated | 347system.cpu.numCycles 3841706084 # number of cpu cycles simulated |
| 348system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 349system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 350system.cpu.committedInsts 56187824 # Number of instructions committed 351system.cpu.committedOps 56187824 # Number of ops (including micro ops) committed 352system.cpu.num_int_alu_accesses 52059470 # Number of integer alu accesses 353system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 354system.cpu.num_func_calls 1483670 # number of times a function call or return occured 355system.cpu.num_conditional_control_insts 6469221 # number of instructions that are conditional controls 356system.cpu.num_int_insts 52059470 # number of integer instructions 357system.cpu.num_fp_insts 324460 # number of float instructions 358system.cpu.num_int_register_reads 71329755 # number of times the integer registers were read 359system.cpu.num_int_register_writes 38524240 # number of times the integer registers were written 360system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 361system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 362system.cpu.num_mem_refs 15475451 # number of memory refs 363system.cpu.num_load_insts 9102635 # Number of load instructions 364system.cpu.num_store_insts 6372816 # Number of store instructions | 348system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 349system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 350system.cpu.committedInsts 56187824 # Number of instructions committed 351system.cpu.committedOps 56187824 # Number of ops (including micro ops) committed 352system.cpu.num_int_alu_accesses 52059470 # Number of integer alu accesses 353system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 354system.cpu.num_func_calls 1483670 # number of times a function call or return occured 355system.cpu.num_conditional_control_insts 6469221 # number of instructions that are conditional controls 356system.cpu.num_int_insts 52059470 # number of integer instructions 357system.cpu.num_fp_insts 324460 # number of float instructions 358system.cpu.num_int_register_reads 71329755 # number of times the integer registers were read 359system.cpu.num_int_register_writes 38524240 # number of times the integer registers were written 360system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 361system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 362system.cpu.num_mem_refs 15475451 # number of memory refs 363system.cpu.num_load_insts 9102635 # Number of load instructions 364system.cpu.num_store_insts 6372816 # Number of store instructions |
| 365system.cpu.num_idle_cycles 3589583028.998131 # Number of idle cycles 366system.cpu.num_busy_cycles 252121519.001869 # Number of busy cycles 367system.cpu.not_idle_fraction 0.065628 # Percentage of non-idle cycles 368system.cpu.idle_fraction 0.934372 # Percentage of idle cycles | 365system.cpu.num_idle_cycles 3589579952.998131 # Number of idle cycles 366system.cpu.num_busy_cycles 252126131.001869 # Number of busy cycles 367system.cpu.not_idle_fraction 0.065629 # Percentage of non-idle cycles 368system.cpu.idle_fraction 0.934371 # Percentage of idle cycles |
| 369system.cpu.kern.inst.arm 0 # number of arm instructions executed 370system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 371system.cpu.kern.inst.hwrei 212104 # number of hwrei instructions executed 372system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl 373system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl 374system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl 375system.cpu.kern.ipl_count::31 106285 57.99% 100.00% # number of times we switched to this ipl 376system.cpu.kern.ipl_count::total 183281 # number of times we switched to this ipl 377system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl 378system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 379system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl 380system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl 381system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl | 369system.cpu.kern.inst.arm 0 # number of arm instructions executed 370system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 371system.cpu.kern.inst.hwrei 212104 # number of hwrei instructions executed 372system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl 373system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl 374system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl 375system.cpu.kern.ipl_count::31 106285 57.99% 100.00% # number of times we switched to this ipl 376system.cpu.kern.ipl_count::total 183281 # number of times we switched to this ipl 377system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl 378system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 379system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl 380system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl 381system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl |
| 382system.cpu.kern.ipl_ticks::0 1861395067500 96.90% 96.90% # number of cycles we spent at this ipl | 382system.cpu.kern.ipl_ticks::0 1861395652500 96.90% 96.90% # number of cycles we spent at this ipl |
| 383system.cpu.kern.ipl_ticks::21 90398000 0.00% 96.91% # number of cycles we spent at this ipl | 383system.cpu.kern.ipl_ticks::21 90398000 0.00% 96.91% # number of cycles we spent at this ipl |
| 384system.cpu.kern.ipl_ticks::22 587303500 0.03% 96.94% # number of cycles we spent at this ipl 385system.cpu.kern.ipl_ticks::31 58778672000 3.06% 100.00% # number of cycles we spent at this ipl 386system.cpu.kern.ipl_ticks::total 1920851441000 # number of cycles we spent at this ipl | 384system.cpu.kern.ipl_ticks::22 587366500 0.03% 96.94% # number of cycles we spent at this ipl 385system.cpu.kern.ipl_ticks::31 58778792000 3.06% 100.00% # number of cycles we spent at this ipl 386system.cpu.kern.ipl_ticks::total 1920852209000 # number of cycles we spent at this ipl |
| 387system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl 388system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 389system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 390system.cpu.kern.ipl_used::31 0.692120 # fraction of swpipl calls that actually changed the ipl 391system.cpu.kern.ipl_used::total 0.814001 # fraction of swpipl calls that actually changed the ipl 392system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 393system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 394system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed --- 47 unchanged lines hidden (view full) --- 442system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches 443system.cpu.kern.mode_good::kernel 1908 444system.cpu.kern.mode_good::user 1738 445system.cpu.kern.mode_good::idle 170 446system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches 447system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 448system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches 449system.cpu.kern.mode_switch_good::total 0.391706 # fraction of useful protection mode switches | 387system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl 388system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 389system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 390system.cpu.kern.ipl_used::31 0.692120 # fraction of swpipl calls that actually changed the ipl 391system.cpu.kern.ipl_used::total 0.814001 # fraction of swpipl calls that actually changed the ipl 392system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 393system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 394system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed --- 47 unchanged lines hidden (view full) --- 442system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches 443system.cpu.kern.mode_good::kernel 1908 444system.cpu.kern.mode_good::user 1738 445system.cpu.kern.mode_good::idle 170 446system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches 447system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 448system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches 449system.cpu.kern.mode_switch_good::total 0.391706 # fraction of useful protection mode switches |
| 450system.cpu.kern.mode_ticks::kernel 46234544000 2.41% 2.41% # number of ticks spent at the given mode 451system.cpu.kern.mode_ticks::user 5257252000 0.27% 2.68% # number of ticks spent at the given mode 452system.cpu.kern.mode_ticks::idle 1869359638000 97.32% 100.00% # number of ticks spent at the given mode | 450system.cpu.kern.mode_ticks::kernel 46234707000 2.41% 2.41% # number of ticks spent at the given mode 451system.cpu.kern.mode_ticks::user 5259387000 0.27% 2.68% # number of ticks spent at the given mode 452system.cpu.kern.mode_ticks::idle 1869358108000 97.32% 100.00% # number of ticks spent at the given mode |
| 453system.cpu.kern.swap_context 4178 # number of times the context was actually changed 454system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 455system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 456system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 457system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 458system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 459system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 460system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 477system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 478system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 479system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 480system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 481system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 482system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 483system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 484system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 453system.cpu.kern.swap_context 4178 # number of times the context was actually changed 454system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 455system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 456system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 457system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 458system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 459system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 460system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 16 unchanged lines hidden (view full) --- 477system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 478system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 479system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 480system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 481system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 482system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 483system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 484system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 485system.cpu.icache.replacements 928851 # number of replacements 486system.cpu.icache.tagsinuse 508.732124 # Cycle average of tags in use 487system.cpu.icache.total_refs 55270141 # Total number of references to valid blocks. 488system.cpu.icache.sampled_refs 929362 # Sample count of references to valid blocks. 489system.cpu.icache.avg_refs 59.471058 # Average number of references to valid blocks. | 485system.cpu.icache.replacements 928849 # number of replacements 486system.cpu.icache.tagsinuse 508.732123 # Cycle average of tags in use 487system.cpu.icache.total_refs 55270143 # Total number of references to valid blocks. 488system.cpu.icache.sampled_refs 929360 # Sample count of references to valid blocks. 489system.cpu.icache.avg_refs 59.471188 # Average number of references to valid blocks. |
| 490system.cpu.icache.warmup_cycle 35877190000 # Cycle when the warmup percentage was hit. | 490system.cpu.icache.warmup_cycle 35877190000 # Cycle when the warmup percentage was hit. |
| 491system.cpu.icache.occ_blocks::cpu.inst 508.732124 # Average occupied blocks per requestor | 491system.cpu.icache.occ_blocks::cpu.inst 508.732123 # Average occupied blocks per requestor |
| 492system.cpu.icache.occ_percent::cpu.inst 0.993617 # Average percentage of cache occupancy 493system.cpu.icache.occ_percent::total 0.993617 # Average percentage of cache occupancy | 492system.cpu.icache.occ_percent::cpu.inst 0.993617 # Average percentage of cache occupancy 493system.cpu.icache.occ_percent::total 0.993617 # Average percentage of cache occupancy |
| 494system.cpu.icache.ReadReq_hits::cpu.inst 55270141 # number of ReadReq hits 495system.cpu.icache.ReadReq_hits::total 55270141 # number of ReadReq hits 496system.cpu.icache.demand_hits::cpu.inst 55270141 # number of demand (read+write) hits 497system.cpu.icache.demand_hits::total 55270141 # number of demand (read+write) hits 498system.cpu.icache.overall_hits::cpu.inst 55270141 # number of overall hits 499system.cpu.icache.overall_hits::total 55270141 # number of overall hits 500system.cpu.icache.ReadReq_misses::cpu.inst 929522 # number of ReadReq misses 501system.cpu.icache.ReadReq_misses::total 929522 # number of ReadReq misses 502system.cpu.icache.demand_misses::cpu.inst 929522 # number of demand (read+write) misses 503system.cpu.icache.demand_misses::total 929522 # number of demand (read+write) misses 504system.cpu.icache.overall_misses::cpu.inst 929522 # number of overall misses 505system.cpu.icache.overall_misses::total 929522 # number of overall misses 506system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854472500 # number of ReadReq miss cycles 507system.cpu.icache.ReadReq_miss_latency::total 13854472500 # number of ReadReq miss cycles 508system.cpu.icache.demand_miss_latency::cpu.inst 13854472500 # number of demand (read+write) miss cycles 509system.cpu.icache.demand_miss_latency::total 13854472500 # number of demand (read+write) miss cycles 510system.cpu.icache.overall_miss_latency::cpu.inst 13854472500 # number of overall miss cycles 511system.cpu.icache.overall_miss_latency::total 13854472500 # number of overall miss cycles | 494system.cpu.icache.ReadReq_hits::cpu.inst 55270143 # number of ReadReq hits 495system.cpu.icache.ReadReq_hits::total 55270143 # number of ReadReq hits 496system.cpu.icache.demand_hits::cpu.inst 55270143 # number of demand (read+write) hits 497system.cpu.icache.demand_hits::total 55270143 # number of demand (read+write) hits 498system.cpu.icache.overall_hits::cpu.inst 55270143 # number of overall hits 499system.cpu.icache.overall_hits::total 55270143 # number of overall hits 500system.cpu.icache.ReadReq_misses::cpu.inst 929520 # number of ReadReq misses 501system.cpu.icache.ReadReq_misses::total 929520 # number of ReadReq misses 502system.cpu.icache.demand_misses::cpu.inst 929520 # number of demand (read+write) misses 503system.cpu.icache.demand_misses::total 929520 # number of demand (read+write) misses 504system.cpu.icache.overall_misses::cpu.inst 929520 # number of overall misses 505system.cpu.icache.overall_misses::total 929520 # number of overall misses 506system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854449500 # number of ReadReq miss cycles 507system.cpu.icache.ReadReq_miss_latency::total 13854449500 # number of ReadReq miss cycles 508system.cpu.icache.demand_miss_latency::cpu.inst 13854449500 # number of demand (read+write) miss cycles 509system.cpu.icache.demand_miss_latency::total 13854449500 # number of demand (read+write) miss cycles 510system.cpu.icache.overall_miss_latency::cpu.inst 13854449500 # number of overall miss cycles 511system.cpu.icache.overall_miss_latency::total 13854449500 # number of overall miss cycles |
| 512system.cpu.icache.ReadReq_accesses::cpu.inst 56199663 # number of ReadReq accesses(hits+misses) 513system.cpu.icache.ReadReq_accesses::total 56199663 # number of ReadReq accesses(hits+misses) 514system.cpu.icache.demand_accesses::cpu.inst 56199663 # number of demand (read+write) accesses 515system.cpu.icache.demand_accesses::total 56199663 # number of demand (read+write) accesses 516system.cpu.icache.overall_accesses::cpu.inst 56199663 # number of overall (read+write) accesses 517system.cpu.icache.overall_accesses::total 56199663 # number of overall (read+write) accesses 518system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses 519system.cpu.icache.ReadReq_miss_rate::total 0.016540 # miss rate for ReadReq accesses 520system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses 521system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses 522system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses 523system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses | 512system.cpu.icache.ReadReq_accesses::cpu.inst 56199663 # number of ReadReq accesses(hits+misses) 513system.cpu.icache.ReadReq_accesses::total 56199663 # number of ReadReq accesses(hits+misses) 514system.cpu.icache.demand_accesses::cpu.inst 56199663 # number of demand (read+write) accesses 515system.cpu.icache.demand_accesses::total 56199663 # number of demand (read+write) accesses 516system.cpu.icache.overall_accesses::cpu.inst 56199663 # number of overall (read+write) accesses 517system.cpu.icache.overall_accesses::total 56199663 # number of overall (read+write) accesses 518system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses 519system.cpu.icache.ReadReq_miss_rate::total 0.016540 # miss rate for ReadReq accesses 520system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses 521system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses 522system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses 523system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses |
| 524system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.943078 # average ReadReq miss latency 525system.cpu.icache.ReadReq_avg_miss_latency::total 14904.943078 # average ReadReq miss latency 526system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.943078 # average overall miss latency 527system.cpu.icache.demand_avg_miss_latency::total 14904.943078 # average overall miss latency 528system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.943078 # average overall miss latency 529system.cpu.icache.overall_avg_miss_latency::total 14904.943078 # average overall miss latency | 524system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.950405 # average ReadReq miss latency 525system.cpu.icache.ReadReq_avg_miss_latency::total 14904.950405 # average ReadReq miss latency 526system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency 527system.cpu.icache.demand_avg_miss_latency::total 14904.950405 # average overall miss latency 528system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency 529system.cpu.icache.overall_avg_miss_latency::total 14904.950405 # average overall miss latency |
| 530system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 531system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 532system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 533system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 534system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 535system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 536system.cpu.icache.fast_writes 0 # number of fast writes performed 537system.cpu.icache.cache_copies 0 # number of cache copies performed | 530system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 531system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 532system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 533system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 534system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 535system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 536system.cpu.icache.fast_writes 0 # number of fast writes performed 537system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 538system.cpu.icache.writebacks::writebacks 85 # number of writebacks 539system.cpu.icache.writebacks::total 85 # number of writebacks 540system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929522 # number of ReadReq MSHR misses 541system.cpu.icache.ReadReq_mshr_misses::total 929522 # number of ReadReq MSHR misses 542system.cpu.icache.demand_mshr_misses::cpu.inst 929522 # number of demand (read+write) MSHR misses 543system.cpu.icache.demand_mshr_misses::total 929522 # number of demand (read+write) MSHR misses 544system.cpu.icache.overall_mshr_misses::cpu.inst 929522 # number of overall MSHR misses 545system.cpu.icache.overall_mshr_misses::total 929522 # number of overall MSHR misses 546system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11065220000 # number of ReadReq MSHR miss cycles 547system.cpu.icache.ReadReq_mshr_miss_latency::total 11065220000 # number of ReadReq MSHR miss cycles 548system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11065220000 # number of demand (read+write) MSHR miss cycles 549system.cpu.icache.demand_mshr_miss_latency::total 11065220000 # number of demand (read+write) MSHR miss cycles 550system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11065220000 # number of overall MSHR miss cycles 551system.cpu.icache.overall_mshr_miss_latency::total 11065220000 # number of overall MSHR miss cycles | 538system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929520 # number of ReadReq MSHR misses 539system.cpu.icache.ReadReq_mshr_misses::total 929520 # number of ReadReq MSHR misses 540system.cpu.icache.demand_mshr_misses::cpu.inst 929520 # number of demand (read+write) MSHR misses 541system.cpu.icache.demand_mshr_misses::total 929520 # number of demand (read+write) MSHR misses 542system.cpu.icache.overall_mshr_misses::cpu.inst 929520 # number of overall MSHR misses 543system.cpu.icache.overall_mshr_misses::total 929520 # number of overall MSHR misses 544system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11065203000 # number of ReadReq MSHR miss cycles 545system.cpu.icache.ReadReq_mshr_miss_latency::total 11065203000 # number of ReadReq MSHR miss cycles 546system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11065203000 # number of demand (read+write) MSHR miss cycles 547system.cpu.icache.demand_mshr_miss_latency::total 11065203000 # number of demand (read+write) MSHR miss cycles 548system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11065203000 # number of overall MSHR miss cycles 549system.cpu.icache.overall_mshr_miss_latency::total 11065203000 # number of overall MSHR miss cycles |
| 552system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses 553system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses 554system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses 555system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses 556system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses 557system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses | 550system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses 552system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses 553system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses 554system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses 555system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses |
| 558system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.204527 # average ReadReq mshr miss latency 559system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.204527 # average ReadReq mshr miss latency 560system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.204527 # average overall mshr miss latency 561system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.204527 # average overall mshr miss latency 562system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.204527 # average overall mshr miss latency 563system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.204527 # average overall mshr miss latency | 556system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.211851 # average ReadReq mshr miss latency 557system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.211851 # average ReadReq mshr miss latency 558system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency 559system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency 560system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency 561system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency |
| 564system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 562system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 565system.cpu.dcache.replacements 1390643 # number of replacements | 563system.cpu.dcache.replacements 1390657 # number of replacements |
| 566system.cpu.dcache.tagsinuse 511.983813 # Cycle average of tags in use | 564system.cpu.dcache.tagsinuse 511.983813 # Cycle average of tags in use |
| 567system.cpu.dcache.total_refs 14050710 # Total number of references to valid blocks. 568system.cpu.dcache.sampled_refs 1391155 # Sample count of references to valid blocks. 569system.cpu.dcache.avg_refs 10.100032 # Average number of references to valid blocks. | 565system.cpu.dcache.total_refs 14050696 # Total number of references to valid blocks. 566system.cpu.dcache.sampled_refs 1391169 # Sample count of references to valid blocks. 567system.cpu.dcache.avg_refs 10.099920 # Average number of references to valid blocks. |
| 570system.cpu.dcache.warmup_cycle 85768000 # Cycle when the warmup percentage was hit. 571system.cpu.dcache.occ_blocks::cpu.data 511.983813 # Average occupied blocks per requestor 572system.cpu.dcache.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy 573system.cpu.dcache.occ_percent::total 0.999968 # Average percentage of cache occupancy | 568system.cpu.dcache.warmup_cycle 85768000 # Cycle when the warmup percentage was hit. 569system.cpu.dcache.occ_blocks::cpu.data 511.983813 # Average occupied blocks per requestor 570system.cpu.dcache.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy 571system.cpu.dcache.occ_percent::total 0.999968 # Average percentage of cache occupancy |
| 574system.cpu.dcache.ReadReq_hits::cpu.data 7815347 # number of ReadReq hits 575system.cpu.dcache.ReadReq_hits::total 7815347 # number of ReadReq hits 576system.cpu.dcache.WriteReq_hits::cpu.data 5853082 # number of WriteReq hits 577system.cpu.dcache.WriteReq_hits::total 5853082 # number of WriteReq hits | 572system.cpu.dcache.ReadReq_hits::cpu.data 7815339 # number of ReadReq hits 573system.cpu.dcache.ReadReq_hits::total 7815339 # number of ReadReq hits 574system.cpu.dcache.WriteReq_hits::cpu.data 5853076 # number of WriteReq hits 575system.cpu.dcache.WriteReq_hits::total 5853076 # number of WriteReq hits |
| 578system.cpu.dcache.LoadLockedReq_hits::cpu.data 182979 # number of LoadLockedReq hits 579system.cpu.dcache.LoadLockedReq_hits::total 182979 # number of LoadLockedReq hits 580system.cpu.dcache.StoreCondReq_hits::cpu.data 199284 # number of StoreCondReq hits 581system.cpu.dcache.StoreCondReq_hits::total 199284 # number of StoreCondReq hits | 576system.cpu.dcache.LoadLockedReq_hits::cpu.data 182979 # number of LoadLockedReq hits 577system.cpu.dcache.LoadLockedReq_hits::total 182979 # number of LoadLockedReq hits 578system.cpu.dcache.StoreCondReq_hits::cpu.data 199284 # number of StoreCondReq hits 579system.cpu.dcache.StoreCondReq_hits::total 199284 # number of StoreCondReq hits |
| 582system.cpu.dcache.demand_hits::cpu.data 13668429 # number of demand (read+write) hits 583system.cpu.dcache.demand_hits::total 13668429 # number of demand (read+write) hits 584system.cpu.dcache.overall_hits::cpu.data 13668429 # number of overall hits 585system.cpu.dcache.overall_hits::total 13668429 # number of overall hits 586system.cpu.dcache.ReadReq_misses::cpu.data 1069514 # number of ReadReq misses 587system.cpu.dcache.ReadReq_misses::total 1069514 # number of ReadReq misses 588system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses 589system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses | 580system.cpu.dcache.demand_hits::cpu.data 13668415 # number of demand (read+write) hits 581system.cpu.dcache.demand_hits::total 13668415 # number of demand (read+write) hits 582system.cpu.dcache.overall_hits::cpu.data 13668415 # number of overall hits 583system.cpu.dcache.overall_hits::total 13668415 # number of overall hits 584system.cpu.dcache.ReadReq_misses::cpu.data 1069522 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 1069522 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.data 304341 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 304341 # number of WriteReq misses |
| 590system.cpu.dcache.LoadLockedReq_misses::cpu.data 17326 # number of LoadLockedReq misses 591system.cpu.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses | 588system.cpu.dcache.LoadLockedReq_misses::cpu.data 17326 # number of LoadLockedReq misses 589system.cpu.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses |
| 592system.cpu.dcache.demand_misses::cpu.data 1373849 # number of demand (read+write) misses 593system.cpu.dcache.demand_misses::total 1373849 # number of demand (read+write) misses 594system.cpu.dcache.overall_misses::cpu.data 1373849 # number of overall misses 595system.cpu.dcache.overall_misses::total 1373849 # number of overall misses 596system.cpu.dcache.ReadReq_miss_latency::cpu.data 26655510000 # number of ReadReq miss cycles 597system.cpu.dcache.ReadReq_miss_latency::total 26655510000 # number of ReadReq miss cycles 598system.cpu.dcache.WriteReq_miss_latency::cpu.data 9230954000 # number of WriteReq miss cycles 599system.cpu.dcache.WriteReq_miss_latency::total 9230954000 # number of WriteReq miss cycles | 590system.cpu.dcache.demand_misses::cpu.data 1373863 # number of demand (read+write) misses 591system.cpu.dcache.demand_misses::total 1373863 # number of demand (read+write) misses 592system.cpu.dcache.overall_misses::cpu.data 1373863 # number of overall misses 593system.cpu.dcache.overall_misses::total 1373863 # number of overall misses 594system.cpu.dcache.ReadReq_miss_latency::cpu.data 26656014000 # number of ReadReq miss cycles 595system.cpu.dcache.ReadReq_miss_latency::total 26656014000 # number of ReadReq miss cycles 596system.cpu.dcache.WriteReq_miss_latency::cpu.data 9232792000 # number of WriteReq miss cycles 597system.cpu.dcache.WriteReq_miss_latency::total 9232792000 # number of WriteReq miss cycles |
| 600system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 248493000 # number of LoadLockedReq miss cycles 601system.cpu.dcache.LoadLockedReq_miss_latency::total 248493000 # number of LoadLockedReq miss cycles | 598system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 248493000 # number of LoadLockedReq miss cycles 599system.cpu.dcache.LoadLockedReq_miss_latency::total 248493000 # number of LoadLockedReq miss cycles |
| 602system.cpu.dcache.demand_miss_latency::cpu.data 35886464000 # number of demand (read+write) miss cycles 603system.cpu.dcache.demand_miss_latency::total 35886464000 # number of demand (read+write) miss cycles 604system.cpu.dcache.overall_miss_latency::cpu.data 35886464000 # number of overall miss cycles 605system.cpu.dcache.overall_miss_latency::total 35886464000 # number of overall miss cycles | 600system.cpu.dcache.demand_miss_latency::cpu.data 35888806000 # number of demand (read+write) miss cycles 601system.cpu.dcache.demand_miss_latency::total 35888806000 # number of demand (read+write) miss cycles 602system.cpu.dcache.overall_miss_latency::cpu.data 35888806000 # number of overall miss cycles 603system.cpu.dcache.overall_miss_latency::total 35888806000 # number of overall miss cycles |
| 606system.cpu.dcache.ReadReq_accesses::cpu.data 8884861 # number of ReadReq accesses(hits+misses) 607system.cpu.dcache.ReadReq_accesses::total 8884861 # number of ReadReq accesses(hits+misses) 608system.cpu.dcache.WriteReq_accesses::cpu.data 6157417 # number of WriteReq accesses(hits+misses) 609system.cpu.dcache.WriteReq_accesses::total 6157417 # number of WriteReq accesses(hits+misses) 610system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200305 # number of LoadLockedReq accesses(hits+misses) 611system.cpu.dcache.LoadLockedReq_accesses::total 200305 # number of LoadLockedReq accesses(hits+misses) 612system.cpu.dcache.StoreCondReq_accesses::cpu.data 199284 # number of StoreCondReq accesses(hits+misses) 613system.cpu.dcache.StoreCondReq_accesses::total 199284 # number of StoreCondReq accesses(hits+misses) 614system.cpu.dcache.demand_accesses::cpu.data 15042278 # number of demand (read+write) accesses 615system.cpu.dcache.demand_accesses::total 15042278 # number of demand (read+write) accesses 616system.cpu.dcache.overall_accesses::cpu.data 15042278 # number of overall (read+write) accesses 617system.cpu.dcache.overall_accesses::total 15042278 # number of overall (read+write) accesses | 604system.cpu.dcache.ReadReq_accesses::cpu.data 8884861 # number of ReadReq accesses(hits+misses) 605system.cpu.dcache.ReadReq_accesses::total 8884861 # number of ReadReq accesses(hits+misses) 606system.cpu.dcache.WriteReq_accesses::cpu.data 6157417 # number of WriteReq accesses(hits+misses) 607system.cpu.dcache.WriteReq_accesses::total 6157417 # number of WriteReq accesses(hits+misses) 608system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200305 # number of LoadLockedReq accesses(hits+misses) 609system.cpu.dcache.LoadLockedReq_accesses::total 200305 # number of LoadLockedReq accesses(hits+misses) 610system.cpu.dcache.StoreCondReq_accesses::cpu.data 199284 # number of StoreCondReq accesses(hits+misses) 611system.cpu.dcache.StoreCondReq_accesses::total 199284 # number of StoreCondReq accesses(hits+misses) 612system.cpu.dcache.demand_accesses::cpu.data 15042278 # number of demand (read+write) accesses 613system.cpu.dcache.demand_accesses::total 15042278 # number of demand (read+write) accesses 614system.cpu.dcache.overall_accesses::cpu.data 15042278 # number of overall (read+write) accesses 615system.cpu.dcache.overall_accesses::total 15042278 # number of overall (read+write) accesses |
| 618system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120375 # miss rate for ReadReq accesses 619system.cpu.dcache.ReadReq_miss_rate::total 0.120375 # miss rate for ReadReq accesses 620system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049426 # miss rate for WriteReq accesses 621system.cpu.dcache.WriteReq_miss_rate::total 0.049426 # miss rate for WriteReq accesses | 616system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120376 # miss rate for ReadReq accesses 617system.cpu.dcache.ReadReq_miss_rate::total 0.120376 # miss rate for ReadReq accesses 618system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049427 # miss rate for WriteReq accesses 619system.cpu.dcache.WriteReq_miss_rate::total 0.049427 # miss rate for WriteReq accesses |
| 622system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086498 # miss rate for LoadLockedReq accesses 623system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086498 # miss rate for LoadLockedReq accesses 624system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses 625system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses 626system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses 627system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses | 620system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086498 # miss rate for LoadLockedReq accesses 621system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086498 # miss rate for LoadLockedReq accesses 622system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses 623system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses 624system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses 625system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses |
| 628system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.011760 # average ReadReq miss latency 629system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.011760 # average ReadReq miss latency 630system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30331.555687 # average WriteReq miss latency 631system.cpu.dcache.WriteReq_avg_miss_latency::total 30331.555687 # average WriteReq miss latency | 626system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.296575 # average ReadReq miss latency 627system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.296575 # average ReadReq miss latency 628system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30336.996987 # average WriteReq miss latency 629system.cpu.dcache.WriteReq_avg_miss_latency::total 30336.996987 # average WriteReq miss latency |
| 632system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470 # average LoadLockedReq miss latency 633system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470 # average LoadLockedReq miss latency | 630system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470 # average LoadLockedReq miss latency 631system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470 # average LoadLockedReq miss latency |
| 634system.cpu.dcache.demand_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency 635system.cpu.dcache.demand_avg_miss_latency::total 26121.112291 # average overall miss latency 636system.cpu.dcache.overall_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency 637system.cpu.dcache.overall_avg_miss_latency::total 26121.112291 # average overall miss latency | 632system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency 633system.cpu.dcache.demand_avg_miss_latency::total 26122.550793 # average overall miss latency 634system.cpu.dcache.overall_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::total 26122.550793 # average overall miss latency |
| 638system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 639system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 640system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 641system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 642system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 643system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 644system.cpu.dcache.fast_writes 0 # number of fast writes performed 645system.cpu.dcache.cache_copies 0 # number of cache copies performed | 636system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 637system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 641system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.dcache.fast_writes 0 # number of fast writes performed 643system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 646system.cpu.dcache.writebacks::writebacks 835138 # number of writebacks 647system.cpu.dcache.writebacks::total 835138 # number of writebacks 648system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069514 # number of ReadReq MSHR misses 649system.cpu.dcache.ReadReq_mshr_misses::total 1069514 # number of ReadReq MSHR misses 650system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses 651system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses | 644system.cpu.dcache.writebacks::writebacks 835149 # number of writebacks 645system.cpu.dcache.writebacks::total 835149 # number of writebacks 646system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069522 # number of ReadReq MSHR misses 647system.cpu.dcache.ReadReq_mshr_misses::total 1069522 # number of ReadReq MSHR misses 648system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304341 # number of WriteReq MSHR misses 649system.cpu.dcache.WriteReq_mshr_misses::total 304341 # number of WriteReq MSHR misses |
| 652system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17326 # number of LoadLockedReq MSHR misses 653system.cpu.dcache.LoadLockedReq_mshr_misses::total 17326 # number of LoadLockedReq MSHR misses | 650system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17326 # number of LoadLockedReq MSHR misses 651system.cpu.dcache.LoadLockedReq_mshr_misses::total 17326 # number of LoadLockedReq MSHR misses |
| 654system.cpu.dcache.demand_mshr_misses::cpu.data 1373849 # number of demand (read+write) MSHR misses 655system.cpu.dcache.demand_mshr_misses::total 1373849 # number of demand (read+write) MSHR misses 656system.cpu.dcache.overall_mshr_misses::cpu.data 1373849 # number of overall MSHR misses 657system.cpu.dcache.overall_mshr_misses::total 1373849 # number of overall MSHR misses 658system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23446923000 # number of ReadReq MSHR miss cycles 659system.cpu.dcache.ReadReq_mshr_miss_latency::total 23446923000 # number of ReadReq MSHR miss cycles 660system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8317949000 # number of WriteReq MSHR miss cycles 661system.cpu.dcache.WriteReq_mshr_miss_latency::total 8317949000 # number of WriteReq MSHR miss cycles | 652system.cpu.dcache.demand_mshr_misses::cpu.data 1373863 # number of demand (read+write) MSHR misses 653system.cpu.dcache.demand_mshr_misses::total 1373863 # number of demand (read+write) MSHR misses 654system.cpu.dcache.overall_mshr_misses::cpu.data 1373863 # number of overall MSHR misses 655system.cpu.dcache.overall_mshr_misses::total 1373863 # number of overall MSHR misses 656system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23447403000 # number of ReadReq MSHR miss cycles 657system.cpu.dcache.ReadReq_mshr_miss_latency::total 23447403000 # number of ReadReq MSHR miss cycles 658system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8319769000 # number of WriteReq MSHR miss cycles 659system.cpu.dcache.WriteReq_mshr_miss_latency::total 8319769000 # number of WriteReq MSHR miss cycles |
| 662system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196515000 # number of LoadLockedReq MSHR miss cycles 663system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196515000 # number of LoadLockedReq MSHR miss cycles | 660system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196515000 # number of LoadLockedReq MSHR miss cycles 661system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196515000 # number of LoadLockedReq MSHR miss cycles |
| 664system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31764872000 # number of demand (read+write) MSHR miss cycles 665system.cpu.dcache.demand_mshr_miss_latency::total 31764872000 # number of demand (read+write) MSHR miss cycles 666system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31764872000 # number of overall MSHR miss cycles 667system.cpu.dcache.overall_mshr_miss_latency::total 31764872000 # number of overall MSHR miss cycles | 662system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31767172000 # number of demand (read+write) MSHR miss cycles 663system.cpu.dcache.demand_mshr_miss_latency::total 31767172000 # number of demand (read+write) MSHR miss cycles 664system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31767172000 # number of overall MSHR miss cycles 665system.cpu.dcache.overall_mshr_miss_latency::total 31767172000 # number of overall MSHR miss cycles |
| 668system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862831000 # number of ReadReq MSHR uncacheable cycles 669system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862831000 # number of ReadReq MSHR uncacheable cycles 670system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1190523500 # number of WriteReq MSHR uncacheable cycles 671system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1190523500 # number of WriteReq MSHR uncacheable cycles 672system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2053354500 # number of overall MSHR uncacheable cycles 673system.cpu.dcache.overall_mshr_uncacheable_latency::total 2053354500 # number of overall MSHR uncacheable cycles | 666system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862831000 # number of ReadReq MSHR uncacheable cycles 667system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862831000 # number of ReadReq MSHR uncacheable cycles 668system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1190523500 # number of WriteReq MSHR uncacheable cycles 669system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1190523500 # number of WriteReq MSHR uncacheable cycles 670system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2053354500 # number of overall MSHR uncacheable cycles 671system.cpu.dcache.overall_mshr_uncacheable_latency::total 2053354500 # number of overall MSHR uncacheable cycles |
| 674system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120375 # mshr miss rate for ReadReq accesses 675system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120375 # mshr miss rate for ReadReq accesses 676system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049426 # mshr miss rate for WriteReq accesses 677system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049426 # mshr miss rate for WriteReq accesses | 672system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120376 # mshr miss rate for ReadReq accesses 673system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120376 # mshr miss rate for ReadReq accesses 674system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049427 # mshr miss rate for WriteReq accesses 675system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049427 # mshr miss rate for WriteReq accesses |
| 678system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086498 # mshr miss rate for LoadLockedReq accesses 679system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086498 # mshr miss rate for LoadLockedReq accesses 680system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses 681system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses 682system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses 683system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses | 676system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086498 # mshr miss rate for LoadLockedReq accesses 677system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086498 # mshr miss rate for LoadLockedReq accesses 678system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses 679system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses 680system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses 681system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses |
| 684system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21922.969685 # average ReadReq mshr miss latency 685system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21922.969685 # average ReadReq mshr miss latency 686system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27331.555687 # average WriteReq mshr miss latency 687system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27331.555687 # average WriteReq mshr miss latency | 682system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.254501 # average ReadReq mshr miss latency 683system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.254501 # average ReadReq mshr miss latency 684system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27336.996987 # average WriteReq mshr miss latency 685system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27336.996987 # average WriteReq mshr miss latency |
| 688system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470 # average LoadLockedReq mshr miss latency 689system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470 # average LoadLockedReq mshr miss latency | 686system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470 # average LoadLockedReq mshr miss latency 687system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470 # average LoadLockedReq mshr miss latency |
| 690system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency 691system.cpu.dcache.demand_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency 692system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency 693system.cpu.dcache.overall_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency | 688system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency 690system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency |
| 694system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 695system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 696system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 697system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 698system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 699system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 700system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 701 702---------- End Simulation Statistics ---------- | 692system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 693system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 694system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 695system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 696system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 697system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 698system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 699 700---------- End Simulation Statistics ---------- |