| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.915549 # Number of seconds simulated 4sim_ticks 1915548867000 # Number of ticks simulated 5final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.915549 # Number of seconds simulated 4sim_ticks 1915548867000 # Number of ticks simulated 5final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1998214 # Simulator instruction rate (inst/s) 8host_op_rate 1998212 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 68184353129 # Simulator tick rate (ticks/s) 10host_mem_usage 288188 # Number of bytes of host memory used 11host_seconds 28.09 # Real time elapsed on the host | 7host_inst_rate 646342 # Simulator instruction rate (inst/s) 8host_op_rate 646342 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22054916762 # Simulator tick rate (ticks/s) 10host_mem_usage 292620 # Number of bytes of host memory used 11host_seconds 86.85 # Real time elapsed on the host |
| 12sim_insts 56137087 # Number of instructions simulated 13sim_ops 56137087 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 29663360 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10122368 # Number of bytes written to this memory 17system.physmem.num_reads 463490 # Number of read requests responded to by this memory 18system.physmem.num_writes 158162 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 85 unchanged lines hidden (view full) --- 105system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency 106system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency 107system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency 108system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency 109system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 110system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 111system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 112system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 56137087 # Number of instructions simulated 13sim_ops 56137087 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 29663360 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10122368 # Number of bytes written to this memory 17system.physmem.num_reads 463490 # Number of read requests responded to by this memory 18system.physmem.num_writes 158162 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 85 unchanged lines hidden (view full) --- 105system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency 106system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency 107system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency 108system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency 109system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 110system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 111system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 112system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 113system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 114system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 113system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 114system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 115system.l2c.fast_writes 0 # number of fast writes performed 116system.l2c.cache_copies 0 # number of cache copies performed 117system.l2c.writebacks::writebacks 116650 # number of writebacks 118system.l2c.writebacks::total 116650 # number of writebacks 119system.l2c.ReadReq_mshr_misses::cpu.inst 14735 # number of ReadReq MSHR misses 120system.l2c.ReadReq_mshr_misses::cpu.data 289403 # number of ReadReq MSHR misses 121system.l2c.ReadReq_mshr_misses::total 304138 # number of ReadReq MSHR misses 122system.l2c.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses --- 86 unchanged lines hidden (view full) --- 209system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency 210system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency 211system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency 212system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked 213system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 214system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked 215system.iocache.blocked::no_targets 0 # number of cycles access was blocked 216system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked | 115system.l2c.fast_writes 0 # number of fast writes performed 116system.l2c.cache_copies 0 # number of cache copies performed 117system.l2c.writebacks::writebacks 116650 # number of writebacks 118system.l2c.writebacks::total 116650 # number of writebacks 119system.l2c.ReadReq_mshr_misses::cpu.inst 14735 # number of ReadReq MSHR misses 120system.l2c.ReadReq_mshr_misses::cpu.data 289403 # number of ReadReq MSHR misses 121system.l2c.ReadReq_mshr_misses::total 304138 # number of ReadReq MSHR misses 122system.l2c.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses --- 86 unchanged lines hidden (view full) --- 209system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency 210system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency 211system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency 212system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked 213system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 214system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked 215system.iocache.blocked::no_targets 0 # number of cycles access was blocked 216system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked |
| 217system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 217system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 218system.iocache.fast_writes 0 # number of fast writes performed 219system.iocache.cache_copies 0 # number of cache copies performed 220system.iocache.writebacks::writebacks 41512 # number of writebacks 221system.iocache.writebacks::total 41512 # number of writebacks 222system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 223system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 224system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 225system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses --- 168 unchanged lines hidden (view full) --- 394system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode 395system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode 396system.cpu.kern.swap_context 4174 # number of times the context was actually changed 397system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 398system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 399system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 400system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 401system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU | 218system.iocache.fast_writes 0 # number of fast writes performed 219system.iocache.cache_copies 0 # number of cache copies performed 220system.iocache.writebacks::writebacks 41512 # number of writebacks 221system.iocache.writebacks::total 41512 # number of writebacks 222system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 223system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 224system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 225system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses --- 168 unchanged lines hidden (view full) --- 394system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode 395system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode 396system.cpu.kern.swap_context 4174 # number of times the context was actually changed 397system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 398system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 399system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 400system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 401system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU |
| 402system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post | 402system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post |
| 403system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 404system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU | 403system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 404system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU |
| 405system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post | 405system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post |
| 406system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 407system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU | 406system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 407system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU |
| 408system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post | 408system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post |
| 409system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 410system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU | 409system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 410system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU |
| 411system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post | 411system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post |
| 412system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 413system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU | 412system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 413system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU |
| 414system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post | 414system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post |
| 415system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 416system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU | 415system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 416system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU |
| 417system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post | 417system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post |
| 418system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 419system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU | 418system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 419system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU |
| 420system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post | 420system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post |
| 421system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 422system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU | 421system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 422system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU |
| 423system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post | 423system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post |
| 424system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR | 424system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR |
| 425system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post | 425system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post |
| 426system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 427system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 428system.cpu.icache.replacements 927683 # number of replacements 429system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use 430system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks. 431system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks. 432system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks. 433system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit. --- 29 unchanged lines hidden (view full) --- 463system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses 464system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency 465system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency 466system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency 467system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 468system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 469system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 470system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 426system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 427system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 428system.cpu.icache.replacements 927683 # number of replacements 429system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use 430system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks. 431system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks. 432system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks. 433system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit. --- 29 unchanged lines hidden (view full) --- 463system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses 464system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency 465system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency 466system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency 467system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 468system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 469system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 470system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 471system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 472system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 471system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 472system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 473system.cpu.icache.fast_writes 0 # number of fast writes performed 474system.cpu.icache.cache_copies 0 # number of cache copies performed 475system.cpu.icache.writebacks::writebacks 85 # number of writebacks 476system.cpu.icache.writebacks::total 85 # number of writebacks 477system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses 478system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses 479system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # number of demand (read+write) MSHR misses 480system.cpu.icache.demand_mshr_misses::total 928354 # number of demand (read+write) MSHR misses --- 74 unchanged lines hidden (view full) --- 555system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency 556system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency 557system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency 558system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency 559system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 560system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 561system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 562system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 473system.cpu.icache.fast_writes 0 # number of fast writes performed 474system.cpu.icache.cache_copies 0 # number of cache copies performed 475system.cpu.icache.writebacks::writebacks 85 # number of writebacks 476system.cpu.icache.writebacks::total 85 # number of writebacks 477system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses 478system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses 479system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # number of demand (read+write) MSHR misses 480system.cpu.icache.demand_mshr_misses::total 928354 # number of demand (read+write) MSHR misses --- 74 unchanged lines hidden (view full) --- 555system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency 556system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency 557system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency 558system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency 559system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 560system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 561system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 562system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 563system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 564system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 563system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 564system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 565system.cpu.dcache.fast_writes 0 # number of fast writes performed 566system.cpu.dcache.cache_copies 0 # number of cache copies performed 567system.cpu.dcache.writebacks::writebacks 826586 # number of writebacks 568system.cpu.dcache.writebacks::total 826586 # number of writebacks 569system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069110 # number of ReadReq MSHR misses 570system.cpu.dcache.ReadReq_mshr_misses::total 1069110 # number of ReadReq MSHR misses 571system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses 572system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses --- 38 unchanged lines hidden --- | 565system.cpu.dcache.fast_writes 0 # number of fast writes performed 566system.cpu.dcache.cache_copies 0 # number of cache copies performed 567system.cpu.dcache.writebacks::writebacks 826586 # number of writebacks 568system.cpu.dcache.writebacks::total 826586 # number of writebacks 569system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069110 # number of ReadReq MSHR misses 570system.cpu.dcache.ReadReq_mshr_misses::total 1069110 # number of ReadReq MSHR misses 571system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses 572system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses --- 38 unchanged lines hidden --- |