| stats.txt (11707:1d085f66c4ca) | stats.txt (11754:c209cb86278a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.926421 # Number of seconds simulated 4sim_ticks 1926421414000 # Number of ticks simulated 5final_tick 1926421414000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.926422 # Number of seconds simulated 4sim_ticks 1926421638000 # Number of ticks simulated 5final_tick 1926421638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 834051 # Simulator instruction rate (inst/s) 8host_op_rate 834051 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 28592100047 # Simulator tick rate (ticks/s) 10host_mem_usage 333408 # Number of bytes of host memory used 11host_seconds 67.38 # Real time elapsed on the host | 7host_inst_rate 1739419 # Simulator instruction rate (inst/s) 8host_op_rate 1739418 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59628989604 # Simulator tick rate (ticks/s) 10host_mem_usage 334072 # Number of bytes of host memory used 11host_seconds 32.31 # Real time elapsed on the host |
| 12sim_insts 56195014 # Number of instructions simulated 13sim_ops 56195014 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 56195014 # Number of instructions simulated 13sim_ops 56195014 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 844672 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24856896 # Number of bytes read from this memory 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 20system.physmem.bytes_read::total 25702528 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 844672 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 844672 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7408960 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7408960 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 13198 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388389 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 401602 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 115765 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 115765 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 438467 # Total read bandwidth from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 844672 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24856896 # Number of bytes read from this memory 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 20system.physmem.bytes_read::total 25702528 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 844672 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 844672 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7408960 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7408960 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 13198 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388389 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 401602 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 115765 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 115765 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 438467 # Total read bandwidth from this memory (bytes/s) |
| 32system.physmem.bw_read::cpu.data 12903146 # Total read bandwidth from this memory (bytes/s) | 32system.physmem.bw_read::cpu.data 12903144 # Total read bandwidth from this memory (bytes/s) |
| 33system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::total 13342111 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::total 13342109 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_inst_read::cpu.inst 438467 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 438467 # Instruction read bandwidth from this memory (bytes/s) | 35system.physmem.bw_inst_read::cpu.inst 438467 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 438467 # Instruction read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_write::writebacks 3845971 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 3845971 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 3845971 # Total bandwidth to/from this memory (bytes/s) | 37system.physmem.bw_write::writebacks 3845970 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 3845970 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 3845970 # Total bandwidth to/from this memory (bytes/s) |
| 40system.physmem.bw_total::cpu.inst 438467 # Total bandwidth to/from this memory (bytes/s) | 40system.physmem.bw_total::cpu.inst 438467 # Total bandwidth to/from this memory (bytes/s) |
| 41system.physmem.bw_total::cpu.data 12903146 # Total bandwidth to/from this memory (bytes/s) | 41system.physmem.bw_total::cpu.data 12903144 # Total bandwidth to/from this memory (bytes/s) |
| 42system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) |
| 43system.physmem.bw_total::total 17188081 # Total bandwidth to/from this memory (bytes/s) | 43system.physmem.bw_total::total 17188079 # Total bandwidth to/from this memory (bytes/s) |
| 44system.physmem.readReqs 401602 # Number of read requests accepted 45system.physmem.writeReqs 115765 # Number of write requests accepted 46system.physmem.readBursts 401602 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 115765 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25695552 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7408000 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25702528 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 82system.physmem.perBankWrBursts::10 7117 # Per bank write bursts 83system.physmem.perBankWrBursts::11 6900 # Per bank write bursts 84system.physmem.perBankWrBursts::12 7101 # Per bank write bursts 85system.physmem.perBankWrBursts::13 7827 # Per bank write bursts 86system.physmem.perBankWrBursts::14 7864 # Per bank write bursts 87system.physmem.perBankWrBursts::15 7687 # Per bank write bursts 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 65 # Number of times write queue was full causing retry | 44system.physmem.readReqs 401602 # Number of read requests accepted 45system.physmem.writeReqs 115765 # Number of write requests accepted 46system.physmem.readBursts 401602 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 115765 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25695552 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7408000 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25702528 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 82system.physmem.perBankWrBursts::10 7117 # Per bank write bursts 83system.physmem.perBankWrBursts::11 6900 # Per bank write bursts 84system.physmem.perBankWrBursts::12 7101 # Per bank write bursts 85system.physmem.perBankWrBursts::13 7827 # Per bank write bursts 86system.physmem.perBankWrBursts::14 7864 # Per bank write bursts 87system.physmem.perBankWrBursts::15 7687 # Per bank write bursts 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 65 # Number of times write queue was full causing retry |
| 90system.physmem.totGap 1926409540500 # Total gap between requests | 90system.physmem.totGap 1926409764500 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) 97system.physmem.readPktSize::6 401602 # Read request sizes (log2) 98system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 46 unchanged lines hidden (view full) --- 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::15 1555 # What write queue length does an incoming req see | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) 97system.physmem.readPktSize::6 401602 # Read request sizes (log2) 98system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 46 unchanged lines hidden (view full) --- 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::15 1555 # What write queue length does an incoming req see |
| 153system.physmem.wrQLenPdf::16 2761 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 5433 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 5447 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 5972 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6087 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 6885 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 7936 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6558 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 6936 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 7510 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7184 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 6518 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6660 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 5973 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 5660 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see | 153system.physmem.wrQLenPdf::16 2767 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 5442 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 5449 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 5980 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6090 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 6888 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 7955 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6560 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 6959 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7149 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 6506 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6626 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 5946 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 5824 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 5647 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 5581 # What write queue length does an incoming req see |
| 170system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see | 170system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see |
| 171system.physmem.wrQLenPdf::34 477 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 374 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 327 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 340 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 292 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 286 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 316 # What write queue length does an incoming req see | 171system.physmem.wrQLenPdf::34 478 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 398 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 372 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 319 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 296 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 302 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 330 # What write queue length does an incoming req see |
| 179system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see | 179system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see |
| 180system.physmem.wrQLenPdf::43 363 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 345 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 332 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 309 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 304 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 296 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 281 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 202 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 216 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see | 180system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 365 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 335 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 288 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 356 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 303 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 303 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 205 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 339 # What write queue length does an incoming req see |
| 194system.physmem.wrQLenPdf::57 238 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 176 # What write queue length does an incoming req see | 194system.physmem.wrQLenPdf::57 238 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 176 # What write queue length does an incoming req see |
| 196system.physmem.wrQLenPdf::59 335 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 300 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see | 196system.physmem.wrQLenPdf::59 333 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 299 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see |
| 200system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see | 200system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see |
| 201system.physmem.bytesPerActivate::samples 63474 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 521.529319 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 315.079750 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 415.298836 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 14953 23.56% 23.56% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 11433 18.01% 41.57% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 4319 6.80% 48.37% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3083 4.86% 53.23% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 3219 5.07% 58.30% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 1509 2.38% 60.68% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1583 2.49% 63.17% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 998 1.57% 64.75% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 22377 35.25% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 63474 # Bytes accessed per row activation | 201system.physmem.bytesPerActivate::samples 63476 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 521.512887 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 315.060266 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 415.295929 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 14957 23.56% 23.56% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 11430 18.01% 41.57% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 4320 6.81% 48.38% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3081 4.85% 53.23% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 3222 5.08% 58.31% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 1508 2.38% 60.68% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1584 2.50% 63.18% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 999 1.57% 64.75% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 22375 35.25% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 63476 # Bytes accessed per row activation |
| 215system.physmem.rdPerTurnAround::samples 5049 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 79.519311 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2969.676150 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5046 99.94% 99.94% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 5049 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5049 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.925332 # Writes before turning the bus around for reads | 215system.physmem.rdPerTurnAround::samples 5049 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 79.519311 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2969.676150 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5046 99.94% 99.94% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 5049 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5049 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.925332 # Writes before turning the bus around for reads |
| 225system.physmem.wrPerTurnAround::gmean 18.952060 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 24.989890 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4540 89.92% 89.92% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 33 0.65% 90.57% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 164 3.25% 93.82% # Writes before turning the bus around for reads | 225system.physmem.wrPerTurnAround::gmean 18.953728 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 24.991500 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4538 89.88% 89.88% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 34 0.67% 90.55% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 165 3.27% 93.82% # Writes before turning the bus around for reads |
| 230system.physmem.wrPerTurnAround::40-47 7 0.14% 93.96% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 1 0.02% 93.98% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 14 0.28% 94.26% # Writes before turning the bus around for reads | 230system.physmem.wrPerTurnAround::40-47 7 0.14% 93.96% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 1 0.02% 93.98% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 14 0.28% 94.26% # Writes before turning the bus around for reads |
| 233system.physmem.wrPerTurnAround::64-71 7 0.14% 94.39% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 4 0.08% 94.47% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 36 0.71% 95.19% # Writes before turning the bus around for reads | 233system.physmem.wrPerTurnAround::64-71 8 0.16% 94.41% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 5 0.10% 94.51% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 34 0.67% 95.19% # Writes before turning the bus around for reads |
| 236system.physmem.wrPerTurnAround::88-95 2 0.04% 95.23% # Writes before turning the bus around for reads | 236system.physmem.wrPerTurnAround::88-95 2 0.04% 95.23% # Writes before turning the bus around for reads |
| 237system.physmem.wrPerTurnAround::96-103 139 2.75% 97.98% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 18 0.36% 98.34% # Writes before turning the bus around for reads | 237system.physmem.wrPerTurnAround::96-103 141 2.79% 98.02% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 16 0.32% 98.34% # Writes before turning the bus around for reads |
| 239system.physmem.wrPerTurnAround::112-119 13 0.26% 98.59% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::120-127 3 0.06% 98.65% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::128-135 6 0.12% 98.77% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::136-143 6 0.12% 98.89% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::152-159 3 0.06% 98.95% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-167 2 0.04% 98.99% # Writes before turning the bus around for reads | 239system.physmem.wrPerTurnAround::112-119 13 0.26% 98.59% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::120-127 3 0.06% 98.65% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::128-135 6 0.12% 98.77% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::136-143 6 0.12% 98.89% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::152-159 3 0.06% 98.95% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-167 2 0.04% 98.99% # Writes before turning the bus around for reads |
| 245system.physmem.wrPerTurnAround::168-175 13 0.26% 99.25% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-183 4 0.08% 99.33% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::184-191 12 0.24% 99.56% # Writes before turning the bus around for reads | 245system.physmem.wrPerTurnAround::168-175 12 0.24% 99.23% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-183 4 0.08% 99.31% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::184-191 13 0.26% 99.56% # Writes before turning the bus around for reads |
| 248system.physmem.wrPerTurnAround::192-199 10 0.20% 99.76% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::208-215 1 0.02% 99.80% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::216-223 6 0.12% 99.92% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::total 5049 # Writes before turning the bus around for reads | 248system.physmem.wrPerTurnAround::192-199 10 0.20% 99.76% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::208-215 1 0.02% 99.80% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::216-223 6 0.12% 99.92% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::total 5049 # Writes before turning the bus around for reads |
| 255system.physmem.totQLat 6110965000 # Total ticks spent queuing 256system.physmem.totMemAccLat 13638958750 # Total ticks spent from burst creation until serviced by the DRAM | 255system.physmem.totQLat 6110922250 # Total ticks spent queuing 256system.physmem.totMemAccLat 13638916000 # Total ticks spent from burst creation until serviced by the DRAM |
| 257system.physmem.totBusLat 2007465000 # Total ticks spent in databus transfers | 257system.physmem.totBusLat 2007465000 # Total ticks spent in databus transfers |
| 258system.physmem.avgQLat 15220.60 # Average queueing delay per DRAM burst | 258system.physmem.avgQLat 15220.50 # Average queueing delay per DRAM burst |
| 259system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 259system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 260system.physmem.avgMemAccLat 33970.60 # Average memory access latency per DRAM burst | 260system.physmem.avgMemAccLat 33970.50 # Average memory access latency per DRAM burst |
| 261system.physmem.avgRdBW 13.34 # Average DRAM read bandwidth in MiByte/s 262system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s 263system.physmem.avgRdBWSys 13.34 # Average system read bandwidth in MiByte/s 264system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s 265system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 266system.physmem.busUtil 0.13 # Data bus utilization in percentage 267system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 268system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 269system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 270system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing | 261system.physmem.avgRdBW 13.34 # Average DRAM read bandwidth in MiByte/s 262system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s 263system.physmem.avgRdBWSys 13.34 # Average system read bandwidth in MiByte/s 264system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s 265system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 266system.physmem.busUtil 0.13 # Data bus utilization in percentage 267system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 268system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 269system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 270system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing |
| 271system.physmem.readRowHits 360227 # Number of row buffer hits during reads | 271system.physmem.readRowHits 360225 # Number of row buffer hits during reads |
| 272system.physmem.writeRowHits 93542 # Number of row buffer hits during writes 273system.physmem.readRowHitRate 89.72 # Row buffer hit rate for reads 274system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes | 272system.physmem.writeRowHits 93542 # Number of row buffer hits during writes 273system.physmem.readRowHitRate 89.72 # Row buffer hit rate for reads 274system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes |
| 275system.physmem.avgGap 3723487.47 # Average gap between requests | 275system.physmem.avgGap 3723487.90 # Average gap between requests |
| 276system.physmem.pageHitRate 87.73 # Row buffer hit rate, read and write combined 277system.physmem_0.actEnergy 220840200 # Energy for activate commands per rank (pJ) 278system.physmem_0.preEnergy 117379350 # Energy for precharge commands per rank (pJ) 279system.physmem_0.readEnergy 1432076940 # Energy for read commands per rank (pJ) 280system.physmem_0.writeEnergy 299763720 # Energy for write commands per rank (pJ) 281system.physmem_0.refreshEnergy 5519467200.000001 # Energy for refresh commands per rank (pJ) | 276system.physmem.pageHitRate 87.73 # Row buffer hit rate, read and write combined 277system.physmem_0.actEnergy 220840200 # Energy for activate commands per rank (pJ) 278system.physmem_0.preEnergy 117379350 # Energy for precharge commands per rank (pJ) 279system.physmem_0.readEnergy 1432076940 # Energy for read commands per rank (pJ) 280system.physmem_0.writeEnergy 299763720 # Energy for write commands per rank (pJ) 281system.physmem_0.refreshEnergy 5519467200.000001 # Energy for refresh commands per rank (pJ) |
| 282system.physmem_0.actBackEnergy 5038358250 # Energy for active background per rank (pJ) 283system.physmem_0.preBackEnergy 366301440 # Energy for precharge background per rank (pJ) 284system.physmem_0.actPowerDownEnergy 13030830420 # Energy for active power-down per rank (pJ) 285system.physmem_0.prePowerDownEnergy 6357713760 # Energy for precharge power-down per rank (pJ) 286system.physmem_0.selfRefreshEnergy 449603447400 # Energy for self refresh per rank (pJ) 287system.physmem_0.totalEnergy 481990669050 # Total energy per rank (pJ) 288system.physmem_0.averagePower 250.200016 # Core power per rank (mW) 289system.physmem_0.totalIdleTime 1914256960750 # Total Idle time Per DRAM Rank 290system.physmem_0.memoryStateTime::IDLE 613825000 # Time in different power states | 282system.physmem_0.actBackEnergy 5038088640 # Energy for active background per rank (pJ) 283system.physmem_0.preBackEnergy 365587680 # Energy for precharge background per rank (pJ) 284system.physmem_0.actPowerDownEnergy 13029981120 # Energy for active power-down per rank (pJ) 285system.physmem_0.prePowerDownEnergy 6359365440 # Energy for precharge power-down per rank (pJ) 286system.physmem_0.selfRefreshEnergy 449603503800 # Energy for self refresh per rank (pJ) 287system.physmem_0.totalEnergy 481990544460 # Total energy per rank (pJ) 288system.physmem_0.averagePower 250.199922 # Core power per rank (mW) 289system.physmem_0.totalIdleTime 1914259413500 # Total Idle time Per DRAM Rank 290system.physmem_0.memoryStateTime::IDLE 611958500 # Time in different power states |
| 291system.physmem_0.memoryStateTime::REF 2347892000 # Time in different power states | 291system.physmem_0.memoryStateTime::REF 2347892000 # Time in different power states |
| 292system.physmem_0.memoryStateTime::SREF 1869275563500 # Time in different power states 293system.physmem_0.memoryStateTime::PRE_PDN 16556600250 # Time in different power states 294system.physmem_0.memoryStateTime::ACT 9050884750 # Time in different power states 295system.physmem_0.memoryStateTime::ACT_PDN 28576648500 # Time in different power states 296system.physmem_1.actEnergy 232364160 # Energy for activate commands per rank (pJ) 297system.physmem_1.preEnergy 123504480 # Energy for precharge commands per rank (pJ) | 292system.physmem_0.memoryStateTime::SREF 1869275787500 # Time in different power states 293system.physmem_0.memoryStateTime::PRE_PDN 16560859500 # Time in different power states 294system.physmem_0.memoryStateTime::ACT 9050522500 # Time in different power states 295system.physmem_0.memoryStateTime::ACT_PDN 28574618000 # Time in different power states 296system.physmem_1.actEnergy 232378440 # Energy for activate commands per rank (pJ) 297system.physmem_1.preEnergy 123512070 # Energy for precharge commands per rank (pJ) |
| 298system.physmem_1.readEnergy 1434583080 # Energy for read commands per rank (pJ) 299system.physmem_1.writeEnergy 304451280 # Energy for write commands per rank (pJ) 300system.physmem_1.refreshEnergy 5706932400.000001 # Energy for refresh commands per rank (pJ) | 298system.physmem_1.readEnergy 1434583080 # Energy for read commands per rank (pJ) 299system.physmem_1.writeEnergy 304451280 # Energy for write commands per rank (pJ) 300system.physmem_1.refreshEnergy 5706932400.000001 # Energy for refresh commands per rank (pJ) |
| 301system.physmem_1.actBackEnergy 5157840510 # Energy for active background per rank (pJ) 302system.physmem_1.preBackEnergy 361297920 # Energy for precharge background per rank (pJ) 303system.physmem_1.actPowerDownEnergy 13647845730 # Energy for active power-down per rank (pJ) 304system.physmem_1.prePowerDownEnergy 6595007040 # Energy for precharge power-down per rank (pJ) 305system.physmem_1.selfRefreshEnergy 449082638955 # Energy for self refresh per rank (pJ) 306system.physmem_1.totalEnergy 482651277075 # Total energy per rank (pJ) 307system.physmem_1.averagePower 250.542936 # Core power per rank (mW) 308system.physmem_1.totalIdleTime 1914153639500 # Total Idle time Per DRAM Rank 309system.physmem_1.memoryStateTime::IDLE 598128250 # Time in different power states | 301system.physmem_1.actBackEnergy 5156813940 # Energy for active background per rank (pJ) 302system.physmem_1.preBackEnergy 361085280 # Energy for precharge background per rank (pJ) 303system.physmem_1.actPowerDownEnergy 13650484260 # Energy for active power-down per rank (pJ) 304system.physmem_1.prePowerDownEnergy 6593796000 # Energy for precharge power-down per rank (pJ) 305system.physmem_1.selfRefreshEnergy 449082763260 # Energy for self refresh per rank (pJ) 306system.physmem_1.totalEnergy 482651694330 # Total energy per rank (pJ) 307system.physmem_1.averagePower 250.543123 # Core power per rank (mW) 308system.physmem_1.totalIdleTime 1914156494000 # Total Idle time Per DRAM Rank 309system.physmem_1.memoryStateTime::IDLE 598122250 # Time in different power states |
| 310system.physmem_1.memoryStateTime::REF 2427510000 # Time in different power states | 310system.physmem_1.memoryStateTime::REF 2427510000 # Time in different power states |
| 311system.physmem_1.memoryStateTime::SREF 1867054823500 # Time in different power states 312system.physmem_1.memoryStateTime::PRE_PDN 17174624250 # Time in different power states 313system.physmem_1.memoryStateTime::ACT 9236704750 # Time in different power states 314system.physmem_1.memoryStateTime::ACT_PDN 29929623250 # Time in different power states 315system.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 316system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states | 311system.physmem_1.memoryStateTime::SREF 1867055047500 # Time in different power states 312system.physmem_1.memoryStateTime::PRE_PDN 17171481750 # Time in different power states 313system.physmem_1.memoryStateTime::ACT 9234080250 # Time in different power states 314system.physmem_1.memoryStateTime::ACT_PDN 29935396250 # Time in different power states 315system.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 316system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states |
| 317system.cpu_clk_domain.clock 500 # Clock period in ticks 318system.cpu.dtb.fetch_hits 0 # ITB hits 319system.cpu.dtb.fetch_misses 0 # ITB misses 320system.cpu.dtb.fetch_acv 0 # ITB acv 321system.cpu.dtb.fetch_accesses 0 # ITB accesses 322system.cpu.dtb.read_hits 9066536 # DTB read hits 323system.cpu.dtb.read_misses 10331 # DTB read misses 324system.cpu.dtb.read_acv 210 # DTB read access violations --- 19 unchanged lines hidden (view full) --- 344system.cpu.itb.write_acv 0 # DTB write access violations 345system.cpu.itb.write_accesses 0 # DTB write accesses 346system.cpu.itb.data_hits 0 # DTB hits 347system.cpu.itb.data_misses 0 # DTB misses 348system.cpu.itb.data_acv 0 # DTB access violations 349system.cpu.itb.data_accesses 0 # DTB accesses 350system.cpu.numPwrStateTransitions 12758 # Number of power state transitions 351system.cpu.pwrStateClkGateDist::samples 6379 # Distribution of time spent in the clock gated state | 317system.cpu_clk_domain.clock 500 # Clock period in ticks 318system.cpu.dtb.fetch_hits 0 # ITB hits 319system.cpu.dtb.fetch_misses 0 # ITB misses 320system.cpu.dtb.fetch_acv 0 # ITB acv 321system.cpu.dtb.fetch_accesses 0 # ITB accesses 322system.cpu.dtb.read_hits 9066536 # DTB read hits 323system.cpu.dtb.read_misses 10331 # DTB read misses 324system.cpu.dtb.read_acv 210 # DTB read access violations --- 19 unchanged lines hidden (view full) --- 344system.cpu.itb.write_acv 0 # DTB write access violations 345system.cpu.itb.write_accesses 0 # DTB write accesses 346system.cpu.itb.data_hits 0 # DTB hits 347system.cpu.itb.data_misses 0 # DTB misses 348system.cpu.itb.data_acv 0 # DTB access violations 349system.cpu.itb.data_accesses 0 # DTB accesses 350system.cpu.numPwrStateTransitions 12758 # Number of power state transitions 351system.cpu.pwrStateClkGateDist::samples 6379 # Distribution of time spent in the clock gated state |
| 352system.cpu.pwrStateClkGateDist::mean 281128919.188117 # Distribution of time spent in the clock gated state 353system.cpu.pwrStateClkGateDist::stdev 439406492.836173 # Distribution of time spent in the clock gated state | 352system.cpu.pwrStateClkGateDist::mean 281128919.971939 # Distribution of time spent in the clock gated state 353system.cpu.pwrStateClkGateDist::stdev 439406494.656653 # Distribution of time spent in the clock gated state |
| 354system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state 355system.cpu.pwrStateClkGateDist::1000-5e+10 6378 99.98% 100.00% # Distribution of time spent in the clock gated state 356system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 357system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 358system.cpu.pwrStateClkGateDist::total 6379 # Distribution of time spent in the clock gated state | 354system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state 355system.cpu.pwrStateClkGateDist::1000-5e+10 6378 99.98% 100.00% # Distribution of time spent in the clock gated state 356system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 357system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 358system.cpu.pwrStateClkGateDist::total 6379 # Distribution of time spent in the clock gated state |
| 359system.cpu.pwrStateResidencyTicks::ON 133100038499 # Cumulative time (in ticks) in various power states 360system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321375501 # Cumulative time (in ticks) in various power states 361system.cpu.numCycles 3852842828 # number of cpu cycles simulated | 359system.cpu.pwrStateResidencyTicks::ON 133100257499 # Cumulative time (in ticks) in various power states 360system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321380501 # Cumulative time (in ticks) in various power states 361system.cpu.numCycles 3852843276 # number of cpu cycles simulated |
| 362system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 363system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 364system.cpu.kern.inst.arm 0 # number of arm instructions executed 365system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 366system.cpu.kern.inst.hwrei 212049 # number of hwrei instructions executed 367system.cpu.kern.ipl_count::0 74911 40.89% 40.89% # number of times we switched to this ipl 368system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 369system.cpu.kern.ipl_count::22 1934 1.06% 42.01% # number of times we switched to this ipl 370system.cpu.kern.ipl_count::31 106246 57.99% 100.00% # number of times we switched to this ipl 371system.cpu.kern.ipl_count::total 183222 # number of times we switched to this ipl 372system.cpu.kern.ipl_good::0 73544 49.31% 49.31% # number of times we switched to this ipl from a different ipl 373system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 374system.cpu.kern.ipl_good::22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl 375system.cpu.kern.ipl_good::31 73544 49.31% 100.00% # number of times we switched to this ipl from a different ipl 376system.cpu.kern.ipl_good::total 149153 # number of times we switched to this ipl from a different ipl | 362system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 363system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 364system.cpu.kern.inst.arm 0 # number of arm instructions executed 365system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed 366system.cpu.kern.inst.hwrei 212049 # number of hwrei instructions executed 367system.cpu.kern.ipl_count::0 74911 40.89% 40.89% # number of times we switched to this ipl 368system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 369system.cpu.kern.ipl_count::22 1934 1.06% 42.01% # number of times we switched to this ipl 370system.cpu.kern.ipl_count::31 106246 57.99% 100.00% # number of times we switched to this ipl 371system.cpu.kern.ipl_count::total 183222 # number of times we switched to this ipl 372system.cpu.kern.ipl_good::0 73544 49.31% 49.31% # number of times we switched to this ipl from a different ipl 373system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 374system.cpu.kern.ipl_good::22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl 375system.cpu.kern.ipl_good::31 73544 49.31% 100.00% # number of times we switched to this ipl from a different ipl 376system.cpu.kern.ipl_good::total 149153 # number of times we switched to this ipl from a different ipl |
| 377system.cpu.kern.ipl_ticks::0 1859428695000 96.52% 96.52% # number of cycles we spent at this ipl | 377system.cpu.kern.ipl_ticks::0 1859428733000 96.52% 96.52% # number of cycles we spent at this ipl |
| 378system.cpu.kern.ipl_ticks::21 94503000 0.00% 96.53% # number of cycles we spent at this ipl | 378system.cpu.kern.ipl_ticks::21 94503000 0.00% 96.53% # number of cycles we spent at this ipl |
| 379system.cpu.kern.ipl_ticks::22 772442000 0.04% 96.57% # number of cycles we spent at this ipl 380system.cpu.kern.ipl_ticks::31 66125040000 3.43% 100.00% # number of cycles we spent at this ipl 381system.cpu.kern.ipl_ticks::total 1926420680000 # number of cycles we spent at this ipl | 379system.cpu.kern.ipl_ticks::22 772464500 0.04% 96.57% # number of cycles we spent at this ipl 380system.cpu.kern.ipl_ticks::31 66125203500 3.43% 100.00% # number of cycles we spent at this ipl 381system.cpu.kern.ipl_ticks::total 1926420904000 # number of cycles we spent at this ipl |
| 382system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl 383system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 384system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 385system.cpu.kern.ipl_used::31 0.692205 # fraction of swpipl calls that actually changed the ipl 386system.cpu.kern.ipl_used::total 0.814056 # fraction of swpipl calls that actually changed the ipl 387system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 388system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 389system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed --- 16 unchanged lines hidden (view full) --- 406system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches 407system.cpu.kern.mode_good::kernel 1908 408system.cpu.kern.mode_good::user 1738 409system.cpu.kern.mode_good::idle 170 410system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches 411system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 412system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches 413system.cpu.kern.mode_switch_good::total 0.391786 # fraction of useful protection mode switches | 382system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl 383system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 384system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 385system.cpu.kern.ipl_used::31 0.692205 # fraction of swpipl calls that actually changed the ipl 386system.cpu.kern.ipl_used::total 0.814056 # fraction of swpipl calls that actually changed the ipl 387system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 388system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 389system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed --- 16 unchanged lines hidden (view full) --- 406system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches 407system.cpu.kern.mode_good::kernel 1908 408system.cpu.kern.mode_good::user 1738 409system.cpu.kern.mode_good::idle 170 410system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches 411system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 412system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches 413system.cpu.kern.mode_switch_good::total 0.391786 # fraction of useful protection mode switches |
| 414system.cpu.kern.mode_ticks::kernel 47043056000 2.44% 2.44% # number of ticks spent at the given mode 415system.cpu.kern.mode_ticks::user 5370301500 0.28% 2.72% # number of ticks spent at the given mode 416system.cpu.kern.mode_ticks::idle 1874007320500 97.28% 100.00% # number of ticks spent at the given mode | 414system.cpu.kern.mode_ticks::kernel 47043334000 2.44% 2.44% # number of ticks spent at the given mode 415system.cpu.kern.mode_ticks::user 5370278500 0.28% 2.72% # number of ticks spent at the given mode 416system.cpu.kern.mode_ticks::idle 1874007289500 97.28% 100.00% # number of ticks spent at the given mode |
| 417system.cpu.kern.swap_context 4178 # number of times the context was actually changed 418system.cpu.committedInsts 56195014 # Number of instructions committed 419system.cpu.committedOps 56195014 # Number of ops (including micro ops) committed 420system.cpu.num_int_alu_accesses 52066552 # Number of integer alu accesses 421system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 422system.cpu.num_func_calls 1483758 # number of times a function call or return occured 423system.cpu.num_conditional_control_insts 6469897 # number of instructions that are conditional controls 424system.cpu.num_int_insts 52066552 # number of integer instructions 425system.cpu.num_fp_insts 324460 # number of float instructions 426system.cpu.num_int_register_reads 71340789 # number of times the integer registers were read 427system.cpu.num_int_register_writes 38530081 # number of times the integer registers were written 428system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 429system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 430system.cpu.num_mem_refs 15476659 # number of memory refs 431system.cpu.num_load_insts 9103400 # Number of load instructions 432system.cpu.num_store_insts 6373259 # Number of store instructions | 417system.cpu.kern.swap_context 4178 # number of times the context was actually changed 418system.cpu.committedInsts 56195014 # Number of instructions committed 419system.cpu.committedOps 56195014 # Number of ops (including micro ops) committed 420system.cpu.num_int_alu_accesses 52066552 # Number of integer alu accesses 421system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 422system.cpu.num_func_calls 1483758 # number of times a function call or return occured 423system.cpu.num_conditional_control_insts 6469897 # number of instructions that are conditional controls 424system.cpu.num_int_insts 52066552 # number of integer instructions 425system.cpu.num_fp_insts 324460 # number of float instructions 426system.cpu.num_int_register_reads 71340789 # number of times the integer registers were read 427system.cpu.num_int_register_writes 38530081 # number of times the integer registers were written 428system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 429system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 430system.cpu.num_mem_refs 15476659 # number of memory refs 431system.cpu.num_load_insts 9103400 # Number of load instructions 432system.cpu.num_store_insts 6373259 # Number of store instructions |
| 433system.cpu.num_idle_cycles 3586642751.000138 # Number of idle cycles 434system.cpu.num_busy_cycles 266200076.999862 # Number of busy cycles | 433system.cpu.num_idle_cycles 3586642761.000138 # Number of idle cycles 434system.cpu.num_busy_cycles 266200514.999862 # Number of busy cycles |
| 435system.cpu.not_idle_fraction 0.069092 # Percentage of non-idle cycles 436system.cpu.idle_fraction 0.930908 # Percentage of idle cycles 437system.cpu.Branches 8424278 # Number of branches fetched 438system.cpu.op_class::No_OpClass 3201027 5.70% 5.70% # Class of executed instruction 439system.cpu.op_class::IntAlu 36239709 64.48% 70.17% # Class of executed instruction 440system.cpu.op_class::IntMult 61024 0.11% 70.28% # Class of executed instruction 441system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction 442system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction --- 26 unchanged lines hidden (view full) --- 469system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction 470system.cpu.op_class::MemRead 9185894 16.34% 86.70% # Class of executed instruction 471system.cpu.op_class::MemWrite 6241230 11.10% 97.80% # Class of executed instruction 472system.cpu.op_class::FloatMemRead 144629 0.26% 98.06% # Class of executed instruction 473system.cpu.op_class::FloatMemWrite 138108 0.25% 98.30% # Class of executed instruction 474system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction 475system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 476system.cpu.op_class::total 56206855 # Class of executed instruction | 435system.cpu.not_idle_fraction 0.069092 # Percentage of non-idle cycles 436system.cpu.idle_fraction 0.930908 # Percentage of idle cycles 437system.cpu.Branches 8424278 # Number of branches fetched 438system.cpu.op_class::No_OpClass 3201027 5.70% 5.70% # Class of executed instruction 439system.cpu.op_class::IntAlu 36239709 64.48% 70.17% # Class of executed instruction 440system.cpu.op_class::IntMult 61024 0.11% 70.28% # Class of executed instruction 441system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction 442system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction --- 26 unchanged lines hidden (view full) --- 469system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction 470system.cpu.op_class::MemRead 9185894 16.34% 86.70% # Class of executed instruction 471system.cpu.op_class::MemWrite 6241230 11.10% 97.80% # Class of executed instruction 472system.cpu.op_class::FloatMemRead 144629 0.26% 98.06% # Class of executed instruction 473system.cpu.op_class::FloatMemWrite 138108 0.25% 98.30% # Class of executed instruction 474system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction 475system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 476system.cpu.op_class::total 56206855 # Class of executed instruction |
| 477system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 478system.cpu.dcache.tags.replacements 1390811 # number of replacements | 477system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 478system.cpu.dcache.tags.replacements 1390804 # number of replacements |
| 479system.cpu.dcache.tags.tagsinuse 511.976541 # Cycle average of tags in use | 479system.cpu.dcache.tags.tagsinuse 511.976541 # Cycle average of tags in use |
| 480system.cpu.dcache.tags.total_refs 14051752 # Total number of references to valid blocks. 481system.cpu.dcache.tags.sampled_refs 1391323 # Sample count of references to valid blocks. 482system.cpu.dcache.tags.avg_refs 10.099561 # Average number of references to valid blocks. | 480system.cpu.dcache.tags.total_refs 14051759 # Total number of references to valid blocks. 481system.cpu.dcache.tags.sampled_refs 1391316 # Sample count of references to valid blocks. 482system.cpu.dcache.tags.avg_refs 10.099617 # Average number of references to valid blocks. |
| 483system.cpu.dcache.tags.warmup_cycle 121311500 # Cycle when the warmup percentage was hit. 484system.cpu.dcache.tags.occ_blocks::cpu.data 511.976541 # Average occupied blocks per requestor 485system.cpu.dcache.tags.occ_percent::cpu.data 0.999954 # Average percentage of cache occupancy 486system.cpu.dcache.tags.occ_percent::total 0.999954 # Average percentage of cache occupancy 487system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 488system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 489system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 490system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 491system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 483system.cpu.dcache.tags.warmup_cycle 121311500 # Cycle when the warmup percentage was hit. 484system.cpu.dcache.tags.occ_blocks::cpu.data 511.976541 # Average occupied blocks per requestor 485system.cpu.dcache.tags.occ_percent::cpu.data 0.999954 # Average percentage of cache occupancy 486system.cpu.dcache.tags.occ_percent::total 0.999954 # Average percentage of cache occupancy 487system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 488system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 489system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 490system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 491system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 492system.cpu.dcache.tags.tag_accesses 63163628 # Number of tag accesses 493system.cpu.dcache.tags.data_accesses 63163628 # Number of data accesses 494system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 495system.cpu.dcache.ReadReq_hits::cpu.data 7815905 # number of ReadReq hits 496system.cpu.dcache.ReadReq_hits::total 7815905 # number of ReadReq hits 497system.cpu.dcache.WriteReq_hits::cpu.data 5853570 # number of WriteReq hits 498system.cpu.dcache.WriteReq_hits::total 5853570 # number of WriteReq hits 499system.cpu.dcache.LoadLockedReq_hits::cpu.data 183002 # number of LoadLockedReq hits 500system.cpu.dcache.LoadLockedReq_hits::total 183002 # number of LoadLockedReq hits | 492system.cpu.dcache.tags.tag_accesses 63163621 # Number of tag accesses 493system.cpu.dcache.tags.data_accesses 63163621 # Number of data accesses 494system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 495system.cpu.dcache.ReadReq_hits::cpu.data 7815914 # number of ReadReq hits 496system.cpu.dcache.ReadReq_hits::total 7815914 # number of ReadReq hits 497system.cpu.dcache.WriteReq_hits::cpu.data 5853567 # number of WriteReq hits 498system.cpu.dcache.WriteReq_hits::total 5853567 # number of WriteReq hits 499system.cpu.dcache.LoadLockedReq_hits::cpu.data 183003 # number of LoadLockedReq hits 500system.cpu.dcache.LoadLockedReq_hits::total 183003 # number of LoadLockedReq hits |
| 501system.cpu.dcache.StoreCondReq_hits::cpu.data 199258 # number of StoreCondReq hits 502system.cpu.dcache.StoreCondReq_hits::total 199258 # number of StoreCondReq hits | 501system.cpu.dcache.StoreCondReq_hits::cpu.data 199258 # number of StoreCondReq hits 502system.cpu.dcache.StoreCondReq_hits::total 199258 # number of StoreCondReq hits |
| 503system.cpu.dcache.demand_hits::cpu.data 13669475 # number of demand (read+write) hits 504system.cpu.dcache.demand_hits::total 13669475 # number of demand (read+write) hits 505system.cpu.dcache.overall_hits::cpu.data 13669475 # number of overall hits 506system.cpu.dcache.overall_hits::total 13669475 # number of overall hits 507system.cpu.dcache.ReadReq_misses::cpu.data 1069743 # number of ReadReq misses 508system.cpu.dcache.ReadReq_misses::total 1069743 # number of ReadReq misses 509system.cpu.dcache.WriteReq_misses::cpu.data 304319 # number of WriteReq misses 510system.cpu.dcache.WriteReq_misses::total 304319 # number of WriteReq misses 511system.cpu.dcache.LoadLockedReq_misses::cpu.data 17279 # number of LoadLockedReq misses 512system.cpu.dcache.LoadLockedReq_misses::total 17279 # number of LoadLockedReq misses 513system.cpu.dcache.demand_misses::cpu.data 1374062 # number of demand (read+write) misses 514system.cpu.dcache.demand_misses::total 1374062 # number of demand (read+write) misses 515system.cpu.dcache.overall_misses::cpu.data 1374062 # number of overall misses 516system.cpu.dcache.overall_misses::total 1374062 # number of overall misses 517system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050586500 # number of ReadReq miss cycles 518system.cpu.dcache.ReadReq_miss_latency::total 33050586500 # number of ReadReq miss cycles 519system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442150000 # number of WriteReq miss cycles 520system.cpu.dcache.WriteReq_miss_latency::total 13442150000 # number of WriteReq miss cycles 521system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232520000 # number of LoadLockedReq miss cycles 522system.cpu.dcache.LoadLockedReq_miss_latency::total 232520000 # number of LoadLockedReq miss cycles 523system.cpu.dcache.demand_miss_latency::cpu.data 46492736500 # number of demand (read+write) miss cycles 524system.cpu.dcache.demand_miss_latency::total 46492736500 # number of demand (read+write) miss cycles 525system.cpu.dcache.overall_miss_latency::cpu.data 46492736500 # number of overall miss cycles 526system.cpu.dcache.overall_miss_latency::total 46492736500 # number of overall miss cycles | 503system.cpu.dcache.demand_hits::cpu.data 13669481 # number of demand (read+write) hits 504system.cpu.dcache.demand_hits::total 13669481 # number of demand (read+write) hits 505system.cpu.dcache.overall_hits::cpu.data 13669481 # number of overall hits 506system.cpu.dcache.overall_hits::total 13669481 # number of overall hits 507system.cpu.dcache.ReadReq_misses::cpu.data 1069734 # number of ReadReq misses 508system.cpu.dcache.ReadReq_misses::total 1069734 # number of ReadReq misses 509system.cpu.dcache.WriteReq_misses::cpu.data 304322 # number of WriteReq misses 510system.cpu.dcache.WriteReq_misses::total 304322 # number of WriteReq misses 511system.cpu.dcache.LoadLockedReq_misses::cpu.data 17278 # number of LoadLockedReq misses 512system.cpu.dcache.LoadLockedReq_misses::total 17278 # number of LoadLockedReq misses 513system.cpu.dcache.demand_misses::cpu.data 1374056 # number of demand (read+write) misses 514system.cpu.dcache.demand_misses::total 1374056 # number of demand (read+write) misses 515system.cpu.dcache.overall_misses::cpu.data 1374056 # number of overall misses 516system.cpu.dcache.overall_misses::total 1374056 # number of overall misses 517system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050329500 # number of ReadReq miss cycles 518system.cpu.dcache.ReadReq_miss_latency::total 33050329500 # number of ReadReq miss cycles 519system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442227500 # number of WriteReq miss cycles 520system.cpu.dcache.WriteReq_miss_latency::total 13442227500 # number of WriteReq miss cycles 521system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles 522system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles 523system.cpu.dcache.demand_miss_latency::cpu.data 46492557000 # number of demand (read+write) miss cycles 524system.cpu.dcache.demand_miss_latency::total 46492557000 # number of demand (read+write) miss cycles 525system.cpu.dcache.overall_miss_latency::cpu.data 46492557000 # number of overall miss cycles 526system.cpu.dcache.overall_miss_latency::total 46492557000 # number of overall miss cycles |
| 527system.cpu.dcache.ReadReq_accesses::cpu.data 8885648 # number of ReadReq accesses(hits+misses) 528system.cpu.dcache.ReadReq_accesses::total 8885648 # number of ReadReq accesses(hits+misses) 529system.cpu.dcache.WriteReq_accesses::cpu.data 6157889 # number of WriteReq accesses(hits+misses) 530system.cpu.dcache.WriteReq_accesses::total 6157889 # number of WriteReq accesses(hits+misses) 531system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200281 # number of LoadLockedReq accesses(hits+misses) 532system.cpu.dcache.LoadLockedReq_accesses::total 200281 # number of LoadLockedReq accesses(hits+misses) 533system.cpu.dcache.StoreCondReq_accesses::cpu.data 199258 # number of StoreCondReq accesses(hits+misses) 534system.cpu.dcache.StoreCondReq_accesses::total 199258 # number of StoreCondReq accesses(hits+misses) 535system.cpu.dcache.demand_accesses::cpu.data 15043537 # number of demand (read+write) accesses 536system.cpu.dcache.demand_accesses::total 15043537 # number of demand (read+write) accesses 537system.cpu.dcache.overall_accesses::cpu.data 15043537 # number of overall (read+write) accesses 538system.cpu.dcache.overall_accesses::total 15043537 # number of overall (read+write) accesses | 527system.cpu.dcache.ReadReq_accesses::cpu.data 8885648 # number of ReadReq accesses(hits+misses) 528system.cpu.dcache.ReadReq_accesses::total 8885648 # number of ReadReq accesses(hits+misses) 529system.cpu.dcache.WriteReq_accesses::cpu.data 6157889 # number of WriteReq accesses(hits+misses) 530system.cpu.dcache.WriteReq_accesses::total 6157889 # number of WriteReq accesses(hits+misses) 531system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200281 # number of LoadLockedReq accesses(hits+misses) 532system.cpu.dcache.LoadLockedReq_accesses::total 200281 # number of LoadLockedReq accesses(hits+misses) 533system.cpu.dcache.StoreCondReq_accesses::cpu.data 199258 # number of StoreCondReq accesses(hits+misses) 534system.cpu.dcache.StoreCondReq_accesses::total 199258 # number of StoreCondReq accesses(hits+misses) 535system.cpu.dcache.demand_accesses::cpu.data 15043537 # number of demand (read+write) accesses 536system.cpu.dcache.demand_accesses::total 15043537 # number of demand (read+write) accesses 537system.cpu.dcache.overall_accesses::cpu.data 15043537 # number of overall (read+write) accesses 538system.cpu.dcache.overall_accesses::total 15043537 # number of overall (read+write) accesses |
| 539system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120390 # miss rate for ReadReq accesses 540system.cpu.dcache.ReadReq_miss_rate::total 0.120390 # miss rate for ReadReq accesses 541system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049419 # miss rate for WriteReq accesses 542system.cpu.dcache.WriteReq_miss_rate::total 0.049419 # miss rate for WriteReq accesses 543system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086274 # miss rate for LoadLockedReq accesses 544system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086274 # miss rate for LoadLockedReq accesses | 539system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120389 # miss rate for ReadReq accesses 540system.cpu.dcache.ReadReq_miss_rate::total 0.120389 # miss rate for ReadReq accesses 541system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049420 # miss rate for WriteReq accesses 542system.cpu.dcache.WriteReq_miss_rate::total 0.049420 # miss rate for WriteReq accesses 543system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086269 # miss rate for LoadLockedReq accesses 544system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086269 # miss rate for LoadLockedReq accesses |
| 545system.cpu.dcache.demand_miss_rate::cpu.data 0.091339 # miss rate for demand accesses 546system.cpu.dcache.demand_miss_rate::total 0.091339 # miss rate for demand accesses 547system.cpu.dcache.overall_miss_rate::cpu.data 0.091339 # miss rate for overall accesses 548system.cpu.dcache.overall_miss_rate::total 0.091339 # miss rate for overall accesses | 545system.cpu.dcache.demand_miss_rate::cpu.data 0.091339 # miss rate for demand accesses 546system.cpu.dcache.demand_miss_rate::total 0.091339 # miss rate for demand accesses 547system.cpu.dcache.overall_miss_rate::cpu.data 0.091339 # miss rate for overall accesses 548system.cpu.dcache.overall_miss_rate::total 0.091339 # miss rate for overall accesses |
| 549system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.819370 # average ReadReq miss latency 550system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.819370 # average ReadReq miss latency 551system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.247934 # average WriteReq miss latency 552system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.247934 # average WriteReq miss latency 553system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.797268 # average LoadLockedReq miss latency 554system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.797268 # average LoadLockedReq miss latency 555system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency 556system.cpu.dcache.demand_avg_miss_latency::total 33835.981564 # average overall miss latency 557system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency 558system.cpu.dcache.overall_avg_miss_latency::total 33835.981564 # average overall miss latency | 549system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.839059 # average ReadReq miss latency 550system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.839059 # average ReadReq miss latency 551system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.067159 # average WriteReq miss latency 552system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.067159 # average WriteReq miss latency 553system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.823706 # average LoadLockedReq miss latency 554system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.823706 # average LoadLockedReq miss latency 555system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency 556system.cpu.dcache.demand_avg_miss_latency::total 33835.998678 # average overall miss latency 557system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency 558system.cpu.dcache.overall_avg_miss_latency::total 33835.998678 # average overall miss latency |
| 559system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 560system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 561system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 562system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 563system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 564system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 559system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 560system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 561system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 562system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 563system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 564system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 565system.cpu.dcache.writebacks::writebacks 835205 # number of writebacks 566system.cpu.dcache.writebacks::total 835205 # number of writebacks 567system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069743 # number of ReadReq MSHR misses 568system.cpu.dcache.ReadReq_mshr_misses::total 1069743 # number of ReadReq MSHR misses 569system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304319 # number of WriteReq MSHR misses 570system.cpu.dcache.WriteReq_mshr_misses::total 304319 # number of WriteReq MSHR misses 571system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17279 # number of LoadLockedReq MSHR misses 572system.cpu.dcache.LoadLockedReq_mshr_misses::total 17279 # number of LoadLockedReq MSHR misses 573system.cpu.dcache.demand_mshr_misses::cpu.data 1374062 # number of demand (read+write) MSHR misses 574system.cpu.dcache.demand_mshr_misses::total 1374062 # number of demand (read+write) MSHR misses 575system.cpu.dcache.overall_mshr_misses::cpu.data 1374062 # number of overall MSHR misses 576system.cpu.dcache.overall_mshr_misses::total 1374062 # number of overall MSHR misses | 565system.cpu.dcache.writebacks::writebacks 835203 # number of writebacks 566system.cpu.dcache.writebacks::total 835203 # number of writebacks 567system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069734 # number of ReadReq MSHR misses 568system.cpu.dcache.ReadReq_mshr_misses::total 1069734 # number of ReadReq MSHR misses 569system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304322 # number of WriteReq MSHR misses 570system.cpu.dcache.WriteReq_mshr_misses::total 304322 # number of WriteReq MSHR misses 571system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17278 # number of LoadLockedReq MSHR misses 572system.cpu.dcache.LoadLockedReq_mshr_misses::total 17278 # number of LoadLockedReq MSHR misses 573system.cpu.dcache.demand_mshr_misses::cpu.data 1374056 # number of demand (read+write) MSHR misses 574system.cpu.dcache.demand_mshr_misses::total 1374056 # number of demand (read+write) MSHR misses 575system.cpu.dcache.overall_mshr_misses::cpu.data 1374056 # number of overall MSHR misses 576system.cpu.dcache.overall_mshr_misses::total 1374056 # number of overall MSHR misses |
| 577system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 578system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 579system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable 580system.cpu.dcache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable 581system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses 582system.cpu.dcache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses | 577system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 578system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 579system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable 580system.cpu.dcache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable 581system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses 582system.cpu.dcache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses |
| 583system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980843500 # number of ReadReq MSHR miss cycles 584system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980843500 # number of ReadReq MSHR miss cycles 585system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137831000 # number of WriteReq MSHR miss cycles 586system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137831000 # number of WriteReq MSHR miss cycles 587system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215241000 # number of LoadLockedReq MSHR miss cycles 588system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215241000 # number of LoadLockedReq MSHR miss cycles 589system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118674500 # number of demand (read+write) MSHR miss cycles 590system.cpu.dcache.demand_mshr_miss_latency::total 45118674500 # number of demand (read+write) MSHR miss cycles 591system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118674500 # number of overall MSHR miss cycles 592system.cpu.dcache.overall_mshr_miss_latency::total 45118674500 # number of overall MSHR miss cycles | 583system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980595500 # number of ReadReq MSHR miss cycles 584system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980595500 # number of ReadReq MSHR miss cycles 585system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137905500 # number of WriteReq MSHR miss cycles 586system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137905500 # number of WriteReq MSHR miss cycles 587system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215229000 # number of LoadLockedReq MSHR miss cycles 588system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215229000 # number of LoadLockedReq MSHR miss cycles 589system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118501000 # number of demand (read+write) MSHR miss cycles 590system.cpu.dcache.demand_mshr_miss_latency::total 45118501000 # number of demand (read+write) MSHR miss cycles 591system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118501000 # number of overall MSHR miss cycles 592system.cpu.dcache.overall_mshr_miss_latency::total 45118501000 # number of overall MSHR miss cycles |
| 593system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533908500 # number of ReadReq MSHR uncacheable cycles 594system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533908500 # number of ReadReq MSHR uncacheable cycles 595system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533908500 # number of overall MSHR uncacheable cycles 596system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533908500 # number of overall MSHR uncacheable cycles | 593system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533908500 # number of ReadReq MSHR uncacheable cycles 594system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533908500 # number of ReadReq MSHR uncacheable cycles 595system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533908500 # number of overall MSHR uncacheable cycles 596system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533908500 # number of overall MSHR uncacheable cycles |
| 597system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120390 # mshr miss rate for ReadReq accesses 598system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120390 # mshr miss rate for ReadReq accesses 599system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049419 # mshr miss rate for WriteReq accesses 600system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049419 # mshr miss rate for WriteReq accesses 601system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086274 # mshr miss rate for LoadLockedReq accesses 602system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086274 # mshr miss rate for LoadLockedReq accesses | 597system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120389 # mshr miss rate for ReadReq accesses 598system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120389 # mshr miss rate for ReadReq accesses 599system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049420 # mshr miss rate for WriteReq accesses 600system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049420 # mshr miss rate for WriteReq accesses 601system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086269 # mshr miss rate for LoadLockedReq accesses 602system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086269 # mshr miss rate for LoadLockedReq accesses |
| 603system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for demand accesses 604system.cpu.dcache.demand_mshr_miss_rate::total 0.091339 # mshr miss rate for demand accesses 605system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for overall accesses 606system.cpu.dcache.overall_mshr_miss_rate::total 0.091339 # mshr miss rate for overall accesses | 603system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for demand accesses 604system.cpu.dcache.demand_mshr_miss_rate::total 0.091339 # mshr miss rate for demand accesses 605system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for overall accesses 606system.cpu.dcache.overall_mshr_miss_rate::total 0.091339 # mshr miss rate for overall accesses |
| 607system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.819370 # average ReadReq mshr miss latency 608system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.819370 # average ReadReq mshr miss latency 609system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.247934 # average WriteReq mshr miss latency 610system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.247934 # average WriteReq mshr miss latency 611system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.797268 # average LoadLockedReq mshr miss latency 612system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.797268 # average LoadLockedReq mshr miss latency 613system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency 614system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency 615system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency 616system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency | 607system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.839059 # average ReadReq mshr miss latency 608system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.839059 # average ReadReq mshr miss latency 609system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.067159 # average WriteReq mshr miss latency 610system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.067159 # average WriteReq mshr miss latency 611system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.823706 # average LoadLockedReq mshr miss latency 612system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.823706 # average LoadLockedReq mshr miss latency 613system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency 614system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency 615system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency 616system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency |
| 617system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.217893 # average ReadReq mshr uncacheable latency 618system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.217893 # average ReadReq mshr uncacheable latency 619system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92504.432517 # average overall mshr uncacheable latency 620system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92504.432517 # average overall mshr uncacheable latency | 617system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.217893 # average ReadReq mshr uncacheable latency 618system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.217893 # average ReadReq mshr uncacheable latency 619system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92504.432517 # average overall mshr uncacheable latency 620system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92504.432517 # average overall mshr uncacheable latency |
| 621system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 622system.cpu.icache.tags.replacements 928683 # number of replacements 623system.cpu.icache.tags.tagsinuse 507.830404 # Cycle average of tags in use 624system.cpu.icache.tags.total_refs 55277502 # Total number of references to valid blocks. 625system.cpu.icache.tags.sampled_refs 929194 # Sample count of references to valid blocks. 626system.cpu.icache.tags.avg_refs 59.489732 # Average number of references to valid blocks. | 621system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 622system.cpu.icache.tags.replacements 928685 # number of replacements 623system.cpu.icache.tags.tagsinuse 507.830405 # Cycle average of tags in use 624system.cpu.icache.tags.total_refs 55277500 # Total number of references to valid blocks. 625system.cpu.icache.tags.sampled_refs 929196 # Sample count of references to valid blocks. 626system.cpu.icache.tags.avg_refs 59.489602 # Average number of references to valid blocks. |
| 627system.cpu.icache.tags.warmup_cycle 44439092500 # Cycle when the warmup percentage was hit. | 627system.cpu.icache.tags.warmup_cycle 44439092500 # Cycle when the warmup percentage was hit. |
| 628system.cpu.icache.tags.occ_blocks::cpu.inst 507.830404 # Average occupied blocks per requestor | 628system.cpu.icache.tags.occ_blocks::cpu.inst 507.830405 # Average occupied blocks per requestor |
| 629system.cpu.icache.tags.occ_percent::cpu.inst 0.991856 # Average percentage of cache occupancy 630system.cpu.icache.tags.occ_percent::total 0.991856 # Average percentage of cache occupancy 631system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 632system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 633system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 635system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 636system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 629system.cpu.icache.tags.occ_percent::cpu.inst 0.991856 # Average percentage of cache occupancy 630system.cpu.icache.tags.occ_percent::total 0.991856 # Average percentage of cache occupancy 631system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 632system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 633system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 635system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 636system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 637system.cpu.icache.tags.tag_accesses 57136210 # Number of tag accesses 638system.cpu.icache.tags.data_accesses 57136210 # Number of data accesses 639system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 640system.cpu.icache.ReadReq_hits::cpu.inst 55277502 # number of ReadReq hits 641system.cpu.icache.ReadReq_hits::total 55277502 # number of ReadReq hits 642system.cpu.icache.demand_hits::cpu.inst 55277502 # number of demand (read+write) hits 643system.cpu.icache.demand_hits::total 55277502 # number of demand (read+write) hits 644system.cpu.icache.overall_hits::cpu.inst 55277502 # number of overall hits 645system.cpu.icache.overall_hits::total 55277502 # number of overall hits 646system.cpu.icache.ReadReq_misses::cpu.inst 929354 # number of ReadReq misses 647system.cpu.icache.ReadReq_misses::total 929354 # number of ReadReq misses 648system.cpu.icache.demand_misses::cpu.inst 929354 # number of demand (read+write) misses 649system.cpu.icache.demand_misses::total 929354 # number of demand (read+write) misses 650system.cpu.icache.overall_misses::cpu.inst 929354 # number of overall misses 651system.cpu.icache.overall_misses::total 929354 # number of overall misses 652system.cpu.icache.ReadReq_miss_latency::cpu.inst 13309679000 # number of ReadReq miss cycles 653system.cpu.icache.ReadReq_miss_latency::total 13309679000 # number of ReadReq miss cycles 654system.cpu.icache.demand_miss_latency::cpu.inst 13309679000 # number of demand (read+write) miss cycles 655system.cpu.icache.demand_miss_latency::total 13309679000 # number of demand (read+write) miss cycles 656system.cpu.icache.overall_miss_latency::cpu.inst 13309679000 # number of overall miss cycles 657system.cpu.icache.overall_miss_latency::total 13309679000 # number of overall miss cycles | 637system.cpu.icache.tags.tag_accesses 57136212 # Number of tag accesses 638system.cpu.icache.tags.data_accesses 57136212 # Number of data accesses 639system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 640system.cpu.icache.ReadReq_hits::cpu.inst 55277500 # number of ReadReq hits 641system.cpu.icache.ReadReq_hits::total 55277500 # number of ReadReq hits 642system.cpu.icache.demand_hits::cpu.inst 55277500 # number of demand (read+write) hits 643system.cpu.icache.demand_hits::total 55277500 # number of demand (read+write) hits 644system.cpu.icache.overall_hits::cpu.inst 55277500 # number of overall hits 645system.cpu.icache.overall_hits::total 55277500 # number of overall hits 646system.cpu.icache.ReadReq_misses::cpu.inst 929356 # number of ReadReq misses 647system.cpu.icache.ReadReq_misses::total 929356 # number of ReadReq misses 648system.cpu.icache.demand_misses::cpu.inst 929356 # number of demand (read+write) misses 649system.cpu.icache.demand_misses::total 929356 # number of demand (read+write) misses 650system.cpu.icache.overall_misses::cpu.inst 929356 # number of overall misses 651system.cpu.icache.overall_misses::total 929356 # number of overall misses 652system.cpu.icache.ReadReq_miss_latency::cpu.inst 13310087000 # number of ReadReq miss cycles 653system.cpu.icache.ReadReq_miss_latency::total 13310087000 # number of ReadReq miss cycles 654system.cpu.icache.demand_miss_latency::cpu.inst 13310087000 # number of demand (read+write) miss cycles 655system.cpu.icache.demand_miss_latency::total 13310087000 # number of demand (read+write) miss cycles 656system.cpu.icache.overall_miss_latency::cpu.inst 13310087000 # number of overall miss cycles 657system.cpu.icache.overall_miss_latency::total 13310087000 # number of overall miss cycles |
| 658system.cpu.icache.ReadReq_accesses::cpu.inst 56206856 # number of ReadReq accesses(hits+misses) 659system.cpu.icache.ReadReq_accesses::total 56206856 # number of ReadReq accesses(hits+misses) 660system.cpu.icache.demand_accesses::cpu.inst 56206856 # number of demand (read+write) accesses 661system.cpu.icache.demand_accesses::total 56206856 # number of demand (read+write) accesses 662system.cpu.icache.overall_accesses::cpu.inst 56206856 # number of overall (read+write) accesses 663system.cpu.icache.overall_accesses::total 56206856 # number of overall (read+write) accesses 664system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016535 # miss rate for ReadReq accesses 665system.cpu.icache.ReadReq_miss_rate::total 0.016535 # miss rate for ReadReq accesses 666system.cpu.icache.demand_miss_rate::cpu.inst 0.016535 # miss rate for demand accesses 667system.cpu.icache.demand_miss_rate::total 0.016535 # miss rate for demand accesses 668system.cpu.icache.overall_miss_rate::cpu.inst 0.016535 # miss rate for overall accesses 669system.cpu.icache.overall_miss_rate::total 0.016535 # miss rate for overall accesses | 658system.cpu.icache.ReadReq_accesses::cpu.inst 56206856 # number of ReadReq accesses(hits+misses) 659system.cpu.icache.ReadReq_accesses::total 56206856 # number of ReadReq accesses(hits+misses) 660system.cpu.icache.demand_accesses::cpu.inst 56206856 # number of demand (read+write) accesses 661system.cpu.icache.demand_accesses::total 56206856 # number of demand (read+write) accesses 662system.cpu.icache.overall_accesses::cpu.inst 56206856 # number of overall (read+write) accesses 663system.cpu.icache.overall_accesses::total 56206856 # number of overall (read+write) accesses 664system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016535 # miss rate for ReadReq accesses 665system.cpu.icache.ReadReq_miss_rate::total 0.016535 # miss rate for ReadReq accesses 666system.cpu.icache.demand_miss_rate::cpu.inst 0.016535 # miss rate for demand accesses 667system.cpu.icache.demand_miss_rate::total 0.016535 # miss rate for demand accesses 668system.cpu.icache.overall_miss_rate::cpu.inst 0.016535 # miss rate for overall accesses 669system.cpu.icache.overall_miss_rate::total 0.016535 # miss rate for overall accesses |
| 670system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.430800 # average ReadReq miss latency 671system.cpu.icache.ReadReq_avg_miss_latency::total 14321.430800 # average ReadReq miss latency 672system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency 673system.cpu.icache.demand_avg_miss_latency::total 14321.430800 # average overall miss latency 674system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency 675system.cpu.icache.overall_avg_miss_latency::total 14321.430800 # average overall miss latency | 670system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.838994 # average ReadReq miss latency 671system.cpu.icache.ReadReq_avg_miss_latency::total 14321.838994 # average ReadReq miss latency 672system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.838994 # average overall miss latency 673system.cpu.icache.demand_avg_miss_latency::total 14321.838994 # average overall miss latency 674system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.838994 # average overall miss latency 675system.cpu.icache.overall_avg_miss_latency::total 14321.838994 # average overall miss latency |
| 676system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 677system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 678system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 679system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 680system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 681system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 676system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 677system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 678system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 679system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 680system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 681system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 682system.cpu.icache.writebacks::writebacks 928683 # number of writebacks 683system.cpu.icache.writebacks::total 928683 # number of writebacks 684system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929354 # number of ReadReq MSHR misses 685system.cpu.icache.ReadReq_mshr_misses::total 929354 # number of ReadReq MSHR misses 686system.cpu.icache.demand_mshr_misses::cpu.inst 929354 # number of demand (read+write) MSHR misses 687system.cpu.icache.demand_mshr_misses::total 929354 # number of demand (read+write) MSHR misses 688system.cpu.icache.overall_mshr_misses::cpu.inst 929354 # number of overall MSHR misses 689system.cpu.icache.overall_mshr_misses::total 929354 # number of overall MSHR misses 690system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380325000 # number of ReadReq MSHR miss cycles 691system.cpu.icache.ReadReq_mshr_miss_latency::total 12380325000 # number of ReadReq MSHR miss cycles 692system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12380325000 # number of demand (read+write) MSHR miss cycles 693system.cpu.icache.demand_mshr_miss_latency::total 12380325000 # number of demand (read+write) MSHR miss cycles 694system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12380325000 # number of overall MSHR miss cycles 695system.cpu.icache.overall_mshr_miss_latency::total 12380325000 # number of overall MSHR miss cycles | 682system.cpu.icache.writebacks::writebacks 928685 # number of writebacks 683system.cpu.icache.writebacks::total 928685 # number of writebacks 684system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929356 # number of ReadReq MSHR misses 685system.cpu.icache.ReadReq_mshr_misses::total 929356 # number of ReadReq MSHR misses 686system.cpu.icache.demand_mshr_misses::cpu.inst 929356 # number of demand (read+write) MSHR misses 687system.cpu.icache.demand_mshr_misses::total 929356 # number of demand (read+write) MSHR misses 688system.cpu.icache.overall_mshr_misses::cpu.inst 929356 # number of overall MSHR misses 689system.cpu.icache.overall_mshr_misses::total 929356 # number of overall MSHR misses 690system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380731000 # number of ReadReq MSHR miss cycles 691system.cpu.icache.ReadReq_mshr_miss_latency::total 12380731000 # number of ReadReq MSHR miss cycles 692system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12380731000 # number of demand (read+write) MSHR miss cycles 693system.cpu.icache.demand_mshr_miss_latency::total 12380731000 # number of demand (read+write) MSHR miss cycles 694system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12380731000 # number of overall MSHR miss cycles 695system.cpu.icache.overall_mshr_miss_latency::total 12380731000 # number of overall MSHR miss cycles |
| 696system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for ReadReq accesses 697system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016535 # mshr miss rate for ReadReq accesses 698system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for demand accesses 699system.cpu.icache.demand_mshr_miss_rate::total 0.016535 # mshr miss rate for demand accesses 700system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for overall accesses 701system.cpu.icache.overall_mshr_miss_rate::total 0.016535 # mshr miss rate for overall accesses | 696system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for ReadReq accesses 697system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016535 # mshr miss rate for ReadReq accesses 698system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for demand accesses 699system.cpu.icache.demand_mshr_miss_rate::total 0.016535 # mshr miss rate for demand accesses 700system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for overall accesses 701system.cpu.icache.overall_mshr_miss_rate::total 0.016535 # mshr miss rate for overall accesses |
| 702system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.430800 # average ReadReq mshr miss latency 703system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.430800 # average ReadReq mshr miss latency 704system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.430800 # average overall mshr miss latency 705system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.430800 # average overall mshr miss latency 706system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.430800 # average overall mshr miss latency 707system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.430800 # average overall mshr miss latency 708system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states | 702system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.838994 # average ReadReq mshr miss latency 703system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.838994 # average ReadReq mshr miss latency 704system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency 705system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency 706system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency 707system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency 708system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states |
| 709system.cpu.l2cache.tags.replacements 336397 # number of replacements | 709system.cpu.l2cache.tags.replacements 336397 # number of replacements |
| 710system.cpu.l2cache.tags.tagsinuse 65387.710851 # Cycle average of tags in use 711system.cpu.l2cache.tags.total_refs 4236321 # Total number of references to valid blocks. | 710system.cpu.l2cache.tags.tagsinuse 65387.710870 # Cycle average of tags in use 711system.cpu.l2cache.tags.total_refs 4236311 # Total number of references to valid blocks. |
| 712system.cpu.l2cache.tags.sampled_refs 401919 # Sample count of references to valid blocks. | 712system.cpu.l2cache.tags.sampled_refs 401919 # Sample count of references to valid blocks. |
| 713system.cpu.l2cache.tags.avg_refs 10.540236 # Average number of references to valid blocks. | 713system.cpu.l2cache.tags.avg_refs 10.540211 # Average number of references to valid blocks. |
| 714system.cpu.l2cache.tags.warmup_cycle 7724199000 # Cycle when the warmup percentage was hit. | 714system.cpu.l2cache.tags.warmup_cycle 7724199000 # Cycle when the warmup percentage was hit. |
| 715system.cpu.l2cache.tags.occ_blocks::writebacks 234.658578 # Average occupied blocks per requestor 716system.cpu.l2cache.tags.occ_blocks::cpu.inst 4730.574413 # Average occupied blocks per requestor 717system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477860 # Average occupied blocks per requestor | 715system.cpu.l2cache.tags.occ_blocks::writebacks 234.658565 # Average occupied blocks per requestor 716system.cpu.l2cache.tags.occ_blocks::cpu.inst 4730.574877 # Average occupied blocks per requestor 717system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477428 # Average occupied blocks per requestor |
| 718system.cpu.l2cache.tags.occ_percent::writebacks 0.003581 # Average percentage of cache occupancy 719system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072183 # Average percentage of cache occupancy 720system.cpu.l2cache.tags.occ_percent::cpu.data 0.921974 # Average percentage of cache occupancy 721system.cpu.l2cache.tags.occ_percent::total 0.997737 # Average percentage of cache occupancy 722system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 723system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id 724system.cpu.l2cache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id 725system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4685 # Occupied blocks per task id 726system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59935 # Occupied blocks per task id 727system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id | 718system.cpu.l2cache.tags.occ_percent::writebacks 0.003581 # Average percentage of cache occupancy 719system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072183 # Average percentage of cache occupancy 720system.cpu.l2cache.tags.occ_percent::cpu.data 0.921974 # Average percentage of cache occupancy 721system.cpu.l2cache.tags.occ_percent::total 0.997737 # Average percentage of cache occupancy 722system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 723system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id 724system.cpu.l2cache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id 725system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4685 # Occupied blocks per task id 726system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59935 # Occupied blocks per task id 727system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id |
| 728system.cpu.l2cache.tags.tag_accesses 37511490 # Number of tag accesses 729system.cpu.l2cache.tags.data_accesses 37511490 # Number of data accesses 730system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 731system.cpu.l2cache.WritebackDirty_hits::writebacks 835205 # number of WritebackDirty hits 732system.cpu.l2cache.WritebackDirty_hits::total 835205 # number of WritebackDirty hits 733system.cpu.l2cache.WritebackClean_hits::writebacks 928450 # number of WritebackClean hits 734system.cpu.l2cache.WritebackClean_hits::total 928450 # number of WritebackClean hits | 728system.cpu.l2cache.tags.tag_accesses 37511410 # Number of tag accesses 729system.cpu.l2cache.tags.data_accesses 37511410 # Number of data accesses 730system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 731system.cpu.l2cache.WritebackDirty_hits::writebacks 835203 # number of WritebackDirty hits 732system.cpu.l2cache.WritebackDirty_hits::total 835203 # number of WritebackDirty hits 733system.cpu.l2cache.WritebackClean_hits::writebacks 928452 # number of WritebackClean hits 734system.cpu.l2cache.WritebackClean_hits::total 928452 # number of WritebackClean hits |
| 735system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits 736system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits | 735system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits 736system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits |
| 737system.cpu.l2cache.ReadExReq_hits::cpu.data 187485 # number of ReadExReq hits 738system.cpu.l2cache.ReadExReq_hits::total 187485 # number of ReadExReq hits 739system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916136 # number of ReadCleanReq hits 740system.cpu.l2cache.ReadCleanReq_hits::total 916136 # number of ReadCleanReq hits 741system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815048 # number of ReadSharedReq hits 742system.cpu.l2cache.ReadSharedReq_hits::total 815048 # number of ReadSharedReq hits 743system.cpu.l2cache.demand_hits::cpu.inst 916136 # number of demand (read+write) hits 744system.cpu.l2cache.demand_hits::cpu.data 1002533 # number of demand (read+write) hits 745system.cpu.l2cache.demand_hits::total 1918669 # number of demand (read+write) hits 746system.cpu.l2cache.overall_hits::cpu.inst 916136 # number of overall hits 747system.cpu.l2cache.overall_hits::cpu.data 1002533 # number of overall hits 748system.cpu.l2cache.overall_hits::total 1918669 # number of overall hits | 737system.cpu.l2cache.ReadExReq_hits::cpu.data 187488 # number of ReadExReq hits 738system.cpu.l2cache.ReadExReq_hits::total 187488 # number of ReadExReq hits 739system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916138 # number of ReadCleanReq hits 740system.cpu.l2cache.ReadCleanReq_hits::total 916138 # number of ReadCleanReq hits 741system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815038 # number of ReadSharedReq hits 742system.cpu.l2cache.ReadSharedReq_hits::total 815038 # number of ReadSharedReq hits 743system.cpu.l2cache.demand_hits::cpu.inst 916138 # number of demand (read+write) hits 744system.cpu.l2cache.demand_hits::cpu.data 1002526 # number of demand (read+write) hits 745system.cpu.l2cache.demand_hits::total 1918664 # number of demand (read+write) hits 746system.cpu.l2cache.overall_hits::cpu.inst 916138 # number of overall hits 747system.cpu.l2cache.overall_hits::cpu.data 1002526 # number of overall hits 748system.cpu.l2cache.overall_hits::total 1918664 # number of overall hits |
| 749system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 750system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses 751system.cpu.l2cache.ReadExReq_misses::cpu.data 116817 # number of ReadExReq misses 752system.cpu.l2cache.ReadExReq_misses::total 116817 # number of ReadExReq misses 753system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13198 # number of ReadCleanReq misses 754system.cpu.l2cache.ReadCleanReq_misses::total 13198 # number of ReadCleanReq misses 755system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271974 # number of ReadSharedReq misses 756system.cpu.l2cache.ReadSharedReq_misses::total 271974 # number of ReadSharedReq misses 757system.cpu.l2cache.demand_misses::cpu.inst 13198 # number of demand (read+write) misses 758system.cpu.l2cache.demand_misses::cpu.data 388791 # number of demand (read+write) misses 759system.cpu.l2cache.demand_misses::total 401989 # number of demand (read+write) misses 760system.cpu.l2cache.overall_misses::cpu.inst 13198 # number of overall misses 761system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses 762system.cpu.l2cache.overall_misses::total 401989 # number of overall misses 763system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 246500 # number of UpgradeReq miss cycles 764system.cpu.l2cache.UpgradeReq_miss_latency::total 246500 # number of UpgradeReq miss cycles | 749system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 750system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses 751system.cpu.l2cache.ReadExReq_misses::cpu.data 116817 # number of ReadExReq misses 752system.cpu.l2cache.ReadExReq_misses::total 116817 # number of ReadExReq misses 753system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13198 # number of ReadCleanReq misses 754system.cpu.l2cache.ReadCleanReq_misses::total 13198 # number of ReadCleanReq misses 755system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271974 # number of ReadSharedReq misses 756system.cpu.l2cache.ReadSharedReq_misses::total 271974 # number of ReadSharedReq misses 757system.cpu.l2cache.demand_misses::cpu.inst 13198 # number of demand (read+write) misses 758system.cpu.l2cache.demand_misses::cpu.data 388791 # number of demand (read+write) misses 759system.cpu.l2cache.demand_misses::total 401989 # number of demand (read+write) misses 760system.cpu.l2cache.overall_misses::cpu.inst 13198 # number of overall misses 761system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses 762system.cpu.l2cache.overall_misses::total 401989 # number of overall misses 763system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 246500 # number of UpgradeReq miss cycles 764system.cpu.l2cache.UpgradeReq_miss_latency::total 246500 # number of UpgradeReq miss cycles |
| 765system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10709040500 # number of ReadExReq miss cycles 766system.cpu.l2cache.ReadExReq_miss_latency::total 10709040500 # number of ReadExReq miss cycles 767system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1353538000 # number of ReadCleanReq miss cycles 768system.cpu.l2cache.ReadCleanReq_miss_latency::total 1353538000 # number of ReadCleanReq miss cycles 769system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21993492000 # number of ReadSharedReq miss cycles 770system.cpu.l2cache.ReadSharedReq_miss_latency::total 21993492000 # number of ReadSharedReq miss cycles 771system.cpu.l2cache.demand_miss_latency::cpu.inst 1353538000 # number of demand (read+write) miss cycles 772system.cpu.l2cache.demand_miss_latency::cpu.data 32702532500 # number of demand (read+write) miss cycles 773system.cpu.l2cache.demand_miss_latency::total 34056070500 # number of demand (read+write) miss cycles 774system.cpu.l2cache.overall_miss_latency::cpu.inst 1353538000 # number of overall miss cycles 775system.cpu.l2cache.overall_miss_latency::cpu.data 32702532500 # number of overall miss cycles 776system.cpu.l2cache.overall_miss_latency::total 34056070500 # number of overall miss cycles 777system.cpu.l2cache.WritebackDirty_accesses::writebacks 835205 # number of WritebackDirty accesses(hits+misses) 778system.cpu.l2cache.WritebackDirty_accesses::total 835205 # number of WritebackDirty accesses(hits+misses) 779system.cpu.l2cache.WritebackClean_accesses::writebacks 928450 # number of WritebackClean accesses(hits+misses) 780system.cpu.l2cache.WritebackClean_accesses::total 928450 # number of WritebackClean accesses(hits+misses) | 765system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10708900500 # number of ReadExReq miss cycles 766system.cpu.l2cache.ReadExReq_miss_latency::total 10708900500 # number of ReadExReq miss cycles 767system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1353922000 # number of ReadCleanReq miss cycles 768system.cpu.l2cache.ReadCleanReq_miss_latency::total 1353922000 # number of ReadCleanReq miss cycles 769system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21993208500 # number of ReadSharedReq miss cycles 770system.cpu.l2cache.ReadSharedReq_miss_latency::total 21993208500 # number of ReadSharedReq miss cycles 771system.cpu.l2cache.demand_miss_latency::cpu.inst 1353922000 # number of demand (read+write) miss cycles 772system.cpu.l2cache.demand_miss_latency::cpu.data 32702109000 # number of demand (read+write) miss cycles 773system.cpu.l2cache.demand_miss_latency::total 34056031000 # number of demand (read+write) miss cycles 774system.cpu.l2cache.overall_miss_latency::cpu.inst 1353922000 # number of overall miss cycles 775system.cpu.l2cache.overall_miss_latency::cpu.data 32702109000 # number of overall miss cycles 776system.cpu.l2cache.overall_miss_latency::total 34056031000 # number of overall miss cycles 777system.cpu.l2cache.WritebackDirty_accesses::writebacks 835203 # number of WritebackDirty accesses(hits+misses) 778system.cpu.l2cache.WritebackDirty_accesses::total 835203 # number of WritebackDirty accesses(hits+misses) 779system.cpu.l2cache.WritebackClean_accesses::writebacks 928452 # number of WritebackClean accesses(hits+misses) 780system.cpu.l2cache.WritebackClean_accesses::total 928452 # number of WritebackClean accesses(hits+misses) |
| 781system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 782system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) | 781system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 782system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) |
| 783system.cpu.l2cache.ReadExReq_accesses::cpu.data 304302 # number of ReadExReq accesses(hits+misses) 784system.cpu.l2cache.ReadExReq_accesses::total 304302 # number of ReadExReq accesses(hits+misses) 785system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929334 # number of ReadCleanReq accesses(hits+misses) 786system.cpu.l2cache.ReadCleanReq_accesses::total 929334 # number of ReadCleanReq accesses(hits+misses) 787system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087022 # number of ReadSharedReq accesses(hits+misses) 788system.cpu.l2cache.ReadSharedReq_accesses::total 1087022 # number of ReadSharedReq accesses(hits+misses) 789system.cpu.l2cache.demand_accesses::cpu.inst 929334 # number of demand (read+write) accesses 790system.cpu.l2cache.demand_accesses::cpu.data 1391324 # number of demand (read+write) accesses 791system.cpu.l2cache.demand_accesses::total 2320658 # number of demand (read+write) accesses 792system.cpu.l2cache.overall_accesses::cpu.inst 929334 # number of overall (read+write) accesses 793system.cpu.l2cache.overall_accesses::cpu.data 1391324 # number of overall (read+write) accesses 794system.cpu.l2cache.overall_accesses::total 2320658 # number of overall (read+write) accesses | 783system.cpu.l2cache.ReadExReq_accesses::cpu.data 304305 # number of ReadExReq accesses(hits+misses) 784system.cpu.l2cache.ReadExReq_accesses::total 304305 # number of ReadExReq accesses(hits+misses) 785system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929336 # number of ReadCleanReq accesses(hits+misses) 786system.cpu.l2cache.ReadCleanReq_accesses::total 929336 # number of ReadCleanReq accesses(hits+misses) 787system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087012 # number of ReadSharedReq accesses(hits+misses) 788system.cpu.l2cache.ReadSharedReq_accesses::total 1087012 # number of ReadSharedReq accesses(hits+misses) 789system.cpu.l2cache.demand_accesses::cpu.inst 929336 # number of demand (read+write) accesses 790system.cpu.l2cache.demand_accesses::cpu.data 1391317 # number of demand (read+write) accesses 791system.cpu.l2cache.demand_accesses::total 2320653 # number of demand (read+write) accesses 792system.cpu.l2cache.overall_accesses::cpu.inst 929336 # number of overall (read+write) accesses 793system.cpu.l2cache.overall_accesses::cpu.data 1391317 # number of overall (read+write) accesses 794system.cpu.l2cache.overall_accesses::total 2320653 # number of overall (read+write) accesses |
| 795system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for UpgradeReq accesses 796system.cpu.l2cache.UpgradeReq_miss_rate::total 0.294118 # miss rate for UpgradeReq accesses | 795system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for UpgradeReq accesses 796system.cpu.l2cache.UpgradeReq_miss_rate::total 0.294118 # miss rate for UpgradeReq accesses |
| 797system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383885 # miss rate for ReadExReq accesses 798system.cpu.l2cache.ReadExReq_miss_rate::total 0.383885 # miss rate for ReadExReq accesses | 797system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383881 # miss rate for ReadExReq accesses 798system.cpu.l2cache.ReadExReq_miss_rate::total 0.383881 # miss rate for ReadExReq accesses |
| 799system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014202 # miss rate for ReadCleanReq accesses 800system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014202 # miss rate for ReadCleanReq accesses | 799system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014202 # miss rate for ReadCleanReq accesses 800system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014202 # miss rate for ReadCleanReq accesses |
| 801system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250201 # miss rate for ReadSharedReq accesses 802system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250201 # miss rate for ReadSharedReq accesses | 801system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250203 # miss rate for ReadSharedReq accesses 802system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250203 # miss rate for ReadSharedReq accesses |
| 803system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014202 # miss rate for demand accesses | 803system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014202 # miss rate for demand accesses |
| 804system.cpu.l2cache.demand_miss_rate::cpu.data 0.279440 # miss rate for demand accesses | 804system.cpu.l2cache.demand_miss_rate::cpu.data 0.279441 # miss rate for demand accesses |
| 805system.cpu.l2cache.demand_miss_rate::total 0.173222 # miss rate for demand accesses 806system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014202 # miss rate for overall accesses | 805system.cpu.l2cache.demand_miss_rate::total 0.173222 # miss rate for demand accesses 806system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014202 # miss rate for overall accesses |
| 807system.cpu.l2cache.overall_miss_rate::cpu.data 0.279440 # miss rate for overall accesses | 807system.cpu.l2cache.overall_miss_rate::cpu.data 0.279441 # miss rate for overall accesses |
| 808system.cpu.l2cache.overall_miss_rate::total 0.173222 # miss rate for overall accesses 809system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49300 # average UpgradeReq miss latency 810system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49300 # average UpgradeReq miss latency | 808system.cpu.l2cache.overall_miss_rate::total 0.173222 # miss rate for overall accesses 809system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49300 # average UpgradeReq miss latency 810system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49300 # average UpgradeReq miss latency |
| 811system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91673.647671 # average ReadExReq miss latency 812system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91673.647671 # average ReadExReq miss latency 813system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102556.296409 # average ReadCleanReq miss latency 814system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102556.296409 # average ReadCleanReq miss latency 815system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80866.156324 # average ReadSharedReq miss latency 816system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80866.156324 # average ReadSharedReq miss latency 817system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102556.296409 # average overall miss latency 818system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84113.398973 # average overall miss latency 819system.cpu.l2cache.demand_avg_miss_latency::total 84718.911463 # average overall miss latency 820system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102556.296409 # average overall miss latency 821system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84113.398973 # average overall miss latency 822system.cpu.l2cache.overall_avg_miss_latency::total 84718.911463 # average overall miss latency | 811system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91672.449215 # average ReadExReq miss latency 812system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91672.449215 # average ReadExReq miss latency 813system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102585.391726 # average ReadCleanReq miss latency 814system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102585.391726 # average ReadCleanReq miss latency 815system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80865.113945 # average ReadSharedReq miss latency 816system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80865.113945 # average ReadSharedReq miss latency 817system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102585.391726 # average overall miss latency 818system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84112.309699 # average overall miss latency 819system.cpu.l2cache.demand_avg_miss_latency::total 84718.813201 # average overall miss latency 820system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102585.391726 # average overall miss latency 821system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84112.309699 # average overall miss latency 822system.cpu.l2cache.overall_avg_miss_latency::total 84718.813201 # average overall miss latency |
| 823system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 824system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 825system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 826system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 827system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 828system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 829system.cpu.l2cache.writebacks::writebacks 74253 # number of writebacks 830system.cpu.l2cache.writebacks::total 74253 # number of writebacks --- 14 unchanged lines hidden (view full) --- 845system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 846system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 847system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable 848system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable 849system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses 850system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses 851system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles 852system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles | 823system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 824system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 825system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 826system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 827system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 828system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 829system.cpu.l2cache.writebacks::writebacks 74253 # number of writebacks 830system.cpu.l2cache.writebacks::total 74253 # number of writebacks --- 14 unchanged lines hidden (view full) --- 845system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 846system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 847system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable 848system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable 849system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses 850system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses 851system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles 852system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles |
| 853system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540870500 # number of ReadExReq MSHR miss cycles 854system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540870500 # number of ReadExReq MSHR miss cycles 855system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221558000 # number of ReadCleanReq MSHR miss cycles 856system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221558000 # number of ReadCleanReq MSHR miss cycles 857system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273752000 # number of ReadSharedReq MSHR miss cycles 858system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273752000 # number of ReadSharedReq MSHR miss cycles 859system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221558000 # number of demand (read+write) MSHR miss cycles 860system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814622500 # number of demand (read+write) MSHR miss cycles 861system.cpu.l2cache.demand_mshr_miss_latency::total 30036180500 # number of demand (read+write) MSHR miss cycles 862system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221558000 # number of overall MSHR miss cycles 863system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814622500 # number of overall MSHR miss cycles 864system.cpu.l2cache.overall_mshr_miss_latency::total 30036180500 # number of overall MSHR miss cycles | 853system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540730500 # number of ReadExReq MSHR miss cycles 854system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540730500 # number of ReadExReq MSHR miss cycles 855system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221942000 # number of ReadCleanReq MSHR miss cycles 856system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221942000 # number of ReadCleanReq MSHR miss cycles 857system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273468500 # number of ReadSharedReq MSHR miss cycles 858system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273468500 # number of ReadSharedReq MSHR miss cycles 859system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221942000 # number of demand (read+write) MSHR miss cycles 860system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814199000 # number of demand (read+write) MSHR miss cycles 861system.cpu.l2cache.demand_mshr_miss_latency::total 30036141000 # number of demand (read+write) MSHR miss cycles 862system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221942000 # number of overall MSHR miss cycles 863system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814199000 # number of overall MSHR miss cycles 864system.cpu.l2cache.overall_mshr_miss_latency::total 30036141000 # number of overall MSHR miss cycles |
| 865system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447252500 # number of ReadReq MSHR uncacheable cycles 866system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447252500 # number of ReadReq MSHR uncacheable cycles 867system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447252500 # number of overall MSHR uncacheable cycles 868system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447252500 # number of overall MSHR uncacheable cycles 869system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses 870system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses | 865system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447252500 # number of ReadReq MSHR uncacheable cycles 866system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447252500 # number of ReadReq MSHR uncacheable cycles 867system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447252500 # number of overall MSHR uncacheable cycles 868system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447252500 # number of overall MSHR uncacheable cycles 869system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses 870system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses |
| 871system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses 872system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses | 871system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383881 # mshr miss rate for ReadExReq accesses 872system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383881 # mshr miss rate for ReadExReq accesses |
| 873system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for ReadCleanReq accesses 874system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014202 # mshr miss rate for ReadCleanReq accesses | 873system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for ReadCleanReq accesses 874system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014202 # mshr miss rate for ReadCleanReq accesses |
| 875system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250201 # mshr miss rate for ReadSharedReq accesses 876system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250201 # mshr miss rate for ReadSharedReq accesses | 875system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250203 # mshr miss rate for ReadSharedReq accesses 876system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250203 # mshr miss rate for ReadSharedReq accesses |
| 877system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for demand accesses | 877system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for demand accesses |
| 878system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for demand accesses | 878system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for demand accesses |
| 879system.cpu.l2cache.demand_mshr_miss_rate::total 0.173222 # mshr miss rate for demand accesses 880system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for overall accesses | 879system.cpu.l2cache.demand_mshr_miss_rate::total 0.173222 # mshr miss rate for demand accesses 880system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for overall accesses |
| 881system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for overall accesses | 881system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for overall accesses |
| 882system.cpu.l2cache.overall_mshr_miss_rate::total 0.173222 # mshr miss rate for overall accesses 883system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency 884system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency | 882system.cpu.l2cache.overall_mshr_miss_rate::total 0.173222 # mshr miss rate for overall accesses 883system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency 884system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency |
| 885system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81673.647671 # average ReadExReq mshr miss latency 886system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81673.647671 # average ReadExReq mshr miss latency 887system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92556.296409 # average ReadCleanReq mshr miss latency 888system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92556.296409 # average ReadCleanReq mshr miss latency 889system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70866.156324 # average ReadSharedReq mshr miss latency 890system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70866.156324 # average ReadSharedReq mshr miss latency 891system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency 892system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency 893system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency 894system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency 895system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency 896system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency | 885system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81672.449215 # average ReadExReq mshr miss latency 886system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81672.449215 # average ReadExReq mshr miss latency 887system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92585.391726 # average ReadCleanReq mshr miss latency 888system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92585.391726 # average ReadCleanReq mshr miss latency 889system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70865.113945 # average ReadSharedReq mshr miss latency 890system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70865.113945 # average ReadSharedReq mshr miss latency 891system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency 892system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency 893system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency 894system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency 895system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency 896system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency |
| 897system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589 # average ReadReq mshr uncacheable latency 898system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589 # average ReadReq mshr uncacheable latency 899system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907 # average overall mshr uncacheable latency 900system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907 # average overall mshr uncacheable latency | 897system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589 # average ReadReq mshr uncacheable latency 898system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589 # average ReadReq mshr uncacheable latency 899system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907 # average overall mshr uncacheable latency 900system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907 # average overall mshr uncacheable latency |
| 901system.cpu.toL2Bus.snoop_filter.tot_requests 4640189 # Total number of requests made to the snoop filter. 902system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319660 # Number of requests hitting in the snoop filter with a single holder of the requested data. 903system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1516 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 901system.cpu.toL2Bus.snoop_filter.tot_requests 4640179 # Total number of requests made to the snoop filter. 902system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319543 # Number of requests hitting in the snoop filter with a single holder of the requested data. 903system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 904system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter. 905system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 906system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 904system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter. 905system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 906system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 907system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states | 907system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states |
| 908system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution | 908system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution |
| 909system.cpu.toL2Bus.trans_dist::ReadResp 2023463 # Transaction distribution | 909system.cpu.toL2Bus.trans_dist::ReadResp 2023455 # Transaction distribution |
| 910system.cpu.toL2Bus.trans_dist::WriteReq 9652 # Transaction distribution 911system.cpu.toL2Bus.trans_dist::WriteResp 9652 # Transaction distribution | 910system.cpu.toL2Bus.trans_dist::WriteReq 9652 # Transaction distribution 911system.cpu.toL2Bus.trans_dist::WriteResp 9652 # Transaction distribution |
| 912system.cpu.toL2Bus.trans_dist::WritebackDirty 909458 # Transaction distribution 913system.cpu.toL2Bus.trans_dist::WritebackClean 928683 # Transaction distribution 914system.cpu.toL2Bus.trans_dist::CleanEvict 817750 # Transaction distribution | 912system.cpu.toL2Bus.trans_dist::WritebackDirty 909456 # Transaction distribution 913system.cpu.toL2Bus.trans_dist::WritebackClean 928685 # Transaction distribution 914system.cpu.toL2Bus.trans_dist::CleanEvict 817745 # Transaction distribution |
| 915system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 916system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution | 915system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 916system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution |
| 917system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution 918system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution 919system.cpu.toL2Bus.trans_dist::ReadCleanReq 929354 # Transaction distribution 920system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087182 # Transaction distribution | 917system.cpu.toL2Bus.trans_dist::ReadExReq 304305 # Transaction distribution 918system.cpu.toL2Bus.trans_dist::ReadExResp 304305 # Transaction distribution 919system.cpu.toL2Bus.trans_dist::ReadCleanReq 929356 # Transaction distribution 920system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087173 # Transaction distribution |
| 921system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution | 921system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution |
| 922system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787371 # Packet count per connected master and slave (bytes) 923system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206814 # Packet count per connected master and slave (bytes) 924system.cpu.toL2Bus.pkt_count::total 6994185 # Packet count per connected master and slave (bytes) 925system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913088 # Cumulative packet size per connected master and slave (bytes) 926system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142552484 # Cumulative packet size per connected master and slave (bytes) 927system.cpu.toL2Bus.pkt_size::total 261465572 # Cumulative packet size per connected master and slave (bytes) 928system.cpu.toL2Bus.snoops 336953 # Total snoops (count) | 922system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution 923system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787377 # Packet count per connected master and slave (bytes) 924system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206794 # Packet count per connected master and slave (bytes) 925system.cpu.toL2Bus.pkt_count::total 6994171 # Packet count per connected master and slave (bytes) 926system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913344 # Cumulative packet size per connected master and slave (bytes) 927system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142551908 # Cumulative packet size per connected master and slave (bytes) 928system.cpu.toL2Bus.pkt_size::total 261465252 # Cumulative packet size per connected master and slave (bytes) 929system.cpu.toL2Bus.snoops 336955 # Total snoops (count) |
| 929system.cpu.toL2Bus.snoopTraffic 4763520 # Total snoop traffic (bytes) | 930system.cpu.toL2Bus.snoopTraffic 4763520 # Total snoop traffic (bytes) |
| 930system.cpu.toL2Bus.snoop_fanout::samples 2674053 # Request fanout histogram 931system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram 932system.cpu.toL2Bus.snoop_fanout::stdev 0.030932 # Request fanout histogram | 931system.cpu.toL2Bus.snoop_fanout::samples 2674049 # Request fanout histogram 932system.cpu.toL2Bus.snoop_fanout::mean 0.001078 # Request fanout histogram 933system.cpu.toL2Bus.snoop_fanout::stdev 0.032812 # Request fanout histogram |
| 933system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 934system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 934system.cpu.toL2Bus.snoop_fanout::0 2671492 99.90% 99.90% # Request fanout histogram 935system.cpu.toL2Bus.snoop_fanout::1 2561 0.10% 100.00% # Request fanout histogram | 935system.cpu.toL2Bus.snoop_fanout::0 2671167 99.89% 99.89% # Request fanout histogram 936system.cpu.toL2Bus.snoop_fanout::1 2882 0.11% 100.00% # Request fanout histogram |
| 936system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 937system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 938system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 939system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 937system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 938system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 939system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 940system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 940system.cpu.toL2Bus.snoop_fanout::total 2674053 # Request fanout histogram 941system.cpu.toL2Bus.reqLayer0.occupancy 4097099500 # Layer occupancy (ticks) | 941system.cpu.toL2Bus.snoop_fanout::total 2674049 # Request fanout histogram 942system.cpu.toL2Bus.reqLayer0.occupancy 4097094500 # Layer occupancy (ticks) |
| 942system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 943system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 943system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) | 944system.cpu.toL2Bus.snoopLayer0.occupancy 293883 # Layer occupancy (ticks) |
| 944system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 945system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 945system.cpu.toL2Bus.respLayer0.occupancy 1394031000 # Layer occupancy (ticks) | 946system.cpu.toL2Bus.respLayer0.occupancy 1394034000 # Layer occupancy (ticks) |
| 946system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 947system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 947system.cpu.toL2Bus.respLayer1.occupancy 2098750500 # Layer occupancy (ticks) | 948system.cpu.toL2Bus.respLayer1.occupancy 2098740000 # Layer occupancy (ticks) |
| 948system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 949system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 950system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 951system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 952system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 953system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 954system.disk0.dma_write_txs 395 # Number of DMA write transactions. 955system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 956system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 957system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 958system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 959system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 960system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 949system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 950system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 951system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 952system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 953system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 954system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 955system.disk0.dma_write_txs 395 # Number of DMA write transactions. 956system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 957system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 958system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 959system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 960system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 961system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 961system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states | 962system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states |
| 962system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 963system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 964system.iobus.trans_dist::WriteReq 51204 # Transaction distribution 965system.iobus.trans_dist::WriteResp 51204 # Transaction distribution 966system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5160 # Packet count per connected master and slave (bytes) 967system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 968system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 969system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 984system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 985system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 986system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 987system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 988system.iobus.pkt_size_system.bridge.master::total 44580 # Cumulative packet size per connected master and slave (bytes) 989system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 990system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 991system.iobus.pkt_size::total 2706188 # Cumulative packet size per connected master and slave (bytes) | 963system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 964system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 965system.iobus.trans_dist::WriteReq 51204 # Transaction distribution 966system.iobus.trans_dist::WriteResp 51204 # Transaction distribution 967system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5160 # Packet count per connected master and slave (bytes) 968system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 969system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 970system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 985system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 986system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 987system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 988system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 989system.iobus.pkt_size_system.bridge.master::total 44580 # Cumulative packet size per connected master and slave (bytes) 990system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 991system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 992system.iobus.pkt_size::total 2706188 # Cumulative packet size per connected master and slave (bytes) |
| 992system.iobus.reqLayer0.occupancy 5344500 # Layer occupancy (ticks) | 993system.iobus.reqLayer0.occupancy 5344000 # Layer occupancy (ticks) |
| 993system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 994system.iobus.reqLayer1.occupancy 757500 # Layer occupancy (ticks) 995system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 996system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 997system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 998system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 999system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1000system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) 1001system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1002system.iobus.reqLayer23.occupancy 15813000 # Layer occupancy (ticks) 1003system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1004system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) 1005system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1006system.iobus.reqLayer25.occupancy 6041500 # Layer occupancy (ticks) 1007system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1008system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) 1009system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 994system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 995system.iobus.reqLayer1.occupancy 757500 # Layer occupancy (ticks) 996system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 997system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 998system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 999system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1000system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1001system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) 1002system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1003system.iobus.reqLayer23.occupancy 15813000 # Layer occupancy (ticks) 1004system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1005system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) 1006system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1007system.iobus.reqLayer25.occupancy 6041500 # Layer occupancy (ticks) 1008system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1009system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) 1010system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1010system.iobus.reqLayer27.occupancy 216215769 # Layer occupancy (ticks) | 1011system.iobus.reqLayer27.occupancy 216206774 # Layer occupancy (ticks) |
| 1011system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1012system.iobus.respLayer0.occupancy 23512000 # Layer occupancy (ticks) 1013system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1014system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1015system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1012system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1013system.iobus.respLayer0.occupancy 23512000 # Layer occupancy (ticks) 1014system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1015system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1016system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1016system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states | 1017system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states |
| 1017system.iocache.tags.replacements 41685 # number of replacements | 1018system.iocache.tags.replacements 41685 # number of replacements |
| 1018system.iocache.tags.tagsinuse 1.340614 # Cycle average of tags in use | 1019system.iocache.tags.tagsinuse 1.342515 # Cycle average of tags in use |
| 1019system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1020system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1021system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1022system.iocache.tags.warmup_cycle 1760392723000 # Cycle when the warmup percentage was hit. | 1020system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1021system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1022system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1023system.iocache.tags.warmup_cycle 1760392723000 # Cycle when the warmup percentage was hit. |
| 1023system.iocache.tags.occ_blocks::tsunami.ide 1.340614 # Average occupied blocks per requestor 1024system.iocache.tags.occ_percent::tsunami.ide 0.083788 # Average percentage of cache occupancy 1025system.iocache.tags.occ_percent::total 0.083788 # Average percentage of cache occupancy | 1024system.iocache.tags.occ_blocks::tsunami.ide 1.342515 # Average occupied blocks per requestor 1025system.iocache.tags.occ_percent::tsunami.ide 0.083907 # Average percentage of cache occupancy 1026system.iocache.tags.occ_percent::total 0.083907 # Average percentage of cache occupancy |
| 1026system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1027system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1028system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1029system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1030system.iocache.tags.data_accesses 375525 # Number of data accesses | 1027system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1028system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1029system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1030system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1031system.iocache.tags.data_accesses 375525 # Number of data accesses |
| 1031system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states | 1032system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states |
| 1032system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1033system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1034system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1035system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1036system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1037system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1038system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1039system.iocache.overall_misses::total 41725 # number of overall misses 1040system.iocache.ReadReq_miss_latency::tsunami.ide 21848883 # number of ReadReq miss cycles 1041system.iocache.ReadReq_miss_latency::total 21848883 # number of ReadReq miss cycles | 1033system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1034system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1035system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1036system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1037system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1038system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1039system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1040system.iocache.overall_misses::total 41725 # number of overall misses 1041system.iocache.ReadReq_miss_latency::tsunami.ide 21848883 # number of ReadReq miss cycles 1042system.iocache.ReadReq_miss_latency::total 21848883 # number of ReadReq miss cycles |
| 1042system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937126886 # number of WriteLineReq miss cycles 1043system.iocache.WriteLineReq_miss_latency::total 4937126886 # number of WriteLineReq miss cycles 1044system.iocache.demand_miss_latency::tsunami.ide 4958975769 # number of demand (read+write) miss cycles 1045system.iocache.demand_miss_latency::total 4958975769 # number of demand (read+write) miss cycles 1046system.iocache.overall_miss_latency::tsunami.ide 4958975769 # number of overall miss cycles 1047system.iocache.overall_miss_latency::total 4958975769 # number of overall miss cycles | 1043system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937049891 # number of WriteLineReq miss cycles 1044system.iocache.WriteLineReq_miss_latency::total 4937049891 # number of WriteLineReq miss cycles 1045system.iocache.demand_miss_latency::tsunami.ide 4958898774 # number of demand (read+write) miss cycles 1046system.iocache.demand_miss_latency::total 4958898774 # number of demand (read+write) miss cycles 1047system.iocache.overall_miss_latency::tsunami.ide 4958898774 # number of overall miss cycles 1048system.iocache.overall_miss_latency::total 4958898774 # number of overall miss cycles |
| 1048system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1049system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1050system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1051system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1052system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1053system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1054system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1055system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1056system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1057system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1058system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1059system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1060system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1061system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1062system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1063system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1064system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387 # average ReadReq miss latency 1065system.iocache.ReadReq_avg_miss_latency::total 126294.121387 # average ReadReq miss latency | 1049system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1050system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1051system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1052system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1053system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1054system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1055system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1056system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1057system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1058system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1059system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1060system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1061system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1062system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1063system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1064system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1065system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387 # average ReadReq miss latency 1066system.iocache.ReadReq_avg_miss_latency::total 126294.121387 # average ReadReq miss latency |
| 1066system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118818.032489 # average WriteLineReq miss latency 1067system.iocache.WriteLineReq_avg_miss_latency::total 118818.032489 # average WriteLineReq miss latency 1068system.iocache.demand_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency 1069system.iocache.demand_avg_miss_latency::total 118849.029814 # average overall miss latency 1070system.iocache.overall_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency 1071system.iocache.overall_avg_miss_latency::total 118849.029814 # average overall miss latency | 1067system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118816.179510 # average WriteLineReq miss latency 1068system.iocache.WriteLineReq_avg_miss_latency::total 118816.179510 # average WriteLineReq miss latency 1069system.iocache.demand_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency 1070system.iocache.demand_avg_miss_latency::total 118847.184518 # average overall miss latency 1071system.iocache.overall_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency 1072system.iocache.overall_avg_miss_latency::total 118847.184518 # average overall miss latency |
| 1072system.iocache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked 1073system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1074system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked 1075system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1076system.iocache.avg_blocked_cycles::no_mshrs 175 # average number of cycles each access was blocked 1077system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1078system.iocache.writebacks::writebacks 41512 # number of writebacks 1079system.iocache.writebacks::total 41512 # number of writebacks 1080system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1081system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1082system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1083system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1084system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1085system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1086system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1087system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 1088system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13198883 # number of ReadReq MSHR miss cycles 1089system.iocache.ReadReq_mshr_miss_latency::total 13198883 # number of ReadReq MSHR miss cycles | 1073system.iocache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked 1074system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1075system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked 1076system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1077system.iocache.avg_blocked_cycles::no_mshrs 175 # average number of cycles each access was blocked 1078system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1079system.iocache.writebacks::writebacks 41512 # number of writebacks 1080system.iocache.writebacks::total 41512 # number of writebacks 1081system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1082system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1083system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1084system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1085system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1086system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1087system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1088system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 1089system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13198883 # number of ReadReq MSHR miss cycles 1090system.iocache.ReadReq_mshr_miss_latency::total 13198883 # number of ReadReq MSHR miss cycles |
| 1090system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857073994 # number of WriteLineReq MSHR miss cycles 1091system.iocache.WriteLineReq_mshr_miss_latency::total 2857073994 # number of WriteLineReq MSHR miss cycles 1092system.iocache.demand_mshr_miss_latency::tsunami.ide 2870272877 # number of demand (read+write) MSHR miss cycles 1093system.iocache.demand_mshr_miss_latency::total 2870272877 # number of demand (read+write) MSHR miss cycles 1094system.iocache.overall_mshr_miss_latency::tsunami.ide 2870272877 # number of overall MSHR miss cycles 1095system.iocache.overall_mshr_miss_latency::total 2870272877 # number of overall MSHR miss cycles | 1091system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857005811 # number of WriteLineReq MSHR miss cycles 1092system.iocache.WriteLineReq_mshr_miss_latency::total 2857005811 # number of WriteLineReq MSHR miss cycles 1093system.iocache.demand_mshr_miss_latency::tsunami.ide 2870204694 # number of demand (read+write) MSHR miss cycles 1094system.iocache.demand_mshr_miss_latency::total 2870204694 # number of demand (read+write) MSHR miss cycles 1095system.iocache.overall_mshr_miss_latency::tsunami.ide 2870204694 # number of overall MSHR miss cycles 1096system.iocache.overall_mshr_miss_latency::total 2870204694 # number of overall MSHR miss cycles |
| 1096system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1097system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1098system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1099system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1100system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1101system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1102system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1103system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1104system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387 # average ReadReq mshr miss latency 1105system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387 # average ReadReq mshr miss latency | 1097system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1098system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1099system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1100system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1101system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1102system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1103system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1104system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1105system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387 # average ReadReq mshr miss latency 1106system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387 # average ReadReq mshr miss latency |
| 1106system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68759.000626 # average WriteLineReq mshr miss latency 1107system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68759.000626 # average WriteLineReq mshr miss latency 1108system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency 1109system.iocache.demand_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency 1110system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency 1111system.iocache.overall_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency | 1107system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68757.359718 # average WriteLineReq mshr miss latency 1108system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68757.359718 # average WriteLineReq mshr miss latency 1109system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency 1110system.iocache.demand_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency 1111system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency 1112system.iocache.overall_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency |
| 1112system.membus.snoop_filter.tot_requests 821141 # Total number of requests made to the snoop filter. | 1113system.membus.snoop_filter.tot_requests 821141 # Total number of requests made to the snoop filter. |
| 1113system.membus.snoop_filter.hit_single_requests 378246 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1114system.membus.snoop_filter.hit_multi_requests 407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1114system.membus.snoop_filter.hit_single_requests 378172 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1115system.membus.snoop_filter.hit_multi_requests 503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1115system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1116system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1117system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1116system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1117system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1118system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1118system.membus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states | 1119system.membus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states |
| 1119system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1120system.membus.trans_dist::ReadResp 292275 # Transaction distribution 1121system.membus.trans_dist::WriteReq 9652 # Transaction distribution 1122system.membus.trans_dist::WriteResp 9652 # Transaction distribution 1123system.membus.trans_dist::WritebackDirty 115765 # Transaction distribution 1124system.membus.trans_dist::CleanEvict 261592 # Transaction distribution 1125system.membus.trans_dist::UpgradeReq 136 # Transaction distribution 1126system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1127system.membus.trans_dist::ReadExReq 116686 # Transaction distribution 1128system.membus.trans_dist::ReadExResp 116686 # Transaction distribution 1129system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution 1130system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution | 1120system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1121system.membus.trans_dist::ReadResp 292275 # Transaction distribution 1122system.membus.trans_dist::WriteReq 9652 # Transaction distribution 1123system.membus.trans_dist::WriteResp 9652 # Transaction distribution 1124system.membus.trans_dist::WritebackDirty 115765 # Transaction distribution 1125system.membus.trans_dist::CleanEvict 261592 # Transaction distribution 1126system.membus.trans_dist::UpgradeReq 136 # Transaction distribution 1127system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1128system.membus.trans_dist::ReadExReq 116686 # Transaction distribution 1129system.membus.trans_dist::ReadExResp 116686 # Transaction distribution 1130system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution 1131system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| 1132system.membus.trans_dist::InvalidateResp 124 # Transaction distribution |
|
| 1131system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33164 # Packet count per connected master and slave (bytes) 1132system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139253 # Packet count per connected master and slave (bytes) 1133system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172417 # Packet count per connected master and slave (bytes) 1134system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1135system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) 1136system.membus.pkt_count::total 1255842 # Packet count per connected master and slave (bytes) 1137system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44580 # Cumulative packet size per connected master and slave (bytes) 1138system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30453760 # Cumulative packet size per connected master and slave (bytes) 1139system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30498340 # Cumulative packet size per connected master and slave (bytes) 1140system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1141system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 1142system.membus.pkt_size::total 33156068 # Cumulative packet size per connected master and slave (bytes) | 1133system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33164 # Packet count per connected master and slave (bytes) 1134system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139253 # Packet count per connected master and slave (bytes) 1135system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172417 # Packet count per connected master and slave (bytes) 1136system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1137system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) 1138system.membus.pkt_count::total 1255842 # Packet count per connected master and slave (bytes) 1139system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44580 # Cumulative packet size per connected master and slave (bytes) 1140system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30453760 # Cumulative packet size per connected master and slave (bytes) 1141system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30498340 # Cumulative packet size per connected master and slave (bytes) 1142system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1143system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) 1144system.membus.pkt_size::total 33156068 # Cumulative packet size per connected master and slave (bytes) |
| 1143system.membus.snoops 431 # Total snoops (count) | 1145system.membus.snoops 555 # Total snoops (count) |
| 1144system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) 1145system.membus.snoop_fanout::samples 460301 # Request fanout histogram | 1146system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) 1147system.membus.snoop_fanout::samples 460301 # Request fanout histogram |
| 1146system.membus.snoop_fanout::mean 0.001416 # Request fanout histogram 1147system.membus.snoop_fanout::stdev 0.037609 # Request fanout histogram | 1148system.membus.snoop_fanout::mean 0.001419 # Request fanout histogram 1149system.membus.snoop_fanout::stdev 0.037638 # Request fanout histogram |
| 1148system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1150system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1149system.membus.snoop_fanout::0 459649 99.86% 99.86% # Request fanout histogram 1150system.membus.snoop_fanout::1 652 0.14% 100.00% # Request fanout histogram | 1151system.membus.snoop_fanout::0 459648 99.86% 99.86% # Request fanout histogram 1152system.membus.snoop_fanout::1 653 0.14% 100.00% # Request fanout histogram |
| 1151system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1152system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1153system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1154system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1155system.membus.snoop_fanout::total 460301 # Request fanout histogram | 1153system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1154system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1155system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1156system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1157system.membus.snoop_fanout::total 460301 # Request fanout histogram |
| 1156system.membus.reqLayer0.occupancy 30124000 # Layer occupancy (ticks) | 1158system.membus.reqLayer0.occupancy 30123500 # Layer occupancy (ticks) |
| 1157system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1159system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1158system.membus.reqLayer1.occupancy 1287045337 # Layer occupancy (ticks) | 1160system.membus.reqLayer1.occupancy 1287046834 # Layer occupancy (ticks) |
| 1159system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1161system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1160system.membus.respLayer1.occupancy 2142987750 # Layer occupancy (ticks) | 1162system.membus.respLayer1.occupancy 2142988500 # Layer occupancy (ticks) |
| 1161system.membus.respLayer1.utilization 0.1 # Layer utilization (%) | 1163system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1162system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) | 1164system.membus.respLayer2.occupancy 1022522 # Layer occupancy (ticks) |
| 1163system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1165system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1164system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1165system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1166system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1167system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1168system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states | 1166system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1167system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1168system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1169system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1170system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states |
| 1169system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1170system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1171system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1172system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1173system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1174system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1175system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1176system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1192system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1193system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1194system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1195system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1196system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1197system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1198system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1199system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 1171system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1172system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1173system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1174system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1175system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1176system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1177system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1178system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1194system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1195system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1196system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1197system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1198system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1199system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1200system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1201system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 1200system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1201system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1202system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1203system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1204system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1205system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1206system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1207system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1208system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1209system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1210system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1211system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1212system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1213system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1214system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1215system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1216system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1217system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1218system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1219system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1220system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1221system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states 1222system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states | 1202system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1203system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1204system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1205system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1206system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1207system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1208system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1209system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1210system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1211system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1212system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1213system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1214system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1215system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1216system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1217system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1218system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1219system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1220system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1221system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1222system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1223system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states 1224system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states |
| 1223 1224---------- End Simulation Statistics ---------- | 1225 1226---------- End Simulation Statistics ---------- |