| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.941276 # Number of seconds simulated 4sim_ticks 1941275996000 # Number of ticks simulated 5final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.922415 # Number of seconds simulated 4sim_ticks 1922415409000 # Number of ticks simulated 5final_tick 1922415409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 780683 # Simulator instruction rate (inst/s) 8host_op_rate 780683 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 26974878622 # Simulator tick rate (ticks/s) 10host_mem_usage 326192 # Number of bytes of host memory used 11host_seconds 71.97 # Real time elapsed on the host 12sim_insts 56182685 # Number of instructions simulated 13sim_ops 56182685 # Number of ops (including micro ops) simulated | 7host_inst_rate 933149 # Simulator instruction rate (inst/s) 8host_op_rate 933149 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 31931169584 # Simulator tick rate (ticks/s) 10host_mem_usage 334404 # Number of bytes of host memory used 11host_seconds 60.21 # Real time elapsed on the host 12sim_insts 56180200 # Number of instructions simulated 13sim_ops 56180200 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 844608 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24856576 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 844800 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 844800 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7410752 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7410752 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 13200 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388383 # Number of read requests responded to by this memory | 20system.physmem.bytes_read::total 25702144 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 844608 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 844608 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7408512 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7408512 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 13197 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388384 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::total 401598 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 115793 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 115793 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 435178 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 12804213 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 13239886 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 435178 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 435178 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 3817464 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 3817464 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 3817464 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 435178 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 12804213 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 17057350 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 401598 # Number of read requests accepted 45system.physmem.writeReqs 115793 # Number of write requests accepted 46system.physmem.readBursts 401598 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 115793 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25694784 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7408704 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25702272 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 7410752 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue | 28system.physmem.num_reads::total 401596 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 115758 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 115758 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 439347 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 12929867 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 13369714 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 439347 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 439347 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 3853752 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 3853752 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 3853752 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 439347 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 12929867 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 17223466 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 401596 # Number of read requests accepted 45system.physmem.writeReqs 115758 # Number of write requests accepted 46system.physmem.readBursts 401596 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 115758 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 25695616 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue 50system.physmem.bytesWritten 7407424 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 25702144 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 7408512 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue |
| 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 54system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 56system.physmem.perBankRdBursts::0 25225 # Per bank write bursts 57system.physmem.perBankRdBursts::1 25628 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25541 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25494 # Per bank write bursts 60system.physmem.perBankRdBursts::4 25069 # Per bank write bursts 61system.physmem.perBankRdBursts::5 24955 # Per bank write bursts 62system.physmem.perBankRdBursts::6 24242 # Per bank write bursts 63system.physmem.perBankRdBursts::7 24604 # Per bank write bursts 64system.physmem.perBankRdBursts::8 25085 # Per bank write bursts 65system.physmem.perBankRdBursts::9 24651 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25269 # Per bank write bursts 67system.physmem.perBankRdBursts::11 24875 # Per bank write bursts 68system.physmem.perBankRdBursts::12 24508 # Per bank write bursts 69system.physmem.perBankRdBursts::13 25360 # Per bank write bursts 70system.physmem.perBankRdBursts::14 25616 # Per bank write bursts 71system.physmem.perBankRdBursts::15 25359 # Per bank write bursts 72system.physmem.perBankWrBursts::0 7625 # Per bank write bursts 73system.physmem.perBankWrBursts::1 7638 # Per bank write bursts 74system.physmem.perBankWrBursts::2 7842 # Per bank write bursts 75system.physmem.perBankWrBursts::3 7532 # Per bank write bursts 76system.physmem.perBankWrBursts::4 7224 # Per bank write bursts 77system.physmem.perBankWrBursts::5 6973 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6356 # Per bank write bursts 79system.physmem.perBankWrBursts::7 6427 # Per bank write bursts 80system.physmem.perBankWrBursts::8 7248 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6409 # Per bank write bursts 82system.physmem.perBankWrBursts::10 7117 # Per bank write bursts | 56system.physmem.perBankRdBursts::0 25227 # Per bank write bursts 57system.physmem.perBankRdBursts::1 25633 # Per bank write bursts 58system.physmem.perBankRdBursts::2 25570 # Per bank write bursts 59system.physmem.perBankRdBursts::3 25510 # Per bank write bursts 60system.physmem.perBankRdBursts::4 24963 # Per bank write bursts 61system.physmem.perBankRdBursts::5 24975 # Per bank write bursts 62system.physmem.perBankRdBursts::6 24200 # Per bank write bursts 63system.physmem.perBankRdBursts::7 24494 # Per bank write bursts 64system.physmem.perBankRdBursts::8 25179 # Per bank write bursts 65system.physmem.perBankRdBursts::9 24767 # Per bank write bursts 66system.physmem.perBankRdBursts::10 25265 # Per bank write bursts 67system.physmem.perBankRdBursts::11 24877 # Per bank write bursts 68system.physmem.perBankRdBursts::12 24504 # Per bank write bursts 69system.physmem.perBankRdBursts::13 25368 # Per bank write bursts 70system.physmem.perBankRdBursts::14 25615 # Per bank write bursts 71system.physmem.perBankRdBursts::15 25347 # Per bank write bursts 72system.physmem.perBankWrBursts::0 7623 # Per bank write bursts 73system.physmem.perBankWrBursts::1 7643 # Per bank write bursts 74system.physmem.perBankWrBursts::2 7871 # Per bank write bursts 75system.physmem.perBankWrBursts::3 7543 # Per bank write bursts 76system.physmem.perBankWrBursts::4 7113 # Per bank write bursts 77system.physmem.perBankWrBursts::5 6990 # Per bank write bursts 78system.physmem.perBankWrBursts::6 6317 # Per bank write bursts 79system.physmem.perBankWrBursts::7 6320 # Per bank write bursts 80system.physmem.perBankWrBursts::8 7316 # Per bank write bursts 81system.physmem.perBankWrBursts::9 6519 # Per bank write bursts 82system.physmem.perBankWrBursts::10 7114 # Per bank write bursts |
| 83system.physmem.perBankWrBursts::11 6905 # Per bank write bursts | 83system.physmem.perBankWrBursts::11 6905 # Per bank write bursts |
| 84system.physmem.perBankWrBursts::12 7093 # Per bank write bursts 85system.physmem.perBankWrBursts::13 7822 # Per bank write bursts 86system.physmem.perBankWrBursts::14 7863 # Per bank write bursts 87system.physmem.perBankWrBursts::15 7687 # Per bank write bursts | 84system.physmem.perBankWrBursts::12 7090 # Per bank write bursts 85system.physmem.perBankWrBursts::13 7827 # Per bank write bursts 86system.physmem.perBankWrBursts::14 7864 # Per bank write bursts 87system.physmem.perBankWrBursts::15 7686 # Per bank write bursts |
| 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 89system.physmem.numWrRetry 8 # Number of times write queue was full causing retry 90system.physmem.totGap 1941264122500 # Total gap between requests | 89system.physmem.numWrRetry 12 # Number of times write queue was full causing retry 90system.physmem.totGap 1922403535500 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 401598 # Read request sizes (log2) | 97system.physmem.readPktSize::6 401596 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 115793 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 401467 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 115758 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 401480 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see --- 30 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see --- 30 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 1807 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 3254 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 7109 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::15 1798 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 3043 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 5632 # What write queue length does an incoming req see |
| 155system.physmem.wrQLenPdf::18 5708 # What write queue length does an incoming req see | 155system.physmem.wrQLenPdf::18 5708 # What write queue length does an incoming req see |
| 156system.physmem.wrQLenPdf::19 6721 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 5891 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 5694 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 6225 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6741 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 6246 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 8116 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 8397 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 7082 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 7394 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 6721 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 6957 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 5808 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 5411 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 229 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 172 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 137 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 104 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 108 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 175 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 221 # What write queue length does an incoming req see | 156system.physmem.wrQLenPdf::19 6464 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 6441 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 7460 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 8593 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 6948 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 7656 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 8317 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 7511 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 6845 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 6921 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 6031 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 5597 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 5475 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 5364 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 235 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 176 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 158 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see |
| 182system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see | 182system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see |
| 183system.physmem.wrQLenPdf::46 216 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 262 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 260 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 158 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 147 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 179 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 91 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 111 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 96 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 58 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 64912 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 509.974858 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 310.437414 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 406.111966 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 15297 23.57% 23.57% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 11509 17.73% 41.30% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 4968 7.65% 48.95% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3096 4.77% 53.72% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 2466 3.80% 57.52% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 4203 6.47% 63.99% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1427 2.20% 66.19% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 2060 3.17% 69.36% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 19886 30.64% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 64912 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5094 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 78.810561 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2956.623385 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5091 99.94% 99.94% # Reads before turning the bus around for writes | 183system.physmem.wrQLenPdf::46 133 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 149 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 161 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 193 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 133 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 100 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 131 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 139 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 63 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 71 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 44 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 63567 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 520.758255 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 315.623593 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 415.134860 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 14658 23.06% 23.06% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 11541 18.16% 41.21% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 4861 7.65% 48.86% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 3298 5.19% 54.05% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 2285 3.59% 57.64% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 1919 3.02% 60.66% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 1565 2.46% 63.13% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 1066 1.68% 64.80% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 22374 35.20% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 63567 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 5112 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 78.539124 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2951.473216 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 5109 99.94% 99.94% # Reads before turning the bus around for writes |
| 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 219system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 222system.physmem.rdPerTurnAround::total 5094 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5094 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.724971 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 19.335038 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 21.028996 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-23 4499 88.32% 88.32% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-31 29 0.57% 88.89% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-39 21 0.41% 89.30% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::40-47 41 0.80% 90.11% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-55 209 4.10% 94.21% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-63 11 0.22% 94.42% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-71 11 0.22% 94.64% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-79 30 0.59% 95.23% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-87 184 3.61% 98.84% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::88-95 6 0.12% 98.96% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::96-103 5 0.10% 99.06% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::104-111 4 0.08% 99.14% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::120-127 1 0.02% 99.16% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::128-135 8 0.16% 99.31% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::136-143 5 0.10% 99.41% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::160-167 4 0.08% 99.51% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::168-175 6 0.12% 99.63% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::176-183 5 0.10% 99.73% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::184-191 1 0.02% 99.74% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::192-199 2 0.04% 99.78% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::208-215 6 0.12% 99.90% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::240-247 1 0.02% 99.92% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::256-263 4 0.08% 100.00% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::total 5094 # Writes before turning the bus around for reads 252system.physmem.totQLat 2720435750 # Total ticks spent queuing 253system.physmem.totMemAccLat 10248204500 # Total ticks spent from burst creation until serviced by the DRAM 254system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers 255system.physmem.avgQLat 6776.00 # Average queueing delay per DRAM burst | 222system.physmem.rdPerTurnAround::total 5112 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 5112 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 22.641041 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 19.167929 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 21.759533 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16-19 4475 87.54% 87.54% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20-23 34 0.67% 88.20% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::24-27 11 0.22% 88.42% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::28-31 14 0.27% 88.69% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::32-35 223 4.36% 93.06% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::36-39 16 0.31% 93.37% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::40-43 14 0.27% 93.64% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::44-47 12 0.23% 93.88% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::48-51 3 0.06% 93.94% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::52-55 7 0.14% 94.07% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::56-59 5 0.10% 94.17% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::60-63 2 0.04% 94.21% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::64-67 12 0.23% 94.44% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::68-71 2 0.04% 94.48% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::72-75 3 0.06% 94.54% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::76-79 1 0.02% 94.56% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::80-83 33 0.65% 95.21% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::84-87 3 0.06% 95.27% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::88-91 18 0.35% 95.62% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::92-95 1 0.02% 95.64% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::96-99 174 3.40% 99.04% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::100-103 4 0.08% 99.12% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::104-107 1 0.02% 99.14% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::112-115 4 0.08% 99.22% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::116-119 2 0.04% 99.26% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::128-131 2 0.04% 99.33% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::136-139 1 0.02% 99.35% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::140-143 1 0.02% 99.37% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::148-151 1 0.02% 99.39% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::156-159 1 0.02% 99.43% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::160-163 4 0.08% 99.51% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::164-167 1 0.02% 99.53% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::172-175 9 0.18% 99.71% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::176-179 2 0.04% 99.75% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::180-183 2 0.04% 99.78% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::188-191 3 0.06% 99.84% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::196-199 1 0.02% 99.86% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::208-211 1 0.02% 99.88% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::224-227 5 0.10% 99.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::total 5112 # Writes before turning the bus around for reads 270system.physmem.totQLat 2082530750 # Total ticks spent queuing 271system.physmem.totMemAccLat 9610543250 # Total ticks spent from burst creation until serviced by the DRAM 272system.physmem.totBusLat 2007470000 # Total ticks spent in databus transfers 273system.physmem.avgQLat 5186.95 # Average queueing delay per DRAM burst |
| 256system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 257system.physmem.avgMemAccLat 25526.00 # Average memory access latency per DRAM burst 258system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s 259system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s 260system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s 261system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s | 275system.physmem.avgMemAccLat 23936.95 # Average memory access latency per DRAM burst 276system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s 277system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s 278system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s 279system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s |
| 262system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 263system.physmem.busUtil 0.13 # Data bus utilization in percentage 264system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 265system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 266system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 281system.physmem.busUtil 0.13 # Data bus utilization in percentage 282system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 283system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 284system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 267system.physmem.avgWrQLen 22.10 # Average write queue length when enqueuing 268system.physmem.readRowHits 358846 # Number of row buffer hits during reads 269system.physmem.writeRowHits 93484 # Number of row buffer hits during writes 270system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads 271system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes 272system.physmem.avgGap 3752025.30 # Average gap between requests 273system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined 274system.physmem_0.actEnergy 240264360 # Energy for activate commands per rank (pJ) 275system.physmem_0.preEnergy 131096625 # Energy for precharge commands per rank (pJ) 276system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) 277system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) 278system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) 279system.physmem_0.actBackEnergy 71567881875 # Energy for active background per rank (pJ) 280system.physmem_0.preBackEnergy 1101986685750 # Energy for precharge background per rank (pJ) 281system.physmem_0.totalEnergy 1302659886930 # Total energy per rank (pJ) 282system.physmem_0.averagePower 671.032849 # Core power per rank (mW) 283system.physmem_0.memoryStateTime::IDLE 1832974732500 # Time in different power states 284system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states | 285system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing 286system.physmem.readRowHits 359878 # Number of row buffer hits during reads 287system.physmem.writeRowHits 93790 # Number of row buffer hits during writes 288system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads 289system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes 290system.physmem.avgGap 3715837.77 # Average gap between requests 291system.physmem.pageHitRate 87.71 # Row buffer hit rate, read and write combined 292system.physmem_0.actEnergy 235297440 # Energy for activate commands per rank (pJ) 293system.physmem_0.preEnergy 128386500 # Energy for precharge commands per rank (pJ) 294system.physmem_0.readEnergy 1564461600 # Energy for read commands per rank (pJ) 295system.physmem_0.writeEnergy 372081600 # Energy for write commands per rank (pJ) 296system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) 297system.physmem_0.actBackEnergy 64706229855 # Energy for active background per rank (pJ) 298system.physmem_0.preBackEnergy 1096686028500 # Energy for precharge background per rank (pJ) 299system.physmem_0.totalEnergy 1289254932375 # Total energy per rank (pJ) 300system.physmem_0.averagePower 670.645215 # Core power per rank (mW) 301system.physmem_0.memoryStateTime::IDLE 1824198256500 # Time in different power states 302system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states |
| 285system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 303system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 286system.physmem_0.memoryStateTime::ACT 43477703750 # Time in different power states | 304system.physmem_0.memoryStateTime::ACT 34018076000 # Time in different power states |
| 287system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 305system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 288system.physmem_1.actEnergy 250470360 # Energy for activate commands per rank (pJ) 289system.physmem_1.preEnergy 136665375 # Energy for precharge commands per rank (pJ) 290system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) 291system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) 292system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) 293system.physmem_1.actBackEnergy 72629135235 # Energy for active background per rank (pJ) 294system.physmem_1.preBackEnergy 1101055761750 # Energy for precharge background per rank (pJ) 295system.physmem_1.totalEnergy 1302809133000 # Total energy per rank (pJ) 296system.physmem_1.averagePower 671.109730 # Core power per rank (mW) 297system.physmem_1.memoryStateTime::IDLE 1831423337250 # Time in different power states 298system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states | 306system.physmem_1.actEnergy 245269080 # Energy for activate commands per rank (pJ) 307system.physmem_1.preEnergy 133827375 # Energy for precharge commands per rank (pJ) 308system.physmem_1.readEnergy 1567191600 # Energy for read commands per rank (pJ) 309system.physmem_1.writeEnergy 377920080 # Energy for write commands per rank (pJ) 310system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) 311system.physmem_1.actBackEnergy 65408106195 # Energy for active background per rank (pJ) 312system.physmem_1.preBackEnergy 1096070355750 # Energy for precharge background per rank (pJ) 313system.physmem_1.totalEnergy 1289365116960 # Total energy per rank (pJ) 314system.physmem_1.averagePower 670.702526 # Core power per rank (mW) 315system.physmem_1.memoryStateTime::IDLE 1823171088500 # Time in different power states 316system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states |
| 299system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 317system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 300system.physmem_1.memoryStateTime::ACT 45029099000 # Time in different power states | 318system.physmem_1.memoryStateTime::ACT 35045257750 # Time in different power states |
| 301system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 319system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 302system.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 303system.bridge.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states | 320system.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 321system.bridge.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states |
| 304system.cpu_clk_domain.clock 500 # Clock period in ticks 305system.cpu.dtb.fetch_hits 0 # ITB hits 306system.cpu.dtb.fetch_misses 0 # ITB misses 307system.cpu.dtb.fetch_acv 0 # ITB acv 308system.cpu.dtb.fetch_accesses 0 # ITB accesses | 322system.cpu_clk_domain.clock 500 # Clock period in ticks 323system.cpu.dtb.fetch_hits 0 # ITB hits 324system.cpu.dtb.fetch_misses 0 # ITB misses 325system.cpu.dtb.fetch_acv 0 # ITB acv 326system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 309system.cpu.dtb.read_hits 9064642 # DTB read hits 310system.cpu.dtb.read_misses 10324 # DTB read misses | 327system.cpu.dtb.read_hits 9064160 # DTB read hits 328system.cpu.dtb.read_misses 10312 # DTB read misses |
| 311system.cpu.dtb.read_acv 210 # DTB read access violations | 329system.cpu.dtb.read_acv 210 # DTB read access violations |
| 312system.cpu.dtb.read_accesses 728853 # DTB read accesses 313system.cpu.dtb.write_hits 6356200 # DTB write hits 314system.cpu.dtb.write_misses 1142 # DTB write misses | 330system.cpu.dtb.read_accesses 728817 # DTB read accesses 331system.cpu.dtb.write_hits 6356116 # DTB write hits 332system.cpu.dtb.write_misses 1140 # DTB write misses |
| 315system.cpu.dtb.write_acv 157 # DTB write access violations | 333system.cpu.dtb.write_acv 157 # DTB write access violations |
| 316system.cpu.dtb.write_accesses 291931 # DTB write accesses 317system.cpu.dtb.data_hits 15420842 # DTB hits 318system.cpu.dtb.data_misses 11466 # DTB misses | 334system.cpu.dtb.write_accesses 291929 # DTB write accesses 335system.cpu.dtb.data_hits 15420276 # DTB hits 336system.cpu.dtb.data_misses 11452 # DTB misses |
| 319system.cpu.dtb.data_acv 367 # DTB access violations | 337system.cpu.dtb.data_acv 367 # DTB access violations |
| 320system.cpu.dtb.data_accesses 1020784 # DTB accesses 321system.cpu.itb.fetch_hits 4975134 # ITB hits 322system.cpu.itb.fetch_misses 5010 # ITB misses | 338system.cpu.dtb.data_accesses 1020746 # DTB accesses 339system.cpu.itb.fetch_hits 4973965 # ITB hits 340system.cpu.itb.fetch_misses 4997 # ITB misses |
| 323system.cpu.itb.fetch_acv 184 # ITB acv | 341system.cpu.itb.fetch_acv 184 # ITB acv |
| 324system.cpu.itb.fetch_accesses 4980144 # ITB accesses | 342system.cpu.itb.fetch_accesses 4978962 # ITB accesses |
| 325system.cpu.itb.read_hits 0 # DTB read hits 326system.cpu.itb.read_misses 0 # DTB read misses 327system.cpu.itb.read_acv 0 # DTB read access violations 328system.cpu.itb.read_accesses 0 # DTB read accesses 329system.cpu.itb.write_hits 0 # DTB write hits 330system.cpu.itb.write_misses 0 # DTB write misses 331system.cpu.itb.write_acv 0 # DTB write access violations 332system.cpu.itb.write_accesses 0 # DTB write accesses 333system.cpu.itb.data_hits 0 # DTB hits 334system.cpu.itb.data_misses 0 # DTB misses 335system.cpu.itb.data_acv 0 # DTB access violations 336system.cpu.itb.data_accesses 0 # DTB accesses | 343system.cpu.itb.read_hits 0 # DTB read hits 344system.cpu.itb.read_misses 0 # DTB read misses 345system.cpu.itb.read_acv 0 # DTB read access violations 346system.cpu.itb.read_accesses 0 # DTB read accesses 347system.cpu.itb.write_hits 0 # DTB write hits 348system.cpu.itb.write_misses 0 # DTB write misses 349system.cpu.itb.write_acv 0 # DTB write access violations 350system.cpu.itb.write_accesses 0 # DTB write accesses 351system.cpu.itb.data_hits 0 # DTB hits 352system.cpu.itb.data_misses 0 # DTB misses 353system.cpu.itb.data_acv 0 # DTB access violations 354system.cpu.itb.data_accesses 0 # DTB accesses |
| 337system.cpu.numPwrStateTransitions 12750 # Number of power state transitions 338system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state 339system.cpu.pwrStateClkGateDist::mean 281084850.117804 # Distribution of time spent in the clock gated state 340system.cpu.pwrStateClkGateDist::stdev 439246512.061173 # Distribution of time spent in the clock gated state | 355system.cpu.numPwrStateTransitions 12754 # Number of power state transitions 356system.cpu.pwrStateClkGateDist::samples 6377 # Distribution of time spent in the clock gated state 357system.cpu.pwrStateClkGateDist::mean 281224726.046887 # Distribution of time spent in the clock gated state 358system.cpu.pwrStateClkGateDist::stdev 439034613.415905 # Distribution of time spent in the clock gated state |
| 341system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state | 359system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state |
| 342system.cpu.pwrStateClkGateDist::1000-5e+10 6374 99.98% 100.00% # Distribution of time spent in the clock gated state | 360system.cpu.pwrStateClkGateDist::1000-5e+10 6376 99.98% 100.00% # Distribution of time spent in the clock gated state |
| 343system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 344system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state | 361system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 362system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state |
| 345system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state 346system.cpu.pwrStateResidencyTicks::ON 149360076499 # Cumulative time (in ticks) in various power states 347system.cpu.pwrStateResidencyTicks::CLK_GATED 1791915919501 # Cumulative time (in ticks) in various power states 348system.cpu.numCycles 3882551992 # number of cpu cycles simulated | 363system.cpu.pwrStateClkGateDist::total 6377 # Distribution of time spent in the clock gated state 364system.cpu.pwrStateResidencyTicks::ON 129045330999 # Cumulative time (in ticks) in various power states 365system.cpu.pwrStateResidencyTicks::CLK_GATED 1793370078001 # Cumulative time (in ticks) in various power states 366system.cpu.numCycles 3844830818 # number of cpu cycles simulated |
| 349system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 350system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 351system.cpu.kern.inst.arm 0 # number of arm instructions executed | 367system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 368system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 369system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 352system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed 353system.cpu.kern.inst.hwrei 212050 # number of hwrei instructions executed 354system.cpu.kern.ipl_count::0 74912 40.88% 40.88% # number of times we switched to this ipl | 370system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed 371system.cpu.kern.inst.hwrei 211971 # number of hwrei instructions executed 372system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl |
| 355system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl | 373system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl |
| 356system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl 357system.cpu.kern.ipl_count::31 106253 57.99% 100.00% # number of times we switched to this ipl 358system.cpu.kern.ipl_count::total 183231 # number of times we switched to this ipl 359system.cpu.kern.ipl_good::0 73545 49.31% 49.31% # number of times we switched to this ipl from a different ipl | 374system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl 375system.cpu.kern.ipl_count::31 106221 57.99% 100.00% # number of times we switched to this ipl 376system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl 377system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl |
| 360system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl | 378system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl |
| 361system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl 362system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl 363system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl 364system.cpu.kern.ipl_ticks::0 1860509959000 95.84% 95.84% # number of cycles we spent at this ipl 365system.cpu.kern.ipl_ticks::21 94068000 0.00% 95.84% # number of cycles we spent at this ipl 366system.cpu.kern.ipl_ticks::22 770529000 0.04% 95.88% # number of cycles we spent at this ipl 367system.cpu.kern.ipl_ticks::31 79900706000 4.12% 100.00% # number of cycles we spent at this ipl 368system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl 369system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl | 379system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl 380system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl 381system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl 382system.cpu.kern.ipl_ticks::0 1857710123500 96.63% 96.63% # number of cycles we spent at this ipl 383system.cpu.kern.ipl_ticks::21 93945500 0.00% 96.64% # number of cycles we spent at this ipl 384system.cpu.kern.ipl_ticks::22 769790000 0.04% 96.68% # number of cycles we spent at this ipl 385system.cpu.kern.ipl_ticks::31 63840816000 3.32% 100.00% # number of cycles we spent at this ipl 386system.cpu.kern.ipl_ticks::total 1922414675000 # number of cycles we spent at this ipl 387system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl |
| 370system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 371system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 388system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 389system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 372system.cpu.kern.ipl_used::31 0.692169 # fraction of swpipl calls that actually changed the ipl 373system.cpu.kern.ipl_used::total 0.814033 # fraction of swpipl calls that actually changed the ipl | 390system.cpu.kern.ipl_used::31 0.692255 # fraction of swpipl calls that actually changed the ipl 391system.cpu.kern.ipl_used::total 0.814088 # fraction of swpipl calls that actually changed the ipl |
| 374system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 375system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 376system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 377system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 378system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 379system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 380system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 381system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 401system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 402system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 403system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 404system.cpu.kern.syscall::total 326 # number of syscalls executed 405system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 406system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 407system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 408system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 392system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 393system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 394system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 395system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 396system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 397system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 398system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 399system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 419system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 420system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 421system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 422system.cpu.kern.syscall::total 326 # number of syscalls executed 423system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 424system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 425system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 426system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 409system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed | 427system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed |
| 410system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 411system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 428system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 429system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 412system.cpu.kern.callpal::swpipl 176004 91.22% 93.41% # number of callpals executed 413system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed | 430system.cpu.kern.callpal::swpipl 175962 91.22% 93.41% # number of callpals executed 431system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed |
| 414system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 415system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 416system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed 417system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed | 432system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 433system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 434system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed 435system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed |
| 418system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed | 436system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed |
| 419system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 420system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 437system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 438system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 421system.cpu.kern.callpal::total 192955 # number of callpals executed 422system.cpu.kern.mode_switch::kernel 5908 # number of protection mode switches 423system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 424system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 425system.cpu.kern.mode_good::kernel 1909 426system.cpu.kern.mode_good::user 1739 427system.cpu.kern.mode_good::idle 170 428system.cpu.kern.mode_switch_good::kernel 0.323121 # fraction of useful protection mode switches | 439system.cpu.kern.callpal::total 192906 # number of callpals executed 440system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches 441system.cpu.kern.mode_switch::user 1741 # number of protection mode switches 442system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches 443system.cpu.kern.mode_good::kernel 1910 444system.cpu.kern.mode_good::user 1741 445system.cpu.kern.mode_good::idle 169 446system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches |
| 429system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 447system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 430system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches 431system.cpu.kern.mode_switch_good::total 0.391952 # fraction of useful protection mode switches 432system.cpu.kern.mode_ticks::kernel 48613391500 2.50% 2.50% # number of ticks spent at the given mode 433system.cpu.kern.mode_ticks::user 5603093000 0.29% 2.79% # number of ticks spent at the given mode 434system.cpu.kern.mode_ticks::idle 1887058775500 97.21% 100.00% # number of ticks spent at the given mode 435system.cpu.kern.swap_context 4177 # number of times the context was actually changed 436system.cpu.committedInsts 56182685 # Number of instructions committed 437system.cpu.committedOps 56182685 # Number of ops (including micro ops) committed 438system.cpu.num_int_alu_accesses 52054580 # Number of integer alu accesses 439system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses 440system.cpu.num_func_calls 1483390 # number of times a function call or return occured 441system.cpu.num_conditional_control_insts 6468674 # number of instructions that are conditional controls 442system.cpu.num_int_insts 52054580 # number of integer instructions 443system.cpu.num_fp_insts 324393 # number of float instructions 444system.cpu.num_int_register_reads 71322431 # number of times the integer registers were read 445system.cpu.num_int_register_writes 38520860 # number of times the integer registers were written 446system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read 447system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written 448system.cpu.num_mem_refs 15473452 # number of memory refs 449system.cpu.num_load_insts 9101488 # Number of load instructions 450system.cpu.num_store_insts 6371964 # Number of store instructions 451system.cpu.num_idle_cycles 3583831839.000154 # Number of idle cycles 452system.cpu.num_busy_cycles 298720152.999846 # Number of busy cycles 453system.cpu.not_idle_fraction 0.076939 # Percentage of non-idle cycles 454system.cpu.idle_fraction 0.923061 # Percentage of idle cycles 455system.cpu.Branches 8422715 # Number of branches fetched 456system.cpu.op_class::No_OpClass 3200634 5.70% 5.70% # Class of executed instruction 457system.cpu.op_class::IntAlu 36230987 64.47% 70.17% # Class of executed instruction 458system.cpu.op_class::IntMult 61043 0.11% 70.28% # Class of executed instruction | 448system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches 449system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches 450system.cpu.kern.mode_ticks::kernel 46528757000 2.42% 2.42% # number of ticks spent at the given mode 451system.cpu.kern.mode_ticks::user 5244548000 0.27% 2.69% # number of ticks spent at the given mode 452system.cpu.kern.mode_ticks::idle 1870641368000 97.31% 100.00% # number of ticks spent at the given mode 453system.cpu.kern.swap_context 4175 # number of times the context was actually changed 454system.cpu.committedInsts 56180200 # Number of instructions committed 455system.cpu.committedOps 56180200 # Number of ops (including micro ops) committed 456system.cpu.num_int_alu_accesses 52052716 # Number of integer alu accesses 457system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses 458system.cpu.num_func_calls 1483318 # number of times a function call or return occured 459system.cpu.num_conditional_control_insts 6468478 # number of instructions that are conditional controls 460system.cpu.num_int_insts 52052716 # number of integer instructions 461system.cpu.num_fp_insts 324259 # number of float instructions 462system.cpu.num_int_register_reads 71320481 # number of times the integer registers were read 463system.cpu.num_int_register_writes 38519316 # number of times the integer registers were written 464system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read 465system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written 466system.cpu.num_mem_refs 15472847 # number of memory refs 467system.cpu.num_load_insts 9100978 # Number of load instructions 468system.cpu.num_store_insts 6371869 # Number of store instructions 469system.cpu.num_idle_cycles 3586740156.000134 # Number of idle cycles 470system.cpu.num_busy_cycles 258090661.999866 # Number of busy cycles 471system.cpu.not_idle_fraction 0.067127 # Percentage of non-idle cycles 472system.cpu.idle_fraction 0.932873 # Percentage of idle cycles 473system.cpu.Branches 8422318 # Number of branches fetched 474system.cpu.op_class::No_OpClass 3200272 5.70% 5.70% # Class of executed instruction 475system.cpu.op_class::IntAlu 36230015 64.48% 70.17% # Class of executed instruction 476system.cpu.op_class::IntMult 60990 0.11% 70.28% # Class of executed instruction |
| 459system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction | 477system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction |
| 460system.cpu.op_class::FloatAdd 38085 0.07% 70.35% # Class of executed instruction | 478system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction |
| 461system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction 462system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction 463system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction 464system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction 465system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction 466system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction 467system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction 468system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction --- 9 unchanged lines hidden (view full) --- 478system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction 479system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction 480system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction 481system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction 482system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction 483system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction 484system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction 485system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction | 479system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction 480system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction 481system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction 482system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction 483system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction 484system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction 485system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction 486system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction --- 9 unchanged lines hidden (view full) --- 496system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction 497system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction 498system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction 499system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction 500system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction 501system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction 502system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction 503system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction |
| 486system.cpu.op_class::MemRead 9328618 16.60% 86.95% # Class of executed instruction 487system.cpu.op_class::MemWrite 6378045 11.35% 98.30% # Class of executed instruction 488system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction | 504system.cpu.op_class::MemRead 9328048 16.60% 86.95% # Class of executed instruction 505system.cpu.op_class::MemWrite 6377943 11.35% 98.30% # Class of executed instruction 506system.cpu.op_class::IprAccess 953034 1.70% 100.00% # Class of executed instruction |
| 489system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 507system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 490system.cpu.op_class::total 56194518 # Class of executed instruction 491system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 492system.cpu.dcache.tags.replacements 1390398 # number of replacements 493system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use 494system.cpu.dcache.tags.total_refs 14048965 # Total number of references to valid blocks. 495system.cpu.dcache.tags.sampled_refs 1390910 # Sample count of references to valid blocks. 496system.cpu.dcache.tags.avg_refs 10.100556 # Average number of references to valid blocks. 497system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. 498system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor 499system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy 500system.cpu.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy | 508system.cpu.op_class::total 56192019 # Class of executed instruction 509system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 510system.cpu.dcache.tags.replacements 1390892 # number of replacements 511system.cpu.dcache.tags.tagsinuse 511.977567 # Cycle average of tags in use 512system.cpu.dcache.tags.total_refs 14047886 # Total number of references to valid blocks. 513system.cpu.dcache.tags.sampled_refs 1391404 # Sample count of references to valid blocks. 514system.cpu.dcache.tags.avg_refs 10.096195 # Average number of references to valid blocks. 515system.cpu.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. 516system.cpu.dcache.tags.occ_blocks::cpu.data 511.977567 # Average occupied blocks per requestor 517system.cpu.dcache.tags.occ_percent::cpu.data 0.999956 # Average percentage of cache occupancy 518system.cpu.dcache.tags.occ_percent::total 0.999956 # Average percentage of cache occupancy |
| 501system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 502system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id | 519system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 520system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id |
| 503system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 504system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id | 521system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 522system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id |
| 505system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 523system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 506system.cpu.dcache.tags.tag_accesses 63150415 # Number of tag accesses 507system.cpu.dcache.tags.data_accesses 63150415 # Number of data accesses 508system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 509system.cpu.dcache.ReadReq_hits::cpu.data 7814386 # number of ReadReq hits 510system.cpu.dcache.ReadReq_hits::total 7814386 # number of ReadReq hits 511system.cpu.dcache.WriteReq_hits::cpu.data 5852266 # number of WriteReq hits 512system.cpu.dcache.WriteReq_hits::total 5852266 # number of WriteReq hits 513system.cpu.dcache.LoadLockedReq_hits::cpu.data 183036 # number of LoadLockedReq hits 514system.cpu.dcache.LoadLockedReq_hits::total 183036 # number of LoadLockedReq hits 515system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits 516system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits 517system.cpu.dcache.demand_hits::cpu.data 13666652 # number of demand (read+write) hits 518system.cpu.dcache.demand_hits::total 13666652 # number of demand (read+write) hits 519system.cpu.dcache.overall_hits::cpu.data 13666652 # number of overall hits 520system.cpu.dcache.overall_hits::total 13666652 # number of overall hits 521system.cpu.dcache.ReadReq_misses::cpu.data 1069356 # number of ReadReq misses 522system.cpu.dcache.ReadReq_misses::total 1069356 # number of ReadReq misses 523system.cpu.dcache.WriteReq_misses::cpu.data 304326 # number of WriteReq misses 524system.cpu.dcache.WriteReq_misses::total 304326 # number of WriteReq misses 525system.cpu.dcache.LoadLockedReq_misses::cpu.data 17246 # number of LoadLockedReq misses 526system.cpu.dcache.LoadLockedReq_misses::total 17246 # number of LoadLockedReq misses 527system.cpu.dcache.demand_misses::cpu.data 1373682 # number of demand (read+write) misses 528system.cpu.dcache.demand_misses::total 1373682 # number of demand (read+write) misses 529system.cpu.dcache.overall_misses::cpu.data 1373682 # number of overall misses 530system.cpu.dcache.overall_misses::total 1373682 # number of overall misses 531system.cpu.dcache.ReadReq_miss_latency::cpu.data 44772600000 # number of ReadReq miss cycles 532system.cpu.dcache.ReadReq_miss_latency::total 44772600000 # number of ReadReq miss cycles 533system.cpu.dcache.WriteReq_miss_latency::cpu.data 17635207000 # number of WriteReq miss cycles 534system.cpu.dcache.WriteReq_miss_latency::total 17635207000 # number of WriteReq miss cycles 535system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232797500 # number of LoadLockedReq miss cycles 536system.cpu.dcache.LoadLockedReq_miss_latency::total 232797500 # number of LoadLockedReq miss cycles 537system.cpu.dcache.demand_miss_latency::cpu.data 62407807000 # number of demand (read+write) miss cycles 538system.cpu.dcache.demand_miss_latency::total 62407807000 # number of demand (read+write) miss cycles 539system.cpu.dcache.overall_miss_latency::cpu.data 62407807000 # number of overall miss cycles 540system.cpu.dcache.overall_miss_latency::total 62407807000 # number of overall miss cycles 541system.cpu.dcache.ReadReq_accesses::cpu.data 8883742 # number of ReadReq accesses(hits+misses) 542system.cpu.dcache.ReadReq_accesses::total 8883742 # number of ReadReq accesses(hits+misses) 543system.cpu.dcache.WriteReq_accesses::cpu.data 6156592 # number of WriteReq accesses(hits+misses) 544system.cpu.dcache.WriteReq_accesses::total 6156592 # number of WriteReq accesses(hits+misses) 545system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200282 # number of LoadLockedReq accesses(hits+misses) 546system.cpu.dcache.LoadLockedReq_accesses::total 200282 # number of LoadLockedReq accesses(hits+misses) 547system.cpu.dcache.StoreCondReq_accesses::cpu.data 199260 # number of StoreCondReq accesses(hits+misses) 548system.cpu.dcache.StoreCondReq_accesses::total 199260 # number of StoreCondReq accesses(hits+misses) 549system.cpu.dcache.demand_accesses::cpu.data 15040334 # number of demand (read+write) accesses 550system.cpu.dcache.demand_accesses::total 15040334 # number of demand (read+write) accesses 551system.cpu.dcache.overall_accesses::cpu.data 15040334 # number of overall (read+write) accesses 552system.cpu.dcache.overall_accesses::total 15040334 # number of overall (read+write) accesses 553system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120372 # miss rate for ReadReq accesses 554system.cpu.dcache.ReadReq_miss_rate::total 0.120372 # miss rate for ReadReq accesses 555system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049431 # miss rate for WriteReq accesses 556system.cpu.dcache.WriteReq_miss_rate::total 0.049431 # miss rate for WriteReq accesses 557system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086109 # miss rate for LoadLockedReq accesses 558system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086109 # miss rate for LoadLockedReq accesses 559system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses 560system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses 561system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses 562system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses 563system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41868.750912 # average ReadReq miss latency 564system.cpu.dcache.ReadReq_avg_miss_latency::total 41868.750912 # average ReadReq miss latency 565system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57948.407300 # average WriteReq miss latency 566system.cpu.dcache.WriteReq_avg_miss_latency::total 57948.407300 # average WriteReq miss latency 567system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.637365 # average LoadLockedReq miss latency 568system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.637365 # average LoadLockedReq miss latency 569system.cpu.dcache.demand_avg_miss_latency::cpu.data 45431.043720 # average overall miss latency 570system.cpu.dcache.demand_avg_miss_latency::total 45431.043720 # average overall miss latency 571system.cpu.dcache.overall_avg_miss_latency::cpu.data 45431.043720 # average overall miss latency 572system.cpu.dcache.overall_avg_miss_latency::total 45431.043720 # average overall miss latency | 524system.cpu.dcache.tags.tag_accesses 63148569 # Number of tag accesses 525system.cpu.dcache.tags.data_accesses 63148569 # Number of data accesses 526system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 527system.cpu.dcache.ReadReq_hits::cpu.data 7813455 # number of ReadReq hits 528system.cpu.dcache.ReadReq_hits::total 7813455 # number of ReadReq hits 529system.cpu.dcache.WriteReq_hits::cpu.data 5852226 # number of WriteReq hits 530system.cpu.dcache.WriteReq_hits::total 5852226 # number of WriteReq hits 531system.cpu.dcache.LoadLockedReq_hits::cpu.data 182968 # number of LoadLockedReq hits 532system.cpu.dcache.LoadLockedReq_hits::total 182968 # number of LoadLockedReq hits 533system.cpu.dcache.StoreCondReq_hits::cpu.data 199220 # number of StoreCondReq hits 534system.cpu.dcache.StoreCondReq_hits::total 199220 # number of StoreCondReq hits 535system.cpu.dcache.demand_hits::cpu.data 13665681 # number of demand (read+write) hits 536system.cpu.dcache.demand_hits::total 13665681 # number of demand (read+write) hits 537system.cpu.dcache.overall_hits::cpu.data 13665681 # number of overall hits 538system.cpu.dcache.overall_hits::total 13665681 # number of overall hits 539system.cpu.dcache.ReadReq_misses::cpu.data 1069828 # number of ReadReq misses 540system.cpu.dcache.ReadReq_misses::total 1069828 # number of ReadReq misses 541system.cpu.dcache.WriteReq_misses::cpu.data 304319 # number of WriteReq misses 542system.cpu.dcache.WriteReq_misses::total 304319 # number of WriteReq misses 543system.cpu.dcache.LoadLockedReq_misses::cpu.data 17275 # number of LoadLockedReq misses 544system.cpu.dcache.LoadLockedReq_misses::total 17275 # number of LoadLockedReq misses 545system.cpu.dcache.demand_misses::cpu.data 1374147 # number of demand (read+write) misses 546system.cpu.dcache.demand_misses::total 1374147 # number of demand (read+write) misses 547system.cpu.dcache.overall_misses::cpu.data 1374147 # number of overall misses 548system.cpu.dcache.overall_misses::total 1374147 # number of overall misses 549system.cpu.dcache.ReadReq_miss_latency::cpu.data 30980928500 # number of ReadReq miss cycles 550system.cpu.dcache.ReadReq_miss_latency::total 30980928500 # number of ReadReq miss cycles 551system.cpu.dcache.WriteReq_miss_latency::cpu.data 11763694500 # number of WriteReq miss cycles 552system.cpu.dcache.WriteReq_miss_latency::total 11763694500 # number of WriteReq miss cycles 553system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230325000 # number of LoadLockedReq miss cycles 554system.cpu.dcache.LoadLockedReq_miss_latency::total 230325000 # number of LoadLockedReq miss cycles 555system.cpu.dcache.demand_miss_latency::cpu.data 42744623000 # number of demand (read+write) miss cycles 556system.cpu.dcache.demand_miss_latency::total 42744623000 # number of demand (read+write) miss cycles 557system.cpu.dcache.overall_miss_latency::cpu.data 42744623000 # number of overall miss cycles 558system.cpu.dcache.overall_miss_latency::total 42744623000 # number of overall miss cycles 559system.cpu.dcache.ReadReq_accesses::cpu.data 8883283 # number of ReadReq accesses(hits+misses) 560system.cpu.dcache.ReadReq_accesses::total 8883283 # number of ReadReq accesses(hits+misses) 561system.cpu.dcache.WriteReq_accesses::cpu.data 6156545 # number of WriteReq accesses(hits+misses) 562system.cpu.dcache.WriteReq_accesses::total 6156545 # number of WriteReq accesses(hits+misses) 563system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) 564system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) 565system.cpu.dcache.StoreCondReq_accesses::cpu.data 199220 # number of StoreCondReq accesses(hits+misses) 566system.cpu.dcache.StoreCondReq_accesses::total 199220 # number of StoreCondReq accesses(hits+misses) 567system.cpu.dcache.demand_accesses::cpu.data 15039828 # number of demand (read+write) accesses 568system.cpu.dcache.demand_accesses::total 15039828 # number of demand (read+write) accesses 569system.cpu.dcache.overall_accesses::cpu.data 15039828 # number of overall (read+write) accesses 570system.cpu.dcache.overall_accesses::total 15039828 # number of overall (read+write) accesses 571system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120432 # miss rate for ReadReq accesses 572system.cpu.dcache.ReadReq_miss_rate::total 0.120432 # miss rate for ReadReq accesses 573system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049430 # miss rate for WriteReq accesses 574system.cpu.dcache.WriteReq_miss_rate::total 0.049430 # miss rate for WriteReq accesses 575system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086270 # miss rate for LoadLockedReq accesses 576system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086270 # miss rate for LoadLockedReq accesses 577system.cpu.dcache.demand_miss_rate::cpu.data 0.091367 # miss rate for demand accesses 578system.cpu.dcache.demand_miss_rate::total 0.091367 # miss rate for demand accesses 579system.cpu.dcache.overall_miss_rate::cpu.data 0.091367 # miss rate for overall accesses 580system.cpu.dcache.overall_miss_rate::total 0.091367 # miss rate for overall accesses 581system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.793843 # average ReadReq miss latency 582system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.793843 # average ReadReq miss latency 583system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38655.800328 # average WriteReq miss latency 584system.cpu.dcache.WriteReq_avg_miss_latency::total 38655.800328 # average WriteReq miss latency 585system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13332.850941 # average LoadLockedReq miss latency 586system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13332.850941 # average LoadLockedReq miss latency 587system.cpu.dcache.demand_avg_miss_latency::cpu.data 31106.295760 # average overall miss latency 588system.cpu.dcache.demand_avg_miss_latency::total 31106.295760 # average overall miss latency 589system.cpu.dcache.overall_avg_miss_latency::cpu.data 31106.295760 # average overall miss latency 590system.cpu.dcache.overall_avg_miss_latency::total 31106.295760 # average overall miss latency |
| 573system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 574system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 575system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 576system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 577system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 578system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 591system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 592system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 593system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 594system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 595system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 596system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 579system.cpu.dcache.writebacks::writebacks 834943 # number of writebacks 580system.cpu.dcache.writebacks::total 834943 # number of writebacks 581system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069356 # number of ReadReq MSHR misses 582system.cpu.dcache.ReadReq_mshr_misses::total 1069356 # number of ReadReq MSHR misses 583system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304326 # number of WriteReq MSHR misses 584system.cpu.dcache.WriteReq_mshr_misses::total 304326 # number of WriteReq MSHR misses 585system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17246 # number of LoadLockedReq MSHR misses 586system.cpu.dcache.LoadLockedReq_mshr_misses::total 17246 # number of LoadLockedReq MSHR misses 587system.cpu.dcache.demand_mshr_misses::cpu.data 1373682 # number of demand (read+write) MSHR misses 588system.cpu.dcache.demand_mshr_misses::total 1373682 # number of demand (read+write) MSHR misses 589system.cpu.dcache.overall_mshr_misses::cpu.data 1373682 # number of overall MSHR misses 590system.cpu.dcache.overall_mshr_misses::total 1373682 # number of overall MSHR misses | 597system.cpu.dcache.writebacks::writebacks 835265 # number of writebacks 598system.cpu.dcache.writebacks::total 835265 # number of writebacks 599system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069828 # number of ReadReq MSHR misses 600system.cpu.dcache.ReadReq_mshr_misses::total 1069828 # number of ReadReq MSHR misses 601system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304319 # number of WriteReq MSHR misses 602system.cpu.dcache.WriteReq_mshr_misses::total 304319 # number of WriteReq MSHR misses 603system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17275 # number of LoadLockedReq MSHR misses 604system.cpu.dcache.LoadLockedReq_mshr_misses::total 17275 # number of LoadLockedReq MSHR misses 605system.cpu.dcache.demand_mshr_misses::cpu.data 1374147 # number of demand (read+write) MSHR misses 606system.cpu.dcache.demand_mshr_misses::total 1374147 # number of demand (read+write) MSHR misses 607system.cpu.dcache.overall_mshr_misses::cpu.data 1374147 # number of overall MSHR misses 608system.cpu.dcache.overall_mshr_misses::total 1374147 # number of overall MSHR misses |
| 591system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 592system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable | 609system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 610system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable |
| 593system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable 594system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable 595system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses 596system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses 597system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43703244000 # number of ReadReq MSHR miss cycles 598system.cpu.dcache.ReadReq_mshr_miss_latency::total 43703244000 # number of ReadReq MSHR miss cycles 599system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330881000 # number of WriteReq MSHR miss cycles 600system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330881000 # number of WriteReq MSHR miss cycles 601system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215551500 # number of LoadLockedReq MSHR miss cycles 602system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215551500 # number of LoadLockedReq MSHR miss cycles 603system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61034125000 # number of demand (read+write) MSHR miss cycles 604system.cpu.dcache.demand_mshr_miss_latency::total 61034125000 # number of demand (read+write) MSHR miss cycles 605system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61034125000 # number of overall MSHR miss cycles 606system.cpu.dcache.overall_mshr_miss_latency::total 61034125000 # number of overall MSHR miss cycles 607system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526980000 # number of ReadReq MSHR uncacheable cycles 608system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526980000 # number of ReadReq MSHR uncacheable cycles 609system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1526980000 # number of overall MSHR uncacheable cycles 610system.cpu.dcache.overall_mshr_uncacheable_latency::total 1526980000 # number of overall MSHR uncacheable cycles 611system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120372 # mshr miss rate for ReadReq accesses 612system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120372 # mshr miss rate for ReadReq accesses 613system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses 614system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses 615system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086109 # mshr miss rate for LoadLockedReq accesses 616system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086109 # mshr miss rate for LoadLockedReq accesses 617system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses 618system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses 619system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses 620system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses 621system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40868.750912 # average ReadReq mshr miss latency 622system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40868.750912 # average ReadReq mshr miss latency 623system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56948.407300 # average WriteReq mshr miss latency 624system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56948.407300 # average WriteReq mshr miss latency 625system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.637365 # average LoadLockedReq mshr miss latency 626system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.637365 # average LoadLockedReq mshr miss latency 627system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44431.043720 # average overall mshr miss latency 628system.cpu.dcache.demand_avg_mshr_miss_latency::total 44431.043720 # average overall mshr miss latency 629system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44431.043720 # average overall mshr miss latency 630system.cpu.dcache.overall_avg_mshr_miss_latency::total 44431.043720 # average overall mshr miss latency 631system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.434343 # average ReadReq mshr uncacheable latency 632system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.434343 # average ReadReq mshr uncacheable latency 633system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92081.046855 # average overall mshr uncacheable latency 634system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92081.046855 # average overall mshr uncacheable latency 635system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 636system.cpu.icache.tags.replacements 928931 # number of replacements 637system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use 638system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks. 639system.cpu.icache.tags.sampled_refs 929442 # Sample count of references to valid blocks. 640system.cpu.icache.tags.avg_refs 59.460318 # Average number of references to valid blocks. 641system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. 642system.cpu.icache.tags.occ_blocks::cpu.inst 506.355616 # Average occupied blocks per requestor 643system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy 644system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy | 611system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable 612system.cpu.dcache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable 613system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses 614system.cpu.dcache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses 615system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29911100500 # number of ReadReq MSHR miss cycles 616system.cpu.dcache.ReadReq_mshr_miss_latency::total 29911100500 # number of ReadReq MSHR miss cycles 617system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11459375500 # number of WriteReq MSHR miss cycles 618system.cpu.dcache.WriteReq_mshr_miss_latency::total 11459375500 # number of WriteReq MSHR miss cycles 619system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 213050000 # number of LoadLockedReq MSHR miss cycles 620system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 213050000 # number of LoadLockedReq MSHR miss cycles 621system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41370476000 # number of demand (read+write) MSHR miss cycles 622system.cpu.dcache.demand_mshr_miss_latency::total 41370476000 # number of demand (read+write) MSHR miss cycles 623system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41370476000 # number of overall MSHR miss cycles 624system.cpu.dcache.overall_mshr_miss_latency::total 41370476000 # number of overall MSHR miss cycles 625system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533911000 # number of ReadReq MSHR uncacheable cycles 626system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533911000 # number of ReadReq MSHR uncacheable cycles 627system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533911000 # number of overall MSHR uncacheable cycles 628system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533911000 # number of overall MSHR uncacheable cycles 629system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120432 # mshr miss rate for ReadReq accesses 630system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120432 # mshr miss rate for ReadReq accesses 631system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049430 # mshr miss rate for WriteReq accesses 632system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049430 # mshr miss rate for WriteReq accesses 633system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086270 # mshr miss rate for LoadLockedReq accesses 634system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086270 # mshr miss rate for LoadLockedReq accesses 635system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091367 # mshr miss rate for demand accesses 636system.cpu.dcache.demand_mshr_miss_rate::total 0.091367 # mshr miss rate for demand accesses 637system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091367 # mshr miss rate for overall accesses 638system.cpu.dcache.overall_mshr_miss_rate::total 0.091367 # mshr miss rate for overall accesses 639system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27958.793843 # average ReadReq mshr miss latency 640system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27958.793843 # average ReadReq mshr miss latency 641system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37655.800328 # average WriteReq mshr miss latency 642system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37655.800328 # average WriteReq mshr miss latency 643system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12332.850941 # average LoadLockedReq mshr miss latency 644system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12332.850941 # average LoadLockedReq mshr miss latency 645system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.295760 # average overall mshr miss latency 646system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.295760 # average overall mshr miss latency 647system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.295760 # average overall mshr miss latency 648system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.295760 # average overall mshr miss latency 649system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.578644 # average ReadReq mshr uncacheable latency 650system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.578644 # average ReadReq mshr uncacheable latency 651system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92515.741858 # average overall mshr uncacheable latency 652system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92515.741858 # average overall mshr uncacheable latency 653system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 654system.cpu.icache.tags.replacements 928034 # number of replacements 655system.cpu.icache.tags.tagsinuse 508.064469 # Cycle average of tags in use 656system.cpu.icache.tags.total_refs 55263315 # Total number of references to valid blocks. 657system.cpu.icache.tags.sampled_refs 928545 # Sample count of references to valid blocks. 658system.cpu.icache.tags.avg_refs 59.516033 # Average number of references to valid blocks. 659system.cpu.icache.tags.warmup_cycle 42160205500 # Cycle when the warmup percentage was hit. 660system.cpu.icache.tags.occ_blocks::cpu.inst 508.064469 # Average occupied blocks per requestor 661system.cpu.icache.tags.occ_percent::cpu.inst 0.992313 # Average percentage of cache occupancy 662system.cpu.icache.tags.occ_percent::total 0.992313 # Average percentage of cache occupancy |
| 645system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 646system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 647system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 648system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 649system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 650system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 663system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 664system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 665system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 666system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 667system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 668system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 651system.cpu.icache.tags.tag_accesses 57124121 # Number of tag accesses 652system.cpu.icache.tags.data_accesses 57124121 # Number of data accesses 653system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 654system.cpu.icache.ReadReq_hits::cpu.inst 55264917 # number of ReadReq hits 655system.cpu.icache.ReadReq_hits::total 55264917 # number of ReadReq hits 656system.cpu.icache.demand_hits::cpu.inst 55264917 # number of demand (read+write) hits 657system.cpu.icache.demand_hits::total 55264917 # number of demand (read+write) hits 658system.cpu.icache.overall_hits::cpu.inst 55264917 # number of overall hits 659system.cpu.icache.overall_hits::total 55264917 # number of overall hits 660system.cpu.icache.ReadReq_misses::cpu.inst 929602 # number of ReadReq misses 661system.cpu.icache.ReadReq_misses::total 929602 # number of ReadReq misses 662system.cpu.icache.demand_misses::cpu.inst 929602 # number of demand (read+write) misses 663system.cpu.icache.demand_misses::total 929602 # number of demand (read+write) misses 664system.cpu.icache.overall_misses::cpu.inst 929602 # number of overall misses 665system.cpu.icache.overall_misses::total 929602 # number of overall misses 666system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686093000 # number of ReadReq miss cycles 667system.cpu.icache.ReadReq_miss_latency::total 13686093000 # number of ReadReq miss cycles 668system.cpu.icache.demand_miss_latency::cpu.inst 13686093000 # number of demand (read+write) miss cycles 669system.cpu.icache.demand_miss_latency::total 13686093000 # number of demand (read+write) miss cycles 670system.cpu.icache.overall_miss_latency::cpu.inst 13686093000 # number of overall miss cycles 671system.cpu.icache.overall_miss_latency::total 13686093000 # number of overall miss cycles 672system.cpu.icache.ReadReq_accesses::cpu.inst 56194519 # number of ReadReq accesses(hits+misses) 673system.cpu.icache.ReadReq_accesses::total 56194519 # number of ReadReq accesses(hits+misses) 674system.cpu.icache.demand_accesses::cpu.inst 56194519 # number of demand (read+write) accesses 675system.cpu.icache.demand_accesses::total 56194519 # number of demand (read+write) accesses 676system.cpu.icache.overall_accesses::cpu.inst 56194519 # number of overall (read+write) accesses 677system.cpu.icache.overall_accesses::total 56194519 # number of overall (read+write) accesses 678system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016543 # miss rate for ReadReq accesses 679system.cpu.icache.ReadReq_miss_rate::total 0.016543 # miss rate for ReadReq accesses 680system.cpu.icache.demand_miss_rate::cpu.inst 0.016543 # miss rate for demand accesses 681system.cpu.icache.demand_miss_rate::total 0.016543 # miss rate for demand accesses 682system.cpu.icache.overall_miss_rate::cpu.inst 0.016543 # miss rate for overall accesses 683system.cpu.icache.overall_miss_rate::total 0.016543 # miss rate for overall accesses 684system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14722.529642 # average ReadReq miss latency 685system.cpu.icache.ReadReq_avg_miss_latency::total 14722.529642 # average ReadReq miss latency 686system.cpu.icache.demand_avg_miss_latency::cpu.inst 14722.529642 # average overall miss latency 687system.cpu.icache.demand_avg_miss_latency::total 14722.529642 # average overall miss latency 688system.cpu.icache.overall_avg_miss_latency::cpu.inst 14722.529642 # average overall miss latency 689system.cpu.icache.overall_avg_miss_latency::total 14722.529642 # average overall miss latency | 669system.cpu.icache.tags.tag_accesses 57120725 # Number of tag accesses 670system.cpu.icache.tags.data_accesses 57120725 # Number of data accesses 671system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 672system.cpu.icache.ReadReq_hits::cpu.inst 55263315 # number of ReadReq hits 673system.cpu.icache.ReadReq_hits::total 55263315 # number of ReadReq hits 674system.cpu.icache.demand_hits::cpu.inst 55263315 # number of demand (read+write) hits 675system.cpu.icache.demand_hits::total 55263315 # number of demand (read+write) hits 676system.cpu.icache.overall_hits::cpu.inst 55263315 # number of overall hits 677system.cpu.icache.overall_hits::total 55263315 # number of overall hits 678system.cpu.icache.ReadReq_misses::cpu.inst 928705 # number of ReadReq misses 679system.cpu.icache.ReadReq_misses::total 928705 # number of ReadReq misses 680system.cpu.icache.demand_misses::cpu.inst 928705 # number of demand (read+write) misses 681system.cpu.icache.demand_misses::total 928705 # number of demand (read+write) misses 682system.cpu.icache.overall_misses::cpu.inst 928705 # number of overall misses 683system.cpu.icache.overall_misses::total 928705 # number of overall misses 684system.cpu.icache.ReadReq_miss_latency::cpu.inst 13023819500 # number of ReadReq miss cycles 685system.cpu.icache.ReadReq_miss_latency::total 13023819500 # number of ReadReq miss cycles 686system.cpu.icache.demand_miss_latency::cpu.inst 13023819500 # number of demand (read+write) miss cycles 687system.cpu.icache.demand_miss_latency::total 13023819500 # number of demand (read+write) miss cycles 688system.cpu.icache.overall_miss_latency::cpu.inst 13023819500 # number of overall miss cycles 689system.cpu.icache.overall_miss_latency::total 13023819500 # number of overall miss cycles 690system.cpu.icache.ReadReq_accesses::cpu.inst 56192020 # number of ReadReq accesses(hits+misses) 691system.cpu.icache.ReadReq_accesses::total 56192020 # number of ReadReq accesses(hits+misses) 692system.cpu.icache.demand_accesses::cpu.inst 56192020 # number of demand (read+write) accesses 693system.cpu.icache.demand_accesses::total 56192020 # number of demand (read+write) accesses 694system.cpu.icache.overall_accesses::cpu.inst 56192020 # number of overall (read+write) accesses 695system.cpu.icache.overall_accesses::total 56192020 # number of overall (read+write) accesses 696system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016527 # miss rate for ReadReq accesses 697system.cpu.icache.ReadReq_miss_rate::total 0.016527 # miss rate for ReadReq accesses 698system.cpu.icache.demand_miss_rate::cpu.inst 0.016527 # miss rate for demand accesses 699system.cpu.icache.demand_miss_rate::total 0.016527 # miss rate for demand accesses 700system.cpu.icache.overall_miss_rate::cpu.inst 0.016527 # miss rate for overall accesses 701system.cpu.icache.overall_miss_rate::total 0.016527 # miss rate for overall accesses 702system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14023.634523 # average ReadReq miss latency 703system.cpu.icache.ReadReq_avg_miss_latency::total 14023.634523 # average ReadReq miss latency 704system.cpu.icache.demand_avg_miss_latency::cpu.inst 14023.634523 # average overall miss latency 705system.cpu.icache.demand_avg_miss_latency::total 14023.634523 # average overall miss latency 706system.cpu.icache.overall_avg_miss_latency::cpu.inst 14023.634523 # average overall miss latency 707system.cpu.icache.overall_avg_miss_latency::total 14023.634523 # average overall miss latency |
| 690system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 691system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 692system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 693system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 694system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 695system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 708system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 709system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 710system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 711system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 712system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 713system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 696system.cpu.icache.writebacks::writebacks 928931 # number of writebacks 697system.cpu.icache.writebacks::total 928931 # number of writebacks 698system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929602 # number of ReadReq MSHR misses 699system.cpu.icache.ReadReq_mshr_misses::total 929602 # number of ReadReq MSHR misses 700system.cpu.icache.demand_mshr_misses::cpu.inst 929602 # number of demand (read+write) MSHR misses 701system.cpu.icache.demand_mshr_misses::total 929602 # number of demand (read+write) MSHR misses 702system.cpu.icache.overall_mshr_misses::cpu.inst 929602 # number of overall MSHR misses 703system.cpu.icache.overall_mshr_misses::total 929602 # number of overall MSHR misses 704system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12756491000 # number of ReadReq MSHR miss cycles 705system.cpu.icache.ReadReq_mshr_miss_latency::total 12756491000 # number of ReadReq MSHR miss cycles 706system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12756491000 # number of demand (read+write) MSHR miss cycles 707system.cpu.icache.demand_mshr_miss_latency::total 12756491000 # number of demand (read+write) MSHR miss cycles 708system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12756491000 # number of overall MSHR miss cycles 709system.cpu.icache.overall_mshr_miss_latency::total 12756491000 # number of overall MSHR miss cycles 710system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses 711system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses 712system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses 713system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses 714system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses 715system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses 716system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.529642 # average ReadReq mshr miss latency 717system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.529642 # average ReadReq mshr miss latency 718system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.529642 # average overall mshr miss latency 719system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.529642 # average overall mshr miss latency 720system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.529642 # average overall mshr miss latency 721system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.529642 # average overall mshr miss latency 722system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 723system.cpu.l2cache.tags.replacements 336393 # number of replacements 724system.cpu.l2cache.tags.tagsinuse 65234.359958 # Cycle average of tags in use 725system.cpu.l2cache.tags.total_refs 3930396 # Total number of references to valid blocks. 726system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. 727system.cpu.l2cache.tags.avg_refs 9.787915 # Average number of references to valid blocks. 728system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. 729system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820449 # Average occupied blocks per requestor 730system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.121272 # Average occupied blocks per requestor 731system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418237 # Average occupied blocks per requestor 732system.cpu.l2cache.tags.occ_percent::writebacks 0.840345 # Average percentage of cache occupancy 733system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071505 # Average percentage of cache occupancy 734system.cpu.l2cache.tags.occ_percent::cpu.data 0.083548 # Average percentage of cache occupancy 735system.cpu.l2cache.tags.occ_percent::total 0.995397 # Average percentage of cache occupancy 736system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id 737system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id 738system.cpu.l2cache.tags.age_task_id_blocks_1024::1 722 # Occupied blocks per task id 739system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id 740system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id 741system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id 742system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 743system.cpu.l2cache.tags.tag_accesses 37812907 # Number of tag accesses 744system.cpu.l2cache.tags.data_accesses 37812907 # Number of data accesses 745system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 746system.cpu.l2cache.WritebackDirty_hits::writebacks 834943 # number of WritebackDirty hits 747system.cpu.l2cache.WritebackDirty_hits::total 834943 # number of WritebackDirty hits 748system.cpu.l2cache.WritebackClean_hits::writebacks 928709 # number of WritebackClean hits 749system.cpu.l2cache.WritebackClean_hits::total 928709 # number of WritebackClean hits 750system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 751system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 752system.cpu.l2cache.ReadExReq_hits::cpu.data 187489 # number of ReadExReq hits 753system.cpu.l2cache.ReadExReq_hits::total 187489 # number of ReadExReq hits 754system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916382 # number of ReadCleanReq hits 755system.cpu.l2cache.ReadCleanReq_hits::total 916382 # number of ReadCleanReq hits 756system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814631 # number of ReadSharedReq hits 757system.cpu.l2cache.ReadSharedReq_hits::total 814631 # number of ReadSharedReq hits 758system.cpu.l2cache.demand_hits::cpu.inst 916382 # number of demand (read+write) hits 759system.cpu.l2cache.demand_hits::cpu.data 1002120 # number of demand (read+write) hits 760system.cpu.l2cache.demand_hits::total 1918502 # number of demand (read+write) hits 761system.cpu.l2cache.overall_hits::cpu.inst 916382 # number of overall hits 762system.cpu.l2cache.overall_hits::cpu.data 1002120 # number of overall hits 763system.cpu.l2cache.overall_hits::total 1918502 # number of overall hits 764system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 765system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses 766system.cpu.l2cache.ReadExReq_misses::cpu.data 116820 # number of ReadExReq misses 767system.cpu.l2cache.ReadExReq_misses::total 116820 # number of ReadExReq misses 768system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13200 # number of ReadCleanReq misses 769system.cpu.l2cache.ReadCleanReq_misses::total 13200 # number of ReadCleanReq misses 770system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271971 # number of ReadSharedReq misses 771system.cpu.l2cache.ReadSharedReq_misses::total 271971 # number of ReadSharedReq misses 772system.cpu.l2cache.demand_misses::cpu.inst 13200 # number of demand (read+write) misses 773system.cpu.l2cache.demand_misses::cpu.data 388791 # number of demand (read+write) misses 774system.cpu.l2cache.demand_misses::total 401991 # number of demand (read+write) misses 775system.cpu.l2cache.overall_misses::cpu.inst 13200 # number of overall misses 776system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses 777system.cpu.l2cache.overall_misses::total 401991 # number of overall misses 778system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 315000 # number of UpgradeReq miss cycles 779system.cpu.l2cache.UpgradeReq_miss_latency::total 315000 # number of UpgradeReq miss cycles 780system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14901397500 # number of ReadExReq miss cycles 781system.cpu.l2cache.ReadExReq_miss_latency::total 14901397500 # number of ReadExReq miss cycles 782system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1726772000 # number of ReadCleanReq miss cycles 783system.cpu.l2cache.ReadCleanReq_miss_latency::total 1726772000 # number of ReadCleanReq miss cycles 784system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33721234500 # number of ReadSharedReq miss cycles 785system.cpu.l2cache.ReadSharedReq_miss_latency::total 33721234500 # number of ReadSharedReq miss cycles 786system.cpu.l2cache.demand_miss_latency::cpu.inst 1726772000 # number of demand (read+write) miss cycles 787system.cpu.l2cache.demand_miss_latency::cpu.data 48622632000 # number of demand (read+write) miss cycles 788system.cpu.l2cache.demand_miss_latency::total 50349404000 # number of demand (read+write) miss cycles 789system.cpu.l2cache.overall_miss_latency::cpu.inst 1726772000 # number of overall miss cycles 790system.cpu.l2cache.overall_miss_latency::cpu.data 48622632000 # number of overall miss cycles 791system.cpu.l2cache.overall_miss_latency::total 50349404000 # number of overall miss cycles 792system.cpu.l2cache.WritebackDirty_accesses::writebacks 834943 # number of WritebackDirty accesses(hits+misses) 793system.cpu.l2cache.WritebackDirty_accesses::total 834943 # number of WritebackDirty accesses(hits+misses) 794system.cpu.l2cache.WritebackClean_accesses::writebacks 928709 # number of WritebackClean accesses(hits+misses) 795system.cpu.l2cache.WritebackClean_accesses::total 928709 # number of WritebackClean accesses(hits+misses) | 714system.cpu.icache.writebacks::writebacks 928034 # number of writebacks 715system.cpu.icache.writebacks::total 928034 # number of writebacks 716system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928705 # number of ReadReq MSHR misses 717system.cpu.icache.ReadReq_mshr_misses::total 928705 # number of ReadReq MSHR misses 718system.cpu.icache.demand_mshr_misses::cpu.inst 928705 # number of demand (read+write) MSHR misses 719system.cpu.icache.demand_mshr_misses::total 928705 # number of demand (read+write) MSHR misses 720system.cpu.icache.overall_mshr_misses::cpu.inst 928705 # number of overall MSHR misses 721system.cpu.icache.overall_mshr_misses::total 928705 # number of overall MSHR misses 722system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12095114500 # number of ReadReq MSHR miss cycles 723system.cpu.icache.ReadReq_mshr_miss_latency::total 12095114500 # number of ReadReq MSHR miss cycles 724system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12095114500 # number of demand (read+write) MSHR miss cycles 725system.cpu.icache.demand_mshr_miss_latency::total 12095114500 # number of demand (read+write) MSHR miss cycles 726system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12095114500 # number of overall MSHR miss cycles 727system.cpu.icache.overall_mshr_miss_latency::total 12095114500 # number of overall MSHR miss cycles 728system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for ReadReq accesses 729system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016527 # mshr miss rate for ReadReq accesses 730system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for demand accesses 731system.cpu.icache.demand_mshr_miss_rate::total 0.016527 # mshr miss rate for demand accesses 732system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for overall accesses 733system.cpu.icache.overall_mshr_miss_rate::total 0.016527 # mshr miss rate for overall accesses 734system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13023.634523 # average ReadReq mshr miss latency 735system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13023.634523 # average ReadReq mshr miss latency 736system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13023.634523 # average overall mshr miss latency 737system.cpu.icache.demand_avg_mshr_miss_latency::total 13023.634523 # average overall mshr miss latency 738system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13023.634523 # average overall mshr miss latency 739system.cpu.icache.overall_avg_mshr_miss_latency::total 13023.634523 # average overall mshr miss latency 740system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 741system.cpu.l2cache.tags.replacements 336391 # number of replacements 742system.cpu.l2cache.tags.tagsinuse 65395.484463 # Cycle average of tags in use 743system.cpu.l2cache.tags.total_refs 4235202 # Total number of references to valid blocks. 744system.cpu.l2cache.tags.sampled_refs 401913 # Sample count of references to valid blocks. 745system.cpu.l2cache.tags.avg_refs 10.537609 # Average number of references to valid blocks. 746system.cpu.l2cache.tags.warmup_cycle 7260348000 # Cycle when the warmup percentage was hit. 747system.cpu.l2cache.tags.occ_blocks::writebacks 235.775942 # Average occupied blocks per requestor 748system.cpu.l2cache.tags.occ_blocks::cpu.inst 4738.507265 # Average occupied blocks per requestor 749system.cpu.l2cache.tags.occ_blocks::cpu.data 60421.201256 # Average occupied blocks per requestor 750system.cpu.l2cache.tags.occ_percent::writebacks 0.003598 # Average percentage of cache occupancy 751system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072304 # Average percentage of cache occupancy 752system.cpu.l2cache.tags.occ_percent::cpu.data 0.921954 # Average percentage of cache occupancy 753system.cpu.l2cache.tags.occ_percent::total 0.997856 # Average percentage of cache occupancy 754system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id 755system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id 756system.cpu.l2cache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id 757system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4753 # Occupied blocks per task id 758system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59867 # Occupied blocks per task id 759system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id 760system.cpu.l2cache.tags.tag_accesses 37502484 # Number of tag accesses 761system.cpu.l2cache.tags.data_accesses 37502484 # Number of data accesses 762system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 763system.cpu.l2cache.WritebackDirty_hits::writebacks 835265 # number of WritebackDirty hits 764system.cpu.l2cache.WritebackDirty_hits::total 835265 # number of WritebackDirty hits 765system.cpu.l2cache.WritebackClean_hits::writebacks 927811 # number of WritebackClean hits 766system.cpu.l2cache.WritebackClean_hits::total 927811 # number of WritebackClean hits 767system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits 768system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits 769system.cpu.l2cache.ReadExReq_hits::cpu.data 187491 # number of ReadExReq hits 770system.cpu.l2cache.ReadExReq_hits::total 187491 # number of ReadExReq hits 771system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 915488 # number of ReadCleanReq hits 772system.cpu.l2cache.ReadCleanReq_hits::total 915488 # number of ReadCleanReq hits 773system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815128 # number of ReadSharedReq hits 774system.cpu.l2cache.ReadSharedReq_hits::total 815128 # number of ReadSharedReq hits 775system.cpu.l2cache.demand_hits::cpu.inst 915488 # number of demand (read+write) hits 776system.cpu.l2cache.demand_hits::cpu.data 1002619 # number of demand (read+write) hits 777system.cpu.l2cache.demand_hits::total 1918107 # number of demand (read+write) hits 778system.cpu.l2cache.overall_hits::cpu.inst 915488 # number of overall hits 779system.cpu.l2cache.overall_hits::cpu.data 1002619 # number of overall hits 780system.cpu.l2cache.overall_hits::total 1918107 # number of overall hits 781system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 782system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses 783system.cpu.l2cache.ReadExReq_misses::cpu.data 116811 # number of ReadExReq misses 784system.cpu.l2cache.ReadExReq_misses::total 116811 # number of ReadExReq misses 785system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13197 # number of ReadCleanReq misses 786system.cpu.l2cache.ReadCleanReq_misses::total 13197 # number of ReadCleanReq misses 787system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271975 # number of ReadSharedReq misses 788system.cpu.l2cache.ReadSharedReq_misses::total 271975 # number of ReadSharedReq misses 789system.cpu.l2cache.demand_misses::cpu.inst 13197 # number of demand (read+write) misses 790system.cpu.l2cache.demand_misses::cpu.data 388786 # number of demand (read+write) misses 791system.cpu.l2cache.demand_misses::total 401983 # number of demand (read+write) misses 792system.cpu.l2cache.overall_misses::cpu.inst 13197 # number of overall misses 793system.cpu.l2cache.overall_misses::cpu.data 388786 # number of overall misses 794system.cpu.l2cache.overall_misses::total 401983 # number of overall misses 795system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 246500 # number of UpgradeReq miss cycles 796system.cpu.l2cache.UpgradeReq_miss_latency::total 246500 # number of UpgradeReq miss cycles 797system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9030572500 # number of ReadExReq miss cycles 798system.cpu.l2cache.ReadExReq_miss_latency::total 9030572500 # number of ReadExReq miss cycles 799system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1076146500 # number of ReadCleanReq miss cycles 800system.cpu.l2cache.ReadCleanReq_miss_latency::total 1076146500 # number of ReadCleanReq miss cycles 801system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19920583000 # number of ReadSharedReq miss cycles 802system.cpu.l2cache.ReadSharedReq_miss_latency::total 19920583000 # number of ReadSharedReq miss cycles 803system.cpu.l2cache.demand_miss_latency::cpu.inst 1076146500 # number of demand (read+write) miss cycles 804system.cpu.l2cache.demand_miss_latency::cpu.data 28951155500 # number of demand (read+write) miss cycles 805system.cpu.l2cache.demand_miss_latency::total 30027302000 # number of demand (read+write) miss cycles 806system.cpu.l2cache.overall_miss_latency::cpu.inst 1076146500 # number of overall miss cycles 807system.cpu.l2cache.overall_miss_latency::cpu.data 28951155500 # number of overall miss cycles 808system.cpu.l2cache.overall_miss_latency::total 30027302000 # number of overall miss cycles 809system.cpu.l2cache.WritebackDirty_accesses::writebacks 835265 # number of WritebackDirty accesses(hits+misses) 810system.cpu.l2cache.WritebackDirty_accesses::total 835265 # number of WritebackDirty accesses(hits+misses) 811system.cpu.l2cache.WritebackClean_accesses::writebacks 927811 # number of WritebackClean accesses(hits+misses) 812system.cpu.l2cache.WritebackClean_accesses::total 927811 # number of WritebackClean accesses(hits+misses) |
| 796system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 797system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) | 813system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 814system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) |
| 798system.cpu.l2cache.ReadExReq_accesses::cpu.data 304309 # number of ReadExReq accesses(hits+misses) 799system.cpu.l2cache.ReadExReq_accesses::total 304309 # number of ReadExReq accesses(hits+misses) 800system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929582 # number of ReadCleanReq accesses(hits+misses) 801system.cpu.l2cache.ReadCleanReq_accesses::total 929582 # number of ReadCleanReq accesses(hits+misses) 802system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086602 # number of ReadSharedReq accesses(hits+misses) 803system.cpu.l2cache.ReadSharedReq_accesses::total 1086602 # number of ReadSharedReq accesses(hits+misses) 804system.cpu.l2cache.demand_accesses::cpu.inst 929582 # number of demand (read+write) accesses 805system.cpu.l2cache.demand_accesses::cpu.data 1390911 # number of demand (read+write) accesses 806system.cpu.l2cache.demand_accesses::total 2320493 # number of demand (read+write) accesses 807system.cpu.l2cache.overall_accesses::cpu.inst 929582 # number of overall (read+write) accesses 808system.cpu.l2cache.overall_accesses::cpu.data 1390911 # number of overall (read+write) accesses 809system.cpu.l2cache.overall_accesses::total 2320493 # number of overall (read+write) accesses 810system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 811system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses 812system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383886 # miss rate for ReadExReq accesses 813system.cpu.l2cache.ReadExReq_miss_rate::total 0.383886 # miss rate for ReadExReq accesses 814system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014200 # miss rate for ReadCleanReq accesses 815system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014200 # miss rate for ReadCleanReq accesses 816system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250295 # miss rate for ReadSharedReq accesses 817system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250295 # miss rate for ReadSharedReq accesses 818system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014200 # miss rate for demand accesses 819system.cpu.l2cache.demand_miss_rate::cpu.data 0.279523 # miss rate for demand accesses 820system.cpu.l2cache.demand_miss_rate::total 0.173235 # miss rate for demand accesses 821system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014200 # miss rate for overall accesses 822system.cpu.l2cache.overall_miss_rate::cpu.data 0.279523 # miss rate for overall accesses 823system.cpu.l2cache.overall_miss_rate::total 0.173235 # miss rate for overall accesses 824system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24230.769231 # average UpgradeReq miss latency 825system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24230.769231 # average UpgradeReq miss latency 826system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127558.615819 # average ReadExReq miss latency 827system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127558.615819 # average ReadExReq miss latency 828system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130816.060606 # average ReadCleanReq miss latency 829system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130816.060606 # average ReadCleanReq miss latency 830system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123988.346184 # average ReadSharedReq miss latency 831system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123988.346184 # average ReadSharedReq miss latency 832system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130816.060606 # average overall miss latency 833system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125061.104810 # average overall miss latency 834system.cpu.l2cache.demand_avg_miss_latency::total 125250.077738 # average overall miss latency 835system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130816.060606 # average overall miss latency 836system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125061.104810 # average overall miss latency 837system.cpu.l2cache.overall_avg_miss_latency::total 125250.077738 # average overall miss latency | 815system.cpu.l2cache.ReadExReq_accesses::cpu.data 304302 # number of ReadExReq accesses(hits+misses) 816system.cpu.l2cache.ReadExReq_accesses::total 304302 # number of ReadExReq accesses(hits+misses) 817system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 928685 # number of ReadCleanReq accesses(hits+misses) 818system.cpu.l2cache.ReadCleanReq_accesses::total 928685 # number of ReadCleanReq accesses(hits+misses) 819system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087103 # number of ReadSharedReq accesses(hits+misses) 820system.cpu.l2cache.ReadSharedReq_accesses::total 1087103 # number of ReadSharedReq accesses(hits+misses) 821system.cpu.l2cache.demand_accesses::cpu.inst 928685 # number of demand (read+write) accesses 822system.cpu.l2cache.demand_accesses::cpu.data 1391405 # number of demand (read+write) accesses 823system.cpu.l2cache.demand_accesses::total 2320090 # number of demand (read+write) accesses 824system.cpu.l2cache.overall_accesses::cpu.inst 928685 # number of overall (read+write) accesses 825system.cpu.l2cache.overall_accesses::cpu.data 1391405 # number of overall (read+write) accesses 826system.cpu.l2cache.overall_accesses::total 2320090 # number of overall (read+write) accesses 827system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for UpgradeReq accesses 828system.cpu.l2cache.UpgradeReq_miss_rate::total 0.294118 # miss rate for UpgradeReq accesses 829system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383865 # miss rate for ReadExReq accesses 830system.cpu.l2cache.ReadExReq_miss_rate::total 0.383865 # miss rate for ReadExReq accesses 831system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014210 # miss rate for ReadCleanReq accesses 832system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014210 # miss rate for ReadCleanReq accesses 833system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250183 # miss rate for ReadSharedReq accesses 834system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250183 # miss rate for ReadSharedReq accesses 835system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014210 # miss rate for demand accesses 836system.cpu.l2cache.demand_miss_rate::cpu.data 0.279420 # miss rate for demand accesses 837system.cpu.l2cache.demand_miss_rate::total 0.173262 # miss rate for demand accesses 838system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014210 # miss rate for overall accesses 839system.cpu.l2cache.overall_miss_rate::cpu.data 0.279420 # miss rate for overall accesses 840system.cpu.l2cache.overall_miss_rate::total 0.173262 # miss rate for overall accesses 841system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49300 # average UpgradeReq miss latency 842system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49300 # average UpgradeReq miss latency 843system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77309.264538 # average ReadExReq miss latency 844system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77309.264538 # average ReadExReq miss latency 845system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81544.782905 # average ReadCleanReq miss latency 846system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81544.782905 # average ReadCleanReq miss latency 847system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73244.169501 # average ReadSharedReq miss latency 848system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73244.169501 # average ReadSharedReq miss latency 849system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81544.782905 # average overall miss latency 850system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74465.529880 # average overall miss latency 851system.cpu.l2cache.demand_avg_miss_latency::total 74697.939963 # average overall miss latency 852system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81544.782905 # average overall miss latency 853system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74465.529880 # average overall miss latency 854system.cpu.l2cache.overall_avg_miss_latency::total 74697.939963 # average overall miss latency |
| 838system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 839system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 840system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 841system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 842system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 843system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 855system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 856system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 857system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 858system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 859system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 860system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 844system.cpu.l2cache.writebacks::writebacks 74281 # number of writebacks 845system.cpu.l2cache.writebacks::total 74281 # number of writebacks 846system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 847system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 848system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116820 # number of ReadExReq MSHR misses 849system.cpu.l2cache.ReadExReq_mshr_misses::total 116820 # number of ReadExReq MSHR misses 850system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13200 # number of ReadCleanReq MSHR misses 851system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13200 # number of ReadCleanReq MSHR misses 852system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271971 # number of ReadSharedReq MSHR misses 853system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271971 # number of ReadSharedReq MSHR misses 854system.cpu.l2cache.demand_mshr_misses::cpu.inst 13200 # number of demand (read+write) MSHR misses 855system.cpu.l2cache.demand_mshr_misses::cpu.data 388791 # number of demand (read+write) MSHR misses 856system.cpu.l2cache.demand_mshr_misses::total 401991 # number of demand (read+write) MSHR misses 857system.cpu.l2cache.overall_mshr_misses::cpu.inst 13200 # number of overall MSHR misses 858system.cpu.l2cache.overall_mshr_misses::cpu.data 388791 # number of overall MSHR misses 859system.cpu.l2cache.overall_mshr_misses::total 401991 # number of overall MSHR misses | 861system.cpu.l2cache.writebacks::writebacks 74246 # number of writebacks 862system.cpu.l2cache.writebacks::total 74246 # number of writebacks 863system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses 864system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses 865system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116811 # number of ReadExReq MSHR misses 866system.cpu.l2cache.ReadExReq_mshr_misses::total 116811 # number of ReadExReq MSHR misses 867system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13197 # number of ReadCleanReq MSHR misses 868system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13197 # number of ReadCleanReq MSHR misses 869system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271975 # number of ReadSharedReq MSHR misses 870system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271975 # number of ReadSharedReq MSHR misses 871system.cpu.l2cache.demand_mshr_misses::cpu.inst 13197 # number of demand (read+write) MSHR misses 872system.cpu.l2cache.demand_mshr_misses::cpu.data 388786 # number of demand (read+write) MSHR misses 873system.cpu.l2cache.demand_mshr_misses::total 401983 # number of demand (read+write) MSHR misses 874system.cpu.l2cache.overall_mshr_misses::cpu.inst 13197 # number of overall MSHR misses 875system.cpu.l2cache.overall_mshr_misses::cpu.data 388786 # number of overall MSHR misses 876system.cpu.l2cache.overall_mshr_misses::total 401983 # number of overall MSHR misses |
| 860system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 861system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable | 877system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 878system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable |
| 862system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable 863system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable 864system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses 865system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses 866system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 893500 # number of UpgradeReq MSHR miss cycles 867system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 893500 # number of UpgradeReq MSHR miss cycles 868system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13733197500 # number of ReadExReq MSHR miss cycles 869system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13733197500 # number of ReadExReq MSHR miss cycles 870system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1594772000 # number of ReadCleanReq MSHR miss cycles 871system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1594772000 # number of ReadCleanReq MSHR miss cycles 872system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31001524500 # number of ReadSharedReq MSHR miss cycles 873system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31001524500 # number of ReadSharedReq MSHR miss cycles 874system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1594772000 # number of demand (read+write) MSHR miss cycles 875system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44734722000 # number of demand (read+write) MSHR miss cycles 876system.cpu.l2cache.demand_mshr_miss_latency::total 46329494000 # number of demand (read+write) MSHR miss cycles 877system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1594772000 # number of overall MSHR miss cycles 878system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44734722000 # number of overall MSHR miss cycles 879system.cpu.l2cache.overall_mshr_miss_latency::total 46329494000 # number of overall MSHR miss cycles 880system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440324000 # number of ReadReq MSHR uncacheable cycles 881system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440324000 # number of ReadReq MSHR uncacheable cycles 882system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1440324000 # number of overall MSHR uncacheable cycles 883system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1440324000 # number of overall MSHR uncacheable cycles 884system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 885system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 886system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383886 # mshr miss rate for ReadExReq accesses 887system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383886 # mshr miss rate for ReadExReq accesses 888system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses 889system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses 890system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250295 # mshr miss rate for ReadSharedReq accesses 891system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250295 # mshr miss rate for ReadSharedReq accesses 892system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses 893system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279523 # mshr miss rate for demand accesses 894system.cpu.l2cache.demand_mshr_miss_rate::total 0.173235 # mshr miss rate for demand accesses 895system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses 896system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279523 # mshr miss rate for overall accesses 897system.cpu.l2cache.overall_mshr_miss_rate::total 0.173235 # mshr miss rate for overall accesses 898system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68730.769231 # average UpgradeReq mshr miss latency 899system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68730.769231 # average UpgradeReq mshr miss latency 900system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117558.615819 # average ReadExReq mshr miss latency 901system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117558.615819 # average ReadExReq mshr miss latency 902system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120816.060606 # average ReadCleanReq mshr miss latency 903system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120816.060606 # average ReadCleanReq mshr miss latency 904system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113988.346184 # average ReadSharedReq mshr miss latency 905system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113988.346184 # average ReadSharedReq mshr miss latency 906system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120816.060606 # average overall mshr miss latency 907system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115061.104810 # average overall mshr miss latency 908system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.077738 # average overall mshr miss latency 909system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120816.060606 # average overall mshr miss latency 910system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115061.104810 # average overall mshr miss latency 911system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.077738 # average overall mshr miss latency 912system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.961039 # average ReadReq mshr uncacheable latency 913system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.961039 # average ReadReq mshr uncacheable latency 914system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.454381 # average overall mshr uncacheable latency 915system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.454381 # average overall mshr uncacheable latency 916system.cpu.toL2Bus.snoop_filter.tot_requests 4639859 # Total number of requests made to the snoop filter. 917system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319495 # Number of requests hitting in the snoop filter with a single holder of the requested data. 918system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 919system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. 920system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 879system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable 880system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable 881system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses 882system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses 883system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles 884system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles 885system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7862462500 # number of ReadExReq MSHR miss cycles 886system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7862462500 # number of ReadExReq MSHR miss cycles 887system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 944176500 # number of ReadCleanReq MSHR miss cycles 888system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 944176500 # number of ReadCleanReq MSHR miss cycles 889system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17200833000 # number of ReadSharedReq MSHR miss cycles 890system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17200833000 # number of ReadSharedReq MSHR miss cycles 891system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 944176500 # number of demand (read+write) MSHR miss cycles 892system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25063295500 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.demand_mshr_miss_latency::total 26007472000 # number of demand (read+write) MSHR miss cycles 894system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 944176500 # number of overall MSHR miss cycles 895system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25063295500 # number of overall MSHR miss cycles 896system.cpu.l2cache.overall_mshr_miss_latency::total 26007472000 # number of overall MSHR miss cycles 897system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447255500 # number of ReadReq MSHR uncacheable cycles 898system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447255500 # number of ReadReq MSHR uncacheable cycles 899system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447255500 # number of overall MSHR uncacheable cycles 900system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447255500 # number of overall MSHR uncacheable cycles 901system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses 902system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses 903system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383865 # mshr miss rate for ReadExReq accesses 904system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383865 # mshr miss rate for ReadExReq accesses 905system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for ReadCleanReq accesses 906system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014210 # mshr miss rate for ReadCleanReq accesses 907system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250183 # mshr miss rate for ReadSharedReq accesses 908system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250183 # mshr miss rate for ReadSharedReq accesses 909system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for demand accesses 910system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279420 # mshr miss rate for demand accesses 911system.cpu.l2cache.demand_mshr_miss_rate::total 0.173262 # mshr miss rate for demand accesses 912system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for overall accesses 913system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279420 # mshr miss rate for overall accesses 914system.cpu.l2cache.overall_mshr_miss_rate::total 0.173262 # mshr miss rate for overall accesses 915system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency 916system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency 917system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67309.264538 # average ReadExReq mshr miss latency 918system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67309.264538 # average ReadExReq mshr miss latency 919system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71544.782905 # average ReadCleanReq mshr miss latency 920system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71544.782905 # average ReadCleanReq mshr miss latency 921system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63244.169501 # average ReadSharedReq mshr miss latency 922system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63244.169501 # average ReadSharedReq mshr miss latency 923system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71544.782905 # average overall mshr miss latency 924system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64465.529880 # average overall mshr miss latency 925system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64697.939963 # average overall mshr miss latency 926system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71544.782905 # average overall mshr miss latency 927system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64465.529880 # average overall mshr miss latency 928system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64697.939963 # average overall mshr miss latency 929system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208839.177489 # average ReadReq mshr uncacheable latency 930system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208839.177489 # average ReadReq mshr uncacheable latency 931system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87289.234017 # average overall mshr uncacheable latency 932system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87289.234017 # average overall mshr uncacheable latency 933system.cpu.toL2Bus.snoop_filter.tot_requests 4639053 # Total number of requests made to the snoop filter. 934system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319092 # Number of requests hitting in the snoop filter with a single holder of the requested data. 935system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 936system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter. 937system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 921system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 938system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 922system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states | 939system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states |
| 923system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution | 940system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution |
| 924system.cpu.toL2Bus.trans_dist::ReadResp 2023291 # Transaction distribution 925system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution 926system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution 927system.cpu.toL2Bus.trans_dist::WritebackDirty 950744 # Transaction distribution 928system.cpu.toL2Bus.trans_dist::WritebackClean 928931 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::CleanEvict 817740 # Transaction distribution | 941system.cpu.toL2Bus.trans_dist::ReadResp 2022895 # Transaction distribution 942system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution 943system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution 944system.cpu.toL2Bus.trans_dist::WritebackDirty 909511 # Transaction distribution 945system.cpu.toL2Bus.trans_dist::WritebackClean 928034 # Transaction distribution 946system.cpu.toL2Bus.trans_dist::CleanEvict 817772 # Transaction distribution |
| 930system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution | 947system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 948system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution |
| 932system.cpu.toL2Bus.trans_dist::ReadExReq 304309 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::ReadExResp 304309 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::ReadCleanReq 929602 # Transaction distribution 935system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086775 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution 937system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2788115 # Packet count per connected master and slave (bytes) 938system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205577 # Packet count per connected master and slave (bytes) 939system.cpu.toL2Bus.pkt_count::total 6993692 # Packet count per connected master and slave (bytes) 940system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118944832 # Cumulative packet size per connected master and slave (bytes) 941system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142509292 # Cumulative packet size per connected master and slave (bytes) 942system.cpu.toL2Bus.pkt_size::total 261454124 # Cumulative packet size per connected master and slave (bytes) 943system.cpu.toL2Bus.snoops 419988 # Total snoops (count) 944system.cpu.toL2Bus.snoopTraffic 7422592 # Total snoop traffic (bytes) 945system.cpu.toL2Bus.snoop_fanout::samples 2756924 # Request fanout histogram 946system.cpu.toL2Bus.snoop_fanout::mean 0.001015 # Request fanout histogram 947system.cpu.toL2Bus.snoop_fanout::stdev 0.031847 # Request fanout histogram | 949system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution 950system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution 951system.cpu.toL2Bus.trans_dist::ReadCleanReq 928705 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087263 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution 954system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2785424 # Packet count per connected master and slave (bytes) 955system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4207053 # Packet count per connected master and slave (bytes) 956system.cpu.toL2Bus.pkt_count::total 6992477 # Packet count per connected master and slave (bytes) 957system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118830016 # Cumulative packet size per connected master and slave (bytes) 958system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142561492 # Cumulative packet size per connected master and slave (bytes) 959system.cpu.toL2Bus.pkt_size::total 261391508 # Cumulative packet size per connected master and slave (bytes) 960system.cpu.toL2Bus.snoops 336947 # Total snoops (count) 961system.cpu.toL2Bus.snoopTraffic 4763072 # Total snoop traffic (bytes) 962system.cpu.toL2Bus.snoop_fanout::samples 2673477 # Request fanout histogram 963system.cpu.toL2Bus.snoop_fanout::mean 0.000954 # Request fanout histogram 964system.cpu.toL2Bus.snoop_fanout::stdev 0.030869 # Request fanout histogram |
| 948system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 965system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 949system.cpu.toL2Bus.snoop_fanout::0 2754125 99.90% 99.90% # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::1 2799 0.10% 100.00% # Request fanout histogram | 966system.cpu.toL2Bus.snoop_fanout::0 2670927 99.90% 99.90% # Request fanout histogram 967system.cpu.toL2Bus.snoop_fanout::1 2550 0.10% 100.00% # Request fanout histogram |
| 951system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 954system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 968system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 969system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 970system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 971system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 955system.cpu.toL2Bus.snoop_fanout::total 2756924 # Request fanout histogram 956system.cpu.toL2Bus.reqLayer0.occupancy 4096921500 # Layer occupancy (ticks) | 972system.cpu.toL2Bus.snoop_fanout::total 2673477 # Request fanout histogram 973system.cpu.toL2Bus.reqLayer0.occupancy 4095940500 # Layer occupancy (ticks) |
| 957system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 958system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) 959system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 974system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 975system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) 976system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 960system.cpu.toL2Bus.respLayer0.occupancy 1394403000 # Layer occupancy (ticks) | 977system.cpu.toL2Bus.respLayer0.occupancy 1393057500 # Layer occupancy (ticks) |
| 961system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 978system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 962system.cpu.toL2Bus.respLayer1.occupancy 2098131500 # Layer occupancy (ticks) | 979system.cpu.toL2Bus.respLayer1.occupancy 2098871000 # Layer occupancy (ticks) |
| 963system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 964system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 965system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 966system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 967system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 968system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 969system.disk0.dma_write_txs 395 # Number of DMA write transactions. 970system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 971system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 972system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 973system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 974system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 975system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 980system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 981system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 982system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 983system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 984system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 985system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 986system.disk0.dma_write_txs 395 # Number of DMA write transactions. 987system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 988system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 989system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 990system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 991system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 992system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 976system.iobus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states | 993system.iobus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states |
| 977system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 978system.iobus.trans_dist::ReadResp 7103 # Transaction distribution | 994system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 995system.iobus.trans_dist::ReadResp 7103 # Transaction distribution |
| 979system.iobus.trans_dist::WriteReq 51205 # Transaction distribution 980system.iobus.trans_dist::WriteResp 51205 # Transaction distribution 981system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) | 996system.iobus.trans_dist::WriteReq 51202 # Transaction distribution 997system.iobus.trans_dist::WriteResp 51202 # Transaction distribution 998system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) |
| 982system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 983system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 984system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 985system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 986system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 987system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 988system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 989system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) | 999system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1000system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1001system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1002system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1003system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 1004system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 1005system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1006system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) |
| 990system.iobus.pkt_count_system.bridge.master::total 33166 # Packet count per connected master and slave (bytes) | 1007system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) |
| 991system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 992system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) | 1008system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 1009system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) |
| 993system.iobus.pkt_count::total 116616 # Packet count per connected master and slave (bytes) 994system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20648 # Cumulative packet size per connected master and slave (bytes) | 1010system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) 1011system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) |
| 995system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 996system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 997system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 998system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 999system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1000system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1001system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1002system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) | 1012system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 1013system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1014system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1015system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1016system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1017system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1018system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1019system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) |
| 1003system.iobus.pkt_size_system.bridge.master::total 44588 # Cumulative packet size per connected master and slave (bytes) | 1020system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) |
| 1004system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1005system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) | 1021system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1022system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) |
| 1006system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) 1007system.iobus.reqLayer0.occupancy 5341000 # Layer occupancy (ticks) | 1023system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) 1024system.iobus.reqLayer0.occupancy 5337500 # Layer occupancy (ticks) |
| 1008system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1025system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1009system.iobus.reqLayer1.occupancy 759000 # Layer occupancy (ticks) | 1026system.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks) |
| 1010system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1011system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 1012system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1013system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1014system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1015system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) 1016system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) | 1027system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1028system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 1029system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1030system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1031system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1032system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) 1033system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) |
| 1017system.iobus.reqLayer23.occupancy 15817500 # Layer occupancy (ticks) | 1034system.iobus.reqLayer23.occupancy 15814000 # Layer occupancy (ticks) |
| 1018system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1019system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) 1020system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1035system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1036system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) 1037system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1021system.iobus.reqLayer25.occupancy 6038000 # Layer occupancy (ticks) | 1038system.iobus.reqLayer25.occupancy 6041500 # Layer occupancy (ticks) |
| 1022system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) | 1039system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) |
| 1023system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) | 1040system.iobus.reqLayer26.occupancy 82000 # Layer occupancy (ticks) |
| 1024system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1041system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1025system.iobus.reqLayer27.occupancy 215662167 # Layer occupancy (ticks) | 1042system.iobus.reqLayer27.occupancy 216133054 # Layer occupancy (ticks) |
| 1026system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) | 1043system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) |
| 1027system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) | 1044system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) |
| 1028system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1029system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1030system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1045system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1046system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1047system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1031system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states | 1048system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states |
| 1032system.iocache.tags.replacements 41685 # number of replacements | 1049system.iocache.tags.replacements 41685 # number of replacements |
| 1033system.iocache.tags.tagsinuse 1.339384 # Cycle average of tags in use | 1050system.iocache.tags.tagsinuse 1.342865 # Cycle average of tags in use |
| 1034system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1035system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1036system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1051system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1052system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1053system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1037system.iocache.tags.warmup_cycle 1774106669000 # Cycle when the warmup percentage was hit. 1038system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor 1039system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy 1040system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy | 1054system.iocache.tags.warmup_cycle 1756469369000 # Cycle when the warmup percentage was hit. 1055system.iocache.tags.occ_blocks::tsunami.ide 1.342865 # Average occupied blocks per requestor 1056system.iocache.tags.occ_percent::tsunami.ide 0.083929 # Average percentage of cache occupancy 1057system.iocache.tags.occ_percent::total 0.083929 # Average percentage of cache occupancy |
| 1041system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1042system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1043system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1044system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1045system.iocache.tags.data_accesses 375525 # Number of data accesses | 1058system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1059system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1060system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1061system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1062system.iocache.tags.data_accesses 375525 # Number of data accesses |
| 1046system.iocache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states | 1063system.iocache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states |
| 1047system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1048system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1049system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1050system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1051system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1052system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1053system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1054system.iocache.overall_misses::total 41725 # number of overall misses | 1064system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1065system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1066system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1067system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1068system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1069system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1070system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1071system.iocache.overall_misses::total 41725 # number of overall misses |
| 1055system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles 1056system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles 1057system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244723284 # number of WriteLineReq miss cycles 1058system.iocache.WriteLineReq_miss_latency::total 5244723284 # number of WriteLineReq miss cycles 1059system.iocache.demand_miss_latency::tsunami.ide 5266466167 # number of demand (read+write) miss cycles 1060system.iocache.demand_miss_latency::total 5266466167 # number of demand (read+write) miss cycles 1061system.iocache.overall_miss_latency::tsunami.ide 5266466167 # number of overall miss cycles 1062system.iocache.overall_miss_latency::total 5266466167 # number of overall miss cycles | 1072system.iocache.ReadReq_miss_latency::tsunami.ide 21758883 # number of ReadReq miss cycles 1073system.iocache.ReadReq_miss_latency::total 21758883 # number of ReadReq miss cycles 1074system.iocache.WriteLineReq_miss_latency::tsunami.ide 4857806171 # number of WriteLineReq miss cycles 1075system.iocache.WriteLineReq_miss_latency::total 4857806171 # number of WriteLineReq miss cycles 1076system.iocache.demand_miss_latency::tsunami.ide 4879565054 # number of demand (read+write) miss cycles 1077system.iocache.demand_miss_latency::total 4879565054 # number of demand (read+write) miss cycles 1078system.iocache.overall_miss_latency::tsunami.ide 4879565054 # number of overall miss cycles 1079system.iocache.overall_miss_latency::total 4879565054 # number of overall miss cycles |
| 1063system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1064system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1065system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1066system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1067system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1068system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1069system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1070system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1071system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1072system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1073system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1074system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1075system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1076system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1077system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1078system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1080system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1081system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1082system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1083system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1084system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1085system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1086system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1087system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 1088system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1089system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1090system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1091system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1092system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1093system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1094system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1095system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1079system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency 1080system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency 1081system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.718233 # average WriteLineReq miss latency 1082system.iocache.WriteLineReq_avg_miss_latency::total 126220.718233 # average WriteLineReq miss latency 1083system.iocache.demand_avg_miss_latency::tsunami.ide 126218.482133 # average overall miss latency 1084system.iocache.demand_avg_miss_latency::total 126218.482133 # average overall miss latency 1085system.iocache.overall_avg_miss_latency::tsunami.ide 126218.482133 # average overall miss latency 1086system.iocache.overall_avg_miss_latency::total 126218.482133 # average overall miss latency 1087system.iocache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked | 1096system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125773.890173 # average ReadReq miss latency 1097system.iocache.ReadReq_avg_miss_latency::total 125773.890173 # average ReadReq miss latency 1098system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116909.081897 # average WriteLineReq miss latency 1099system.iocache.WriteLineReq_avg_miss_latency::total 116909.081897 # average WriteLineReq miss latency 1100system.iocache.demand_avg_miss_latency::tsunami.ide 116945.837124 # average overall miss latency 1101system.iocache.demand_avg_miss_latency::total 116945.837124 # average overall miss latency 1102system.iocache.overall_avg_miss_latency::tsunami.ide 116945.837124 # average overall miss latency 1103system.iocache.overall_avg_miss_latency::total 116945.837124 # average overall miss latency 1104system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 1088system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1105system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1089system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked | 1106system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 1090system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1107system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1091system.iocache.avg_blocked_cycles::no_mshrs 14.500000 # average number of cycles each access was blocked | 1108system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 1092system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1093system.iocache.writebacks::writebacks 41512 # number of writebacks 1094system.iocache.writebacks::total 41512 # number of writebacks 1095system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1096system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1097system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1098system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1099system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1100system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1101system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1102system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 1109system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1110system.iocache.writebacks::writebacks 41512 # number of writebacks 1111system.iocache.writebacks::total 41512 # number of writebacks 1112system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1113system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1114system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1115system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1116system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1117system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1118system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1119system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 1103system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles 1104system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles 1105system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165324984 # number of WriteLineReq MSHR miss cycles 1106system.iocache.WriteLineReq_mshr_miss_latency::total 3165324984 # number of WriteLineReq MSHR miss cycles 1107system.iocache.demand_mshr_miss_latency::tsunami.ide 3178417867 # number of demand (read+write) MSHR miss cycles 1108system.iocache.demand_mshr_miss_latency::total 3178417867 # number of demand (read+write) MSHR miss cycles 1109system.iocache.overall_mshr_miss_latency::tsunami.ide 3178417867 # number of overall MSHR miss cycles 1110system.iocache.overall_mshr_miss_latency::total 3178417867 # number of overall MSHR miss cycles | 1120system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13108883 # number of ReadReq MSHR miss cycles 1121system.iocache.ReadReq_mshr_miss_latency::total 13108883 # number of ReadReq MSHR miss cycles 1122system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2777800981 # number of WriteLineReq MSHR miss cycles 1123system.iocache.WriteLineReq_mshr_miss_latency::total 2777800981 # number of WriteLineReq MSHR miss cycles 1124system.iocache.demand_mshr_miss_latency::tsunami.ide 2790909864 # number of demand (read+write) MSHR miss cycles 1125system.iocache.demand_mshr_miss_latency::total 2790909864 # number of demand (read+write) MSHR miss cycles 1126system.iocache.overall_mshr_miss_latency::tsunami.ide 2790909864 # number of overall MSHR miss cycles 1127system.iocache.overall_mshr_miss_latency::total 2790909864 # number of overall MSHR miss cycles |
| 1111system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1112system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1113system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1114system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1115system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1116system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1117system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1118system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1128system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1129system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1130system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1131system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1132system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1133system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1134system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1135system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1119system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency 1120system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency 1121system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.439931 # average WriteLineReq mshr miss latency 1122system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.439931 # average WriteLineReq mshr miss latency 1123system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.383271 # average overall mshr miss latency 1124system.iocache.demand_avg_mshr_miss_latency::total 76175.383271 # average overall mshr miss latency 1125system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.383271 # average overall mshr miss latency 1126system.iocache.overall_avg_mshr_miss_latency::total 76175.383271 # average overall mshr miss latency 1127system.membus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states | 1136system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75773.890173 # average ReadReq mshr miss latency 1137system.iocache.ReadReq_avg_mshr_miss_latency::total 75773.890173 # average ReadReq mshr miss latency 1138system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66851.198041 # average WriteLineReq mshr miss latency 1139system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66851.198041 # average WriteLineReq mshr miss latency 1140system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66888.193265 # average overall mshr miss latency 1141system.iocache.demand_avg_mshr_miss_latency::total 66888.193265 # average overall mshr miss latency 1142system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66888.193265 # average overall mshr miss latency 1143system.iocache.overall_avg_mshr_miss_latency::total 66888.193265 # average overall mshr miss latency 1144system.membus.snoop_filter.tot_requests 821076 # Total number of requests made to the snoop filter. 1145system.membus.snoop_filter.hit_single_requests 378187 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1146system.membus.snoop_filter.hit_multi_requests 407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1147system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1148system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1149system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1150system.membus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states |
| 1128system.membus.trans_dist::ReadReq 6930 # Transaction distribution | 1151system.membus.trans_dist::ReadReq 6930 # Transaction distribution |
| 1129system.membus.trans_dist::ReadResp 292274 # Transaction distribution 1130system.membus.trans_dist::WriteReq 9653 # Transaction distribution 1131system.membus.trans_dist::WriteResp 9653 # Transaction distribution 1132system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution 1133system.membus.trans_dist::CleanEvict 261560 # Transaction distribution 1134system.membus.trans_dist::UpgradeReq 150 # Transaction distribution | 1152system.membus.trans_dist::ReadResp 292275 # Transaction distribution 1153system.membus.trans_dist::WriteReq 9650 # Transaction distribution 1154system.membus.trans_dist::WriteResp 9650 # Transaction distribution 1155system.membus.trans_dist::WritebackDirty 115758 # Transaction distribution 1156system.membus.trans_dist::CleanEvict 261593 # Transaction distribution 1157system.membus.trans_dist::UpgradeReq 136 # Transaction distribution |
| 1135system.membus.trans_dist::UpgradeResp 2 # Transaction distribution | 1158system.membus.trans_dist::UpgradeResp 2 # Transaction distribution |
| 1136system.membus.trans_dist::ReadExReq 116683 # Transaction distribution 1137system.membus.trans_dist::ReadExResp 116683 # Transaction distribution 1138system.membus.trans_dist::ReadSharedReq 285344 # Transaction distribution | 1159system.membus.trans_dist::ReadExReq 116680 # Transaction distribution 1160system.membus.trans_dist::ReadExResp 116680 # Transaction distribution 1161system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution |
| 1139system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution | 1162system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| 1140system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) 1141system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139255 # Packet count per connected master and slave (bytes) 1142system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172421 # Packet count per connected master and slave (bytes) | 1163system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) 1164system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139235 # Packet count per connected master and slave (bytes) 1165system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172395 # Packet count per connected master and slave (bytes) |
| 1143system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1144system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) | 1166system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) 1167system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) |
| 1145system.membus.pkt_count::total 1255846 # Packet count per connected master and slave (bytes) 1146system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) 1147system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455296 # Cumulative packet size per connected master and slave (bytes) 1148system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499884 # Cumulative packet size per connected master and slave (bytes) | 1168system.membus.pkt_count::total 1255820 # Packet count per connected master and slave (bytes) 1169system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) 1170system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30452928 # Cumulative packet size per connected master and slave (bytes) 1171system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30497492 # Cumulative packet size per connected master and slave (bytes) |
| 1149system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1150system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) | 1172system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1173system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) |
| 1151system.membus.pkt_size::total 33157612 # Cumulative packet size per connected master and slave (bytes) | 1174system.membus.pkt_size::total 33155220 # Cumulative packet size per connected master and slave (bytes) |
| 1152system.membus.snoops 431 # Total snoops (count) 1153system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) | 1175system.membus.snoops 431 # Total snoops (count) 1176system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) |
| 1154system.membus.snoop_fanout::samples 837673 # Request fanout histogram 1155system.membus.snoop_fanout::mean 1 # Request fanout histogram 1156system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 1177system.membus.snoop_fanout::samples 460293 # Request fanout histogram 1178system.membus.snoop_fanout::mean 0.001416 # Request fanout histogram 1179system.membus.snoop_fanout::stdev 0.037610 # Request fanout histogram |
| 1157system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1180system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1158system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1159system.membus.snoop_fanout::1 837673 100.00% 100.00% # Request fanout histogram | 1181system.membus.snoop_fanout::0 459641 99.86% 99.86% # Request fanout histogram 1182system.membus.snoop_fanout::1 652 0.14% 100.00% # Request fanout histogram |
| 1160system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1161system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1183system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1184system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1162system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 1185system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| 1163system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1186system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1164system.membus.snoop_fanout::total 837673 # Request fanout histogram 1165system.membus.reqLayer0.occupancy 30123000 # Layer occupancy (ticks) | 1187system.membus.snoop_fanout::total 460293 # Request fanout histogram 1188system.membus.reqLayer0.occupancy 30118500 # Layer occupancy (ticks) |
| 1166system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1189system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1167system.membus.reqLayer1.occupancy 1287200717 # Layer occupancy (ticks) | 1190system.membus.reqLayer1.occupancy 1286935040 # Layer occupancy (ticks) |
| 1168system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1191system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1169system.membus.respLayer1.occupancy 2143013000 # Layer occupancy (ticks) | 1192system.membus.respLayer1.occupancy 2142767250 # Layer occupancy (ticks) |
| 1170system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1171system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) 1172system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1193system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1194system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) 1195system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1173system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1174system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1175system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1176system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1177system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states | 1196system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1197system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1198system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1199system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1200system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states |
| 1178system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1179system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1180system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1181system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1182system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1183system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1184system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1185system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1201system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1202system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1203system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1204system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1205system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1206system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1207system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1208system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 1201system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1202system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1203system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1204system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1205system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1206system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1207system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1208system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1224system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1225system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1226system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1227system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1228system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1229system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1230system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1231system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 1209system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1210system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1211system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1212system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1213system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1214system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1215system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1216system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1217system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1218system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1219system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1220system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1221system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1222system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1223system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1224system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1225system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1226system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1227system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1228system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1229system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1230system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1231system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states | 1232system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1233system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1234system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1235system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1236system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1237system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1238system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1239system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1240system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1241system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1242system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1243system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1244system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1245system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1246system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1247system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1248system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1249system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1250system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1251system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1252system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1253system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states 1254system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states |
| 1232 1233---------- End Simulation Statistics ---------- | 1255 1256---------- End Simulation Statistics ---------- |