| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.941276 # Number of seconds simulated 4sim_ticks 1941275996000 # Number of ticks simulated 5final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.941276 # Number of seconds simulated 4sim_ticks 1941275996000 # Number of ticks simulated 5final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1255554 # Simulator instruction rate (inst/s) 8host_op_rate 1255553 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43383023327 # Simulator tick rate (ticks/s) 10host_mem_usage 332188 # Number of bytes of host memory used 11host_seconds 44.75 # Real time elapsed on the host | 7host_inst_rate 1048317 # Simulator instruction rate (inst/s) 8host_op_rate 1048317 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36222399744 # Simulator tick rate (ticks/s) 10host_mem_usage 330588 # Number of bytes of host memory used 11host_seconds 53.59 # Real time elapsed on the host |
| 12sim_insts 56182685 # Number of instructions simulated 13sim_ops 56182685 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory --- 535 unchanged lines hidden (view full) --- 555system.cpu.dcache.overall_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency 556system.cpu.dcache.overall_avg_miss_latency::total 45430.915799 # average overall miss latency 557system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 558system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 559system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 560system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 561system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 562system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 56182685 # Number of instructions simulated 13sim_ops 56182685 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory --- 535 unchanged lines hidden (view full) --- 555system.cpu.dcache.overall_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency 556system.cpu.dcache.overall_avg_miss_latency::total 45430.915799 # average overall miss latency 557system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 558system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 559system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 560system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 561system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 562system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 563system.cpu.dcache.fast_writes 0 # number of fast writes performed 564system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 565system.cpu.dcache.writebacks::writebacks 834944 # number of writebacks 566system.cpu.dcache.writebacks::total 834944 # number of writebacks 567system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069359 # number of ReadReq MSHR misses 568system.cpu.dcache.ReadReq_mshr_misses::total 1069359 # number of ReadReq MSHR misses 569system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304327 # number of WriteReq MSHR misses 570system.cpu.dcache.WriteReq_mshr_misses::total 304327 # number of WriteReq MSHR misses 571system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17246 # number of LoadLockedReq MSHR misses 572system.cpu.dcache.LoadLockedReq_mshr_misses::total 17246 # number of LoadLockedReq MSHR misses --- 14 unchanged lines hidden (view full) --- 587system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215551500 # number of LoadLockedReq MSHR miss cycles 588system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215551500 # number of LoadLockedReq MSHR miss cycles 589system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61034127000 # number of demand (read+write) MSHR miss cycles 590system.cpu.dcache.demand_mshr_miss_latency::total 61034127000 # number of demand (read+write) MSHR miss cycles 591system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61034127000 # number of overall MSHR miss cycles 592system.cpu.dcache.overall_mshr_miss_latency::total 61034127000 # number of overall MSHR miss cycles 593system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526978500 # number of ReadReq MSHR uncacheable cycles 594system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526978500 # number of ReadReq MSHR uncacheable cycles | 563system.cpu.dcache.writebacks::writebacks 834944 # number of writebacks 564system.cpu.dcache.writebacks::total 834944 # number of writebacks 565system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069359 # number of ReadReq MSHR misses 566system.cpu.dcache.ReadReq_mshr_misses::total 1069359 # number of ReadReq MSHR misses 567system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304327 # number of WriteReq MSHR misses 568system.cpu.dcache.WriteReq_mshr_misses::total 304327 # number of WriteReq MSHR misses 569system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17246 # number of LoadLockedReq MSHR misses 570system.cpu.dcache.LoadLockedReq_mshr_misses::total 17246 # number of LoadLockedReq MSHR misses --- 14 unchanged lines hidden (view full) --- 585system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215551500 # number of LoadLockedReq MSHR miss cycles 586system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215551500 # number of LoadLockedReq MSHR miss cycles 587system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61034127000 # number of demand (read+write) MSHR miss cycles 588system.cpu.dcache.demand_mshr_miss_latency::total 61034127000 # number of demand (read+write) MSHR miss cycles 589system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61034127000 # number of overall MSHR miss cycles 590system.cpu.dcache.overall_mshr_miss_latency::total 61034127000 # number of overall MSHR miss cycles 591system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526978500 # number of ReadReq MSHR uncacheable cycles 592system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526978500 # number of ReadReq MSHR uncacheable cycles |
| 595system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172486500 # number of WriteReq MSHR uncacheable cycles 596system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172486500 # number of WriteReq MSHR uncacheable cycles 597system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699465000 # number of overall MSHR uncacheable cycles 598system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699465000 # number of overall MSHR uncacheable cycles | 593system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1526978500 # number of overall MSHR uncacheable cycles 594system.cpu.dcache.overall_mshr_uncacheable_latency::total 1526978500 # number of overall MSHR uncacheable cycles |
| 599system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120373 # mshr miss rate for ReadReq accesses 600system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120373 # mshr miss rate for ReadReq accesses 601system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses 602system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses 603system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086109 # mshr miss rate for LoadLockedReq accesses 604system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086109 # mshr miss rate for LoadLockedReq accesses 605system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses 606system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses --- 6 unchanged lines hidden (view full) --- 613system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.637365 # average LoadLockedReq mshr miss latency 614system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.637365 # average LoadLockedReq mshr miss latency 615system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency 616system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency 617system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency 618system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency 619system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency 620system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency | 595system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120373 # mshr miss rate for ReadReq accesses 596system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120373 # mshr miss rate for ReadReq accesses 597system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses 598system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses 599system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086109 # mshr miss rate for LoadLockedReq accesses 600system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086109 # mshr miss rate for LoadLockedReq accesses 601system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses 602system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses --- 6 unchanged lines hidden (view full) --- 609system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.637365 # average LoadLockedReq mshr miss latency 610system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.637365 # average LoadLockedReq mshr miss latency 611system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency 612system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency 613system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency 614system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency 615system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency 616system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency |
| 621system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225058.168445 # average WriteReq mshr uncacheable latency 622system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225058.168445 # average WriteReq mshr uncacheable latency 623system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223087.800760 # average overall mshr uncacheable latency 624system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223087.800760 # average overall mshr uncacheable latency 625system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 617system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401 # average overall mshr uncacheable latency 618system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401 # average overall mshr uncacheable latency |
| 626system.cpu.icache.tags.replacements 928931 # number of replacements 627system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use 628system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks. 629system.cpu.icache.tags.sampled_refs 929442 # Sample count of references to valid blocks. 630system.cpu.icache.tags.avg_refs 59.460318 # Average number of references to valid blocks. 631system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. 632system.cpu.icache.tags.occ_blocks::cpu.inst 506.355616 # Average occupied blocks per requestor 633system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 677system.cpu.icache.overall_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency 678system.cpu.icache.overall_avg_miss_latency::total 14722.555459 # average overall miss latency 679system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 680system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 681system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 682system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 683system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 684system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 619system.cpu.icache.tags.replacements 928931 # number of replacements 620system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use 621system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks. 622system.cpu.icache.tags.sampled_refs 929442 # Sample count of references to valid blocks. 623system.cpu.icache.tags.avg_refs 59.460318 # Average number of references to valid blocks. 624system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. 625system.cpu.icache.tags.occ_blocks::cpu.inst 506.355616 # Average occupied blocks per requestor 626system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 670system.cpu.icache.overall_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency 671system.cpu.icache.overall_avg_miss_latency::total 14722.555459 # average overall miss latency 672system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 673system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 674system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 675system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 676system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 677system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 685system.cpu.icache.fast_writes 0 # number of fast writes performed 686system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 687system.cpu.icache.writebacks::writebacks 928931 # number of writebacks 688system.cpu.icache.writebacks::total 928931 # number of writebacks 689system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929602 # number of ReadReq MSHR misses 690system.cpu.icache.ReadReq_mshr_misses::total 929602 # number of ReadReq MSHR misses 691system.cpu.icache.demand_mshr_misses::cpu.inst 929602 # number of demand (read+write) MSHR misses 692system.cpu.icache.demand_mshr_misses::total 929602 # number of demand (read+write) MSHR misses 693system.cpu.icache.overall_mshr_misses::cpu.inst 929602 # number of overall MSHR misses 694system.cpu.icache.overall_mshr_misses::total 929602 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 705system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses 706system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses 707system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459 # average ReadReq mshr miss latency 708system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459 # average ReadReq mshr miss latency 709system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency 710system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency 711system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency 712system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency | 678system.cpu.icache.writebacks::writebacks 928931 # number of writebacks 679system.cpu.icache.writebacks::total 928931 # number of writebacks 680system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929602 # number of ReadReq MSHR misses 681system.cpu.icache.ReadReq_mshr_misses::total 929602 # number of ReadReq MSHR misses 682system.cpu.icache.demand_mshr_misses::cpu.inst 929602 # number of demand (read+write) MSHR misses 683system.cpu.icache.demand_mshr_misses::total 929602 # number of demand (read+write) MSHR misses 684system.cpu.icache.overall_mshr_misses::cpu.inst 929602 # number of overall MSHR misses 685system.cpu.icache.overall_mshr_misses::total 929602 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 696system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses 697system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses 698system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459 # average ReadReq mshr miss latency 699system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459 # average ReadReq mshr miss latency 700system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency 701system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency 702system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency 703system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency |
| 713system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 714system.cpu.l2cache.tags.replacements 336393 # number of replacements 715system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use 716system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks. 717system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. 718system.cpu.l2cache.tags.avg_refs 9.787932 # Average number of references to valid blocks. 719system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. 720system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820493 # Average occupied blocks per requestor 721system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.121272 # Average occupied blocks per requestor --- 104 unchanged lines hidden (view full) --- 826system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency 827system.cpu.l2cache.overall_avg_miss_latency::total 125250.023010 # average overall miss latency 828system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 829system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 830system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 831system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 832system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 833system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 704system.cpu.l2cache.tags.replacements 336393 # number of replacements 705system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use 706system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks. 707system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. 708system.cpu.l2cache.tags.avg_refs 9.787932 # Average number of references to valid blocks. 709system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. 710system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820493 # Average occupied blocks per requestor 711system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.121272 # Average occupied blocks per requestor --- 104 unchanged lines hidden (view full) --- 816system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency 817system.cpu.l2cache.overall_avg_miss_latency::total 125250.023010 # average overall miss latency 818system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 819system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 820system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 821system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 822system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 823system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 834system.cpu.l2cache.fast_writes 0 # number of fast writes performed 835system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 836system.cpu.l2cache.writebacks::writebacks 74281 # number of writebacks 837system.cpu.l2cache.writebacks::total 74281 # number of writebacks 838system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 839system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 840system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116820 # number of ReadExReq MSHR misses 841system.cpu.l2cache.ReadExReq_mshr_misses::total 116820 # number of ReadExReq MSHR misses 842system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13200 # number of ReadCleanReq MSHR misses 843system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13200 # number of ReadCleanReq MSHR misses --- 22 unchanged lines hidden (view full) --- 866system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1594796000 # number of demand (read+write) MSHR miss cycles 867system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44734676000 # number of demand (read+write) MSHR miss cycles 868system.cpu.l2cache.demand_mshr_miss_latency::total 46329472000 # number of demand (read+write) MSHR miss cycles 869system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1594796000 # number of overall MSHR miss cycles 870system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44734676000 # number of overall MSHR miss cycles 871system.cpu.l2cache.overall_mshr_miss_latency::total 46329472000 # number of overall MSHR miss cycles 872system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440322500 # number of ReadReq MSHR uncacheable cycles 873system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440322500 # number of ReadReq MSHR uncacheable cycles | 824system.cpu.l2cache.writebacks::writebacks 74281 # number of writebacks 825system.cpu.l2cache.writebacks::total 74281 # number of writebacks 826system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 827system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 828system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116820 # number of ReadExReq MSHR misses 829system.cpu.l2cache.ReadExReq_mshr_misses::total 116820 # number of ReadExReq MSHR misses 830system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13200 # number of ReadCleanReq MSHR misses 831system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13200 # number of ReadCleanReq MSHR misses --- 22 unchanged lines hidden (view full) --- 854system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1594796000 # number of demand (read+write) MSHR miss cycles 855system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44734676000 # number of demand (read+write) MSHR miss cycles 856system.cpu.l2cache.demand_mshr_miss_latency::total 46329472000 # number of demand (read+write) MSHR miss cycles 857system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1594796000 # number of overall MSHR miss cycles 858system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44734676000 # number of overall MSHR miss cycles 859system.cpu.l2cache.overall_mshr_miss_latency::total 46329472000 # number of overall MSHR miss cycles 860system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440322500 # number of ReadReq MSHR uncacheable cycles 861system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440322500 # number of ReadReq MSHR uncacheable cycles |
| 874system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061396500 # number of WriteReq MSHR uncacheable cycles 875system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061396500 # number of WriteReq MSHR uncacheable cycles 876system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501719000 # number of overall MSHR uncacheable cycles 877system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501719000 # number of overall MSHR uncacheable cycles | 862system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1440322500 # number of overall MSHR uncacheable cycles 863system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1440322500 # number of overall MSHR uncacheable cycles |
| 878system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 879system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 880system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses 881system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses 882system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses 883system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses 884system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250294 # mshr miss rate for ReadSharedReq accesses 885system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250294 # mshr miss rate for ReadSharedReq accesses --- 14 unchanged lines hidden (view full) --- 900system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency 901system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency 902system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency 903system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency 904system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency 905system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency 906system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589 # average ReadReq mshr uncacheable latency 907system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589 # average ReadReq mshr uncacheable latency | 864system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 865system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses 866system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses 867system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses 868system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses 869system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses 870system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250294 # mshr miss rate for ReadSharedReq accesses 871system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250294 # mshr miss rate for ReadSharedReq accesses --- 14 unchanged lines hidden (view full) --- 886system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency 887system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency 888system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency 890system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency 891system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency 892system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589 # average ReadReq mshr uncacheable latency 893system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589 # average ReadReq mshr uncacheable latency |
| 908system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213549.829069 # average WriteReq mshr uncacheable latency 909system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213549.829069 # average WriteReq mshr uncacheable latency 910system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211163.179159 # average overall mshr uncacheable latency 911system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211163.179159 # average overall mshr uncacheable latency 912system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 894system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927 # average overall mshr uncacheable latency 895system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927 # average overall mshr uncacheable latency |
| 913system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter. 914system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data. 915system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 916system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. 917system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 918system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 919system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 920system.cpu.toL2Bus.trans_dist::ReadResp 2023294 # Transaction distribution --- 114 unchanged lines hidden (view full) --- 1035system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1036system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1037system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1038system.iocache.tags.data_accesses 375525 # Number of data accesses 1039system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1040system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1041system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1042system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses | 896system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter. 897system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data. 898system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 899system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. 900system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 901system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 902system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 903system.cpu.toL2Bus.trans_dist::ReadResp 2023294 # Transaction distribution --- 114 unchanged lines hidden (view full) --- 1018system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1019system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1020system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1021system.iocache.tags.data_accesses 375525 # Number of data accesses 1022system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1023system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1024system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1025system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses |
| 1043system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1044system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1045system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1046system.iocache.overall_misses::total 173 # number of overall misses | 1026system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1027system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1028system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1029system.iocache.overall_misses::total 41725 # number of overall misses |
| 1047system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles 1048system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles 1049system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244713284 # number of WriteLineReq miss cycles 1050system.iocache.WriteLineReq_miss_latency::total 5244713284 # number of WriteLineReq miss cycles | 1030system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles 1031system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles 1032system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244713284 # number of WriteLineReq miss cycles 1033system.iocache.WriteLineReq_miss_latency::total 5244713284 # number of WriteLineReq miss cycles |
| 1051system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles 1052system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles 1053system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles 1054system.iocache.overall_miss_latency::total 21742883 # number of overall miss cycles | 1034system.iocache.demand_miss_latency::tsunami.ide 5266456167 # number of demand (read+write) miss cycles 1035system.iocache.demand_miss_latency::total 5266456167 # number of demand (read+write) miss cycles 1036system.iocache.overall_miss_latency::tsunami.ide 5266456167 # number of overall miss cycles 1037system.iocache.overall_miss_latency::total 5266456167 # number of overall miss cycles |
| 1055system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1056system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1057system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1058system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) | 1038system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1039system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1040system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1041system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) |
| 1059system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1060system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1061system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1062system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses | 1042system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 1043system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 1044system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 1045system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses |
| 1063system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1064system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1065system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1066system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1067system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1068system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1069system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1070system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1071system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency 1072system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency 1073system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570 # average WriteLineReq miss latency 1074system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570 # average WriteLineReq miss latency | 1046system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1047system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1048system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1049system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1050system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1051system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1052system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1053system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1054system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency 1055system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency 1056system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570 # average WriteLineReq miss latency 1057system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570 # average WriteLineReq miss latency |
| 1075system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency 1076system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency 1077system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency 1078system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency | 1058system.iocache.demand_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency 1059system.iocache.demand_avg_miss_latency::total 126218.242469 # average overall miss latency 1060system.iocache.overall_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency 1061system.iocache.overall_avg_miss_latency::total 126218.242469 # average overall miss latency |
| 1079system.iocache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked 1080system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1081system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 1082system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1083system.iocache.avg_blocked_cycles::no_mshrs 14.500000 # average number of cycles each access was blocked 1084system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1062system.iocache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked 1063system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1064system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked 1065system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1066system.iocache.avg_blocked_cycles::no_mshrs 14.500000 # average number of cycles each access was blocked 1067system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1085system.iocache.fast_writes 0 # number of fast writes performed 1086system.iocache.cache_copies 0 # number of cache copies performed | |
| 1087system.iocache.writebacks::writebacks 41512 # number of writebacks 1088system.iocache.writebacks::total 41512 # number of writebacks 1089system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1090system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1091system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1092system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses | 1068system.iocache.writebacks::writebacks 41512 # number of writebacks 1069system.iocache.writebacks::total 41512 # number of writebacks 1070system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1071system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1072system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1073system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses |
| 1093system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1094system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1095system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1096system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses | 1074system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 1075system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 1076system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 1077system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 1097system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles 1098system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles 1099system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165314984 # number of WriteLineReq MSHR miss cycles 1100system.iocache.WriteLineReq_mshr_miss_latency::total 3165314984 # number of WriteLineReq MSHR miss cycles | 1078system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles 1079system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles 1080system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165314984 # number of WriteLineReq MSHR miss cycles 1081system.iocache.WriteLineReq_mshr_miss_latency::total 3165314984 # number of WriteLineReq MSHR miss cycles |
| 1101system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles 1102system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles 1103system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles 1104system.iocache.overall_mshr_miss_latency::total 13092883 # number of overall MSHR miss cycles | 1082system.iocache.demand_mshr_miss_latency::tsunami.ide 3178407867 # number of demand (read+write) MSHR miss cycles 1083system.iocache.demand_mshr_miss_latency::total 3178407867 # number of demand (read+write) MSHR miss cycles 1084system.iocache.overall_mshr_miss_latency::tsunami.ide 3178407867 # number of overall MSHR miss cycles 1085system.iocache.overall_mshr_miss_latency::total 3178407867 # number of overall MSHR miss cycles |
| 1105system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1106system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1107system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1108system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1109system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1110system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1111system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1112system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1113system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency 1114system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency 1115system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency 1116system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency | 1086system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1087system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1088system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1089system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1090system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1091system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1092system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1093system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1094system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency 1095system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency 1096system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency 1097system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency |
| 1117system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency 1118system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency 1119system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency 1120system.iocache.overall_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency 1121system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1098system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency 1099system.iocache.demand_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency 1100system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency 1101system.iocache.overall_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency |
| 1122system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1123system.membus.trans_dist::ReadResp 292274 # Transaction distribution 1124system.membus.trans_dist::WriteReq 9653 # Transaction distribution 1125system.membus.trans_dist::WriteResp 9653 # Transaction distribution 1126system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution 1127system.membus.trans_dist::CleanEvict 261560 # Transaction distribution 1128system.membus.trans_dist::UpgradeReq 150 # Transaction distribution 1129system.membus.trans_dist::UpgradeResp 2 # Transaction distribution --- 69 unchanged lines hidden --- | 1102system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1103system.membus.trans_dist::ReadResp 292274 # Transaction distribution 1104system.membus.trans_dist::WriteReq 9653 # Transaction distribution 1105system.membus.trans_dist::WriteResp 9653 # Transaction distribution 1106system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution 1107system.membus.trans_dist::CleanEvict 261560 # Transaction distribution 1108system.membus.trans_dist::UpgradeReq 150 # Transaction distribution 1109system.membus.trans_dist::UpgradeResp 2 # Transaction distribution --- 69 unchanged lines hidden --- |