| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.922397 # Number of seconds simulated 4sim_ticks 1922397182500 # Number of ticks simulated 5final_tick 1922397182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.941266 # Number of seconds simulated 4sim_ticks 1941266487500 # Number of ticks simulated 5final_tick 1941266487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1085217 # Simulator instruction rate (inst/s) 8host_op_rate 1085217 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37124537063 # Simulator tick rate (ticks/s) 10host_mem_usage 372212 # Number of bytes of host memory used 11host_seconds 51.78 # Real time elapsed on the host 12sim_insts 56195121 # Number of instructions simulated 13sim_ops 56195121 # Number of ops (including micro ops) simulated | 7host_inst_rate 1056307 # Simulator instruction rate (inst/s) 8host_op_rate 1056307 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36524098946 # Simulator tick rate (ticks/s) 10host_mem_usage 374096 # Number of bytes of host memory used 11host_seconds 53.15 # Real time elapsed on the host 12sim_insts 56143021 # Number of instructions simulated 13sim_ops 56143021 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 848768 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24858048 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 848832 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24855488 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 25707776 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 848768 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 848768 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7409088 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7409088 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 13262 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388407 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 25705280 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 848832 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 848832 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7407552 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7407552 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 13263 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388367 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::total 401684 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115767 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115767 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 441515 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 12930756 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 13372770 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 441515 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 441515 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 3854088 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 3854088 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 3854088 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 441515 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 12930756 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17226858 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 401684 # Number of read requests accepted 44system.physmem.writeReqs 115767 # Number of write requests accepted 45system.physmem.readBursts 401684 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 115767 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25700352 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7407168 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25707776 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7409088 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue | 27system.physmem.num_reads::total 401645 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115743 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115743 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 437257 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 12803749 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 13241500 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 437257 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 437257 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 3815835 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 3815835 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 3815835 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 437257 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 12803749 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17057335 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 401645 # Number of read requests accepted 44system.physmem.writeReqs 115743 # Number of write requests accepted 45system.physmem.readBursts 401645 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 115743 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25697728 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7406016 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25705280 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7407552 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue |
| 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write | 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write |
| 55system.physmem.perBankRdBursts::0 25233 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25641 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25574 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25503 # Per bank write bursts 59system.physmem.perBankRdBursts::4 24973 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24969 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24206 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24501 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25169 # Per bank write bursts 64system.physmem.perBankRdBursts::9 24770 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25259 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24898 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24500 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25360 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25653 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25359 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7624 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7642 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7864 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7542 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7123 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6988 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6319 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6328 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7314 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6525 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7109 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6927 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7069 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7821 # Per bank write bursts 85system.physmem.perBankWrBursts::14 7867 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7675 # Per bank write bursts | 55system.physmem.perBankRdBursts::0 25168 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25510 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25518 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25527 # Per bank write bursts 59system.physmem.perBankRdBursts::4 25065 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24960 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24241 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24604 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25078 # Per bank write bursts 64system.physmem.perBankRdBursts::9 24653 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25359 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24824 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24407 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25357 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25770 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25486 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7561 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7519 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7810 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7560 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7221 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6978 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6351 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6424 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7248 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6410 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7207 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6855 # Per bank write bursts 83system.physmem.perBankWrBursts::12 6980 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7819 # Per bank write bursts 85system.physmem.perBankWrBursts::14 7982 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7794 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 88system.physmem.numWrRetry 15 # Number of times write queue was full causing retry 89system.physmem.totGap 1922385313500 # Total gap between requests | 88system.physmem.numWrRetry 23 # Number of times write queue was full causing retry 89system.physmem.totGap 1941254508500 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 401684 # Read request sizes (log2) | 96system.physmem.readPktSize::6 401645 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 115767 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 401554 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 115743 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 401513 # What read queue length does an incoming req see |
| 105system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see --- 30 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 105system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see --- 30 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 1797 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 6091 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 5828 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 6150 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 6866 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 7083 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 9305 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 8529 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 7247 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 6596 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6432 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 6732 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 5761 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 5438 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5376 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 262 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 166 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 199 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 167 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 220 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 130 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 145 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 48 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 64336 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 514.603333 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 307.690032 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 416.700723 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 15764 24.50% 24.50% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 11265 17.51% 42.01% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 5118 7.96% 49.97% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3016 4.69% 54.66% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2317 3.60% 58.26% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1789 2.78% 61.04% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1464 2.28% 63.31% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1374 2.14% 65.45% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 22229 34.55% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 64336 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5099 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 78.750735 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2955.508201 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5096 99.94% 99.94% # Reads before turning the bus around for writes | 151system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 2226 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 5414 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 6011 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 6311 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5840 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 6199 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 7562 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 8014 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 8956 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 8190 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8289 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 6616 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 5981 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 5547 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5325 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 247 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 263 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 188 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 194 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 173 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 64921 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 509.908104 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 310.461658 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 406.215984 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 15228 23.46% 23.46% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 11644 17.94% 41.39% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4997 7.70% 49.09% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 2980 4.59% 53.68% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 2446 3.77% 57.45% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 4228 6.51% 63.96% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1452 2.24% 66.20% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.37% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 19883 30.63% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 64921 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5102 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 78.697570 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2954.645683 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5099 99.94% 99.94% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::total 5099 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5099 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 22.697980 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 19.062005 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 23.025558 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-19 4477 87.80% 87.80% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20-23 19 0.37% 88.17% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24-27 190 3.73% 91.90% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::28-31 14 0.27% 92.17% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::32-35 27 0.53% 92.70% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::36-39 53 1.04% 93.74% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::40-43 14 0.27% 94.02% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::44-47 3 0.06% 94.08% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::48-51 6 0.12% 94.19% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::52-55 3 0.06% 94.25% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::56-59 3 0.06% 94.31% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::60-63 3 0.06% 94.37% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::64-67 8 0.16% 94.53% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::68-71 3 0.06% 94.59% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::72-75 2 0.04% 94.63% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::76-79 10 0.20% 94.82% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::84-87 4 0.08% 94.90% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::88-91 16 0.31% 95.21% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::92-95 21 0.41% 95.63% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::96-99 18 0.35% 95.98% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::100-103 148 2.90% 98.88% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-107 12 0.24% 99.12% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::108-111 1 0.02% 99.14% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::112-115 1 0.02% 99.16% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::124-127 1 0.02% 99.18% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::128-131 3 0.06% 99.24% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::144-147 1 0.02% 99.25% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::152-155 2 0.04% 99.29% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::164-167 5 0.10% 99.41% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::168-171 2 0.04% 99.45% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::172-175 4 0.08% 99.53% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::176-179 1 0.02% 99.55% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::180-183 4 0.08% 99.63% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::184-187 5 0.10% 99.73% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::192-195 1 0.02% 99.75% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::196-199 3 0.06% 99.80% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::200-203 2 0.04% 99.84% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::212-215 1 0.02% 99.86% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::216-219 1 0.02% 99.88% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::224-227 1 0.02% 99.90% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::228-231 5 0.10% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::total 5099 # Writes before turning the bus around for reads 269system.physmem.totQLat 2147063750 # Total ticks spent queuing 270system.physmem.totMemAccLat 9676463750 # Total ticks spent from burst creation until serviced by the DRAM 271system.physmem.totBusLat 2007840000 # Total ticks spent in databus transfers 272system.physmem.avgQLat 5346.70 # Average queueing delay per DRAM burst | 221system.physmem.rdPerTurnAround::total 5102 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5102 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 22.681105 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 19.154688 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 22.203626 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-23 4492 88.04% 88.04% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::24-31 201 3.94% 91.98% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::32-39 29 0.57% 92.55% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-47 48 0.94% 93.49% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::48-55 38 0.74% 94.24% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::56-63 6 0.12% 94.36% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::64-71 11 0.22% 94.57% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::72-79 38 0.74% 95.32% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::80-87 34 0.67% 95.98% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::88-95 1 0.02% 96.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::96-103 159 3.12% 99.12% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::112-119 2 0.04% 99.16% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::120-127 2 0.04% 99.20% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::128-135 5 0.10% 99.29% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::136-143 1 0.02% 99.31% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::144-151 2 0.04% 99.35% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::152-159 3 0.06% 99.41% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::160-167 3 0.06% 99.47% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::168-175 4 0.08% 99.55% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::176-183 8 0.16% 99.71% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::184-191 4 0.08% 99.78% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::192-199 3 0.06% 99.84% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::200-207 1 0.02% 99.86% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::208-215 2 0.04% 99.90% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::224-231 4 0.08% 99.98% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::total 5102 # Writes before turning the bus around for reads 253system.physmem.totQLat 2705942000 # Total ticks spent queuing 254system.physmem.totMemAccLat 10234573250 # Total ticks spent from burst creation until serviced by the DRAM 255system.physmem.totBusLat 2007635000 # Total ticks spent in databus transfers 256system.physmem.avgQLat 6739.13 # Average queueing delay per DRAM burst |
| 273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 257system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 274system.physmem.avgMemAccLat 24096.70 # Average memory access latency per DRAM burst 275system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s 276system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s 277system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s 278system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s | 258system.physmem.avgMemAccLat 25489.13 # Average memory access latency per DRAM burst 259system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s 260system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s 261system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s 262system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s |
| 279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 280system.physmem.busUtil 0.13 # Data bus utilization in percentage 281system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 282system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 283system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 263system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 264system.physmem.busUtil 0.13 # Data bus utilization in percentage 265system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 266system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 267system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 284system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing 285system.physmem.readRowHits 359411 # Number of row buffer hits during reads 286system.physmem.writeRowHits 93558 # Number of row buffer hits during writes 287system.physmem.readRowHitRate 89.50 # Row buffer hit rate for reads 288system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes 289system.physmem.avgGap 3715106.00 # Average gap between requests 290system.physmem.pageHitRate 87.56 # Row buffer hit rate, read and write combined 291system.physmem_0.actEnergy 236030760 # Energy for activate commands per rank (pJ) 292system.physmem_0.preEnergy 128786625 # Energy for precharge commands per rank (pJ) 293system.physmem_0.readEnergy 1564680000 # Energy for read commands per rank (pJ) 294system.physmem_0.writeEnergy 372146400 # Energy for write commands per rank (pJ) 295system.physmem_0.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) 296system.physmem_0.actBackEnergy 64059295815 # Energy for active background per rank (pJ) 297system.physmem_0.preBackEnergy 1097244171000 # Energy for precharge background per rank (pJ) 298system.physmem_0.totalEnergy 1289166540360 # Total energy per rank (pJ) 299system.physmem_0.averagePower 670.604667 # Core power per rank (mW) 300system.physmem_0.memoryStateTime::IDLE 1825128497250 # Time in different power states 301system.physmem_0.memoryStateTime::REF 64192960000 # Time in different power states | 268system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing 269system.physmem.readRowHits 358859 # Number of row buffer hits during reads 270system.physmem.writeRowHits 93466 # Number of row buffer hits during writes 271system.physmem.readRowHitRate 89.37 # Row buffer hit rate for reads 272system.physmem.writeRowHitRate 80.75 # Row buffer hit rate for writes 273system.physmem.avgGap 3752028.47 # Average gap between requests 274system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined 275system.physmem_0.actEnergy 239349600 # Energy for activate commands per rank (pJ) 276system.physmem_0.preEnergy 130597500 # Energy for precharge commands per rank (pJ) 277system.physmem_0.readEnergy 1564625400 # Energy for read commands per rank (pJ) 278system.physmem_0.writeEnergy 372107520 # Energy for write commands per rank (pJ) 279system.physmem_0.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) 280system.physmem_0.actBackEnergy 71640444015 # Energy for active background per rank (pJ) 281system.physmem_0.preBackEnergy 1101913691250 # Energy for precharge background per rank (pJ) 282system.physmem_0.totalEnergy 1302654485925 # Total energy per rank (pJ) 283system.physmem_0.averagePower 671.035450 # Core power per rank (mW) 284system.physmem_0.memoryStateTime::IDLE 1832853481750 # Time in different power states 285system.physmem_0.memoryStateTime::REF 64822940000 # Time in different power states |
| 302system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 286system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 303system.physmem_0.memoryStateTime::ACT 33072782750 # Time in different power states | 287system.physmem_0.memoryStateTime::ACT 43583902000 # Time in different power states |
| 304system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 288system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 305system.physmem_1.actEnergy 250349400 # Energy for activate commands per rank (pJ) 306system.physmem_1.preEnergy 136599375 # Energy for precharge commands per rank (pJ) 307system.physmem_1.readEnergy 1567550400 # Energy for read commands per rank (pJ) 308system.physmem_1.writeEnergy 377829360 # Energy for write commands per rank (pJ) 309system.physmem_1.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) 310system.physmem_1.actBackEnergy 65774789190 # Energy for active background per rank (pJ) 311system.physmem_1.preBackEnergy 1095739352250 # Energy for precharge background per rank (pJ) 312system.physmem_1.totalEnergy 1289407899735 # Total energy per rank (pJ) 313system.physmem_1.averagePower 670.730219 # Core power per rank (mW) 314system.physmem_1.memoryStateTime::IDLE 1822618194250 # Time in different power states 315system.physmem_1.memoryStateTime::REF 64192960000 # Time in different power states | 289system.physmem_1.actEnergy 251453160 # Energy for activate commands per rank (pJ) 290system.physmem_1.preEnergy 137201625 # Energy for precharge commands per rank (pJ) 291system.physmem_1.readEnergy 1567285200 # Energy for read commands per rank (pJ) 292system.physmem_1.writeEnergy 377751600 # Energy for write commands per rank (pJ) 293system.physmem_1.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) 294system.physmem_1.actBackEnergy 72584952255 # Energy for active background per rank (pJ) 295system.physmem_1.preBackEnergy 1101085183500 # Energy for precharge background per rank (pJ) 296system.physmem_1.totalEnergy 1302797497980 # Total energy per rank (pJ) 297system.physmem_1.averagePower 671.109115 # Core power per rank (mW) 298system.physmem_1.memoryStateTime::IDLE 1831469435000 # Time in different power states 299system.physmem_1.memoryStateTime::REF 64822940000 # Time in different power states |
| 316system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 300system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 317system.physmem_1.memoryStateTime::ACT 35583085750 # Time in different power states | 301system.physmem_1.memoryStateTime::ACT 44967962500 # Time in different power states |
| 318system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 319system.cpu_clk_domain.clock 500 # Clock period in ticks 320system.cpu.dtb.fetch_hits 0 # ITB hits 321system.cpu.dtb.fetch_misses 0 # ITB misses 322system.cpu.dtb.fetch_acv 0 # ITB acv 323system.cpu.dtb.fetch_accesses 0 # ITB accesses | 302system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 303system.cpu_clk_domain.clock 500 # Clock period in ticks 304system.cpu.dtb.fetch_hits 0 # ITB hits 305system.cpu.dtb.fetch_misses 0 # ITB misses 306system.cpu.dtb.fetch_acv 0 # ITB acv 307system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 324system.cpu.dtb.read_hits 9066440 # DTB read hits 325system.cpu.dtb.read_misses 10312 # DTB read misses | 308system.cpu.dtb.read_hits 9058452 # DTB read hits 309system.cpu.dtb.read_misses 10327 # DTB read misses |
| 326system.cpu.dtb.read_acv 210 # DTB read access violations | 310system.cpu.dtb.read_acv 210 # DTB read access violations |
| 327system.cpu.dtb.read_accesses 728817 # DTB read accesses 328system.cpu.dtb.write_hits 6357400 # DTB write hits 329system.cpu.dtb.write_misses 1140 # DTB write misses | 311system.cpu.dtb.read_accesses 728858 # DTB read accesses 312system.cpu.dtb.write_hits 6353129 # DTB write hits 313system.cpu.dtb.write_misses 1143 # DTB write misses |
| 330system.cpu.dtb.write_acv 157 # DTB write access violations | 314system.cpu.dtb.write_acv 157 # DTB write access violations |
| 331system.cpu.dtb.write_accesses 291929 # DTB write accesses 332system.cpu.dtb.data_hits 15423840 # DTB hits 333system.cpu.dtb.data_misses 11452 # DTB misses | 315system.cpu.dtb.write_accesses 291932 # DTB write accesses 316system.cpu.dtb.data_hits 15411581 # DTB hits 317system.cpu.dtb.data_misses 11470 # DTB misses |
| 334system.cpu.dtb.data_acv 367 # DTB access violations | 318system.cpu.dtb.data_acv 367 # DTB access violations |
| 335system.cpu.dtb.data_accesses 1020746 # DTB accesses 336system.cpu.itb.fetch_hits 4973902 # ITB hits 337system.cpu.itb.fetch_misses 4997 # ITB misses | 319system.cpu.dtb.data_accesses 1020790 # DTB accesses 320system.cpu.itb.fetch_hits 4975133 # ITB hits 321system.cpu.itb.fetch_misses 5010 # ITB misses |
| 338system.cpu.itb.fetch_acv 184 # ITB acv | 322system.cpu.itb.fetch_acv 184 # ITB acv |
| 339system.cpu.itb.fetch_accesses 4978899 # ITB accesses | 323system.cpu.itb.fetch_accesses 4980143 # ITB accesses |
| 340system.cpu.itb.read_hits 0 # DTB read hits 341system.cpu.itb.read_misses 0 # DTB read misses 342system.cpu.itb.read_acv 0 # DTB read access violations 343system.cpu.itb.read_accesses 0 # DTB read accesses 344system.cpu.itb.write_hits 0 # DTB write hits 345system.cpu.itb.write_misses 0 # DTB write misses 346system.cpu.itb.write_acv 0 # DTB write access violations 347system.cpu.itb.write_accesses 0 # DTB write accesses 348system.cpu.itb.data_hits 0 # DTB hits 349system.cpu.itb.data_misses 0 # DTB misses 350system.cpu.itb.data_acv 0 # DTB access violations 351system.cpu.itb.data_accesses 0 # DTB accesses | 324system.cpu.itb.read_hits 0 # DTB read hits 325system.cpu.itb.read_misses 0 # DTB read misses 326system.cpu.itb.read_acv 0 # DTB read access violations 327system.cpu.itb.read_accesses 0 # DTB read accesses 328system.cpu.itb.write_hits 0 # DTB write hits 329system.cpu.itb.write_misses 0 # DTB write misses 330system.cpu.itb.write_acv 0 # DTB write access violations 331system.cpu.itb.write_accesses 0 # DTB write accesses 332system.cpu.itb.data_hits 0 # DTB hits 333system.cpu.itb.data_misses 0 # DTB misses 334system.cpu.itb.data_acv 0 # DTB access violations 335system.cpu.itb.data_accesses 0 # DTB accesses |
| 352system.cpu.numCycles 3844794365 # number of cpu cycles simulated | 336system.cpu.numCycles 3882532975 # number of cpu cycles simulated |
| 353system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 354system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 337system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 338system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 355system.cpu.committedInsts 56195121 # Number of instructions committed 356system.cpu.committedOps 56195121 # Number of ops (including micro ops) committed 357system.cpu.num_int_alu_accesses 52066883 # Number of integer alu accesses 358system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses 359system.cpu.num_func_calls 1483708 # number of times a function call or return occured 360system.cpu.num_conditional_control_insts 6469750 # number of instructions that are conditional controls 361system.cpu.num_int_insts 52066883 # number of integer instructions 362system.cpu.num_fp_insts 324259 # number of float instructions 363system.cpu.num_int_register_reads 71341331 # number of times the integer registers were read 364system.cpu.num_int_register_writes 38530727 # number of times the integer registers were written 365system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read 366system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written 367system.cpu.num_mem_refs 15476411 # number of memory refs 368system.cpu.num_load_insts 9103258 # Number of load instructions 369system.cpu.num_store_insts 6373153 # Number of store instructions 370system.cpu.num_idle_cycles 3587818415.000134 # Number of idle cycles 371system.cpu.num_busy_cycles 256975949.999866 # Number of busy cycles 372system.cpu.not_idle_fraction 0.066837 # Percentage of non-idle cycles 373system.cpu.idle_fraction 0.933163 # Percentage of idle cycles 374system.cpu.Branches 8423975 # Number of branches fetched 375system.cpu.op_class::No_OpClass 3201032 5.70% 5.70% # Class of executed instruction 376system.cpu.op_class::IntAlu 36240615 64.48% 70.17% # Class of executed instruction 377system.cpu.op_class::IntMult 61007 0.11% 70.28% # Class of executed instruction 378system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction 379system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction 380system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction 381system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction 382system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction | 339system.cpu.committedInsts 56143021 # Number of instructions committed 340system.cpu.committedOps 56143021 # Number of ops (including micro ops) committed 341system.cpu.num_int_alu_accesses 52016582 # Number of integer alu accesses 342system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses 343system.cpu.num_func_calls 1482534 # number of times a function call or return occured 344system.cpu.num_conditional_control_insts 6465507 # number of instructions that are conditional controls 345system.cpu.num_int_insts 52016582 # number of integer instructions 346system.cpu.num_fp_insts 324393 # number of float instructions 347system.cpu.num_int_register_reads 71267420 # number of times the integer registers were read 348system.cpu.num_int_register_writes 38489507 # number of times the integer registers were written 349system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read 350system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written 351system.cpu.num_mem_refs 15464199 # number of memory refs 352system.cpu.num_load_insts 9095305 # Number of load instructions 353system.cpu.num_store_insts 6368894 # Number of store instructions 354system.cpu.num_idle_cycles 3584401371.998154 # Number of idle cycles 355system.cpu.num_busy_cycles 298131603.001846 # Number of busy cycles 356system.cpu.not_idle_fraction 0.076788 # Percentage of non-idle cycles 357system.cpu.idle_fraction 0.923212 # Percentage of idle cycles 358system.cpu.Branches 8418668 # Number of branches fetched 359system.cpu.op_class::No_OpClass 3199011 5.70% 5.70% # Class of executed instruction 360system.cpu.op_class::IntAlu 36202225 64.47% 70.17% # Class of executed instruction 361system.cpu.op_class::IntMult 61032 0.11% 70.27% # Class of executed instruction 362system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction 363system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction 364system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction 365system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction 366system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction |
| 383system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction 384system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction 385system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction 386system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction 387system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction 388system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction 389system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction 390system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction --- 6 unchanged lines hidden (view full) --- 397system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction 398system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction 399system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction 400system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction 401system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction 402system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction 403system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction 404system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction | 367system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction 368system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction 369system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction 370system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction 371system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction 372system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction 373system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction 374system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction --- 6 unchanged lines hidden (view full) --- 381system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction 382system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction 383system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction 384system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction 385system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction 386system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction 387system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction 388system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction |
| 405system.cpu.op_class::MemRead 9330336 16.60% 86.95% # Class of executed instruction 406system.cpu.op_class::MemWrite 6379227 11.35% 98.30% # Class of executed instruction 407system.cpu.op_class::IprAccess 953006 1.70% 100.00% # Class of executed instruction | 389system.cpu.op_class::MemRead 9322424 16.60% 86.95% # Class of executed instruction 390system.cpu.op_class::MemWrite 6374975 11.35% 98.30% # Class of executed instruction 391system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction |
| 408system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 392system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 409system.cpu.op_class::total 56206940 # Class of executed instruction | 393system.cpu.op_class::total 56154858 # Class of executed instruction |
| 410system.cpu.kern.inst.arm 0 # number of arm instructions executed | 394system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 411system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed 412system.cpu.kern.inst.hwrei 211964 # number of hwrei instructions executed 413system.cpu.kern.ipl_count::0 74896 40.89% 40.89% # number of times we switched to this ipl 414system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 415system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl 416system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl 417system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl 418system.cpu.kern.ipl_good::0 73529 49.31% 49.31% # number of times we switched to this ipl from a different ipl | 395system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed 396system.cpu.kern.inst.hwrei 212043 # number of hwrei instructions executed 397system.cpu.kern.ipl_count::0 74906 40.88% 40.88% # number of times we switched to this ipl 398system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl 399system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl 400system.cpu.kern.ipl_count::31 106248 57.99% 100.00% # number of times we switched to this ipl 401system.cpu.kern.ipl_count::total 183220 # number of times we switched to this ipl 402system.cpu.kern.ipl_good::0 73539 49.31% 49.31% # number of times we switched to this ipl from a different ipl |
| 419system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl | 403system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl |
| 420system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl 421system.cpu.kern.ipl_good::31 73529 49.31% 100.00% # number of times we switched to this ipl from a different ipl 422system.cpu.kern.ipl_good::total 149121 # number of times we switched to this ipl from a different ipl 423system.cpu.kern.ipl_ticks::0 1858096797000 96.66% 96.66% # number of cycles we spent at this ipl 424system.cpu.kern.ipl_ticks::21 92317000 0.00% 96.66% # number of cycles we spent at this ipl 425system.cpu.kern.ipl_ticks::22 743733500 0.04% 96.70% # number of cycles we spent at this ipl 426system.cpu.kern.ipl_ticks::31 63463601000 3.30% 100.00% # number of cycles we spent at this ipl 427system.cpu.kern.ipl_ticks::total 1922396448500 # number of cycles we spent at this ipl 428system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl | 404system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl 405system.cpu.kern.ipl_good::31 73539 49.31% 100.00% # number of times we switched to this ipl from a different ipl 406system.cpu.kern.ipl_good::total 149144 # number of times we switched to this ipl from a different ipl 407system.cpu.kern.ipl_ticks::0 1860736112500 95.85% 95.85% # number of cycles we spent at this ipl 408system.cpu.kern.ipl_ticks::21 92522000 0.00% 95.86% # number of cycles we spent at this ipl 409system.cpu.kern.ipl_ticks::22 746030500 0.04% 95.89% # number of cycles we spent at this ipl 410system.cpu.kern.ipl_ticks::31 79691088500 4.11% 100.00% # number of cycles we spent at this ipl 411system.cpu.kern.ipl_ticks::total 1941265753500 # number of cycles we spent at this ipl 412system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl |
| 429system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 430system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 413system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 414system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 431system.cpu.kern.ipl_used::31 0.692253 # fraction of swpipl calls that actually changed the ipl 432system.cpu.kern.ipl_used::total 0.814086 # fraction of swpipl calls that actually changed the ipl | 415system.cpu.kern.ipl_used::31 0.692145 # fraction of swpipl calls that actually changed the ipl 416system.cpu.kern.ipl_used::total 0.814016 # fraction of swpipl calls that actually changed the ipl |
| 433system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 434system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 435system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 436system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 437system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 438system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 439system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 440system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 460system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 461system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 462system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 463system.cpu.kern.syscall::total 326 # number of syscalls executed 464system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 465system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 466system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 467system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 417system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 418system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 419system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 420system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 421system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 422system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 423system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 424system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 444system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 445system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 446system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 447system.cpu.kern.syscall::total 326 # number of syscalls executed 448system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 449system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 450system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 451system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 468system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed | 452system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed |
| 469system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 470system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 453system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 454system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 471system.cpu.kern.callpal::swpipl 175955 91.22% 93.41% # number of callpals executed 472system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed | 455system.cpu.kern.callpal::swpipl 175993 91.21% 93.41% # number of callpals executed 456system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed |
| 473system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 474system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 475system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed | 457system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 458system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 459system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed |
| 476system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 477system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed | 460system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed 461system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed |
| 478system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 479system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 462system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 463system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 480system.cpu.kern.callpal::total 192899 # number of callpals executed 481system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches 482system.cpu.kern.mode_switch::user 1741 # number of protection mode switches 483system.cpu.kern.mode_switch::idle 2093 # number of protection mode switches | 464system.cpu.kern.callpal::total 192944 # number of callpals executed 465system.cpu.kern.mode_switch::kernel 5907 # number of protection mode switches 466system.cpu.kern.mode_switch::user 1740 # number of protection mode switches 467system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches |
| 484system.cpu.kern.mode_good::kernel 1910 | 468system.cpu.kern.mode_good::kernel 1910 |
| 485system.cpu.kern.mode_good::user 1741 486system.cpu.kern.mode_good::idle 169 487system.cpu.kern.mode_switch_good::kernel 0.323509 # fraction of useful protection mode switches | 469system.cpu.kern.mode_good::user 1740 470system.cpu.kern.mode_good::idle 170 471system.cpu.kern.mode_switch_good::kernel 0.323345 # fraction of useful protection mode switches |
| 488system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 472system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 489system.cpu.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches 490system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches 491system.cpu.kern.mode_ticks::kernel 46413360000 2.41% 2.41% # number of ticks spent at the given mode 492system.cpu.kern.mode_ticks::user 5233781000 0.27% 2.69% # number of ticks spent at the given mode 493system.cpu.kern.mode_ticks::idle 1870749305500 97.31% 100.00% # number of ticks spent at the given mode 494system.cpu.kern.swap_context 4175 # number of times the context was actually changed 495system.cpu.dcache.tags.replacements 1390740 # number of replacements 496system.cpu.dcache.tags.tagsinuse 511.978175 # Cycle average of tags in use 497system.cpu.dcache.tags.total_refs 14051600 # Total number of references to valid blocks. 498system.cpu.dcache.tags.sampled_refs 1391252 # Sample count of references to valid blocks. 499system.cpu.dcache.tags.avg_refs 10.099968 # Average number of references to valid blocks. 500system.cpu.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. 501system.cpu.dcache.tags.occ_blocks::cpu.data 511.978175 # Average occupied blocks per requestor 502system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy 503system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy | 473system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches 474system.cpu.kern.mode_switch_good::total 0.392117 # fraction of useful protection mode switches 475system.cpu.kern.mode_ticks::kernel 48524962500 2.50% 2.50% # number of ticks spent at the given mode 476system.cpu.kern.mode_ticks::user 5595783500 0.29% 2.79% # number of ticks spent at the given mode 477system.cpu.kern.mode_ticks::idle 1887145005500 97.21% 100.00% # number of ticks spent at the given mode 478system.cpu.kern.swap_context 4177 # number of times the context was actually changed 479system.cpu.dcache.tags.replacements 1390004 # number of replacements 480system.cpu.dcache.tags.tagsinuse 511.973850 # Cycle average of tags in use 481system.cpu.dcache.tags.total_refs 14040102 # Total number of references to valid blocks. 482system.cpu.dcache.tags.sampled_refs 1390516 # Sample count of references to valid blocks. 483system.cpu.dcache.tags.avg_refs 10.097045 # Average number of references to valid blocks. 484system.cpu.dcache.tags.warmup_cycle 143374500 # Cycle when the warmup percentage was hit. 485system.cpu.dcache.tags.occ_blocks::cpu.data 511.973850 # Average occupied blocks per requestor 486system.cpu.dcache.tags.occ_percent::cpu.data 0.999949 # Average percentage of cache occupancy 487system.cpu.dcache.tags.occ_percent::total 0.999949 # Average percentage of cache occupancy |
| 504system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 505system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id | 488system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 489system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id |
| 506system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 507system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id | 490system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 491system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id |
| 508system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 492system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 509system.cpu.dcache.tags.tag_accesses 63162665 # Number of tag accesses 510system.cpu.dcache.tags.data_accesses 63162665 # Number of data accesses 511system.cpu.dcache.ReadReq_hits::cpu.data 7816092 # number of ReadReq hits 512system.cpu.dcache.ReadReq_hits::total 7816092 # number of ReadReq hits 513system.cpu.dcache.WriteReq_hits::cpu.data 5853262 # number of WriteReq hits 514system.cpu.dcache.WriteReq_hits::total 5853262 # number of WriteReq hits 515system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits 516system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits 517system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits 518system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits 519system.cpu.dcache.demand_hits::cpu.data 13669354 # number of demand (read+write) hits 520system.cpu.dcache.demand_hits::total 13669354 # number of demand (read+write) hits 521system.cpu.dcache.overall_hits::cpu.data 13669354 # number of overall hits 522system.cpu.dcache.overall_hits::total 13669354 # number of overall hits 523system.cpu.dcache.ReadReq_misses::cpu.data 1069466 # number of ReadReq misses 524system.cpu.dcache.ReadReq_misses::total 1069466 # number of ReadReq misses 525system.cpu.dcache.WriteReq_misses::cpu.data 304560 # number of WriteReq misses 526system.cpu.dcache.WriteReq_misses::total 304560 # number of WriteReq misses 527system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses 528system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses 529system.cpu.dcache.demand_misses::cpu.data 1374026 # number of demand (read+write) misses 530system.cpu.dcache.demand_misses::total 1374026 # number of demand (read+write) misses 531system.cpu.dcache.overall_misses::cpu.data 1374026 # number of overall misses 532system.cpu.dcache.overall_misses::total 1374026 # number of overall misses 533system.cpu.dcache.ReadReq_miss_latency::cpu.data 30729736500 # number of ReadReq miss cycles 534system.cpu.dcache.ReadReq_miss_latency::total 30729736500 # number of ReadReq miss cycles 535system.cpu.dcache.WriteReq_miss_latency::cpu.data 11677039000 # number of WriteReq miss cycles 536system.cpu.dcache.WriteReq_miss_latency::total 11677039000 # number of WriteReq miss cycles 537system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228891000 # number of LoadLockedReq miss cycles 538system.cpu.dcache.LoadLockedReq_miss_latency::total 228891000 # number of LoadLockedReq miss cycles 539system.cpu.dcache.demand_miss_latency::cpu.data 42406775500 # number of demand (read+write) miss cycles 540system.cpu.dcache.demand_miss_latency::total 42406775500 # number of demand (read+write) miss cycles 541system.cpu.dcache.overall_miss_latency::cpu.data 42406775500 # number of overall miss cycles 542system.cpu.dcache.overall_miss_latency::total 42406775500 # number of overall miss cycles 543system.cpu.dcache.ReadReq_accesses::cpu.data 8885558 # number of ReadReq accesses(hits+misses) 544system.cpu.dcache.ReadReq_accesses::total 8885558 # number of ReadReq accesses(hits+misses) 545system.cpu.dcache.WriteReq_accesses::cpu.data 6157822 # number of WriteReq accesses(hits+misses) 546system.cpu.dcache.WriteReq_accesses::total 6157822 # number of WriteReq accesses(hits+misses) 547system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) 548system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) 549system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses) 550system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses) 551system.cpu.dcache.demand_accesses::cpu.data 15043380 # number of demand (read+write) accesses 552system.cpu.dcache.demand_accesses::total 15043380 # number of demand (read+write) accesses 553system.cpu.dcache.overall_accesses::cpu.data 15043380 # number of overall (read+write) accesses 554system.cpu.dcache.overall_accesses::total 15043380 # number of overall (read+write) accesses 555system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120360 # miss rate for ReadReq accesses 556system.cpu.dcache.ReadReq_miss_rate::total 0.120360 # miss rate for ReadReq accesses 557system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses 558system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses 559system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses 560system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses 561system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses 562system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses 563system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses 564system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses 565system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28733.719913 # average ReadReq miss latency 566system.cpu.dcache.ReadReq_avg_miss_latency::total 28733.719913 # average ReadReq miss latency 567system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38340.684923 # average WriteReq miss latency 568system.cpu.dcache.WriteReq_avg_miss_latency::total 38340.684923 # average WriteReq miss latency 569system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.660404 # average LoadLockedReq miss latency 570system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.660404 # average LoadLockedReq miss latency 571system.cpu.dcache.demand_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency 572system.cpu.dcache.demand_avg_miss_latency::total 30863.153608 # average overall miss latency 573system.cpu.dcache.overall_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency 574system.cpu.dcache.overall_avg_miss_latency::total 30863.153608 # average overall miss latency | 493system.cpu.dcache.tags.tag_accesses 63112993 # Number of tag accesses 494system.cpu.dcache.tags.data_accesses 63112993 # Number of data accesses 495system.cpu.dcache.ReadReq_hits::cpu.data 7808536 # number of ReadReq hits 496system.cpu.dcache.ReadReq_hits::total 7808536 # number of ReadReq hits 497system.cpu.dcache.WriteReq_hits::cpu.data 5849272 # number of WriteReq hits 498system.cpu.dcache.WriteReq_hits::total 5849272 # number of WriteReq hits 499system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits 500system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits 501system.cpu.dcache.StoreCondReq_hits::cpu.data 199252 # number of StoreCondReq hits 502system.cpu.dcache.StoreCondReq_hits::total 199252 # number of StoreCondReq hits 503system.cpu.dcache.demand_hits::cpu.data 13657808 # number of demand (read+write) hits 504system.cpu.dcache.demand_hits::total 13657808 # number of demand (read+write) hits 505system.cpu.dcache.overall_hits::cpu.data 13657808 # number of overall hits 506system.cpu.dcache.overall_hits::total 13657808 # number of overall hits 507system.cpu.dcache.ReadReq_misses::cpu.data 1069028 # number of ReadReq misses 508system.cpu.dcache.ReadReq_misses::total 1069028 # number of ReadReq misses 509system.cpu.dcache.WriteReq_misses::cpu.data 304257 # number of WriteReq misses 510system.cpu.dcache.WriteReq_misses::total 304257 # number of WriteReq misses 511system.cpu.dcache.LoadLockedReq_misses::cpu.data 17249 # number of LoadLockedReq misses 512system.cpu.dcache.LoadLockedReq_misses::total 17249 # number of LoadLockedReq misses 513system.cpu.dcache.demand_misses::cpu.data 1373285 # number of demand (read+write) misses 514system.cpu.dcache.demand_misses::total 1373285 # number of demand (read+write) misses 515system.cpu.dcache.overall_misses::cpu.data 1373285 # number of overall misses 516system.cpu.dcache.overall_misses::total 1373285 # number of overall misses 517system.cpu.dcache.ReadReq_miss_latency::cpu.data 44750637500 # number of ReadReq miss cycles 518system.cpu.dcache.ReadReq_miss_latency::total 44750637500 # number of ReadReq miss cycles 519system.cpu.dcache.WriteReq_miss_latency::cpu.data 17613913000 # number of WriteReq miss cycles 520system.cpu.dcache.WriteReq_miss_latency::total 17613913000 # number of WriteReq miss cycles 521system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles 522system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles 523system.cpu.dcache.demand_miss_latency::cpu.data 62364550500 # number of demand (read+write) miss cycles 524system.cpu.dcache.demand_miss_latency::total 62364550500 # number of demand (read+write) miss cycles 525system.cpu.dcache.overall_miss_latency::cpu.data 62364550500 # number of overall miss cycles 526system.cpu.dcache.overall_miss_latency::total 62364550500 # number of overall miss cycles 527system.cpu.dcache.ReadReq_accesses::cpu.data 8877564 # number of ReadReq accesses(hits+misses) 528system.cpu.dcache.ReadReq_accesses::total 8877564 # number of ReadReq accesses(hits+misses) 529system.cpu.dcache.WriteReq_accesses::cpu.data 6153529 # number of WriteReq accesses(hits+misses) 530system.cpu.dcache.WriteReq_accesses::total 6153529 # number of WriteReq accesses(hits+misses) 531system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200274 # number of LoadLockedReq accesses(hits+misses) 532system.cpu.dcache.LoadLockedReq_accesses::total 200274 # number of LoadLockedReq accesses(hits+misses) 533system.cpu.dcache.StoreCondReq_accesses::cpu.data 199252 # number of StoreCondReq accesses(hits+misses) 534system.cpu.dcache.StoreCondReq_accesses::total 199252 # number of StoreCondReq accesses(hits+misses) 535system.cpu.dcache.demand_accesses::cpu.data 15031093 # number of demand (read+write) accesses 536system.cpu.dcache.demand_accesses::total 15031093 # number of demand (read+write) accesses 537system.cpu.dcache.overall_accesses::cpu.data 15031093 # number of overall (read+write) accesses 538system.cpu.dcache.overall_accesses::total 15031093 # number of overall (read+write) accesses 539system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120419 # miss rate for ReadReq accesses 540system.cpu.dcache.ReadReq_miss_rate::total 0.120419 # miss rate for ReadReq accesses 541system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049444 # miss rate for WriteReq accesses 542system.cpu.dcache.WriteReq_miss_rate::total 0.049444 # miss rate for WriteReq accesses 543system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086127 # miss rate for LoadLockedReq accesses 544system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086127 # miss rate for LoadLockedReq accesses 545system.cpu.dcache.demand_miss_rate::cpu.data 0.091363 # miss rate for demand accesses 546system.cpu.dcache.demand_miss_rate::total 0.091363 # miss rate for demand accesses 547system.cpu.dcache.overall_miss_rate::cpu.data 0.091363 # miss rate for overall accesses 548system.cpu.dcache.overall_miss_rate::total 0.091363 # miss rate for overall accesses 549system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41861.052751 # average ReadReq miss latency 550system.cpu.dcache.ReadReq_avg_miss_latency::total 41861.052751 # average ReadReq miss latency 551system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57891.562068 # average WriteReq miss latency 552system.cpu.dcache.WriteReq_avg_miss_latency::total 57891.562068 # average WriteReq miss latency 553system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13479.448084 # average LoadLockedReq miss latency 554system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13479.448084 # average LoadLockedReq miss latency 555system.cpu.dcache.demand_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency 556system.cpu.dcache.demand_avg_miss_latency::total 45412.678723 # average overall miss latency 557system.cpu.dcache.overall_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency 558system.cpu.dcache.overall_avg_miss_latency::total 45412.678723 # average overall miss latency |
| 575system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 576system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 577system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 578system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 579system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 580system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 581system.cpu.dcache.fast_writes 0 # number of fast writes performed 582system.cpu.dcache.cache_copies 0 # number of cache copies performed | 559system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 560system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 561system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 562system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 563system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 564system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 565system.cpu.dcache.fast_writes 0 # number of fast writes performed 566system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 583system.cpu.dcache.writebacks::writebacks 835293 # number of writebacks 584system.cpu.dcache.writebacks::total 835293 # number of writebacks 585system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069466 # number of ReadReq MSHR misses 586system.cpu.dcache.ReadReq_mshr_misses::total 1069466 # number of ReadReq MSHR misses 587system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304560 # number of WriteReq MSHR misses 588system.cpu.dcache.WriteReq_mshr_misses::total 304560 # number of WriteReq MSHR misses 589system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses 590system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses 591system.cpu.dcache.demand_mshr_misses::cpu.data 1374026 # number of demand (read+write) MSHR misses 592system.cpu.dcache.demand_mshr_misses::total 1374026 # number of demand (read+write) MSHR misses 593system.cpu.dcache.overall_mshr_misses::cpu.data 1374026 # number of overall MSHR misses 594system.cpu.dcache.overall_mshr_misses::total 1374026 # number of overall MSHR misses | 567system.cpu.dcache.writebacks::writebacks 834533 # number of writebacks 568system.cpu.dcache.writebacks::total 834533 # number of writebacks 569system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069028 # number of ReadReq MSHR misses 570system.cpu.dcache.ReadReq_mshr_misses::total 1069028 # number of ReadReq MSHR misses 571system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304257 # number of WriteReq MSHR misses 572system.cpu.dcache.WriteReq_mshr_misses::total 304257 # number of WriteReq MSHR misses 573system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17249 # number of LoadLockedReq MSHR misses 574system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses 575system.cpu.dcache.demand_mshr_misses::cpu.data 1373285 # number of demand (read+write) MSHR misses 576system.cpu.dcache.demand_mshr_misses::total 1373285 # number of demand (read+write) MSHR misses 577system.cpu.dcache.overall_mshr_misses::cpu.data 1373285 # number of overall MSHR misses 578system.cpu.dcache.overall_mshr_misses::total 1373285 # number of overall MSHR misses |
| 595system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 596system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable | 579system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 580system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable |
| 597system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable 598system.cpu.dcache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable 599system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses 600system.cpu.dcache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses 601system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29660270500 # number of ReadReq MSHR miss cycles 602system.cpu.dcache.ReadReq_mshr_miss_latency::total 29660270500 # number of ReadReq MSHR miss cycles 603system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11372479000 # number of WriteReq MSHR miss cycles 604system.cpu.dcache.WriteReq_mshr_miss_latency::total 11372479000 # number of WriteReq MSHR miss cycles 605system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 211647000 # number of LoadLockedReq MSHR miss cycles 606system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 211647000 # number of LoadLockedReq MSHR miss cycles 607system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41032749500 # number of demand (read+write) MSHR miss cycles 608system.cpu.dcache.demand_mshr_miss_latency::total 41032749500 # number of demand (read+write) MSHR miss cycles 609system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41032749500 # number of overall MSHR miss cycles 610system.cpu.dcache.overall_mshr_miss_latency::total 41032749500 # number of overall MSHR miss cycles 611system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450110500 # number of ReadReq MSHR uncacheable cycles 612system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450110500 # number of ReadReq MSHR uncacheable cycles 613system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2049565500 # number of WriteReq MSHR uncacheable cycles 614system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2049565500 # number of WriteReq MSHR uncacheable cycles 615system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3499676000 # number of overall MSHR uncacheable cycles 616system.cpu.dcache.overall_mshr_uncacheable_latency::total 3499676000 # number of overall MSHR uncacheable cycles 617system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120360 # mshr miss rate for ReadReq accesses 618system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120360 # mshr miss rate for ReadReq accesses 619system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses 620system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses 621system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses 622system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses 623system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses 624system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses 625system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses 626system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses 627system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27733.719913 # average ReadReq mshr miss latency 628system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27733.719913 # average ReadReq mshr miss latency 629system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37340.684923 # average WriteReq mshr miss latency 630system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37340.684923 # average WriteReq mshr miss latency 631system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12273.660404 # average LoadLockedReq mshr miss latency 632system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12273.660404 # average LoadLockedReq mshr miss latency 633system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency 634system.cpu.dcache.demand_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency 635system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency 636system.cpu.dcache.overall_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency 637system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.154401 # average ReadReq mshr uncacheable latency 638system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.154401 # average ReadReq mshr uncacheable latency 639system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212390.207254 # average WriteReq mshr uncacheable latency 640system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212390.207254 # average WriteReq mshr uncacheable latency 641system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211078.166466 # average overall mshr uncacheable latency 642system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211078.166466 # average overall mshr uncacheable latency | 581system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable 582system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable 583system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses 584system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses 585system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43681609500 # number of ReadReq MSHR miss cycles 586system.cpu.dcache.ReadReq_mshr_miss_latency::total 43681609500 # number of ReadReq MSHR miss cycles 587system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17309656000 # number of WriteReq MSHR miss cycles 588system.cpu.dcache.WriteReq_mshr_miss_latency::total 17309656000 # number of WriteReq MSHR miss cycles 589system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215258000 # number of LoadLockedReq MSHR miss cycles 590system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215258000 # number of LoadLockedReq MSHR miss cycles 591system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60991265500 # number of demand (read+write) MSHR miss cycles 592system.cpu.dcache.demand_mshr_miss_latency::total 60991265500 # number of demand (read+write) MSHR miss cycles 593system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60991265500 # number of overall MSHR miss cycles 594system.cpu.dcache.overall_mshr_miss_latency::total 60991265500 # number of overall MSHR miss cycles 595system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450109500 # number of ReadReq MSHR uncacheable cycles 596system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450109500 # number of ReadReq MSHR uncacheable cycles 597system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2050243500 # number of WriteReq MSHR uncacheable cycles 598system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2050243500 # number of WriteReq MSHR uncacheable cycles 599system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3500353000 # number of overall MSHR uncacheable cycles 600system.cpu.dcache.overall_mshr_uncacheable_latency::total 3500353000 # number of overall MSHR uncacheable cycles 601system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120419 # mshr miss rate for ReadReq accesses 602system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120419 # mshr miss rate for ReadReq accesses 603system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049444 # mshr miss rate for WriteReq accesses 604system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049444 # mshr miss rate for WriteReq accesses 605system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086127 # mshr miss rate for LoadLockedReq accesses 606system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086127 # mshr miss rate for LoadLockedReq accesses 607system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091363 # mshr miss rate for demand accesses 608system.cpu.dcache.demand_mshr_miss_rate::total 0.091363 # mshr miss rate for demand accesses 609system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091363 # mshr miss rate for overall accesses 610system.cpu.dcache.overall_mshr_miss_rate::total 0.091363 # mshr miss rate for overall accesses 611system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40861.052751 # average ReadReq mshr miss latency 612system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40861.052751 # average ReadReq mshr miss latency 613system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56891.562068 # average WriteReq mshr miss latency 614system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56891.562068 # average WriteReq mshr miss latency 615system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.448084 # average LoadLockedReq mshr miss latency 616system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.448084 # average LoadLockedReq mshr miss latency 617system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency 618system.cpu.dcache.demand_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency 619system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency 620system.cpu.dcache.overall_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency 621system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.010101 # average ReadReq mshr uncacheable latency 622system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.010101 # average ReadReq mshr uncacheable latency 623system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212394.436963 # average WriteReq mshr uncacheable latency 624system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212394.436963 # average WriteReq mshr uncacheable latency 625system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211080.805644 # average overall mshr uncacheable latency 626system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211080.805644 # average overall mshr uncacheable latency |
| 643system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 627system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 644system.cpu.icache.tags.replacements 928306 # number of replacements 645system.cpu.icache.tags.tagsinuse 508.094938 # Cycle average of tags in use 646system.cpu.icache.tags.total_refs 55277964 # Total number of references to valid blocks. 647system.cpu.icache.tags.sampled_refs 928817 # Sample count of references to valid blocks. 648system.cpu.icache.tags.avg_refs 59.514376 # Average number of references to valid blocks. 649system.cpu.icache.tags.warmup_cycle 41861098500 # Cycle when the warmup percentage was hit. 650system.cpu.icache.tags.occ_blocks::cpu.inst 508.094938 # Average occupied blocks per requestor 651system.cpu.icache.tags.occ_percent::cpu.inst 0.992373 # Average percentage of cache occupancy 652system.cpu.icache.tags.occ_percent::total 0.992373 # Average percentage of cache occupancy | 628system.cpu.icache.tags.replacements 928672 # number of replacements 629system.cpu.icache.tags.tagsinuse 506.358595 # Cycle average of tags in use 630system.cpu.icache.tags.total_refs 55225516 # Total number of references to valid blocks. 631system.cpu.icache.tags.sampled_refs 929183 # Sample count of references to valid blocks. 632system.cpu.icache.tags.avg_refs 59.434488 # Average number of references to valid blocks. 633system.cpu.icache.tags.warmup_cycle 58555927500 # Cycle when the warmup percentage was hit. 634system.cpu.icache.tags.occ_blocks::cpu.inst 506.358595 # Average occupied blocks per requestor 635system.cpu.icache.tags.occ_percent::cpu.inst 0.988982 # Average percentage of cache occupancy 636system.cpu.icache.tags.occ_percent::total 0.988982 # Average percentage of cache occupancy |
| 653system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 654system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 655system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 656system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 657system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 658system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 637system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 638system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 639system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 640system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 641system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 642system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 659system.cpu.icache.tags.tag_accesses 57135918 # Number of tag accesses 660system.cpu.icache.tags.data_accesses 57135918 # Number of data accesses 661system.cpu.icache.ReadReq_hits::cpu.inst 55277964 # number of ReadReq hits 662system.cpu.icache.ReadReq_hits::total 55277964 # number of ReadReq hits 663system.cpu.icache.demand_hits::cpu.inst 55277964 # number of demand (read+write) hits 664system.cpu.icache.demand_hits::total 55277964 # number of demand (read+write) hits 665system.cpu.icache.overall_hits::cpu.inst 55277964 # number of overall hits 666system.cpu.icache.overall_hits::total 55277964 # number of overall hits 667system.cpu.icache.ReadReq_misses::cpu.inst 928977 # number of ReadReq misses 668system.cpu.icache.ReadReq_misses::total 928977 # number of ReadReq misses 669system.cpu.icache.demand_misses::cpu.inst 928977 # number of demand (read+write) misses 670system.cpu.icache.demand_misses::total 928977 # number of demand (read+write) misses 671system.cpu.icache.overall_misses::cpu.inst 928977 # number of overall misses 672system.cpu.icache.overall_misses::total 928977 # number of overall misses 673system.cpu.icache.ReadReq_miss_latency::cpu.inst 13003041000 # number of ReadReq miss cycles 674system.cpu.icache.ReadReq_miss_latency::total 13003041000 # number of ReadReq miss cycles 675system.cpu.icache.demand_miss_latency::cpu.inst 13003041000 # number of demand (read+write) miss cycles 676system.cpu.icache.demand_miss_latency::total 13003041000 # number of demand (read+write) miss cycles 677system.cpu.icache.overall_miss_latency::cpu.inst 13003041000 # number of overall miss cycles 678system.cpu.icache.overall_miss_latency::total 13003041000 # number of overall miss cycles 679system.cpu.icache.ReadReq_accesses::cpu.inst 56206941 # number of ReadReq accesses(hits+misses) 680system.cpu.icache.ReadReq_accesses::total 56206941 # number of ReadReq accesses(hits+misses) 681system.cpu.icache.demand_accesses::cpu.inst 56206941 # number of demand (read+write) accesses 682system.cpu.icache.demand_accesses::total 56206941 # number of demand (read+write) accesses 683system.cpu.icache.overall_accesses::cpu.inst 56206941 # number of overall (read+write) accesses 684system.cpu.icache.overall_accesses::total 56206941 # number of overall (read+write) accesses 685system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016528 # miss rate for ReadReq accesses 686system.cpu.icache.ReadReq_miss_rate::total 0.016528 # miss rate for ReadReq accesses 687system.cpu.icache.demand_miss_rate::cpu.inst 0.016528 # miss rate for demand accesses 688system.cpu.icache.demand_miss_rate::total 0.016528 # miss rate for demand accesses 689system.cpu.icache.overall_miss_rate::cpu.inst 0.016528 # miss rate for overall accesses 690system.cpu.icache.overall_miss_rate::total 0.016528 # miss rate for overall accesses 691system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13997.161394 # average ReadReq miss latency 692system.cpu.icache.ReadReq_avg_miss_latency::total 13997.161394 # average ReadReq miss latency 693system.cpu.icache.demand_avg_miss_latency::cpu.inst 13997.161394 # average overall miss latency 694system.cpu.icache.demand_avg_miss_latency::total 13997.161394 # average overall miss latency 695system.cpu.icache.overall_avg_miss_latency::cpu.inst 13997.161394 # average overall miss latency 696system.cpu.icache.overall_avg_miss_latency::total 13997.161394 # average overall miss latency | 643system.cpu.icache.tags.tag_accesses 57084202 # Number of tag accesses 644system.cpu.icache.tags.data_accesses 57084202 # Number of data accesses 645system.cpu.icache.ReadReq_hits::cpu.inst 55225516 # number of ReadReq hits 646system.cpu.icache.ReadReq_hits::total 55225516 # number of ReadReq hits 647system.cpu.icache.demand_hits::cpu.inst 55225516 # number of demand (read+write) hits 648system.cpu.icache.demand_hits::total 55225516 # number of demand (read+write) hits 649system.cpu.icache.overall_hits::cpu.inst 55225516 # number of overall hits 650system.cpu.icache.overall_hits::total 55225516 # number of overall hits 651system.cpu.icache.ReadReq_misses::cpu.inst 929343 # number of ReadReq misses 652system.cpu.icache.ReadReq_misses::total 929343 # number of ReadReq misses 653system.cpu.icache.demand_misses::cpu.inst 929343 # number of demand (read+write) misses 654system.cpu.icache.demand_misses::total 929343 # number of demand (read+write) misses 655system.cpu.icache.overall_misses::cpu.inst 929343 # number of overall misses 656system.cpu.icache.overall_misses::total 929343 # number of overall misses 657system.cpu.icache.ReadReq_miss_latency::cpu.inst 13682743000 # number of ReadReq miss cycles 658system.cpu.icache.ReadReq_miss_latency::total 13682743000 # number of ReadReq miss cycles 659system.cpu.icache.demand_miss_latency::cpu.inst 13682743000 # number of demand (read+write) miss cycles 660system.cpu.icache.demand_miss_latency::total 13682743000 # number of demand (read+write) miss cycles 661system.cpu.icache.overall_miss_latency::cpu.inst 13682743000 # number of overall miss cycles 662system.cpu.icache.overall_miss_latency::total 13682743000 # number of overall miss cycles 663system.cpu.icache.ReadReq_accesses::cpu.inst 56154859 # number of ReadReq accesses(hits+misses) 664system.cpu.icache.ReadReq_accesses::total 56154859 # number of ReadReq accesses(hits+misses) 665system.cpu.icache.demand_accesses::cpu.inst 56154859 # number of demand (read+write) accesses 666system.cpu.icache.demand_accesses::total 56154859 # number of demand (read+write) accesses 667system.cpu.icache.overall_accesses::cpu.inst 56154859 # number of overall (read+write) accesses 668system.cpu.icache.overall_accesses::total 56154859 # number of overall (read+write) accesses 669system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016550 # miss rate for ReadReq accesses 670system.cpu.icache.ReadReq_miss_rate::total 0.016550 # miss rate for ReadReq accesses 671system.cpu.icache.demand_miss_rate::cpu.inst 0.016550 # miss rate for demand accesses 672system.cpu.icache.demand_miss_rate::total 0.016550 # miss rate for demand accesses 673system.cpu.icache.overall_miss_rate::cpu.inst 0.016550 # miss rate for overall accesses 674system.cpu.icache.overall_miss_rate::total 0.016550 # miss rate for overall accesses 675system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.027989 # average ReadReq miss latency 676system.cpu.icache.ReadReq_avg_miss_latency::total 14723.027989 # average ReadReq miss latency 677system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.027989 # average overall miss latency 678system.cpu.icache.demand_avg_miss_latency::total 14723.027989 # average overall miss latency 679system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.027989 # average overall miss latency 680system.cpu.icache.overall_avg_miss_latency::total 14723.027989 # average overall miss latency |
| 697system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 698system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 699system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 700system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 701system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 702system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 703system.cpu.icache.fast_writes 0 # number of fast writes performed 704system.cpu.icache.cache_copies 0 # number of cache copies performed | 681system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 682system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 683system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 684system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 685system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 686system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 687system.cpu.icache.fast_writes 0 # number of fast writes performed 688system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 705system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928977 # number of ReadReq MSHR misses 706system.cpu.icache.ReadReq_mshr_misses::total 928977 # number of ReadReq MSHR misses 707system.cpu.icache.demand_mshr_misses::cpu.inst 928977 # number of demand (read+write) MSHR misses 708system.cpu.icache.demand_mshr_misses::total 928977 # number of demand (read+write) MSHR misses 709system.cpu.icache.overall_mshr_misses::cpu.inst 928977 # number of overall MSHR misses 710system.cpu.icache.overall_mshr_misses::total 928977 # number of overall MSHR misses 711system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12074064000 # number of ReadReq MSHR miss cycles 712system.cpu.icache.ReadReq_mshr_miss_latency::total 12074064000 # number of ReadReq MSHR miss cycles 713system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12074064000 # number of demand (read+write) MSHR miss cycles 714system.cpu.icache.demand_mshr_miss_latency::total 12074064000 # number of demand (read+write) MSHR miss cycles 715system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12074064000 # number of overall MSHR miss cycles 716system.cpu.icache.overall_mshr_miss_latency::total 12074064000 # number of overall MSHR miss cycles 717system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016528 # mshr miss rate for ReadReq accesses 718system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016528 # mshr miss rate for ReadReq accesses 719system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016528 # mshr miss rate for demand accesses 720system.cpu.icache.demand_mshr_miss_rate::total 0.016528 # mshr miss rate for demand accesses 721system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016528 # mshr miss rate for overall accesses 722system.cpu.icache.overall_mshr_miss_rate::total 0.016528 # mshr miss rate for overall accesses 723system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12997.161394 # average ReadReq mshr miss latency 724system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12997.161394 # average ReadReq mshr miss latency 725system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12997.161394 # average overall mshr miss latency 726system.cpu.icache.demand_avg_mshr_miss_latency::total 12997.161394 # average overall mshr miss latency 727system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12997.161394 # average overall mshr miss latency 728system.cpu.icache.overall_avg_mshr_miss_latency::total 12997.161394 # average overall mshr miss latency | 689system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929343 # number of ReadReq MSHR misses 690system.cpu.icache.ReadReq_mshr_misses::total 929343 # number of ReadReq MSHR misses 691system.cpu.icache.demand_mshr_misses::cpu.inst 929343 # number of demand (read+write) MSHR misses 692system.cpu.icache.demand_mshr_misses::total 929343 # number of demand (read+write) MSHR misses 693system.cpu.icache.overall_mshr_misses::cpu.inst 929343 # number of overall MSHR misses 694system.cpu.icache.overall_mshr_misses::total 929343 # number of overall MSHR misses 695system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12753400000 # number of ReadReq MSHR miss cycles 696system.cpu.icache.ReadReq_mshr_miss_latency::total 12753400000 # number of ReadReq MSHR miss cycles 697system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12753400000 # number of demand (read+write) MSHR miss cycles 698system.cpu.icache.demand_mshr_miss_latency::total 12753400000 # number of demand (read+write) MSHR miss cycles 699system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12753400000 # number of overall MSHR miss cycles 700system.cpu.icache.overall_mshr_miss_latency::total 12753400000 # number of overall MSHR miss cycles 701system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016550 # mshr miss rate for ReadReq accesses 702system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016550 # mshr miss rate for ReadReq accesses 703system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016550 # mshr miss rate for demand accesses 704system.cpu.icache.demand_mshr_miss_rate::total 0.016550 # mshr miss rate for demand accesses 705system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016550 # mshr miss rate for overall accesses 706system.cpu.icache.overall_mshr_miss_rate::total 0.016550 # mshr miss rate for overall accesses 707system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.027989 # average ReadReq mshr miss latency 708system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.027989 # average ReadReq mshr miss latency 709system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.027989 # average overall mshr miss latency 710system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.027989 # average overall mshr miss latency 711system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.027989 # average overall mshr miss latency 712system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.027989 # average overall mshr miss latency |
| 729system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 713system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 730system.cpu.l2cache.tags.replacements 336199 # number of replacements 731system.cpu.l2cache.tags.tagsinuse 65288.878091 # Cycle average of tags in use 732system.cpu.l2cache.tags.total_refs 3929497 # Total number of references to valid blocks. 733system.cpu.l2cache.tags.sampled_refs 401361 # Sample count of references to valid blocks. 734system.cpu.l2cache.tags.avg_refs 9.790431 # Average number of references to valid blocks. 735system.cpu.l2cache.tags.warmup_cycle 7193890000 # Cycle when the warmup percentage was hit. 736system.cpu.l2cache.tags.occ_blocks::writebacks 55462.992848 # Average occupied blocks per requestor 737system.cpu.l2cache.tags.occ_blocks::cpu.inst 4782.516669 # Average occupied blocks per requestor 738system.cpu.l2cache.tags.occ_blocks::cpu.data 5043.368573 # Average occupied blocks per requestor 739system.cpu.l2cache.tags.occ_percent::writebacks 0.846298 # Average percentage of cache occupancy 740system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072975 # Average percentage of cache occupancy 741system.cpu.l2cache.tags.occ_percent::cpu.data 0.076956 # Average percentage of cache occupancy 742system.cpu.l2cache.tags.occ_percent::total 0.996229 # Average percentage of cache occupancy 743system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id | 714system.cpu.l2cache.tags.replacements 336158 # number of replacements 715system.cpu.l2cache.tags.tagsinuse 65233.633295 # Cycle average of tags in use 716system.cpu.l2cache.tags.total_refs 3929109 # Total number of references to valid blocks. 717system.cpu.l2cache.tags.sampled_refs 401321 # Sample count of references to valid blocks. 718system.cpu.l2cache.tags.avg_refs 9.790440 # Average number of references to valid blocks. 719system.cpu.l2cache.tags.warmup_cycle 10607812000 # Cycle when the warmup percentage was hit. 720system.cpu.l2cache.tags.occ_blocks::writebacks 54990.166282 # Average occupied blocks per requestor 721system.cpu.l2cache.tags.occ_blocks::cpu.inst 4743.088898 # Average occupied blocks per requestor 722system.cpu.l2cache.tags.occ_blocks::cpu.data 5500.378115 # Average occupied blocks per requestor 723system.cpu.l2cache.tags.occ_percent::writebacks 0.839083 # Average percentage of cache occupancy 724system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072374 # Average percentage of cache occupancy 725system.cpu.l2cache.tags.occ_percent::cpu.data 0.083929 # Average percentage of cache occupancy 726system.cpu.l2cache.tags.occ_percent::total 0.995386 # Average percentage of cache occupancy 727system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id |
| 744system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id | 728system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id |
| 745system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1014 # Occupied blocks per task id 746system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4931 # Occupied blocks per task id 747system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3232 # Occupied blocks per task id 748system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55807 # Occupied blocks per task id 749system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id 750system.cpu.l2cache.tags.tag_accesses 37808402 # Number of tag accesses 751system.cpu.l2cache.tags.data_accesses 37808402 # Number of data accesses 752system.cpu.l2cache.Writeback_hits::writebacks 835293 # number of Writeback hits 753system.cpu.l2cache.Writeback_hits::total 835293 # number of Writeback hits | 729system.cpu.l2cache.tags.age_task_id_blocks_1024::1 718 # Occupied blocks per task id 730system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5223 # Occupied blocks per task id 731system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3222 # Occupied blocks per task id 732system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id 733system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 734system.cpu.l2cache.tags.tag_accesses 37802165 # Number of tag accesses 735system.cpu.l2cache.tags.data_accesses 37802165 # Number of data accesses 736system.cpu.l2cache.Writeback_hits::writebacks 834533 # number of Writeback hits 737system.cpu.l2cache.Writeback_hits::total 834533 # number of Writeback hits |
| 754system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 755system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 738system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 739system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 756system.cpu.l2cache.ReadExReq_hits::cpu.data 187720 # number of ReadExReq hits 757system.cpu.l2cache.ReadExReq_hits::total 187720 # number of ReadExReq hits 758system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 915695 # number of ReadCleanReq hits 759system.cpu.l2cache.ReadCleanReq_hits::total 915695 # number of ReadCleanReq hits 760system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814736 # number of ReadSharedReq hits 761system.cpu.l2cache.ReadSharedReq_hits::total 814736 # number of ReadSharedReq hits 762system.cpu.l2cache.demand_hits::cpu.inst 915695 # number of demand (read+write) hits 763system.cpu.l2cache.demand_hits::cpu.data 1002456 # number of demand (read+write) hits 764system.cpu.l2cache.demand_hits::total 1918151 # number of demand (read+write) hits 765system.cpu.l2cache.overall_hits::cpu.inst 915695 # number of overall hits 766system.cpu.l2cache.overall_hits::cpu.data 1002456 # number of overall hits 767system.cpu.l2cache.overall_hits::total 1918151 # number of overall hits | 740system.cpu.l2cache.ReadExReq_hits::cpu.data 187442 # number of ReadExReq hits 741system.cpu.l2cache.ReadExReq_hits::total 187442 # number of ReadExReq hits 742system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916060 # number of ReadCleanReq hits 743system.cpu.l2cache.ReadCleanReq_hits::total 916060 # number of ReadCleanReq hits 744system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814318 # number of ReadSharedReq hits 745system.cpu.l2cache.ReadSharedReq_hits::total 814318 # number of ReadSharedReq hits 746system.cpu.l2cache.demand_hits::cpu.inst 916060 # number of demand (read+write) hits 747system.cpu.l2cache.demand_hits::cpu.data 1001760 # number of demand (read+write) hits 748system.cpu.l2cache.demand_hits::total 1917820 # number of demand (read+write) hits 749system.cpu.l2cache.overall_hits::cpu.inst 916060 # number of overall hits 750system.cpu.l2cache.overall_hits::cpu.data 1001760 # number of overall hits 751system.cpu.l2cache.overall_hits::total 1917820 # number of overall hits |
| 768system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 769system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses | 752system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 753system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses |
| 770system.cpu.l2cache.ReadExReq_misses::cpu.data 116823 # number of ReadExReq misses 771system.cpu.l2cache.ReadExReq_misses::total 116823 # number of ReadExReq misses 772system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13262 # number of ReadCleanReq misses 773system.cpu.l2cache.ReadCleanReq_misses::total 13262 # number of ReadCleanReq misses 774system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271974 # number of ReadSharedReq misses 775system.cpu.l2cache.ReadSharedReq_misses::total 271974 # number of ReadSharedReq misses 776system.cpu.l2cache.demand_misses::cpu.inst 13262 # number of demand (read+write) misses 777system.cpu.l2cache.demand_misses::cpu.data 388797 # number of demand (read+write) misses 778system.cpu.l2cache.demand_misses::total 402059 # number of demand (read+write) misses 779system.cpu.l2cache.overall_misses::cpu.inst 13262 # number of overall misses 780system.cpu.l2cache.overall_misses::cpu.data 388797 # number of overall misses 781system.cpu.l2cache.overall_misses::total 402059 # number of overall misses 782system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 220000 # number of UpgradeReq miss cycles 783system.cpu.l2cache.UpgradeReq_miss_latency::total 220000 # number of UpgradeReq miss cycles 784system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8944042500 # number of ReadExReq miss cycles 785system.cpu.l2cache.ReadExReq_miss_latency::total 8944042500 # number of ReadExReq miss cycles 786system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1062602000 # number of ReadCleanReq miss cycles 787system.cpu.l2cache.ReadCleanReq_miss_latency::total 1062602000 # number of ReadCleanReq miss cycles 788system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19687124500 # number of ReadSharedReq miss cycles 789system.cpu.l2cache.ReadSharedReq_miss_latency::total 19687124500 # number of ReadSharedReq miss cycles 790system.cpu.l2cache.demand_miss_latency::cpu.inst 1062602000 # number of demand (read+write) miss cycles 791system.cpu.l2cache.demand_miss_latency::cpu.data 28631167000 # number of demand (read+write) miss cycles 792system.cpu.l2cache.demand_miss_latency::total 29693769000 # number of demand (read+write) miss cycles 793system.cpu.l2cache.overall_miss_latency::cpu.inst 1062602000 # number of overall miss cycles 794system.cpu.l2cache.overall_miss_latency::cpu.data 28631167000 # number of overall miss cycles 795system.cpu.l2cache.overall_miss_latency::total 29693769000 # number of overall miss cycles 796system.cpu.l2cache.Writeback_accesses::writebacks 835293 # number of Writeback accesses(hits+misses) 797system.cpu.l2cache.Writeback_accesses::total 835293 # number of Writeback accesses(hits+misses) | 754system.cpu.l2cache.ReadExReq_misses::cpu.data 116798 # number of ReadExReq misses 755system.cpu.l2cache.ReadExReq_misses::total 116798 # number of ReadExReq misses 756system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13263 # number of ReadCleanReq misses 757system.cpu.l2cache.ReadCleanReq_misses::total 13263 # number of ReadCleanReq misses 758system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271959 # number of ReadSharedReq misses 759system.cpu.l2cache.ReadSharedReq_misses::total 271959 # number of ReadSharedReq misses 760system.cpu.l2cache.demand_misses::cpu.inst 13263 # number of demand (read+write) misses 761system.cpu.l2cache.demand_misses::cpu.data 388757 # number of demand (read+write) misses 762system.cpu.l2cache.demand_misses::total 402020 # number of demand (read+write) misses 763system.cpu.l2cache.overall_misses::cpu.inst 13263 # number of overall misses 764system.cpu.l2cache.overall_misses::cpu.data 388757 # number of overall misses 765system.cpu.l2cache.overall_misses::total 402020 # number of overall misses 766system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles 767system.cpu.l2cache.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles 768system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14883886000 # number of ReadExReq miss cycles 769system.cpu.l2cache.ReadExReq_miss_latency::total 14883886000 # number of ReadExReq miss cycles 770system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1737439000 # number of ReadCleanReq miss cycles 771system.cpu.l2cache.ReadCleanReq_miss_latency::total 1737439000 # number of ReadCleanReq miss cycles 772system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33716172000 # number of ReadSharedReq miss cycles 773system.cpu.l2cache.ReadSharedReq_miss_latency::total 33716172000 # number of ReadSharedReq miss cycles 774system.cpu.l2cache.demand_miss_latency::cpu.inst 1737439000 # number of demand (read+write) miss cycles 775system.cpu.l2cache.demand_miss_latency::cpu.data 48600058000 # number of demand (read+write) miss cycles 776system.cpu.l2cache.demand_miss_latency::total 50337497000 # number of demand (read+write) miss cycles 777system.cpu.l2cache.overall_miss_latency::cpu.inst 1737439000 # number of overall miss cycles 778system.cpu.l2cache.overall_miss_latency::cpu.data 48600058000 # number of overall miss cycles 779system.cpu.l2cache.overall_miss_latency::total 50337497000 # number of overall miss cycles 780system.cpu.l2cache.Writeback_accesses::writebacks 834533 # number of Writeback accesses(hits+misses) 781system.cpu.l2cache.Writeback_accesses::total 834533 # number of Writeback accesses(hits+misses) |
| 798system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 799system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) | 782system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 783system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) |
| 800system.cpu.l2cache.ReadExReq_accesses::cpu.data 304543 # number of ReadExReq accesses(hits+misses) 801system.cpu.l2cache.ReadExReq_accesses::total 304543 # number of ReadExReq accesses(hits+misses) 802system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 928957 # number of ReadCleanReq accesses(hits+misses) 803system.cpu.l2cache.ReadCleanReq_accesses::total 928957 # number of ReadCleanReq accesses(hits+misses) 804system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086710 # number of ReadSharedReq accesses(hits+misses) 805system.cpu.l2cache.ReadSharedReq_accesses::total 1086710 # number of ReadSharedReq accesses(hits+misses) 806system.cpu.l2cache.demand_accesses::cpu.inst 928957 # number of demand (read+write) accesses 807system.cpu.l2cache.demand_accesses::cpu.data 1391253 # number of demand (read+write) accesses 808system.cpu.l2cache.demand_accesses::total 2320210 # number of demand (read+write) accesses 809system.cpu.l2cache.overall_accesses::cpu.inst 928957 # number of overall (read+write) accesses 810system.cpu.l2cache.overall_accesses::cpu.data 1391253 # number of overall (read+write) accesses 811system.cpu.l2cache.overall_accesses::total 2320210 # number of overall (read+write) accesses | 784system.cpu.l2cache.ReadExReq_accesses::cpu.data 304240 # number of ReadExReq accesses(hits+misses) 785system.cpu.l2cache.ReadExReq_accesses::total 304240 # number of ReadExReq accesses(hits+misses) 786system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929323 # number of ReadCleanReq accesses(hits+misses) 787system.cpu.l2cache.ReadCleanReq_accesses::total 929323 # number of ReadCleanReq accesses(hits+misses) 788system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086277 # number of ReadSharedReq accesses(hits+misses) 789system.cpu.l2cache.ReadSharedReq_accesses::total 1086277 # number of ReadSharedReq accesses(hits+misses) 790system.cpu.l2cache.demand_accesses::cpu.inst 929323 # number of demand (read+write) accesses 791system.cpu.l2cache.demand_accesses::cpu.data 1390517 # number of demand (read+write) accesses 792system.cpu.l2cache.demand_accesses::total 2319840 # number of demand (read+write) accesses 793system.cpu.l2cache.overall_accesses::cpu.inst 929323 # number of overall (read+write) accesses 794system.cpu.l2cache.overall_accesses::cpu.data 1390517 # number of overall (read+write) accesses 795system.cpu.l2cache.overall_accesses::total 2319840 # number of overall (read+write) accesses |
| 812system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 813system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses | 796system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 797system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses |
| 814system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383601 # miss rate for ReadExReq accesses 815system.cpu.l2cache.ReadExReq_miss_rate::total 0.383601 # miss rate for ReadExReq accesses 816system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014276 # miss rate for ReadCleanReq accesses 817system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014276 # miss rate for ReadCleanReq accesses 818system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250273 # miss rate for ReadSharedReq accesses 819system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250273 # miss rate for ReadSharedReq accesses 820system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014276 # miss rate for demand accesses 821system.cpu.l2cache.demand_miss_rate::cpu.data 0.279458 # miss rate for demand accesses 822system.cpu.l2cache.demand_miss_rate::total 0.173286 # miss rate for demand accesses 823system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014276 # miss rate for overall accesses 824system.cpu.l2cache.overall_miss_rate::cpu.data 0.279458 # miss rate for overall accesses 825system.cpu.l2cache.overall_miss_rate::total 0.173286 # miss rate for overall accesses 826system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16923.076923 # average UpgradeReq miss latency 827system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16923.076923 # average UpgradeReq miss latency 828system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76560.630184 # average ReadExReq miss latency 829system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76560.630184 # average ReadExReq miss latency 830system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80123.812396 # average ReadCleanReq miss latency 831system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80123.812396 # average ReadCleanReq miss latency 832system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72386.053446 # average ReadSharedReq miss latency 833system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72386.053446 # average ReadSharedReq miss latency 834system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80123.812396 # average overall miss latency 835system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73640.401032 # average overall miss latency 836system.cpu.l2cache.demand_avg_miss_latency::total 73854.257708 # average overall miss latency 837system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80123.812396 # average overall miss latency 838system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73640.401032 # average overall miss latency 839system.cpu.l2cache.overall_avg_miss_latency::total 73854.257708 # average overall miss latency | 798system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383901 # miss rate for ReadExReq accesses 799system.cpu.l2cache.ReadExReq_miss_rate::total 0.383901 # miss rate for ReadExReq accesses 800system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014272 # miss rate for ReadCleanReq accesses 801system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014272 # miss rate for ReadCleanReq accesses 802system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250359 # miss rate for ReadSharedReq accesses 803system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250359 # miss rate for ReadSharedReq accesses 804system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014272 # miss rate for demand accesses 805system.cpu.l2cache.demand_miss_rate::cpu.data 0.279577 # miss rate for demand accesses 806system.cpu.l2cache.demand_miss_rate::total 0.173296 # miss rate for demand accesses 807system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014272 # miss rate for overall accesses 808system.cpu.l2cache.overall_miss_rate::cpu.data 0.279577 # miss rate for overall accesses 809system.cpu.l2cache.overall_miss_rate::total 0.173296 # miss rate for overall accesses 810system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24615.384615 # average UpgradeReq miss latency 811system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24615.384615 # average UpgradeReq miss latency 812system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127432.712889 # average ReadExReq miss latency 813system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127432.712889 # average ReadExReq miss latency 814system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130998.944432 # average ReadCleanReq miss latency 815system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130998.944432 # average ReadCleanReq miss latency 816system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123975.202144 # average ReadSharedReq miss latency 817system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123975.202144 # average ReadSharedReq miss latency 818system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130998.944432 # average overall miss latency 819system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency 820system.cpu.l2cache.demand_avg_miss_latency::total 125211.424805 # average overall miss latency 821system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130998.944432 # average overall miss latency 822system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency 823system.cpu.l2cache.overall_avg_miss_latency::total 125211.424805 # average overall miss latency |
| 840system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 841system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 842system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 843system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 844system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 845system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 846system.cpu.l2cache.fast_writes 0 # number of fast writes performed 847system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 824system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 825system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 826system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 827system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 828system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 829system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 830system.cpu.l2cache.fast_writes 0 # number of fast writes performed 831system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 848system.cpu.l2cache.writebacks::writebacks 74255 # number of writebacks 849system.cpu.l2cache.writebacks::total 74255 # number of writebacks | 832system.cpu.l2cache.writebacks::writebacks 74231 # number of writebacks 833system.cpu.l2cache.writebacks::total 74231 # number of writebacks |
| 850system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 280 # number of CleanEvict MSHR misses 851system.cpu.l2cache.CleanEvict_mshr_misses::total 280 # number of CleanEvict MSHR misses 852system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 853system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses | 834system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 280 # number of CleanEvict MSHR misses 835system.cpu.l2cache.CleanEvict_mshr_misses::total 280 # number of CleanEvict MSHR misses 836system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 837system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses |
| 854system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116823 # number of ReadExReq MSHR misses 855system.cpu.l2cache.ReadExReq_mshr_misses::total 116823 # number of ReadExReq MSHR misses 856system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13262 # number of ReadCleanReq MSHR misses 857system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13262 # number of ReadCleanReq MSHR misses 858system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271974 # number of ReadSharedReq MSHR misses 859system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271974 # number of ReadSharedReq MSHR misses 860system.cpu.l2cache.demand_mshr_misses::cpu.inst 13262 # number of demand (read+write) MSHR misses 861system.cpu.l2cache.demand_mshr_misses::cpu.data 388797 # number of demand (read+write) MSHR misses 862system.cpu.l2cache.demand_mshr_misses::total 402059 # number of demand (read+write) MSHR misses 863system.cpu.l2cache.overall_mshr_misses::cpu.inst 13262 # number of overall MSHR misses 864system.cpu.l2cache.overall_mshr_misses::cpu.data 388797 # number of overall MSHR misses 865system.cpu.l2cache.overall_mshr_misses::total 402059 # number of overall MSHR misses | 838system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116798 # number of ReadExReq MSHR misses 839system.cpu.l2cache.ReadExReq_mshr_misses::total 116798 # number of ReadExReq MSHR misses 840system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13263 # number of ReadCleanReq MSHR misses 841system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13263 # number of ReadCleanReq MSHR misses 842system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271959 # number of ReadSharedReq MSHR misses 843system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271959 # number of ReadSharedReq MSHR misses 844system.cpu.l2cache.demand_mshr_misses::cpu.inst 13263 # number of demand (read+write) MSHR misses 845system.cpu.l2cache.demand_mshr_misses::cpu.data 388757 # number of demand (read+write) MSHR misses 846system.cpu.l2cache.demand_mshr_misses::total 402020 # number of demand (read+write) MSHR misses 847system.cpu.l2cache.overall_mshr_misses::cpu.inst 13263 # number of overall MSHR misses 848system.cpu.l2cache.overall_mshr_misses::cpu.data 388757 # number of overall MSHR misses 849system.cpu.l2cache.overall_mshr_misses::total 402020 # number of overall MSHR misses |
| 866system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 867system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable | 850system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 851system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable |
| 868system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable 869system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable 870system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses 871system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses 872system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 364500 # number of UpgradeReq MSHR miss cycles 873system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 364500 # number of UpgradeReq MSHR miss cycles 874system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7775812500 # number of ReadExReq MSHR miss cycles 875system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7775812500 # number of ReadExReq MSHR miss cycles 876system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 929982000 # number of ReadCleanReq MSHR miss cycles 877system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 929982000 # number of ReadCleanReq MSHR miss cycles 878system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16967384500 # number of ReadSharedReq MSHR miss cycles 879system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16967384500 # number of ReadSharedReq MSHR miss cycles 880system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 929982000 # number of demand (read+write) MSHR miss cycles 881system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24743197000 # number of demand (read+write) MSHR miss cycles 882system.cpu.l2cache.demand_mshr_miss_latency::total 25673179000 # number of demand (read+write) MSHR miss cycles 883system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 929982000 # number of overall MSHR miss cycles 884system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24743197000 # number of overall MSHR miss cycles 885system.cpu.l2cache.overall_mshr_miss_latency::total 25673179000 # number of overall MSHR miss cycles 886system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363485500 # number of ReadReq MSHR uncacheable cycles 887system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363485500 # number of ReadReq MSHR uncacheable cycles 888system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1938590500 # number of WriteReq MSHR uncacheable cycles 889system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1938590500 # number of WriteReq MSHR uncacheable cycles 890system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3302076000 # number of overall MSHR uncacheable cycles 891system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3302076000 # number of overall MSHR uncacheable cycles | 852system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable 853system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable 854system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses 855system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses 856system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 922500 # number of UpgradeReq MSHR miss cycles 857system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 922500 # number of UpgradeReq MSHR miss cycles 858system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13715906000 # number of ReadExReq MSHR miss cycles 859system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13715906000 # number of ReadExReq MSHR miss cycles 860system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1604809000 # number of ReadCleanReq MSHR miss cycles 861system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1604809000 # number of ReadCleanReq MSHR miss cycles 862system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30996582000 # number of ReadSharedReq MSHR miss cycles 863system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30996582000 # number of ReadSharedReq MSHR miss cycles 864system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1604809000 # number of demand (read+write) MSHR miss cycles 865system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44712488000 # number of demand (read+write) MSHR miss cycles 866system.cpu.l2cache.demand_mshr_miss_latency::total 46317297000 # number of demand (read+write) MSHR miss cycles 867system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1604809000 # number of overall MSHR miss cycles 868system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44712488000 # number of overall MSHR miss cycles 869system.cpu.l2cache.overall_mshr_miss_latency::total 46317297000 # number of overall MSHR miss cycles 870system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363484500 # number of ReadReq MSHR uncacheable cycles 871system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363484500 # number of ReadReq MSHR uncacheable cycles 872system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1939234000 # number of WriteReq MSHR uncacheable cycles 873system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1939234000 # number of WriteReq MSHR uncacheable cycles 874system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3302718500 # number of overall MSHR uncacheable cycles 875system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3302718500 # number of overall MSHR uncacheable cycles |
| 892system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 893system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 894system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 895system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses | 876system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 877system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 878system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 879system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses |
| 896system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383601 # mshr miss rate for ReadExReq accesses 897system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383601 # mshr miss rate for ReadExReq accesses 898system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for ReadCleanReq accesses 899system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014276 # mshr miss rate for ReadCleanReq accesses 900system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250273 # mshr miss rate for ReadSharedReq accesses 901system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250273 # mshr miss rate for ReadSharedReq accesses 902system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for demand accesses 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for demand accesses 904system.cpu.l2cache.demand_mshr_miss_rate::total 0.173286 # mshr miss rate for demand accesses 905system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for overall accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for overall accesses 907system.cpu.l2cache.overall_mshr_miss_rate::total 0.173286 # mshr miss rate for overall accesses 908system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 28038.461538 # average UpgradeReq mshr miss latency 909system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 28038.461538 # average UpgradeReq mshr miss latency 910system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66560.630184 # average ReadExReq mshr miss latency 911system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66560.630184 # average ReadExReq mshr miss latency 912system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70123.812396 # average ReadCleanReq mshr miss latency 913system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70123.812396 # average ReadCleanReq mshr miss latency 914system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62386.053446 # average ReadSharedReq mshr miss latency 915system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62386.053446 # average ReadSharedReq mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency 921system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency 922system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.154401 # average ReadReq mshr uncacheable latency 923system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.154401 # average ReadReq mshr uncacheable latency 924system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200890.207254 # average WriteReq mshr uncacheable latency 925system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200890.207254 # average WriteReq mshr uncacheable latency 926system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199160.193004 # average overall mshr uncacheable latency 927system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199160.193004 # average overall mshr uncacheable latency | 880system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383901 # mshr miss rate for ReadExReq accesses 881system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383901 # mshr miss rate for ReadExReq accesses 882system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for ReadCleanReq accesses 883system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014272 # mshr miss rate for ReadCleanReq accesses 884system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250359 # mshr miss rate for ReadSharedReq accesses 885system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250359 # mshr miss rate for ReadSharedReq accesses 886system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for demand accesses 887system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for demand accesses 888system.cpu.l2cache.demand_mshr_miss_rate::total 0.173296 # mshr miss rate for demand accesses 889system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for overall accesses 890system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for overall accesses 891system.cpu.l2cache.overall_mshr_miss_rate::total 0.173296 # mshr miss rate for overall accesses 892system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70961.538462 # average UpgradeReq mshr miss latency 893system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70961.538462 # average UpgradeReq mshr miss latency 894system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117432.712889 # average ReadExReq mshr miss latency 895system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117432.712889 # average ReadExReq mshr miss latency 896system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120998.944432 # average ReadCleanReq mshr miss latency 897system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120998.944432 # average ReadCleanReq mshr miss latency 898system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113975.202144 # average ReadSharedReq mshr miss latency 899system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113975.202144 # average ReadSharedReq mshr miss latency 900system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency 901system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency 902system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency 903system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency 904system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency 905system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency 906system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.010101 # average ReadReq mshr uncacheable latency 907system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.010101 # average ReadReq mshr uncacheable latency 908system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200894.436963 # average WriteReq mshr uncacheable latency 909system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200894.436963 # average WriteReq mshr uncacheable latency 910system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199162.907797 # average overall mshr uncacheable latency 911system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199162.907797 # average overall mshr uncacheable latency |
| 928system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 912system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 913system.cpu.toL2Bus.snoop_filter.tot_requests 4638553 # Total number of requests made to the snoop filter. 914system.cpu.toL2Bus.snoop_filter.hit_single_requests 2318842 # Number of requests hitting in the snoop filter with a single holder of the requested data. 915system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 916system.cpu.toL2Bus.snoop_filter.tot_snoops 1135 # Total number of snoops made to the snoop filter. 917system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1135 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 918system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 929system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution | 919system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution |
| 930system.cpu.toL2Bus.trans_dist::ReadResp 2022774 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::Writeback 951075 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::CleanEvict 1744381 # Transaction distribution | 920system.cpu.toL2Bus.trans_dist::ReadResp 2022707 # Transaction distribution 921system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution 922system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution 923system.cpu.toL2Bus.trans_dist::Writeback 950299 # Transaction distribution 924system.cpu.toL2Bus.trans_dist::CleanEvict 1744757 # Transaction distribution |
| 935system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 936system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution | 925system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 926system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution |
| 937system.cpu.toL2Bus.trans_dist::ReadExReq 304543 # Transaction distribution 938system.cpu.toL2Bus.trans_dist::ReadExResp 304543 # Transaction distribution 939system.cpu.toL2Bus.trans_dist::ReadCleanReq 928977 # Transaction distribution 940system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086883 # Transaction distribution | 927system.cpu.toL2Bus.trans_dist::ReadExReq 304240 # Transaction distribution 928system.cpu.toL2Bus.trans_dist::ReadExResp 304240 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::ReadCleanReq 929343 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086450 # Transaction distribution |
| 941system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution | 931system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| 942system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2786015 # Packet count per connected master and slave (bytes) 943system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205333 # Packet count per connected master and slave (bytes) 944system.cpu.toL2Bus.pkt_count::total 6991348 # Packet count per connected master and slave (bytes) 945system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59453248 # Cumulative packet size per connected master and slave (bytes) 946system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142553556 # Cumulative packet size per connected master and slave (bytes) 947system.cpu.toL2Bus.pkt_size::total 202006804 # Cumulative packet size per connected master and slave (bytes) 948system.cpu.toL2Bus.snoops 419801 # Total snoops (count) 949system.cpu.toL2Bus.snoop_fanout::samples 5075497 # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::mean 1.082676 # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::stdev 0.275393 # Request fanout histogram | 932system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787117 # Packet count per connected master and slave (bytes) 933system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4203130 # Packet count per connected master and slave (bytes) 934system.cpu.toL2Bus.pkt_count::total 6990247 # Packet count per connected master and slave (bytes) 935system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476672 # Cumulative packet size per connected master and slave (bytes) 936system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142457836 # Cumulative packet size per connected master and slave (bytes) 937system.cpu.toL2Bus.pkt_size::total 201934508 # Cumulative packet size per connected master and slave (bytes) 938system.cpu.toL2Bus.snoops 419768 # Total snoops (count) 939system.cpu.toL2Bus.snoop_fanout::samples 5074727 # Request fanout histogram 940system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram 941system.cpu.toL2Bus.snoop_fanout::stdev 0.029056 # Request fanout histogram |
| 952system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 942system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 953system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 954system.cpu.toL2Bus.snoop_fanout::1 4655873 91.73% 91.73% # Request fanout histogram 955system.cpu.toL2Bus.snoop_fanout::2 419624 8.27% 100.00% # Request fanout histogram | 943system.cpu.toL2Bus.snoop_fanout::0 5070439 99.92% 99.92% # Request fanout histogram 944system.cpu.toL2Bus.snoop_fanout::1 4288 0.08% 100.00% # Request fanout histogram 945system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| 956system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 946system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 957system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 958system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 959system.cpu.toL2Bus.snoop_fanout::total 5075497 # Request fanout histogram 960system.cpu.toL2Bus.reqLayer0.occupancy 3168054500 # Layer occupancy (ticks) | 947system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 948system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::total 5074727 # Request fanout histogram 950system.cpu.toL2Bus.reqLayer0.occupancy 3166927500 # Layer occupancy (ticks) |
| 961system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 951system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 962system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) | 952system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) |
| 963system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 953system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 964system.cpu.toL2Bus.respLayer0.occupancy 1393465500 # Layer occupancy (ticks) | 954system.cpu.toL2Bus.respLayer0.occupancy 1394014500 # Layer occupancy (ticks) |
| 965system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 955system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 966system.cpu.toL2Bus.respLayer1.occupancy 2098643000 # Layer occupancy (ticks) | 956system.cpu.toL2Bus.respLayer1.occupancy 2097540500 # Layer occupancy (ticks) |
| 967system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 968system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 969system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 970system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 971system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 972system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 973system.disk0.dma_write_txs 395 # Number of DMA write transactions. 974system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 975system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 976system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 977system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 978system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 979system.disk2.dma_write_txs 1 # Number of DMA write transactions. 980system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 981system.iobus.trans_dist::ReadResp 7103 # Transaction distribution | 957system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 958system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 959system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 960system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 961system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 962system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 963system.disk0.dma_write_txs 395 # Number of DMA write transactions. 964system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 965system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 966system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 967system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 968system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 969system.disk2.dma_write_txs 1 # Number of DMA write transactions. 970system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 971system.iobus.trans_dist::ReadResp 7103 # Transaction distribution |
| 982system.iobus.trans_dist::WriteReq 51202 # Transaction distribution 983system.iobus.trans_dist::WriteResp 51202 # Transaction distribution 984system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) | 972system.iobus.trans_dist::WriteReq 51205 # Transaction distribution 973system.iobus.trans_dist::WriteResp 51205 # Transaction distribution 974system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) |
| 985system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 986system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 987system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 988system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 989system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 990system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 991system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 992system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 993system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 994system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 995system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 975system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 976system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 977system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 978system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 979system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 980system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 981system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 982system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 983system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 984system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 985system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 996system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) | 986system.iobus.pkt_count_system.bridge.master::total 33166 # Packet count per connected master and slave (bytes) |
| 997system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 998system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) | 987system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 988system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) |
| 999system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) 1000system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) | 989system.iobus.pkt_count::total 116616 # Packet count per connected master and slave (bytes) 990system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20648 # Cumulative packet size per connected master and slave (bytes) |
| 1001system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 1002system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1003system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1004system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1005system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 1006system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 1007system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1008system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1009system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1010system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1011system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 991system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 992system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 993system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 994system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 995system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 996system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 997system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 998system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 999system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1000system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1001system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 1012system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) | 1002system.iobus.pkt_size_system.bridge.master::total 44588 # Cumulative packet size per connected master and slave (bytes) |
| 1013system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1014system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) | 1003system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 1004system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) |
| 1015system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) 1016system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) | 1005system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) 1006system.iobus.reqLayer0.occupancy 4773000 # Layer occupancy (ticks) |
| 1017system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1018system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 1019system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1020system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1021system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1022system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1023system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1024system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1030system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1031system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1032system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1033system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1034system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1035system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1036system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1037system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 1007system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1008system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 1009system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1010system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1011system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1012system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1013system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1014system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1020system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1021system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1022system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1023system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1024system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1025system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1026system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1027system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1038system.iobus.reqLayer29.occupancy 216066756 # Layer occupancy (ticks) | 1028system.iobus.reqLayer29.occupancy 215085744 # Layer occupancy (ticks) |
| 1039system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1040system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1041system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | 1029system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1030system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1031system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) |
| 1042system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) | 1032system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) |
| 1043system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1044system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1045system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1046system.iocache.tags.replacements 41685 # number of replacements | 1033system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1034system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1035system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1036system.iocache.tags.replacements 41685 # number of replacements |
| 1047system.iocache.tags.tagsinuse 1.342844 # Cycle average of tags in use | 1037system.iocache.tags.tagsinuse 1.339381 # Cycle average of tags in use |
| 1048system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1049system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1050system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1038system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1039system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1040system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1051system.iocache.tags.warmup_cycle 1756461860000 # Cycle when the warmup percentage was hit. 1052system.iocache.tags.occ_blocks::tsunami.ide 1.342844 # Average occupied blocks per requestor 1053system.iocache.tags.occ_percent::tsunami.ide 0.083928 # Average percentage of cache occupancy 1054system.iocache.tags.occ_percent::total 0.083928 # Average percentage of cache occupancy | 1041system.iocache.tags.warmup_cycle 1774103808000 # Cycle when the warmup percentage was hit. 1042system.iocache.tags.occ_blocks::tsunami.ide 1.339381 # Average occupied blocks per requestor 1043system.iocache.tags.occ_percent::tsunami.ide 0.083711 # Average percentage of cache occupancy 1044system.iocache.tags.occ_percent::total 0.083711 # Average percentage of cache occupancy |
| 1055system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1056system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1057system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1058system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1059system.iocache.tags.data_accesses 375525 # Number of data accesses 1060system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1061system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1062system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1063system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1064system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1065system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1066system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1067system.iocache.overall_misses::total 173 # number of overall misses | 1045system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1046system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1047system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1048system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1049system.iocache.tags.data_accesses 375525 # Number of data accesses 1050system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1051system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1052system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1053system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1054system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1055system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1056system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1057system.iocache.overall_misses::total 173 # number of overall misses |
| 1068system.iocache.ReadReq_miss_latency::tsunami.ide 21632883 # number of ReadReq miss cycles 1069system.iocache.ReadReq_miss_latency::total 21632883 # number of ReadReq miss cycles 1070system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907244873 # number of WriteLineReq miss cycles 1071system.iocache.WriteLineReq_miss_latency::total 4907244873 # number of WriteLineReq miss cycles 1072system.iocache.demand_miss_latency::tsunami.ide 21632883 # number of demand (read+write) miss cycles 1073system.iocache.demand_miss_latency::total 21632883 # number of demand (read+write) miss cycles 1074system.iocache.overall_miss_latency::tsunami.ide 21632883 # number of overall miss cycles 1075system.iocache.overall_miss_latency::total 21632883 # number of overall miss cycles | 1058system.iocache.ReadReq_miss_latency::tsunami.ide 21913883 # number of ReadReq miss cycles 1059system.iocache.ReadReq_miss_latency::total 21913883 # number of ReadReq miss cycles 1060system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427871861 # number of WriteLineReq miss cycles 1061system.iocache.WriteLineReq_miss_latency::total 5427871861 # number of WriteLineReq miss cycles 1062system.iocache.demand_miss_latency::tsunami.ide 21913883 # number of demand (read+write) miss cycles 1063system.iocache.demand_miss_latency::total 21913883 # number of demand (read+write) miss cycles 1064system.iocache.overall_miss_latency::tsunami.ide 21913883 # number of overall miss cycles 1065system.iocache.overall_miss_latency::total 21913883 # number of overall miss cycles |
| 1076system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1077system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1078system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1079system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1080system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1081system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1082system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1083system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1084system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1085system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1086system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1087system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1088system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1089system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1090system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1091system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1066system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1067system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1068system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1069system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1070system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1071system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1072system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1073system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1074system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1075system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1076system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1077system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1078system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1079system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1080system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1081system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1092system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125045.566474 # average ReadReq miss latency 1093system.iocache.ReadReq_avg_miss_latency::total 125045.566474 # average ReadReq miss latency 1094system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118098.885084 # average WriteLineReq miss latency 1095system.iocache.WriteLineReq_avg_miss_latency::total 118098.885084 # average WriteLineReq miss latency 1096system.iocache.demand_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency 1097system.iocache.demand_avg_miss_latency::total 125045.566474 # average overall miss latency 1098system.iocache.overall_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency 1099system.iocache.overall_avg_miss_latency::total 125045.566474 # average overall miss latency | 1082system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126669.843931 # average ReadReq miss latency 1083system.iocache.ReadReq_avg_miss_latency::total 126669.843931 # average ReadReq miss latency 1084system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130628.414059 # average WriteLineReq miss latency 1085system.iocache.WriteLineReq_avg_miss_latency::total 130628.414059 # average WriteLineReq miss latency 1086system.iocache.demand_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency 1087system.iocache.demand_avg_miss_latency::total 126669.843931 # average overall miss latency 1088system.iocache.overall_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency 1089system.iocache.overall_avg_miss_latency::total 126669.843931 # average overall miss latency |
| 1100system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1101system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1102system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1103system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1104system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1105system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1106system.iocache.fast_writes 0 # number of fast writes performed 1107system.iocache.cache_copies 0 # number of cache copies performed 1108system.iocache.writebacks::writebacks 41512 # number of writebacks 1109system.iocache.writebacks::total 41512 # number of writebacks 1110system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1111system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1112system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1113system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1114system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1115system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1116system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1117system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses | 1090system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1091system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1092system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1093system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1094system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1095system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1096system.iocache.fast_writes 0 # number of fast writes performed 1097system.iocache.cache_copies 0 # number of cache copies performed 1098system.iocache.writebacks::writebacks 41512 # number of writebacks 1099system.iocache.writebacks::total 41512 # number of writebacks 1100system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1101system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1102system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1103system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1104system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1105system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1106system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1107system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses |
| 1118system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12982883 # number of ReadReq MSHR miss cycles 1119system.iocache.ReadReq_mshr_miss_latency::total 12982883 # number of ReadReq MSHR miss cycles 1120system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829644873 # number of WriteLineReq MSHR miss cycles 1121system.iocache.WriteLineReq_mshr_miss_latency::total 2829644873 # number of WriteLineReq MSHR miss cycles 1122system.iocache.demand_mshr_miss_latency::tsunami.ide 12982883 # number of demand (read+write) MSHR miss cycles 1123system.iocache.demand_mshr_miss_latency::total 12982883 # number of demand (read+write) MSHR miss cycles 1124system.iocache.overall_mshr_miss_latency::tsunami.ide 12982883 # number of overall MSHR miss cycles 1125system.iocache.overall_mshr_miss_latency::total 12982883 # number of overall MSHR miss cycles | 1108system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13263883 # number of ReadReq MSHR miss cycles 1109system.iocache.ReadReq_mshr_miss_latency::total 13263883 # number of ReadReq MSHR miss cycles 1110system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350271861 # number of WriteLineReq MSHR miss cycles 1111system.iocache.WriteLineReq_mshr_miss_latency::total 3350271861 # number of WriteLineReq MSHR miss cycles 1112system.iocache.demand_mshr_miss_latency::tsunami.ide 13263883 # number of demand (read+write) MSHR miss cycles 1113system.iocache.demand_mshr_miss_latency::total 13263883 # number of demand (read+write) MSHR miss cycles 1114system.iocache.overall_mshr_miss_latency::tsunami.ide 13263883 # number of overall MSHR miss cycles 1115system.iocache.overall_mshr_miss_latency::total 13263883 # number of overall MSHR miss cycles |
| 1126system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1127system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1128system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1129system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1130system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1131system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1132system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1133system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1116system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1117system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1118system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1119system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1120system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1121system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1122system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1123system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1134system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average ReadReq mshr miss latency 1135system.iocache.ReadReq_avg_mshr_miss_latency::total 75045.566474 # average ReadReq mshr miss latency 1136system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68098.885084 # average WriteLineReq mshr miss latency 1137system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68098.885084 # average WriteLineReq mshr miss latency 1138system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency 1139system.iocache.demand_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency 1140system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency 1141system.iocache.overall_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency | 1124system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average ReadReq mshr miss latency 1125system.iocache.ReadReq_avg_mshr_miss_latency::total 76669.843931 # average ReadReq mshr miss latency 1126system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80628.414059 # average WriteLineReq mshr miss latency 1127system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80628.414059 # average WriteLineReq mshr miss latency 1128system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency 1129system.iocache.demand_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency 1130system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency 1131system.iocache.overall_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency |
| 1142system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1143system.membus.trans_dist::ReadReq 6930 # Transaction distribution | 1132system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1133system.membus.trans_dist::ReadReq 6930 # Transaction distribution |
| 1144system.membus.trans_dist::ReadResp 292339 # Transaction distribution 1145system.membus.trans_dist::WriteReq 9650 # Transaction distribution 1146system.membus.trans_dist::WriteResp 9650 # Transaction distribution 1147system.membus.trans_dist::Writeback 115767 # Transaction distribution 1148system.membus.trans_dist::CleanEvict 261512 # Transaction distribution | 1134system.membus.trans_dist::ReadResp 292325 # Transaction distribution 1135system.membus.trans_dist::WriteReq 9653 # Transaction distribution 1136system.membus.trans_dist::WriteResp 9653 # Transaction distribution 1137system.membus.trans_dist::Writeback 115743 # Transaction distribution 1138system.membus.trans_dist::CleanEvict 261495 # Transaction distribution |
| 1149system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 1150system.membus.trans_dist::UpgradeResp 132 # Transaction distribution | 1139system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 1140system.membus.trans_dist::UpgradeResp 132 # Transaction distribution |
| 1151system.membus.trans_dist::ReadExReq 116704 # Transaction distribution 1152system.membus.trans_dist::ReadExResp 116704 # Transaction distribution 1153system.membus.trans_dist::ReadSharedReq 285409 # Transaction distribution | 1141system.membus.trans_dist::ReadExReq 116679 # Transaction distribution 1142system.membus.trans_dist::ReadExResp 116679 # Transaction distribution 1143system.membus.trans_dist::ReadSharedReq 285395 # Transaction distribution |
| 1154system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1155system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution | 1144system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1145system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution |
| 1156system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) 1157system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139625 # Packet count per connected master and slave (bytes) 1158system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172785 # Packet count per connected master and slave (bytes) | 1146system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) 1147system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139506 # Packet count per connected master and slave (bytes) 1148system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172672 # Packet count per connected master and slave (bytes) |
| 1159system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) 1160system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) | 1149system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) 1150system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) |
| 1161system.membus.pkt_count::total 1297602 # Packet count per connected master and slave (bytes) 1162system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) 1163system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30459136 # Cumulative packet size per connected master and slave (bytes) 1164system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30503700 # Cumulative packet size per connected master and slave (bytes) | 1151system.membus.pkt_count::total 1297489 # Packet count per connected master and slave (bytes) 1152system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) 1153system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455104 # Cumulative packet size per connected master and slave (bytes) 1154system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499692 # Cumulative packet size per connected master and slave (bytes) |
| 1165system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1166system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) | 1155system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) 1156system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) |
| 1167system.membus.pkt_size::total 33161428 # Cumulative packet size per connected master and slave (bytes) | 1157system.membus.pkt_size::total 33157420 # Cumulative packet size per connected master and slave (bytes) |
| 1168system.membus.snoops 431 # Total snoops (count) | 1158system.membus.snoops 431 # Total snoops (count) |
| 1169system.membus.snoop_fanout::samples 837831 # Request fanout histogram | 1159system.membus.snoop_fanout::samples 837762 # Request fanout histogram |
| 1170system.membus.snoop_fanout::mean 1 # Request fanout histogram 1171system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1172system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1173system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1160system.membus.snoop_fanout::mean 1 # Request fanout histogram 1161system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1162system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1163system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1174system.membus.snoop_fanout::1 837831 100.00% 100.00% # Request fanout histogram | 1164system.membus.snoop_fanout::1 837762 100.00% 100.00% # Request fanout histogram |
| 1175system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1176system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1177system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1178system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1165system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1166system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1167system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1168system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1179system.membus.snoop_fanout::total 837831 # Request fanout histogram 1180system.membus.reqLayer0.occupancy 30056000 # Layer occupancy (ticks) | 1169system.membus.snoop_fanout::total 837762 # Request fanout histogram 1170system.membus.reqLayer0.occupancy 30061000 # Layer occupancy (ticks) |
| 1181system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1171system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1182system.membus.reqLayer1.occupancy 1285352189 # Layer occupancy (ticks) | 1172system.membus.reqLayer1.occupancy 1285186893 # Layer occupancy (ticks) |
| 1183system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1173system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1184system.membus.respLayer1.occupancy 2143948368 # Layer occupancy (ticks) | 1174system.membus.respLayer1.occupancy 2143459620 # Layer occupancy (ticks) |
| 1185system.membus.respLayer1.utilization 0.1 # Layer utilization (%) | 1175system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1186system.membus.respLayer2.occupancy 72076390 # Layer occupancy (ticks) | 1176system.membus.respLayer2.occupancy 69854947 # Layer occupancy (ticks) |
| 1187system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1188system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1189system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1190system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1191system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1192system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1193system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1194system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- | 1177system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1178system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1179system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1180system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1181system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1182system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1183system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1184system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- |