| stats.txt (10726:8a20e2a1562d) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.922414 # Number of seconds simulated 4sim_ticks 1922413663500 # Number of ticks simulated 5final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.922414 # Number of seconds simulated 4sim_ticks 1922413663500 # Number of ticks simulated 5final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1122927 # Simulator instruction rate (inst/s) 8host_op_rate 1122927 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38428929684 # Simulator tick rate (ticks/s) 10host_mem_usage 370248 # Number of bytes of host memory used 11host_seconds 50.03 # Real time elapsed on the host | 7host_inst_rate 912210 # Simulator instruction rate (inst/s) 8host_op_rate 912209 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 31217732593 # Simulator tick rate (ticks/s) 10host_mem_usage 318584 # Number of bytes of host memory used 11host_seconds 61.58 # Real time elapsed on the host |
| 12sim_insts 56174594 # Number of instructions simulated 13sim_ops 56174594 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory --- 561 unchanged lines hidden (view full) --- 581system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304369 # number of WriteReq MSHR misses 582system.cpu.dcache.WriteReq_mshr_misses::total 304369 # number of WriteReq MSHR misses 583system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17287 # number of LoadLockedReq MSHR misses 584system.cpu.dcache.LoadLockedReq_mshr_misses::total 17287 # number of LoadLockedReq MSHR misses 585system.cpu.dcache.demand_mshr_misses::cpu.data 1374617 # number of demand (read+write) MSHR misses 586system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses 587system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses 588system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses | 12sim_insts 56174594 # Number of instructions simulated 13sim_ops 56174594 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory --- 561 unchanged lines hidden (view full) --- 581system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304369 # number of WriteReq MSHR misses 582system.cpu.dcache.WriteReq_mshr_misses::total 304369 # number of WriteReq MSHR misses 583system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17287 # number of LoadLockedReq MSHR misses 584system.cpu.dcache.LoadLockedReq_mshr_misses::total 17287 # number of LoadLockedReq MSHR misses 585system.cpu.dcache.demand_mshr_misses::cpu.data 1374617 # number of demand (read+write) MSHR misses 586system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses 587system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses 588system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses |
| 589system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 590system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 591system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable 592system.cpu.dcache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable 593system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses 594system.cpu.dcache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses |
|
| 589system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles 590system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles 591system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles 592system.cpu.dcache.WriteReq_mshr_miss_latency::total 11190140370 # number of WriteReq MSHR miss cycles 593system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 203771000 # number of LoadLockedReq MSHR miss cycles 594system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 203771000 # number of LoadLockedReq MSHR miss cycles 595system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40356234870 # number of demand (read+write) MSHR miss cycles 596system.cpu.dcache.demand_mshr_miss_latency::total 40356234870 # number of demand (read+write) MSHR miss cycles --- 20 unchanged lines hidden (view full) --- 617system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36765.046276 # average WriteReq mshr miss latency 618system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36765.046276 # average WriteReq mshr miss latency 619system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11787.528200 # average LoadLockedReq mshr miss latency 620system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11787.528200 # average LoadLockedReq mshr miss latency 621system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency 622system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency 623system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency 624system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency | 595system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles 596system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles 597system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles 598system.cpu.dcache.WriteReq_mshr_miss_latency::total 11190140370 # number of WriteReq MSHR miss cycles 599system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 203771000 # number of LoadLockedReq MSHR miss cycles 600system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 203771000 # number of LoadLockedReq MSHR miss cycles 601system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40356234870 # number of demand (read+write) MSHR miss cycles 602system.cpu.dcache.demand_mshr_miss_latency::total 40356234870 # number of demand (read+write) MSHR miss cycles --- 20 unchanged lines hidden (view full) --- 623system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36765.046276 # average WriteReq mshr miss latency 624system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36765.046276 # average WriteReq mshr miss latency 625system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11787.528200 # average LoadLockedReq mshr miss latency 626system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11787.528200 # average LoadLockedReq mshr miss latency 627system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency 628system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency 629system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency 630system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency |
| 625system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 626system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 627system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 628system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 629system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 630system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 631system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206747.330447 # average ReadReq mshr uncacheable latency 632system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206747.330447 # average ReadReq mshr uncacheable latency 633system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209890.673575 # average WriteReq mshr uncacheable latency 634system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209890.673575 # average WriteReq mshr uncacheable latency 635system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208576.839566 # average overall mshr uncacheable latency 636system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208576.839566 # average overall mshr uncacheable latency |
| 631system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 632system.cpu.icache.tags.replacements 928205 # number of replacements 633system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use 634system.cpu.icache.tags.total_refs 55257552 # Total number of references to valid blocks. 635system.cpu.icache.tags.sampled_refs 928716 # Sample count of references to valid blocks. 636system.cpu.icache.tags.avg_refs 59.498869 # Average number of references to valid blocks. 637system.cpu.icache.tags.warmup_cycle 42087191250 # Cycle when the warmup percentage was hit. 638system.cpu.icache.tags.occ_blocks::cpu.inst 508.070911 # Average occupied blocks per requestor --- 198 unchanged lines hidden (view full) --- 837system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116857 # number of ReadExReq MSHR misses 838system.cpu.l2cache.ReadExReq_mshr_misses::total 116857 # number of ReadExReq MSHR misses 839system.cpu.l2cache.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses 840system.cpu.l2cache.demand_mshr_misses::cpu.data 388821 # number of demand (read+write) MSHR misses 841system.cpu.l2cache.demand_mshr_misses::total 402112 # number of demand (read+write) MSHR misses 842system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses 843system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses 844system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses | 637system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 638system.cpu.icache.tags.replacements 928205 # number of replacements 639system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use 640system.cpu.icache.tags.total_refs 55257552 # Total number of references to valid blocks. 641system.cpu.icache.tags.sampled_refs 928716 # Sample count of references to valid blocks. 642system.cpu.icache.tags.avg_refs 59.498869 # Average number of references to valid blocks. 643system.cpu.icache.tags.warmup_cycle 42087191250 # Cycle when the warmup percentage was hit. 644system.cpu.icache.tags.occ_blocks::cpu.inst 508.070911 # Average occupied blocks per requestor --- 198 unchanged lines hidden (view full) --- 843system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116857 # number of ReadExReq MSHR misses 844system.cpu.l2cache.ReadExReq_mshr_misses::total 116857 # number of ReadExReq MSHR misses 845system.cpu.l2cache.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses 846system.cpu.l2cache.demand_mshr_misses::cpu.data 388821 # number of demand (read+write) MSHR misses 847system.cpu.l2cache.demand_mshr_misses::total 402112 # number of demand (read+write) MSHR misses 848system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses 849system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses 850system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses |
| 851system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable 852system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable 853system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable 854system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable 855system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses 856system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses |
|
| 845system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles 846system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles 847system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles 848system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles 849system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles 850system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles 851system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles 852system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles --- 29 unchanged lines hidden (view full) --- 882system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency 883system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency 884system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency 885system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency 886system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency 887system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency 888system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency | 857system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles 858system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles 859system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles 860system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles 861system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles 862system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles 863system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles 864system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles --- 29 unchanged lines hidden (view full) --- 894system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency 895system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency 896system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency 897system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency 898system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency 899system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency 900system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency 901system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency |
| 890system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 891system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 892system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 893system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 894system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 895system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 902system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192747.330447 # average ReadReq mshr uncacheable latency 903system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192747.330447 # average ReadReq mshr uncacheable latency 904system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196890.673575 # average WriteReq mshr uncacheable latency 905system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196890.673575 # average WriteReq mshr uncacheable latency 906system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195158.866104 # average overall mshr uncacheable latency 907system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195158.866104 # average overall mshr uncacheable latency |
| 896system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 897system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution 898system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution 899system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution 900system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution 901system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution 902system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution 903system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 904system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution 905system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution 906system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution 907system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes) 908system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes) 909system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes) 910system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes) 911system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes) 912system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes) 913system.cpu.toL2Bus.snoops 41937 # Total snoops (count) | 908system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 909system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution 910system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution 911system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution 912system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution 913system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution 914system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution 915system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 916system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution 917system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution 918system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution 919system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes) 920system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes) 921system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes) 922system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes) 923system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes) 924system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes) 925system.cpu.toL2Bus.snoops 41937 # Total snoops (count) |
| 914system.cpu.toL2Bus.snoop_fanout::samples 3198175 # Request fanout histogram 915system.cpu.toL2Bus.snoop_fanout::mean 1.013058 # Request fanout histogram 916system.cpu.toL2Bus.snoop_fanout::stdev 0.113522 # Request fanout histogram | 926system.cpu.toL2Bus.snoop_fanout::samples 3214755 # Request fanout histogram 927system.cpu.toL2Bus.snoop_fanout::mean 1.012990 # Request fanout histogram 928system.cpu.toL2Bus.snoop_fanout::stdev 0.113233 # Request fanout histogram |
| 917system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 918system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 929system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 930system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 919system.cpu.toL2Bus.snoop_fanout::1 3156414 98.69% 98.69% # Request fanout histogram 920system.cpu.toL2Bus.snoop_fanout::2 41761 1.31% 100.00% # Request fanout histogram | 931system.cpu.toL2Bus.snoop_fanout::1 3172994 98.70% 98.70% # Request fanout histogram 932system.cpu.toL2Bus.snoop_fanout::2 41761 1.30% 100.00% # Request fanout histogram |
| 921system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 922system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 923system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 933system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 934system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 935system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 924system.cpu.toL2Bus.snoop_fanout::total 3198175 # Request fanout histogram | 936system.cpu.toL2Bus.snoop_fanout::total 3214755 # Request fanout histogram |
| 925system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks) 926system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 927system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 928system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 929system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks) 930system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 931system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks) 932system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) --- 192 unchanged lines hidden (view full) --- 1125system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes) 1126system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) 1127system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes) 1128system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes) 1129system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1130system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) 1131system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes) 1132system.membus.snoops 431 # Total snoops (count) | 937system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks) 938system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 939system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 940system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 941system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks) 942system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 943system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks) 944system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) --- 192 unchanged lines hidden (view full) --- 1137system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes) 1138system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) 1139system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes) 1140system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes) 1141system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1142system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) 1143system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes) 1144system.membus.snoops 431 # Total snoops (count) |
| 1133system.membus.snoop_fanout::samples 559589 # Request fanout histogram | 1145system.membus.snoop_fanout::samples 576169 # Request fanout histogram |
| 1134system.membus.snoop_fanout::mean 1 # Request fanout histogram 1135system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1136system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1137system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1146system.membus.snoop_fanout::mean 1 # Request fanout histogram 1147system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1148system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1149system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1138system.membus.snoop_fanout::1 559589 100.00% 100.00% # Request fanout histogram | 1150system.membus.snoop_fanout::1 576169 100.00% 100.00% # Request fanout histogram |
| 1139system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1140system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1141system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1142system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1151system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1152system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1153system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1154system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1143system.membus.snoop_fanout::total 559589 # Request fanout histogram | 1155system.membus.snoop_fanout::total 576169 # Request fanout histogram |
| 1144system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks) 1145system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1146system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks) 1147system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1148system.membus.respLayer1.occupancy 2144408870 # Layer occupancy (ticks) 1149system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1150system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) 1151system.membus.respLayer2.utilization 0.0 # Layer utilization (%) --- 33 unchanged lines hidden --- | 1156system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks) 1157system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1158system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks) 1159system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1160system.membus.respLayer1.occupancy 2144408870 # Layer occupancy (ticks) 1161system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1162system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) 1163system.membus.respLayer2.utilization 0.0 # Layer utilization (%) --- 33 unchanged lines hidden --- |