| stats.txt (10513:ca4438b6e39a) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.919439 # Number of seconds simulated 4sim_ticks 1919439025000 # Number of ticks simulated 5final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.920428 # Number of seconds simulated 4sim_ticks 1920427877000 # Number of ticks simulated 5final_tick 1920427877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1406989 # Simulator instruction rate (inst/s) 8host_op_rate 1406988 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 48137648137 # Simulator tick rate (ticks/s) 10host_mem_usage 309300 # Number of bytes of host memory used 11host_seconds 39.87 # Real time elapsed on the host 12sim_insts 56102180 # Number of instructions simulated 13sim_ops 56102180 # Number of ops (including micro ops) simulated | 7host_inst_rate 694902 # Simulator instruction rate (inst/s) 8host_op_rate 694902 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 23785763794 # Simulator tick rate (ticks/s) 10host_mem_usage 317148 # Number of bytes of host memory used 11host_seconds 80.74 # Real time elapsed on the host 12sim_insts 56105324 # Number of instructions simulated 13sim_ops 56105324 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24858304 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4747520 # Number of bytes written to this memory 23system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7406848 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388686 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 25710016 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7404096 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7404096 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388411 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::total 401995 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 74180 # Number of write requests responded to by this memory 30system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 115732 # Number of write requests responded to by this memory 32system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.data 12959987 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.num_reads::total 401719 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115689 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115689 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 443001 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 12944149 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) | 32system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::total 13403750 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s) 38system.physmem.bw_write::writebacks 2473389 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_write::tsunami.ide 1385471 # Write bandwidth from this memory (bytes/s) 40system.physmem.bw_write::total 3858861 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_total::writebacks 2473389 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 12959987 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::total 17262610 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.readReqs 401995 # Number of read requests accepted 47system.physmem.writeReqs 115732 # Number of write requests accepted 48system.physmem.readBursts 401995 # Number of DRAM read bursts, including those serviced by the write queue 49system.physmem.writeBursts 115732 # Number of DRAM write bursts, including those merged in the write queue 50system.physmem.bytesReadDRAM 25715968 # Total number of bytes read from DRAM 51system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue 52system.physmem.bytesWritten 7405120 # Total number of bytes written to DRAM 53system.physmem.bytesReadSys 25727680 # Total read bytes from the system interface side 54system.physmem.bytesWrittenSys 7406848 # Total written bytes from the system interface side 55system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue 56system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 57system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write 58system.physmem.perBankRdBursts::0 25161 # Per bank write bursts | 33system.physmem.bw_read::total 13387650 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 443001 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 443001 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 3855441 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 3855441 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 3855441 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 443001 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 12944149 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 17243091 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 401719 # Number of read requests accepted 44system.physmem.writeReqs 157241 # Number of write requests accepted 45system.physmem.readBursts 401719 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 157241 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 25703424 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue 49system.physmem.bytesWritten 9932992 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 25710016 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 10063424 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 2011 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 25160 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::1 25539 # Per bank write bursts | 56system.physmem.perBankRdBursts::1 25539 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::2 25618 # Per bank write bursts 61system.physmem.perBankRdBursts::3 25536 # Per bank write bursts 62system.physmem.perBankRdBursts::4 24982 # Per bank write bursts 63system.physmem.perBankRdBursts::5 24977 # Per bank write bursts 64system.physmem.perBankRdBursts::6 24228 # Per bank write bursts 65system.physmem.perBankRdBursts::7 24506 # Per bank write bursts 66system.physmem.perBankRdBursts::8 25158 # Per bank write bursts 67system.physmem.perBankRdBursts::9 24823 # Per bank write bursts 68system.physmem.perBankRdBursts::10 25363 # Per bank write bursts 69system.physmem.perBankRdBursts::11 24839 # Per bank write bursts 70system.physmem.perBankRdBursts::12 24418 # Per bank write bursts 71system.physmem.perBankRdBursts::13 25388 # Per bank write bursts 72system.physmem.perBankRdBursts::14 25795 # Per bank write bursts 73system.physmem.perBankRdBursts::15 25481 # Per bank write bursts 74system.physmem.perBankWrBursts::0 7550 # Per bank write bursts 75system.physmem.perBankWrBursts::1 7529 # Per bank write bursts 76system.physmem.perBankWrBursts::2 7880 # Per bank write bursts 77system.physmem.perBankWrBursts::3 7553 # Per bank write bursts 78system.physmem.perBankWrBursts::4 7115 # Per bank write bursts 79system.physmem.perBankWrBursts::5 6983 # Per bank write bursts 80system.physmem.perBankWrBursts::6 6321 # Per bank write bursts 81system.physmem.perBankWrBursts::7 6315 # Per bank write bursts 82system.physmem.perBankWrBursts::8 7293 # Per bank write bursts 83system.physmem.perBankWrBursts::9 6555 # Per bank write bursts 84system.physmem.perBankWrBursts::10 7205 # Per bank write bursts 85system.physmem.perBankWrBursts::11 6861 # Per bank write bursts 86system.physmem.perBankWrBursts::12 6964 # Per bank write bursts 87system.physmem.perBankWrBursts::13 7821 # Per bank write bursts 88system.physmem.perBankWrBursts::14 7980 # Per bank write bursts 89system.physmem.perBankWrBursts::15 7780 # Per bank write bursts | 57system.physmem.perBankRdBursts::2 25602 # Per bank write bursts 58system.physmem.perBankRdBursts::3 25522 # Per bank write bursts 59system.physmem.perBankRdBursts::4 24974 # Per bank write bursts 60system.physmem.perBankRdBursts::5 24970 # Per bank write bursts 61system.physmem.perBankRdBursts::6 24210 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24489 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25140 # Per bank write bursts 64system.physmem.perBankRdBursts::9 24800 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25361 # Per bank write bursts 66system.physmem.perBankRdBursts::11 24836 # Per bank write bursts 67system.physmem.perBankRdBursts::12 24395 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25368 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25772 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25478 # Per bank write bursts 71system.physmem.perBankWrBursts::0 10040 # Per bank write bursts 72system.physmem.perBankWrBursts::1 9905 # Per bank write bursts 73system.physmem.perBankWrBursts::2 10447 # Per bank write bursts 74system.physmem.perBankWrBursts::3 9982 # Per bank write bursts 75system.physmem.perBankWrBursts::4 9551 # Per bank write bursts 76system.physmem.perBankWrBursts::5 9392 # Per bank write bursts 77system.physmem.perBankWrBursts::6 8805 # Per bank write bursts 78system.physmem.perBankWrBursts::7 8555 # Per bank write bursts 79system.physmem.perBankWrBursts::8 9942 # Per bank write bursts 80system.physmem.perBankWrBursts::9 8777 # Per bank write bursts 81system.physmem.perBankWrBursts::10 9524 # Per bank write bursts 82system.physmem.perBankWrBursts::11 9288 # Per bank write bursts 83system.physmem.perBankWrBursts::12 9847 # Per bank write bursts 84system.physmem.perBankWrBursts::13 10608 # Per bank write bursts 85system.physmem.perBankWrBursts::14 10278 # Per bank write bursts 86system.physmem.perBankWrBursts::15 10262 # Per bank write bursts |
| 90system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 91system.physmem.numWrRetry 12 # Number of times write queue was full causing retry 92system.physmem.totGap 1919427104000 # Total gap between requests | 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 1920415956000 # Total gap between requests |
| 93system.physmem.readPktSize::0 0 # Read request sizes (log2) 94system.physmem.readPktSize::1 0 # Read request sizes (log2) 95system.physmem.readPktSize::2 0 # Read request sizes (log2) 96system.physmem.readPktSize::3 0 # Read request sizes (log2) 97system.physmem.readPktSize::4 0 # Read request sizes (log2) 98system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 99system.physmem.readPktSize::6 401995 # Read request sizes (log2) | 96system.physmem.readPktSize::6 401719 # Read request sizes (log2) |
| 100system.physmem.writePktSize::0 0 # Write request sizes (log2) 101system.physmem.writePktSize::1 0 # Write request sizes (log2) 102system.physmem.writePktSize::2 0 # Write request sizes (log2) 103system.physmem.writePktSize::3 0 # Write request sizes (log2) 104system.physmem.writePktSize::4 0 # Write request sizes (log2) 105system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 106system.physmem.writePktSize::6 115732 # Write request sizes (log2) 107system.physmem.rdQLenPdf::0 401798 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 157241 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 401602 # What read queue length does an incoming req see |
| 108system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see --- 30 unchanged lines hidden (view full) --- 146system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 105system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see --- 30 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 154system.physmem.wrQLenPdf::15 1803 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 2465 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 5623 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 5839 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6566 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 6884 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 8073 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::23 8473 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 8504 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 8199 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 6888 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 6495 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 5617 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::30 5359 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::31 5332 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::32 5312 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::35 198 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::38 177 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::45 216 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::46 208 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::47 201 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::48 197 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::49 176 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::50 132 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::56 112 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see 203system.physmem.bytesPerActivate::samples 63991 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::mean 517.589786 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::gmean 312.394273 # Bytes accessed per row activation 206system.physmem.bytesPerActivate::stdev 414.375602 # Bytes accessed per row activation 207system.physmem.bytesPerActivate::0-127 15074 23.56% 23.56% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::128-255 11584 18.10% 41.66% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::256-383 4587 7.17% 48.83% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::384-511 3091 4.83% 53.66% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::512-639 3045 4.76% 58.42% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::640-767 1807 2.82% 61.24% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::768-895 1323 2.07% 63.31% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::896-1023 1474 2.30% 65.61% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1024-1151 22006 34.39% 100.00% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::total 63991 # Bytes accessed per row activation 217system.physmem.rdPerTurnAround::samples 5109 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::mean 78.644353 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::stdev 2952.702952 # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::0-8191 5106 99.94% 99.94% # Reads before turning the bus around for writes | 151system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 4297 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 7960 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 9080 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 9749 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 10574 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 11119 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 12096 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 11614 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 11639 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 10464 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 9678 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8171 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 7710 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 6526 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 6096 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 5950 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5885 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 334 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 315 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 274 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 210 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 95 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 24 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 536.458715 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 326.725513 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 417.454187 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 15065 22.68% 22.68% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 11458 17.25% 39.93% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4677 7.04% 46.97% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3146 4.74% 51.70% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 3014 4.54% 56.24% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1853 2.79% 59.03% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1319 1.99% 61.02% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1472 2.22% 63.23% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 24425 36.77% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5535 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 72.556098 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2836.858046 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 5532 99.95% 99.95% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 224system.physmem.rdPerTurnAround::total 5109 # Reads before turning the bus around for writes 225system.physmem.wrPerTurnAround::samples 5109 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::mean 22.647289 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::gmean 19.199358 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::stdev 21.195525 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::16-19 4460 87.30% 87.30% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20-23 21 0.41% 87.71% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::24-27 12 0.23% 87.94% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::28-31 224 4.38% 92.33% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::32-35 41 0.80% 93.13% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::36-39 20 0.39% 93.52% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::40-43 7 0.14% 93.66% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::44-47 6 0.12% 93.78% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::48-51 14 0.27% 94.05% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::52-55 4 0.08% 94.13% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::56-59 3 0.06% 94.19% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::60-63 1 0.02% 94.21% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::64-67 9 0.18% 94.38% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::68-71 5 0.10% 94.48% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-75 4 0.08% 94.56% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-83 25 0.49% 95.05% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::84-87 9 0.18% 95.22% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::92-95 15 0.29% 95.52% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::96-99 168 3.29% 98.81% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::100-103 2 0.04% 98.85% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::108-111 1 0.02% 98.86% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::112-115 2 0.04% 98.90% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::116-119 1 0.02% 98.92% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::120-123 2 0.04% 98.96% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::128-131 8 0.16% 99.12% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::132-135 5 0.10% 99.22% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::136-139 5 0.10% 99.31% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::140-143 9 0.18% 99.49% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::144-147 13 0.25% 99.75% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::148-151 1 0.02% 99.77% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::152-155 1 0.02% 99.78% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::156-159 2 0.04% 99.82% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::160-163 5 0.10% 99.92% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::172-175 1 0.02% 99.94% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 5109 # Writes before turning the bus around for reads 265system.physmem.totQLat 2129492750 # Total ticks spent queuing 266system.physmem.totMemAccLat 9663467750 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 2009060000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 5299.72 # Average queueing delay per DRAM burst | 221system.physmem.rdPerTurnAround::total 5535 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 5535 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 28.040289 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 21.079799 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 34.913440 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16-23 4499 81.28% 81.28% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::24-31 176 3.18% 84.46% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::32-39 297 5.37% 89.83% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-47 50 0.90% 90.73% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::48-55 97 1.75% 92.48% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::56-63 48 0.87% 93.35% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::64-71 11 0.20% 93.55% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::72-79 7 0.13% 93.68% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::80-87 21 0.38% 94.06% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::88-95 7 0.13% 94.18% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::96-103 14 0.25% 94.44% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::104-111 6 0.11% 94.54% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::112-119 14 0.25% 94.80% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::120-127 3 0.05% 94.85% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::128-135 11 0.20% 95.05% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::136-143 48 0.87% 95.92% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::144-151 16 0.29% 96.21% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::152-159 19 0.34% 96.55% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-167 91 1.64% 98.19% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::168-175 36 0.65% 98.84% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::176-183 6 0.11% 98.95% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::184-191 14 0.25% 99.21% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::192-199 14 0.25% 99.46% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::200-207 5 0.09% 99.55% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::208-215 9 0.16% 99.71% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::216-223 3 0.05% 99.77% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::224-231 5 0.09% 99.86% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::232-239 1 0.02% 99.87% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::240-247 3 0.05% 99.93% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::248-255 2 0.04% 99.96% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::total 5535 # Writes before turning the bus around for reads 259system.physmem.totQLat 2119831750 # Total ticks spent queuing 260system.physmem.totMemAccLat 9650131750 # Total ticks spent from burst creation until serviced by the DRAM 261system.physmem.totBusLat 2008080000 # Total ticks spent in databus transfers 262system.physmem.avgQLat 5278.26 # Average queueing delay per DRAM burst |
| 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 263system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 270system.physmem.avgMemAccLat 24049.72 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s | 264system.physmem.avgMemAccLat 24028.26 # Average memory access latency per DRAM burst 265system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s 266system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s 267system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s 268system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s |
| 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 269system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 276system.physmem.busUtil 0.13 # Data bus utilization in percentage | 270system.physmem.busUtil 0.14 # Data bus utilization in percentage |
| 277system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads | 271system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads |
| 278system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 272system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes |
| 279system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 273system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 280system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing 281system.physmem.readRowHits 359991 # Number of row buffer hits during reads 282system.physmem.writeRowHits 93535 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes 285system.physmem.avgGap 3707411.64 # Average gap between requests 286system.physmem.pageHitRate 87.63 # Row buffer hit rate, read and write combined 287system.physmem.memoryStateTime::IDLE 1800186005000 # Time in different power states 288system.physmem.memoryStateTime::REF 64094160000 # Time in different power states | 274system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing 275system.physmem.readRowHits 359880 # Number of row buffer hits during reads 276system.physmem.writeRowHits 130510 # Number of row buffer hits during writes 277system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads 278system.physmem.writeRowHitRate 84.08 # Row buffer hit rate for writes 279system.physmem.avgGap 3435694.78 # Average gap between requests 280system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined 281system.physmem.memoryStateTime::IDLE 1801057353000 # Time in different power states 282system.physmem.memoryStateTime::REF 64127180000 # Time in different power states |
| 289system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 283system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 290system.physmem.memoryStateTime::ACT 55155300000 # Time in different power states | 284system.physmem.memoryStateTime::ACT 55239785750 # Time in different power states |
| 291system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 285system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 292system.physmem.actEnergy::0 236499480 # Energy for activate commands per rank (pJ) 293system.physmem.actEnergy::1 247272480 # Energy for activate commands per rank (pJ) 294system.physmem.preEnergy::0 129042375 # Energy for precharge commands per rank (pJ) 295system.physmem.preEnergy::1 134920500 # Energy for precharge commands per rank (pJ) 296system.physmem.readEnergy::0 1564266600 # Energy for read commands per rank (pJ) 297system.physmem.readEnergy::1 1569867000 # Energy for read commands per rank (pJ) 298system.physmem.writeEnergy::0 370954080 # Energy for write commands per rank (pJ) 299system.physmem.writeEnergy::1 378814320 # Energy for write commands per rank (pJ) 300system.physmem.refreshEnergy::0 125368176960 # Energy for refresh commands per rank (pJ) 301system.physmem.refreshEnergy::1 125368176960 # Energy for refresh commands per rank (pJ) 302system.physmem.actBackEnergy::0 63948324510 # Energy for active background per rank (pJ) 303system.physmem.actBackEnergy::1 64460493450 # Energy for active background per rank (pJ) 304system.physmem.preBackEnergy::0 1095566249250 # Energy for precharge background per rank (pJ) 305system.physmem.preBackEnergy::1 1095116978250 # Energy for precharge background per rank (pJ) 306system.physmem.totalEnergy::0 1287183513255 # Total energy per rank (pJ) 307system.physmem.totalEnergy::1 1287276522960 # Total energy per rank (pJ) 308system.physmem.averagePower::0 670.605262 # Core power per rank (mW) 309system.physmem.averagePower::1 670.653719 # Core power per rank (mW) 310system.membus.trans_dist::ReadReq 292357 # Transaction distribution 311system.membus.trans_dist::ReadResp 292357 # Transaction distribution 312system.membus.trans_dist::WriteReq 9649 # Transaction distribution 313system.membus.trans_dist::WriteResp 9649 # Transaction distribution 314system.membus.trans_dist::Writeback 74180 # Transaction distribution 315system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 316system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 317system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 318system.membus.trans_dist::UpgradeResp 132 # Transaction distribution 319system.membus.trans_dist::ReadExReq 116726 # Transaction distribution 320system.membus.trans_dist::ReadExResp 116726 # Transaction distribution 321system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) 322system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878404 # Packet count per connected master and slave (bytes) 323system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911562 # Packet count per connected master and slave (bytes) 324system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) 325system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) 326system.membus.pkt_count::total 994854 # Packet count per connected master and slave (bytes) 327system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) 328system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474240 # Cumulative packet size per connected master and slave (bytes) 329system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30518796 # Cumulative packet size per connected master and slave (bytes) 330system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 331system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 332system.membus.pkt_size::total 33179084 # Cumulative packet size per connected master and slave (bytes) 333system.membus.snoops 158 # Total snoops (count) 334system.membus.snoop_fanout::samples 518029 # Request fanout histogram 335system.membus.snoop_fanout::mean 1 # Request fanout histogram 336system.membus.snoop_fanout::stdev 0 # Request fanout histogram 337system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 338system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 339system.membus.snoop_fanout::1 518029 100.00% 100.00% # Request fanout histogram 340system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 341system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 342system.membus.snoop_fanout::min_value 1 # Request fanout histogram 343system.membus.snoop_fanout::max_value 1 # Request fanout histogram 344system.membus.snoop_fanout::total 518029 # Request fanout histogram 345system.membus.reqLayer0.occupancy 30371000 # Layer occupancy (ticks) 346system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 347system.membus.reqLayer1.occupancy 1451093000 # Layer occupancy (ticks) 348system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 349system.membus.respLayer1.occupancy 3752017868 # Layer occupancy (ticks) 350system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 351system.membus.respLayer2.occupancy 43114250 # Layer occupancy (ticks) 352system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 353system.iocache.tags.replacements 41685 # number of replacements 354system.iocache.tags.tagsinuse 1.344808 # Cycle average of tags in use 355system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 356system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 357system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 358system.iocache.tags.warmup_cycle 1753524972000 # Cycle when the warmup percentage was hit. 359system.iocache.tags.occ_blocks::tsunami.ide 1.344808 # Average occupied blocks per requestor 360system.iocache.tags.occ_percent::tsunami.ide 0.084051 # Average percentage of cache occupancy 361system.iocache.tags.occ_percent::total 0.084051 # Average percentage of cache occupancy 362system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 363system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 364system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 365system.iocache.tags.tag_accesses 375557 # Number of tag accesses 366system.iocache.tags.data_accesses 375557 # Number of data accesses 367system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 368system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 369system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 370system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 371system.iocache.WriteInvalidateReq_misses::tsunami.ide 4 # number of WriteInvalidateReq misses 372system.iocache.WriteInvalidateReq_misses::total 4 # number of WriteInvalidateReq misses 373system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 374system.iocache.demand_misses::total 173 # number of demand (read+write) misses 375system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 376system.iocache.overall_misses::total 173 # number of overall misses 377system.iocache.ReadReq_miss_latency::tsunami.ide 24523133 # number of ReadReq miss cycles 378system.iocache.ReadReq_miss_latency::total 24523133 # number of ReadReq miss cycles 379system.iocache.demand_miss_latency::tsunami.ide 24523133 # number of demand (read+write) miss cycles 380system.iocache.demand_miss_latency::total 24523133 # number of demand (read+write) miss cycles 381system.iocache.overall_miss_latency::tsunami.ide 24523133 # number of overall miss cycles 382system.iocache.overall_miss_latency::total 24523133 # number of overall miss cycles 383system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 384system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 385system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41556 # number of WriteInvalidateReq accesses(hits+misses) 386system.iocache.WriteInvalidateReq_accesses::total 41556 # number of WriteInvalidateReq accesses(hits+misses) 387system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 388system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 389system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 390system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 391system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 392system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 393system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000096 # miss rate for WriteInvalidateReq accesses 394system.iocache.WriteInvalidateReq_miss_rate::total 0.000096 # miss rate for WriteInvalidateReq accesses 395system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 396system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 397system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 398system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 399system.iocache.ReadReq_avg_miss_latency::tsunami.ide 141752.213873 # average ReadReq miss latency 400system.iocache.ReadReq_avg_miss_latency::total 141752.213873 # average ReadReq miss latency 401system.iocache.demand_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency 402system.iocache.demand_avg_miss_latency::total 141752.213873 # average overall miss latency 403system.iocache.overall_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency 404system.iocache.overall_avg_miss_latency::total 141752.213873 # average overall miss latency 405system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 406system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 407system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 408system.iocache.blocked::no_targets 0 # number of cycles access was blocked 409system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 410system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 411system.iocache.fast_writes 41552 # number of fast writes performed 412system.iocache.cache_copies 0 # number of cache copies performed 413system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 414system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 415system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 416system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 417system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 418system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 419system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles 420system.iocache.ReadReq_mshr_miss_latency::total 15526633 # number of ReadReq MSHR miss cycles 421system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512178304 # number of WriteInvalidateReq MSHR miss cycles 422system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512178304 # number of WriteInvalidateReq MSHR miss cycles 423system.iocache.demand_mshr_miss_latency::tsunami.ide 15526633 # number of demand (read+write) MSHR miss cycles 424system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles 425system.iocache.overall_mshr_miss_latency::tsunami.ide 15526633 # number of overall MSHR miss cycles 426system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles 427system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 428system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 429system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 431system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 433system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency 434system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency 435system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency 436system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 437system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency 438system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency 439system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency 440system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency 441system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 444system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 445system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 446system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 447system.disk0.dma_write_txs 395 # Number of DMA write transactions. 448system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 449system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 450system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 451system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 452system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 453system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 286system.physmem.actEnergy::0 245964600 # Energy for activate commands per rank (pJ) 287system.physmem.actEnergy::1 256238640 # Energy for activate commands per rank (pJ) 288system.physmem.preEnergy::0 134206875 # Energy for precharge commands per rank (pJ) 289system.physmem.preEnergy::1 139812750 # Energy for precharge commands per rank (pJ) 290system.physmem.readEnergy::0 1563634800 # Energy for read commands per rank (pJ) 291system.physmem.readEnergy::1 1568970000 # Energy for read commands per rank (pJ) 292system.physmem.writeEnergy::0 496866960 # Energy for write commands per rank (pJ) 293system.physmem.writeEnergy::1 508848480 # Energy for write commands per rank (pJ) 294system.physmem.refreshEnergy::0 125432764080 # Energy for refresh commands per rank (pJ) 295system.physmem.refreshEnergy::1 125432764080 # Energy for refresh commands per rank (pJ) 296system.physmem.actBackEnergy::0 64118860245 # Energy for active background per rank (pJ) 297system.physmem.actBackEnergy::1 64485707400 # Energy for active background per rank (pJ) 298system.physmem.preBackEnergy::0 1096009968750 # Energy for precharge background per rank (pJ) 299system.physmem.preBackEnergy::1 1095688173000 # Energy for precharge background per rank (pJ) 300system.physmem.totalEnergy::0 1288002266310 # Total energy per rank (pJ) 301system.physmem.totalEnergy::1 1288080514350 # Total energy per rank (pJ) 302system.physmem.averagePower::0 670.686297 # Core power per rank (mW) 303system.physmem.averagePower::1 670.727042 # Core power per rank (mW) |
| 454system.cpu_clk_domain.clock 500 # Clock period in ticks 455system.cpu.dtb.fetch_hits 0 # ITB hits 456system.cpu.dtb.fetch_misses 0 # ITB misses 457system.cpu.dtb.fetch_acv 0 # ITB acv 458system.cpu.dtb.fetch_accesses 0 # ITB accesses | 304system.cpu_clk_domain.clock 500 # Clock period in ticks 305system.cpu.dtb.fetch_hits 0 # ITB hits 306system.cpu.dtb.fetch_misses 0 # ITB misses 307system.cpu.dtb.fetch_acv 0 # ITB acv 308system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 459system.cpu.dtb.read_hits 9052455 # DTB read hits 460system.cpu.dtb.read_misses 10357 # DTB read misses | 309system.cpu.dtb.read_hits 9053154 # DTB read hits 310system.cpu.dtb.read_misses 10325 # DTB read misses |
| 461system.cpu.dtb.read_acv 210 # DTB read access violations | 311system.cpu.dtb.read_acv 210 # DTB read access violations |
| 462system.cpu.dtb.read_accesses 728916 # DTB read accesses 463system.cpu.dtb.write_hits 6349129 # DTB write hits 464system.cpu.dtb.write_misses 1143 # DTB write misses | 312system.cpu.dtb.read_accesses 728854 # DTB read accesses 313system.cpu.dtb.write_hits 6349573 # DTB write hits 314system.cpu.dtb.write_misses 1142 # DTB write misses |
| 465system.cpu.dtb.write_acv 157 # DTB write access violations | 315system.cpu.dtb.write_acv 157 # DTB write access violations |
| 466system.cpu.dtb.write_accesses 291932 # DTB write accesses 467system.cpu.dtb.data_hits 15401584 # DTB hits 468system.cpu.dtb.data_misses 11500 # DTB misses | 316system.cpu.dtb.write_accesses 291931 # DTB write accesses 317system.cpu.dtb.data_hits 15402727 # DTB hits 318system.cpu.dtb.data_misses 11467 # DTB misses |
| 469system.cpu.dtb.data_acv 367 # DTB access violations | 319system.cpu.dtb.data_acv 367 # DTB access violations |
| 470system.cpu.dtb.data_accesses 1020848 # DTB accesses 471system.cpu.itb.fetch_hits 4974880 # ITB hits | 320system.cpu.dtb.data_accesses 1020785 # DTB accesses 321system.cpu.itb.fetch_hits 4974627 # ITB hits |
| 472system.cpu.itb.fetch_misses 5010 # ITB misses 473system.cpu.itb.fetch_acv 184 # ITB acv | 322system.cpu.itb.fetch_misses 5010 # ITB misses 323system.cpu.itb.fetch_acv 184 # ITB acv |
| 474system.cpu.itb.fetch_accesses 4979890 # ITB accesses | 324system.cpu.itb.fetch_accesses 4979637 # ITB accesses |
| 475system.cpu.itb.read_hits 0 # DTB read hits 476system.cpu.itb.read_misses 0 # DTB read misses 477system.cpu.itb.read_acv 0 # DTB read access violations 478system.cpu.itb.read_accesses 0 # DTB read accesses 479system.cpu.itb.write_hits 0 # DTB write hits 480system.cpu.itb.write_misses 0 # DTB write misses 481system.cpu.itb.write_acv 0 # DTB write access violations 482system.cpu.itb.write_accesses 0 # DTB write accesses 483system.cpu.itb.data_hits 0 # DTB hits 484system.cpu.itb.data_misses 0 # DTB misses 485system.cpu.itb.data_acv 0 # DTB access violations 486system.cpu.itb.data_accesses 0 # DTB accesses | 325system.cpu.itb.read_hits 0 # DTB read hits 326system.cpu.itb.read_misses 0 # DTB read misses 327system.cpu.itb.read_acv 0 # DTB read access violations 328system.cpu.itb.read_accesses 0 # DTB read accesses 329system.cpu.itb.write_hits 0 # DTB write hits 330system.cpu.itb.write_misses 0 # DTB write misses 331system.cpu.itb.write_acv 0 # DTB write access violations 332system.cpu.itb.write_accesses 0 # DTB write accesses 333system.cpu.itb.data_hits 0 # DTB hits 334system.cpu.itb.data_misses 0 # DTB misses 335system.cpu.itb.data_acv 0 # DTB access violations 336system.cpu.itb.data_accesses 0 # DTB accesses |
| 487system.cpu.numCycles 3838878050 # number of cpu cycles simulated | 337system.cpu.numCycles 3840855754 # number of cpu cycles simulated |
| 488system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 489system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 338system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 339system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 490system.cpu.committedInsts 56102180 # Number of instructions committed 491system.cpu.committedOps 56102180 # Number of ops (including micro ops) committed 492system.cpu.num_int_alu_accesses 51977296 # Number of integer alu accesses 493system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses 494system.cpu.num_func_calls 1481232 # number of times a function call or return occured 495system.cpu.num_conditional_control_insts 6461044 # number of instructions that are conditional controls 496system.cpu.num_int_insts 51977296 # number of integer instructions 497system.cpu.num_fp_insts 324326 # number of float instructions 498system.cpu.num_int_register_reads 71206831 # number of times the integer registers were read 499system.cpu.num_int_register_writes 38459262 # number of times the integer registers were written 500system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read 501system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written 502system.cpu.num_mem_refs 15454224 # number of memory refs 503system.cpu.num_load_insts 9089337 # Number of load instructions 504system.cpu.num_store_insts 6364887 # Number of store instructions 505system.cpu.num_idle_cycles 3587231475.998131 # Number of idle cycles 506system.cpu.num_busy_cycles 251646574.001869 # Number of busy cycles 507system.cpu.not_idle_fraction 0.065552 # Percentage of non-idle cycles 508system.cpu.idle_fraction 0.934448 # Percentage of idle cycles 509system.cpu.Branches 8412776 # Number of branches fetched 510system.cpu.op_class::No_OpClass 3197684 5.70% 5.70% # Class of executed instruction 511system.cpu.op_class::IntAlu 36172751 64.46% 70.16% # Class of executed instruction 512system.cpu.op_class::IntMult 60997 0.11% 70.27% # Class of executed instruction | 340system.cpu.committedInsts 56105324 # Number of instructions committed 341system.cpu.committedOps 56105324 # Number of ops (including micro ops) committed 342system.cpu.num_int_alu_accesses 51980283 # Number of integer alu accesses 343system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses 344system.cpu.num_func_calls 1481352 # number of times a function call or return occured 345system.cpu.num_conditional_control_insts 6461346 # number of instructions that are conditional controls 346system.cpu.num_int_insts 51980283 # number of integer instructions 347system.cpu.num_fp_insts 324527 # number of float instructions 348system.cpu.num_int_register_reads 71211532 # number of times the integer registers were read 349system.cpu.num_int_register_writes 38461399 # number of times the integer registers were written 350system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read 351system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written 352system.cpu.num_mem_refs 15455353 # number of memory refs 353system.cpu.num_load_insts 9090013 # Number of load instructions 354system.cpu.num_store_insts 6365340 # Number of store instructions 355system.cpu.num_idle_cycles 3589191785.998131 # Number of idle cycles 356system.cpu.num_busy_cycles 251663968.001869 # Number of busy cycles 357system.cpu.not_idle_fraction 0.065523 # Percentage of non-idle cycles 358system.cpu.idle_fraction 0.934477 # Percentage of idle cycles 359system.cpu.Branches 8413247 # Number of branches fetched 360system.cpu.op_class::No_OpClass 3197750 5.70% 5.70% # Class of executed instruction 361system.cpu.op_class::IntAlu 36174854 64.46% 70.16% # Class of executed instruction 362system.cpu.op_class::IntMult 61015 0.11% 70.27% # Class of executed instruction |
| 513system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction | 363system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction |
| 514system.cpu.op_class::FloatAdd 38083 0.07% 70.34% # Class of executed instruction | 364system.cpu.op_class::FloatAdd 38089 0.07% 70.34% # Class of executed instruction |
| 515system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction 516system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction 517system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction 518system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction 519system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction 520system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction 521system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction 522system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction --- 9 unchanged lines hidden (view full) --- 532system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction 533system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction 534system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction 535system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction 536system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction 537system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction 538system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction 539system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction | 365system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction 366system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction 367system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction 368system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction 369system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction 370system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction 371system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction 372system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction --- 9 unchanged lines hidden (view full) --- 382system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction 383system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction 384system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction 385system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction 386system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction 387system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction 388system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction 389system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction |
| 540system.cpu.op_class::MemRead 9316413 16.60% 86.95% # Class of executed instruction 541system.cpu.op_class::MemWrite 6370959 11.35% 98.30% # Class of executed instruction 542system.cpu.op_class::IprAccess 953524 1.70% 100.00% # Class of executed instruction | 390system.cpu.op_class::MemRead 9317103 16.60% 86.95% # Class of executed instruction 391system.cpu.op_class::MemWrite 6371414 11.35% 98.30% # Class of executed instruction 392system.cpu.op_class::IprAccess 953297 1.70% 100.00% # Class of executed instruction |
| 543system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 393system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 544system.cpu.op_class::total 56114047 # Class of executed instruction | 394system.cpu.op_class::total 56117158 # Class of executed instruction |
| 545system.cpu.kern.inst.arm 0 # number of arm instructions executed | 395system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 546system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed 547system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed 548system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl | 396system.cpu.kern.inst.quiesce 6382 # number of quiesce instructions executed 397system.cpu.kern.inst.hwrei 212003 # number of hwrei instructions executed 398system.cpu.kern.ipl_count::0 74898 40.89% 40.89% # number of times we switched to this ipl |
| 549system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl | 399system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl |
| 550system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl 551system.cpu.kern.ipl_count::31 106211 57.99% 100.00% # number of times we switched to this ipl 552system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl 553system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl | 400system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl 401system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl 402system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl 403system.cpu.kern.ipl_good::0 73531 49.31% 49.31% # number of times we switched to this ipl from a different ipl |
| 554system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl | 404system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl |
| 555system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl 556system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl 557system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl 558system.cpu.kern.ipl_ticks::0 1857251860000 96.76% 96.76% # number of cycles we spent at this ipl 559system.cpu.kern.ipl_ticks::21 91366000 0.00% 96.76% # number of cycles we spent at this ipl 560system.cpu.kern.ipl_ticks::22 736784000 0.04% 96.80% # number of cycles we spent at this ipl 561system.cpu.kern.ipl_ticks::31 61358281000 3.20% 100.00% # number of cycles we spent at this ipl 562system.cpu.kern.ipl_ticks::total 1919438291000 # number of cycles we spent at this ipl 563system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl | 405system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl 406system.cpu.kern.ipl_good::31 73531 49.31% 100.00% # number of times we switched to this ipl from a different ipl 407system.cpu.kern.ipl_good::total 149125 # number of times we switched to this ipl from a different ipl 408system.cpu.kern.ipl_ticks::0 1858233349500 96.76% 96.76% # number of cycles we spent at this ipl 409system.cpu.kern.ipl_ticks::21 91228000 0.00% 96.77% # number of cycles we spent at this ipl 410system.cpu.kern.ipl_ticks::22 737074000 0.04% 96.80% # number of cycles we spent at this ipl 411system.cpu.kern.ipl_ticks::31 61365491500 3.20% 100.00% # number of cycles we spent at this ipl 412system.cpu.kern.ipl_ticks::total 1920427143000 # number of cycles we spent at this ipl 413system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl |
| 564system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 565system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 414system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 415system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 566system.cpu.kern.ipl_used::31 0.692282 # fraction of swpipl calls that actually changed the ipl 567system.cpu.kern.ipl_used::total 0.814105 # fraction of swpipl calls that actually changed the ipl | 416system.cpu.kern.ipl_used::31 0.692239 # fraction of swpipl calls that actually changed the ipl 417system.cpu.kern.ipl_used::total 0.814077 # fraction of swpipl calls that actually changed the ipl |
| 568system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 569system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 570system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 571system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 572system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 573system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 574system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 575system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 595system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 596system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 597system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 598system.cpu.kern.syscall::total 326 # number of syscalls executed 599system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 600system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 601system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 602system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 418system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 419system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 420system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 421system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 422system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 423system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 424system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 425system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 445system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 446system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 447system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 448system.cpu.kern.syscall::total 326 # number of syscalls executed 449system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 450system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 451system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 452system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 603system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed 604system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed | 453system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed 454system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed |
| 605system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 455system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 606system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed 607system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed | 456system.cpu.kern.callpal::swpipl 175962 91.21% 93.41% # number of callpals executed 457system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed |
| 608system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 609system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed | 458system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 459system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed |
| 610system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed | 460system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed |
| 611system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed | 461system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed |
| 612system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed | 462system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed |
| 613system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 614system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 463system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 464system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 615system.cpu.kern.callpal::total 192892 # number of callpals executed 616system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches 617system.cpu.kern.mode_switch::user 1742 # number of protection mode switches 618system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 619system.cpu.kern.mode_good::kernel 1911 620system.cpu.kern.mode_good::user 1742 621system.cpu.kern.mode_good::idle 169 622system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches | 465system.cpu.kern.callpal::total 192910 # number of callpals executed 466system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches 467system.cpu.kern.mode_switch::user 1743 # number of protection mode switches 468system.cpu.kern.mode_switch::idle 2100 # number of protection mode switches 469system.cpu.kern.mode_good::kernel 1914 470system.cpu.kern.mode_good::user 1743 471system.cpu.kern.mode_good::idle 171 472system.cpu.kern.mode_switch_good::kernel 0.324352 # fraction of useful protection mode switches |
| 623system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 473system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 624system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches 625system.cpu.kern.mode_switch_good::total 0.392443 # fraction of useful protection mode switches 626system.cpu.kern.mode_ticks::kernel 46142250000 2.40% 2.40% # number of ticks spent at the given mode 627system.cpu.kern.mode_ticks::user 5192719000 0.27% 2.67% # number of ticks spent at the given mode 628system.cpu.kern.mode_ticks::idle 1868103320000 97.33% 100.00% # number of ticks spent at the given mode 629system.cpu.kern.swap_context 4176 # number of times the context was actually changed 630system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 631system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 632system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 633system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 634system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 635system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 636system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 637system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 638system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 639system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 640system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 641system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 642system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 643system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 644system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 645system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 646system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 647system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 648system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 649system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 650system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 651system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 652system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 653system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 654system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 655system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 656system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 657system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 658system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 659system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 660system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 661system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 662system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 663system.iobus.trans_dist::WriteReq 51197 # Transaction distribution 664system.iobus.trans_dist::WriteResp 51201 # Transaction distribution 665system.iobus.trans_dist::WriteInvalidateReq 4 # Transaction distribution 666system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) 667system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 668system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 669system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 670system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 671system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 672system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 673system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 674system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 675system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 676system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 677system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 678system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) 679system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 680system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 681system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) 682system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) 683system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 684system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 685system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 686system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 687system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 688system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 689system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 690system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 691system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 692system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 693system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 694system.iobus.pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) 695system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 696system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 697system.iobus.pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) 698system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) 699system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 700system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 701system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 702system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 703system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 704system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 705system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 706system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 707system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 708system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 709system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 710system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 711system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 712system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 713system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 714system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 715system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 716system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 717system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 718system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 719system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 720system.iobus.reqLayer29.occupancy 374412187 # Layer occupancy (ticks) 721system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 722system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 723system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 724system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) 725system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 726system.iobus.respLayer1.occupancy 42016750 # Layer occupancy (ticks) 727system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 728system.cpu.icache.tags.replacements 927651 # number of replacements 729system.cpu.icache.tags.tagsinuse 508.304035 # Cycle average of tags in use 730system.cpu.icache.tags.total_refs 55185726 # Total number of references to valid blocks. 731system.cpu.icache.tags.sampled_refs 928162 # Sample count of references to valid blocks. 732system.cpu.icache.tags.avg_refs 59.456998 # Average number of references to valid blocks. | 474system.cpu.kern.mode_switch_good::idle 0.081429 # fraction of useful protection mode switches 475system.cpu.kern.mode_switch_good::total 0.392857 # fraction of useful protection mode switches 476system.cpu.kern.mode_ticks::kernel 46106755000 2.40% 2.40% # number of ticks spent at the given mode 477system.cpu.kern.mode_ticks::user 5190620000 0.27% 2.67% # number of ticks spent at the given mode 478system.cpu.kern.mode_ticks::idle 1869129766000 97.33% 100.00% # number of ticks spent at the given mode 479system.cpu.kern.swap_context 4179 # number of times the context was actually changed 480system.cpu.dcache.tags.replacements 1390139 # number of replacements 481system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use 482system.cpu.dcache.tags.total_refs 14031130 # Total number of references to valid blocks. 483system.cpu.dcache.tags.sampled_refs 1390651 # Sample count of references to valid blocks. 484system.cpu.dcache.tags.avg_refs 10.089613 # Average number of references to valid blocks. 485system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. 486system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor 487system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy 488system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy 489system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 490system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 491system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 492system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 493system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 494system.cpu.dcache.tags.tag_accesses 63077780 # Number of tag accesses 495system.cpu.dcache.tags.data_accesses 63077780 # Number of data accesses 496system.cpu.dcache.ReadReq_hits::cpu.data 7803062 # number of ReadReq hits 497system.cpu.dcache.ReadReq_hits::total 7803062 # number of ReadReq hits 498system.cpu.dcache.WriteReq_hits::cpu.data 5845783 # number of WriteReq hits 499system.cpu.dcache.WriteReq_hits::total 5845783 # number of WriteReq hits 500system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits 501system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits 502system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits 503system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits 504system.cpu.dcache.demand_hits::cpu.data 13648845 # number of demand (read+write) hits 505system.cpu.dcache.demand_hits::total 13648845 # number of demand (read+write) hits 506system.cpu.dcache.overall_hits::cpu.data 13648845 # number of overall hits 507system.cpu.dcache.overall_hits::total 13648845 # number of overall hits 508system.cpu.dcache.ReadReq_misses::cpu.data 1069228 # number of ReadReq misses 509system.cpu.dcache.ReadReq_misses::total 1069228 # number of ReadReq misses 510system.cpu.dcache.WriteReq_misses::cpu.data 304213 # number of WriteReq misses 511system.cpu.dcache.WriteReq_misses::total 304213 # number of WriteReq misses 512system.cpu.dcache.LoadLockedReq_misses::cpu.data 17228 # number of LoadLockedReq misses 513system.cpu.dcache.LoadLockedReq_misses::total 17228 # number of LoadLockedReq misses 514system.cpu.dcache.demand_misses::cpu.data 1373441 # number of demand (read+write) misses 515system.cpu.dcache.demand_misses::total 1373441 # number of demand (read+write) misses 516system.cpu.dcache.overall_misses::cpu.data 1373441 # number of overall misses 517system.cpu.dcache.overall_misses::total 1373441 # number of overall misses 518system.cpu.dcache.ReadReq_miss_latency::cpu.data 29002641750 # number of ReadReq miss cycles 519system.cpu.dcache.ReadReq_miss_latency::total 29002641750 # number of ReadReq miss cycles 520system.cpu.dcache.WriteReq_miss_latency::cpu.data 10915376130 # number of WriteReq miss cycles 521system.cpu.dcache.WriteReq_miss_latency::total 10915376130 # number of WriteReq miss cycles 522system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228802500 # number of LoadLockedReq miss cycles 523system.cpu.dcache.LoadLockedReq_miss_latency::total 228802500 # number of LoadLockedReq miss cycles 524system.cpu.dcache.demand_miss_latency::cpu.data 39918017880 # number of demand (read+write) miss cycles 525system.cpu.dcache.demand_miss_latency::total 39918017880 # number of demand (read+write) miss cycles 526system.cpu.dcache.overall_miss_latency::cpu.data 39918017880 # number of overall miss cycles 527system.cpu.dcache.overall_miss_latency::total 39918017880 # number of overall miss cycles 528system.cpu.dcache.ReadReq_accesses::cpu.data 8872290 # number of ReadReq accesses(hits+misses) 529system.cpu.dcache.ReadReq_accesses::total 8872290 # number of ReadReq accesses(hits+misses) 530system.cpu.dcache.WriteReq_accesses::cpu.data 6149996 # number of WriteReq accesses(hits+misses) 531system.cpu.dcache.WriteReq_accesses::total 6149996 # number of WriteReq accesses(hits+misses) 532system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200258 # number of LoadLockedReq accesses(hits+misses) 533system.cpu.dcache.LoadLockedReq_accesses::total 200258 # number of LoadLockedReq accesses(hits+misses) 534system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses) 535system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses) 536system.cpu.dcache.demand_accesses::cpu.data 15022286 # number of demand (read+write) accesses 537system.cpu.dcache.demand_accesses::total 15022286 # number of demand (read+write) accesses 538system.cpu.dcache.overall_accesses::cpu.data 15022286 # number of overall (read+write) accesses 539system.cpu.dcache.overall_accesses::total 15022286 # number of overall (read+write) accesses 540system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120513 # miss rate for ReadReq accesses 541system.cpu.dcache.ReadReq_miss_rate::total 0.120513 # miss rate for ReadReq accesses 542system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049466 # miss rate for WriteReq accesses 543system.cpu.dcache.WriteReq_miss_rate::total 0.049466 # miss rate for WriteReq accesses 544system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086029 # miss rate for LoadLockedReq accesses 545system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086029 # miss rate for LoadLockedReq accesses 546system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses 547system.cpu.dcache.demand_miss_rate::total 0.091427 # miss rate for demand accesses 548system.cpu.dcache.overall_miss_rate::cpu.data 0.091427 # miss rate for overall accesses 549system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses 550system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27124.843111 # average ReadReq miss latency 551system.cpu.dcache.ReadReq_avg_miss_latency::total 27124.843111 # average ReadReq miss latency 552system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35880.702435 # average WriteReq miss latency 553system.cpu.dcache.WriteReq_avg_miss_latency::total 35880.702435 # average WriteReq miss latency 554system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13280.850940 # average LoadLockedReq miss latency 555system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13280.850940 # average LoadLockedReq miss latency 556system.cpu.dcache.demand_avg_miss_latency::cpu.data 29064.239294 # average overall miss latency 557system.cpu.dcache.demand_avg_miss_latency::total 29064.239294 # average overall miss latency 558system.cpu.dcache.overall_avg_miss_latency::cpu.data 29064.239294 # average overall miss latency 559system.cpu.dcache.overall_avg_miss_latency::total 29064.239294 # average overall miss latency 560system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 561system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 562system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 563system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 564system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 565system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 566system.cpu.dcache.fast_writes 0 # number of fast writes performed 567system.cpu.dcache.cache_copies 0 # number of cache copies performed 568system.cpu.dcache.writebacks::writebacks 834534 # number of writebacks 569system.cpu.dcache.writebacks::total 834534 # number of writebacks 570system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069228 # number of ReadReq MSHR misses 571system.cpu.dcache.ReadReq_mshr_misses::total 1069228 # number of ReadReq MSHR misses 572system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304213 # number of WriteReq MSHR misses 573system.cpu.dcache.WriteReq_mshr_misses::total 304213 # number of WriteReq MSHR misses 574system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17228 # number of LoadLockedReq MSHR misses 575system.cpu.dcache.LoadLockedReq_mshr_misses::total 17228 # number of LoadLockedReq MSHR misses 576system.cpu.dcache.demand_mshr_misses::cpu.data 1373441 # number of demand (read+write) MSHR misses 577system.cpu.dcache.demand_mshr_misses::total 1373441 # number of demand (read+write) MSHR misses 578system.cpu.dcache.overall_mshr_misses::cpu.data 1373441 # number of overall MSHR misses 579system.cpu.dcache.overall_mshr_misses::total 1373441 # number of overall MSHR misses 580system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26738553250 # number of ReadReq MSHR miss cycles 581system.cpu.dcache.ReadReq_mshr_miss_latency::total 26738553250 # number of ReadReq MSHR miss cycles 582system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10254282870 # number of WriteReq MSHR miss cycles 583system.cpu.dcache.WriteReq_mshr_miss_latency::total 10254282870 # number of WriteReq MSHR miss cycles 584system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194333500 # number of LoadLockedReq MSHR miss cycles 585system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194333500 # number of LoadLockedReq MSHR miss cycles 586system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36992836120 # number of demand (read+write) MSHR miss cycles 587system.cpu.dcache.demand_mshr_miss_latency::total 36992836120 # number of demand (read+write) MSHR miss cycles 588system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36992836120 # number of overall MSHR miss cycles 589system.cpu.dcache.overall_mshr_miss_latency::total 36992836120 # number of overall MSHR miss cycles 590system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424273000 # number of ReadReq MSHR uncacheable cycles 591system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles 592system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009400000 # number of WriteReq MSHR uncacheable cycles 593system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009400000 # number of WriteReq MSHR uncacheable cycles 594system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433673000 # number of overall MSHR uncacheable cycles 595system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433673000 # number of overall MSHR uncacheable cycles 596system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120513 # mshr miss rate for ReadReq accesses 597system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120513 # mshr miss rate for ReadReq accesses 598system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049466 # mshr miss rate for WriteReq accesses 599system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049466 # mshr miss rate for WriteReq accesses 600system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086029 # mshr miss rate for LoadLockedReq accesses 601system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086029 # mshr miss rate for LoadLockedReq accesses 602system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses 603system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses 604system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses 605system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses 606system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25007.344785 # average ReadReq mshr miss latency 607system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25007.344785 # average ReadReq mshr miss latency 608system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33707.576172 # average WriteReq mshr miss latency 609system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33707.576172 # average WriteReq mshr miss latency 610system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11280.096355 # average LoadLockedReq mshr miss latency 611system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11280.096355 # average LoadLockedReq mshr miss latency 612system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26934.419549 # average overall mshr miss latency 613system.cpu.dcache.demand_avg_mshr_miss_latency::total 26934.419549 # average overall mshr miss latency 614system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26934.419549 # average overall mshr miss latency 615system.cpu.dcache.overall_avg_mshr_miss_latency::total 26934.419549 # average overall mshr miss latency 616system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 617system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 618system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 619system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 620system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 621system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 622system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 623system.cpu.icache.tags.replacements 927958 # number of replacements 624system.cpu.icache.tags.tagsinuse 508.305941 # Cycle average of tags in use 625system.cpu.icache.tags.total_refs 55188530 # Total number of references to valid blocks. 626system.cpu.icache.tags.sampled_refs 928469 # Sample count of references to valid blocks. 627system.cpu.icache.tags.avg_refs 59.440358 # Average number of references to valid blocks. |
| 733system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit. | 628system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit. |
| 734system.cpu.icache.tags.occ_blocks::cpu.inst 508.304035 # Average occupied blocks per requestor 735system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy 736system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy | 629system.cpu.icache.tags.occ_blocks::cpu.inst 508.305941 # Average occupied blocks per requestor 630system.cpu.icache.tags.occ_percent::cpu.inst 0.992785 # Average percentage of cache occupancy 631system.cpu.icache.tags.occ_percent::total 0.992785 # Average percentage of cache occupancy |
| 737system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 738system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 739system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 740system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 741system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 742system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 632system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 633system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 635system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 636system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 637system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 743system.cpu.icache.tags.tag_accesses 57042370 # Number of tag accesses 744system.cpu.icache.tags.data_accesses 57042370 # Number of data accesses 745system.cpu.icache.ReadReq_hits::cpu.inst 55185726 # number of ReadReq hits 746system.cpu.icache.ReadReq_hits::total 55185726 # number of ReadReq hits 747system.cpu.icache.demand_hits::cpu.inst 55185726 # number of demand (read+write) hits 748system.cpu.icache.demand_hits::total 55185726 # number of demand (read+write) hits 749system.cpu.icache.overall_hits::cpu.inst 55185726 # number of overall hits 750system.cpu.icache.overall_hits::total 55185726 # number of overall hits 751system.cpu.icache.ReadReq_misses::cpu.inst 928322 # number of ReadReq misses 752system.cpu.icache.ReadReq_misses::total 928322 # number of ReadReq misses 753system.cpu.icache.demand_misses::cpu.inst 928322 # number of demand (read+write) misses 754system.cpu.icache.demand_misses::total 928322 # number of demand (read+write) misses 755system.cpu.icache.overall_misses::cpu.inst 928322 # number of overall misses 756system.cpu.icache.overall_misses::total 928322 # number of overall misses 757system.cpu.icache.ReadReq_miss_latency::cpu.inst 12909129000 # number of ReadReq miss cycles 758system.cpu.icache.ReadReq_miss_latency::total 12909129000 # number of ReadReq miss cycles 759system.cpu.icache.demand_miss_latency::cpu.inst 12909129000 # number of demand (read+write) miss cycles 760system.cpu.icache.demand_miss_latency::total 12909129000 # number of demand (read+write) miss cycles 761system.cpu.icache.overall_miss_latency::cpu.inst 12909129000 # number of overall miss cycles 762system.cpu.icache.overall_miss_latency::total 12909129000 # number of overall miss cycles 763system.cpu.icache.ReadReq_accesses::cpu.inst 56114048 # number of ReadReq accesses(hits+misses) 764system.cpu.icache.ReadReq_accesses::total 56114048 # number of ReadReq accesses(hits+misses) 765system.cpu.icache.demand_accesses::cpu.inst 56114048 # number of demand (read+write) accesses 766system.cpu.icache.demand_accesses::total 56114048 # number of demand (read+write) accesses 767system.cpu.icache.overall_accesses::cpu.inst 56114048 # number of overall (read+write) accesses 768system.cpu.icache.overall_accesses::total 56114048 # number of overall (read+write) accesses 769system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016543 # miss rate for ReadReq accesses 770system.cpu.icache.ReadReq_miss_rate::total 0.016543 # miss rate for ReadReq accesses 771system.cpu.icache.demand_miss_rate::cpu.inst 0.016543 # miss rate for demand accesses 772system.cpu.icache.demand_miss_rate::total 0.016543 # miss rate for demand accesses 773system.cpu.icache.overall_miss_rate::cpu.inst 0.016543 # miss rate for overall accesses 774system.cpu.icache.overall_miss_rate::total 0.016543 # miss rate for overall accesses 775system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13905.874255 # average ReadReq miss latency 776system.cpu.icache.ReadReq_avg_miss_latency::total 13905.874255 # average ReadReq miss latency 777system.cpu.icache.demand_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency 778system.cpu.icache.demand_avg_miss_latency::total 13905.874255 # average overall miss latency 779system.cpu.icache.overall_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency 780system.cpu.icache.overall_avg_miss_latency::total 13905.874255 # average overall miss latency | 638system.cpu.icache.tags.tag_accesses 57045788 # Number of tag accesses 639system.cpu.icache.tags.data_accesses 57045788 # Number of data accesses 640system.cpu.icache.ReadReq_hits::cpu.inst 55188530 # number of ReadReq hits 641system.cpu.icache.ReadReq_hits::total 55188530 # number of ReadReq hits 642system.cpu.icache.demand_hits::cpu.inst 55188530 # number of demand (read+write) hits 643system.cpu.icache.demand_hits::total 55188530 # number of demand (read+write) hits 644system.cpu.icache.overall_hits::cpu.inst 55188530 # number of overall hits 645system.cpu.icache.overall_hits::total 55188530 # number of overall hits 646system.cpu.icache.ReadReq_misses::cpu.inst 928629 # number of ReadReq misses 647system.cpu.icache.ReadReq_misses::total 928629 # number of ReadReq misses 648system.cpu.icache.demand_misses::cpu.inst 928629 # number of demand (read+write) misses 649system.cpu.icache.demand_misses::total 928629 # number of demand (read+write) misses 650system.cpu.icache.overall_misses::cpu.inst 928629 # number of overall misses 651system.cpu.icache.overall_misses::total 928629 # number of overall misses 652system.cpu.icache.ReadReq_miss_latency::cpu.inst 12911718500 # number of ReadReq miss cycles 653system.cpu.icache.ReadReq_miss_latency::total 12911718500 # number of ReadReq miss cycles 654system.cpu.icache.demand_miss_latency::cpu.inst 12911718500 # number of demand (read+write) miss cycles 655system.cpu.icache.demand_miss_latency::total 12911718500 # number of demand (read+write) miss cycles 656system.cpu.icache.overall_miss_latency::cpu.inst 12911718500 # number of overall miss cycles 657system.cpu.icache.overall_miss_latency::total 12911718500 # number of overall miss cycles 658system.cpu.icache.ReadReq_accesses::cpu.inst 56117159 # number of ReadReq accesses(hits+misses) 659system.cpu.icache.ReadReq_accesses::total 56117159 # number of ReadReq accesses(hits+misses) 660system.cpu.icache.demand_accesses::cpu.inst 56117159 # number of demand (read+write) accesses 661system.cpu.icache.demand_accesses::total 56117159 # number of demand (read+write) accesses 662system.cpu.icache.overall_accesses::cpu.inst 56117159 # number of overall (read+write) accesses 663system.cpu.icache.overall_accesses::total 56117159 # number of overall (read+write) accesses 664system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016548 # miss rate for ReadReq accesses 665system.cpu.icache.ReadReq_miss_rate::total 0.016548 # miss rate for ReadReq accesses 666system.cpu.icache.demand_miss_rate::cpu.inst 0.016548 # miss rate for demand accesses 667system.cpu.icache.demand_miss_rate::total 0.016548 # miss rate for demand accesses 668system.cpu.icache.overall_miss_rate::cpu.inst 0.016548 # miss rate for overall accesses 669system.cpu.icache.overall_miss_rate::total 0.016548 # miss rate for overall accesses 670system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13904.065563 # average ReadReq miss latency 671system.cpu.icache.ReadReq_avg_miss_latency::total 13904.065563 # average ReadReq miss latency 672system.cpu.icache.demand_avg_miss_latency::cpu.inst 13904.065563 # average overall miss latency 673system.cpu.icache.demand_avg_miss_latency::total 13904.065563 # average overall miss latency 674system.cpu.icache.overall_avg_miss_latency::cpu.inst 13904.065563 # average overall miss latency 675system.cpu.icache.overall_avg_miss_latency::total 13904.065563 # average overall miss latency |
| 781system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 782system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 783system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 784system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 785system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 786system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 787system.cpu.icache.fast_writes 0 # number of fast writes performed 788system.cpu.icache.cache_copies 0 # number of cache copies performed | 676system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 677system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 678system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 679system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 680system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 681system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 682system.cpu.icache.fast_writes 0 # number of fast writes performed 683system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 789system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928322 # number of ReadReq MSHR misses 790system.cpu.icache.ReadReq_mshr_misses::total 928322 # number of ReadReq MSHR misses 791system.cpu.icache.demand_mshr_misses::cpu.inst 928322 # number of demand (read+write) MSHR misses 792system.cpu.icache.demand_mshr_misses::total 928322 # number of demand (read+write) MSHR misses 793system.cpu.icache.overall_mshr_misses::cpu.inst 928322 # number of overall MSHR misses 794system.cpu.icache.overall_mshr_misses::total 928322 # number of overall MSHR misses 795system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11047351000 # number of ReadReq MSHR miss cycles 796system.cpu.icache.ReadReq_mshr_miss_latency::total 11047351000 # number of ReadReq MSHR miss cycles 797system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11047351000 # number of demand (read+write) MSHR miss cycles 798system.cpu.icache.demand_mshr_miss_latency::total 11047351000 # number of demand (read+write) MSHR miss cycles 799system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11047351000 # number of overall MSHR miss cycles 800system.cpu.icache.overall_mshr_miss_latency::total 11047351000 # number of overall MSHR miss cycles 801system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses 802system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses 803system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses 804system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses 805system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses 806system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses 807system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11900.343846 # average ReadReq mshr miss latency 808system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11900.343846 # average ReadReq mshr miss latency 809system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency 810system.cpu.icache.demand_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency 811system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency 812system.cpu.icache.overall_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency | 684system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928629 # number of ReadReq MSHR misses 685system.cpu.icache.ReadReq_mshr_misses::total 928629 # number of ReadReq MSHR misses 686system.cpu.icache.demand_mshr_misses::cpu.inst 928629 # number of demand (read+write) MSHR misses 687system.cpu.icache.demand_mshr_misses::total 928629 # number of demand (read+write) MSHR misses 688system.cpu.icache.overall_mshr_misses::cpu.inst 928629 # number of overall MSHR misses 689system.cpu.icache.overall_mshr_misses::total 928629 # number of overall MSHR misses 690system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11049312500 # number of ReadReq MSHR miss cycles 691system.cpu.icache.ReadReq_mshr_miss_latency::total 11049312500 # number of ReadReq MSHR miss cycles 692system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11049312500 # number of demand (read+write) MSHR miss cycles 693system.cpu.icache.demand_mshr_miss_latency::total 11049312500 # number of demand (read+write) MSHR miss cycles 694system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11049312500 # number of overall MSHR miss cycles 695system.cpu.icache.overall_mshr_miss_latency::total 11049312500 # number of overall MSHR miss cycles 696system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016548 # mshr miss rate for ReadReq accesses 697system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016548 # mshr miss rate for ReadReq accesses 698system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016548 # mshr miss rate for demand accesses 699system.cpu.icache.demand_mshr_miss_rate::total 0.016548 # mshr miss rate for demand accesses 700system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016548 # mshr miss rate for overall accesses 701system.cpu.icache.overall_mshr_miss_rate::total 0.016548 # mshr miss rate for overall accesses 702system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.521907 # average ReadReq mshr miss latency 703system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.521907 # average ReadReq mshr miss latency 704system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.521907 # average overall mshr miss latency 705system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.521907 # average overall mshr miss latency 706system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.521907 # average overall mshr miss latency 707system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.521907 # average overall mshr miss latency |
| 813system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 708system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 814system.cpu.l2cache.tags.replacements 336238 # number of replacements 815system.cpu.l2cache.tags.tagsinuse 65296.035696 # Cycle average of tags in use 816system.cpu.l2cache.tags.total_refs 2445623 # Total number of references to valid blocks. 817system.cpu.l2cache.tags.sampled_refs 401399 # Sample count of references to valid blocks. 818system.cpu.l2cache.tags.avg_refs 6.092748 # Average number of references to valid blocks. | 709system.cpu.l2cache.tags.replacements 336233 # number of replacements 710system.cpu.l2cache.tags.tagsinuse 65296.128852 # Cycle average of tags in use 711system.cpu.l2cache.tags.total_refs 2446119 # Total number of references to valid blocks. 712system.cpu.l2cache.tags.sampled_refs 401395 # Sample count of references to valid blocks. 713system.cpu.l2cache.tags.avg_refs 6.094045 # Average number of references to valid blocks. |
| 819system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit. | 714system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit. |
| 820system.cpu.l2cache.tags.occ_blocks::writebacks 55554.100042 # Average occupied blocks per requestor 821system.cpu.l2cache.tags.occ_blocks::cpu.inst 4767.074149 # Average occupied blocks per requestor 822system.cpu.l2cache.tags.occ_blocks::cpu.data 4974.861505 # Average occupied blocks per requestor 823system.cpu.l2cache.tags.occ_percent::writebacks 0.847688 # Average percentage of cache occupancy 824system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072740 # Average percentage of cache occupancy 825system.cpu.l2cache.tags.occ_percent::cpu.data 0.075910 # Average percentage of cache occupancy 826system.cpu.l2cache.tags.occ_percent::total 0.996338 # Average percentage of cache occupancy 827system.cpu.l2cache.tags.occ_task_id_blocks::1024 65161 # Occupied blocks per task id 828system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id | 715system.cpu.l2cache.tags.occ_blocks::writebacks 55552.665832 # Average occupied blocks per requestor 716system.cpu.l2cache.tags.occ_blocks::cpu.inst 4768.375008 # Average occupied blocks per requestor 717system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.088012 # Average occupied blocks per requestor 718system.cpu.l2cache.tags.occ_percent::writebacks 0.847666 # Average percentage of cache occupancy 719system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy 720system.cpu.l2cache.tags.occ_percent::cpu.data 0.075914 # Average percentage of cache occupancy 721system.cpu.l2cache.tags.occ_percent::total 0.996340 # Average percentage of cache occupancy 722system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 723system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id |
| 829system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id 830system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id | 724system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id 725system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id |
| 831system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3263 # Occupied blocks per task id 832system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55775 # Occupied blocks per task id 833system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994278 # Percentage of cache occupancy per task id 834system.cpu.l2cache.tags.tag_accesses 25932255 # Number of tag accesses 835system.cpu.l2cache.tags.data_accesses 25932255 # Number of data accesses 836system.cpu.l2cache.ReadReq_hits::cpu.inst 915008 # number of ReadReq hits 837system.cpu.l2cache.ReadReq_hits::cpu.data 814389 # number of ReadReq hits 838system.cpu.l2cache.ReadReq_hits::total 1729397 # number of ReadReq hits 839system.cpu.l2cache.Writeback_hits::writebacks 834448 # number of Writeback hits 840system.cpu.l2cache.Writeback_hits::total 834448 # number of Writeback hits | 726system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3259 # Occupied blocks per task id 727system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55779 # Occupied blocks per task id 728system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id 729system.cpu.l2cache.tags.tag_accesses 25936314 # Number of tag accesses 730system.cpu.l2cache.tags.data_accesses 25936314 # Number of data accesses 731system.cpu.l2cache.ReadReq_hits::cpu.inst 915316 # number of ReadReq hits 732system.cpu.l2cache.ReadReq_hits::cpu.data 814497 # number of ReadReq hits 733system.cpu.l2cache.ReadReq_hits::total 1729813 # number of ReadReq hits 734system.cpu.l2cache.Writeback_hits::writebacks 834534 # number of Writeback hits 735system.cpu.l2cache.Writeback_hits::total 834534 # number of Writeback hits |
| 841system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 842system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 736system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 737system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 843system.cpu.l2cache.ReadExReq_hits::cpu.data 187344 # number of ReadExReq hits 844system.cpu.l2cache.ReadExReq_hits::total 187344 # number of ReadExReq hits 845system.cpu.l2cache.demand_hits::cpu.inst 915008 # number of demand (read+write) hits 846system.cpu.l2cache.demand_hits::cpu.data 1001733 # number of demand (read+write) hits 847system.cpu.l2cache.demand_hits::total 1916741 # number of demand (read+write) hits 848system.cpu.l2cache.overall_hits::cpu.inst 915008 # number of overall hits 849system.cpu.l2cache.overall_hits::cpu.data 1001733 # number of overall hits 850system.cpu.l2cache.overall_hits::total 1916741 # number of overall hits 851system.cpu.l2cache.ReadReq_misses::cpu.inst 13294 # number of ReadReq misses 852system.cpu.l2cache.ReadReq_misses::cpu.data 271960 # number of ReadReq misses 853system.cpu.l2cache.ReadReq_misses::total 285254 # number of ReadReq misses | 738system.cpu.l2cache.ReadExReq_hits::cpu.data 187354 # number of ReadExReq hits 739system.cpu.l2cache.ReadExReq_hits::total 187354 # number of ReadExReq hits 740system.cpu.l2cache.demand_hits::cpu.inst 915316 # number of demand (read+write) hits 741system.cpu.l2cache.demand_hits::cpu.data 1001851 # number of demand (read+write) hits 742system.cpu.l2cache.demand_hits::total 1917167 # number of demand (read+write) hits 743system.cpu.l2cache.overall_hits::cpu.inst 915316 # number of overall hits 744system.cpu.l2cache.overall_hits::cpu.data 1001851 # number of overall hits 745system.cpu.l2cache.overall_hits::total 1917167 # number of overall hits 746system.cpu.l2cache.ReadReq_misses::cpu.inst 13293 # number of ReadReq misses 747system.cpu.l2cache.ReadReq_misses::cpu.data 271959 # number of ReadReq misses 748system.cpu.l2cache.ReadReq_misses::total 285252 # number of ReadReq misses |
| 854system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 855system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses | 749system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 750system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses |
| 856system.cpu.l2cache.ReadExReq_misses::cpu.data 116845 # number of ReadExReq misses 857system.cpu.l2cache.ReadExReq_misses::total 116845 # number of ReadExReq misses 858system.cpu.l2cache.demand_misses::cpu.inst 13294 # number of demand (read+write) misses 859system.cpu.l2cache.demand_misses::cpu.data 388805 # number of demand (read+write) misses 860system.cpu.l2cache.demand_misses::total 402099 # number of demand (read+write) misses 861system.cpu.l2cache.overall_misses::cpu.inst 13294 # number of overall misses 862system.cpu.l2cache.overall_misses::cpu.data 388805 # number of overall misses 863system.cpu.l2cache.overall_misses::total 402099 # number of overall misses 864system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 968929000 # number of ReadReq miss cycles 865system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17693938000 # number of ReadReq miss cycles 866system.cpu.l2cache.ReadReq_miss_latency::total 18662867000 # number of ReadReq miss cycles 867system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 93496 # number of UpgradeReq miss cycles 868system.cpu.l2cache.UpgradeReq_miss_latency::total 93496 # number of UpgradeReq miss cycles 869system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8083085881 # number of ReadExReq miss cycles 870system.cpu.l2cache.ReadExReq_miss_latency::total 8083085881 # number of ReadExReq miss cycles 871system.cpu.l2cache.demand_miss_latency::cpu.inst 968929000 # number of demand (read+write) miss cycles 872system.cpu.l2cache.demand_miss_latency::cpu.data 25777023881 # number of demand (read+write) miss cycles 873system.cpu.l2cache.demand_miss_latency::total 26745952881 # number of demand (read+write) miss cycles 874system.cpu.l2cache.overall_miss_latency::cpu.inst 968929000 # number of overall miss cycles 875system.cpu.l2cache.overall_miss_latency::cpu.data 25777023881 # number of overall miss cycles 876system.cpu.l2cache.overall_miss_latency::total 26745952881 # number of overall miss cycles 877system.cpu.l2cache.ReadReq_accesses::cpu.inst 928302 # number of ReadReq accesses(hits+misses) 878system.cpu.l2cache.ReadReq_accesses::cpu.data 1086349 # number of ReadReq accesses(hits+misses) 879system.cpu.l2cache.ReadReq_accesses::total 2014651 # number of ReadReq accesses(hits+misses) 880system.cpu.l2cache.Writeback_accesses::writebacks 834448 # number of Writeback accesses(hits+misses) 881system.cpu.l2cache.Writeback_accesses::total 834448 # number of Writeback accesses(hits+misses) | 751system.cpu.l2cache.ReadExReq_misses::cpu.data 116842 # number of ReadExReq misses 752system.cpu.l2cache.ReadExReq_misses::total 116842 # number of ReadExReq misses 753system.cpu.l2cache.demand_misses::cpu.inst 13293 # number of demand (read+write) misses 754system.cpu.l2cache.demand_misses::cpu.data 388801 # number of demand (read+write) misses 755system.cpu.l2cache.demand_misses::total 402094 # number of demand (read+write) misses 756system.cpu.l2cache.overall_misses::cpu.inst 13293 # number of overall misses 757system.cpu.l2cache.overall_misses::cpu.data 388801 # number of overall misses 758system.cpu.l2cache.overall_misses::total 402094 # number of overall misses 759system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 967503500 # number of ReadReq miss cycles 760system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17701460750 # number of ReadReq miss cycles 761system.cpu.l2cache.ReadReq_miss_latency::total 18668964250 # number of ReadReq miss cycles 762system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles 763system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles 764system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8076097381 # number of ReadExReq miss cycles 765system.cpu.l2cache.ReadExReq_miss_latency::total 8076097381 # number of ReadExReq miss cycles 766system.cpu.l2cache.demand_miss_latency::cpu.inst 967503500 # number of demand (read+write) miss cycles 767system.cpu.l2cache.demand_miss_latency::cpu.data 25777558131 # number of demand (read+write) miss cycles 768system.cpu.l2cache.demand_miss_latency::total 26745061631 # number of demand (read+write) miss cycles 769system.cpu.l2cache.overall_miss_latency::cpu.inst 967503500 # number of overall miss cycles 770system.cpu.l2cache.overall_miss_latency::cpu.data 25777558131 # number of overall miss cycles 771system.cpu.l2cache.overall_miss_latency::total 26745061631 # number of overall miss cycles 772system.cpu.l2cache.ReadReq_accesses::cpu.inst 928609 # number of ReadReq accesses(hits+misses) 773system.cpu.l2cache.ReadReq_accesses::cpu.data 1086456 # number of ReadReq accesses(hits+misses) 774system.cpu.l2cache.ReadReq_accesses::total 2015065 # number of ReadReq accesses(hits+misses) 775system.cpu.l2cache.Writeback_accesses::writebacks 834534 # number of Writeback accesses(hits+misses) 776system.cpu.l2cache.Writeback_accesses::total 834534 # number of Writeback accesses(hits+misses) |
| 882system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 883system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) | 777system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 778system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) |
| 884system.cpu.l2cache.ReadExReq_accesses::cpu.data 304189 # number of ReadExReq accesses(hits+misses) 885system.cpu.l2cache.ReadExReq_accesses::total 304189 # number of ReadExReq accesses(hits+misses) 886system.cpu.l2cache.demand_accesses::cpu.inst 928302 # number of demand (read+write) accesses 887system.cpu.l2cache.demand_accesses::cpu.data 1390538 # number of demand (read+write) accesses 888system.cpu.l2cache.demand_accesses::total 2318840 # number of demand (read+write) accesses 889system.cpu.l2cache.overall_accesses::cpu.inst 928302 # number of overall (read+write) accesses 890system.cpu.l2cache.overall_accesses::cpu.data 1390538 # number of overall (read+write) accesses 891system.cpu.l2cache.overall_accesses::total 2318840 # number of overall (read+write) accesses 892system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014321 # miss rate for ReadReq accesses 893system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250343 # miss rate for ReadReq accesses 894system.cpu.l2cache.ReadReq_miss_rate::total 0.141590 # miss rate for ReadReq accesses | 779system.cpu.l2cache.ReadExReq_accesses::cpu.data 304196 # number of ReadExReq accesses(hits+misses) 780system.cpu.l2cache.ReadExReq_accesses::total 304196 # number of ReadExReq accesses(hits+misses) 781system.cpu.l2cache.demand_accesses::cpu.inst 928609 # number of demand (read+write) accesses 782system.cpu.l2cache.demand_accesses::cpu.data 1390652 # number of demand (read+write) accesses 783system.cpu.l2cache.demand_accesses::total 2319261 # number of demand (read+write) accesses 784system.cpu.l2cache.overall_accesses::cpu.inst 928609 # number of overall (read+write) accesses 785system.cpu.l2cache.overall_accesses::cpu.data 1390652 # number of overall (read+write) accesses 786system.cpu.l2cache.overall_accesses::total 2319261 # number of overall (read+write) accesses 787system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014315 # miss rate for ReadReq accesses 788system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250318 # miss rate for ReadReq accesses 789system.cpu.l2cache.ReadReq_miss_rate::total 0.141560 # miss rate for ReadReq accesses |
| 895system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 896system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses | 790system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 791system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses |
| 897system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384120 # miss rate for ReadExReq accesses 898system.cpu.l2cache.ReadExReq_miss_rate::total 0.384120 # miss rate for ReadExReq accesses 899system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014321 # miss rate for demand accesses 900system.cpu.l2cache.demand_miss_rate::cpu.data 0.279608 # miss rate for demand accesses 901system.cpu.l2cache.demand_miss_rate::total 0.173405 # miss rate for demand accesses 902system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014321 # miss rate for overall accesses 903system.cpu.l2cache.overall_miss_rate::cpu.data 0.279608 # miss rate for overall accesses 904system.cpu.l2cache.overall_miss_rate::total 0.173405 # miss rate for overall accesses 905system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72884.684820 # average ReadReq miss latency 906system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65060.810413 # average ReadReq miss latency 907system.cpu.l2cache.ReadReq_avg_miss_latency::total 65425.434876 # average ReadReq miss latency 908system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7192 # average UpgradeReq miss latency 909system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7192 # average UpgradeReq miss latency 910system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69177.849981 # average ReadExReq miss latency 911system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69177.849981 # average ReadExReq miss latency 912system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72884.684820 # average overall miss latency 913system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66298.077136 # average overall miss latency 914system.cpu.l2cache.demand_avg_miss_latency::total 66515.840330 # average overall miss latency 915system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72884.684820 # average overall miss latency 916system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66298.077136 # average overall miss latency 917system.cpu.l2cache.overall_avg_miss_latency::total 66515.840330 # average overall miss latency | 792system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384101 # miss rate for ReadExReq accesses 793system.cpu.l2cache.ReadExReq_miss_rate::total 0.384101 # miss rate for ReadExReq accesses 794system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014315 # miss rate for demand accesses 795system.cpu.l2cache.demand_miss_rate::cpu.data 0.279582 # miss rate for demand accesses 796system.cpu.l2cache.demand_miss_rate::total 0.173372 # miss rate for demand accesses 797system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014315 # miss rate for overall accesses 798system.cpu.l2cache.overall_miss_rate::cpu.data 0.279582 # miss rate for overall accesses 799system.cpu.l2cache.overall_miss_rate::total 0.173372 # miss rate for overall accesses 800system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72782.930866 # average ReadReq miss latency 801system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65088.710982 # average ReadReq miss latency 802system.cpu.l2cache.ReadReq_avg_miss_latency::total 65447.268556 # average ReadReq miss latency 803system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency 804system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency 805system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69119.814630 # average ReadExReq miss latency 806system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69119.814630 # average ReadExReq miss latency 807system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72782.930866 # average overall miss latency 808system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66300.133310 # average overall miss latency 809system.cpu.l2cache.demand_avg_miss_latency::total 66514.450927 # average overall miss latency 810system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72782.930866 # average overall miss latency 811system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66300.133310 # average overall miss latency 812system.cpu.l2cache.overall_avg_miss_latency::total 66514.450927 # average overall miss latency |
| 918system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 919system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 920system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 921system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 922system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 923system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 924system.cpu.l2cache.fast_writes 0 # number of fast writes performed 925system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 813system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 814system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 815system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 816system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 817system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 818system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 819system.cpu.l2cache.fast_writes 0 # number of fast writes performed 820system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 926system.cpu.l2cache.writebacks::writebacks 74180 # number of writebacks 927system.cpu.l2cache.writebacks::total 74180 # number of writebacks 928system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13294 # number of ReadReq MSHR misses 929system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271960 # number of ReadReq MSHR misses 930system.cpu.l2cache.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses | 821system.cpu.l2cache.writebacks::writebacks 74177 # number of writebacks 822system.cpu.l2cache.writebacks::total 74177 # number of writebacks 823system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13293 # number of ReadReq MSHR misses 824system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271959 # number of ReadReq MSHR misses 825system.cpu.l2cache.ReadReq_mshr_misses::total 285252 # number of ReadReq MSHR misses |
| 931system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 932system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses | 826system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 827system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses |
| 933system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116845 # number of ReadExReq MSHR misses 934system.cpu.l2cache.ReadExReq_mshr_misses::total 116845 # number of ReadExReq MSHR misses 935system.cpu.l2cache.demand_mshr_misses::cpu.inst 13294 # number of demand (read+write) MSHR misses 936system.cpu.l2cache.demand_mshr_misses::cpu.data 388805 # number of demand (read+write) MSHR misses 937system.cpu.l2cache.demand_mshr_misses::total 402099 # number of demand (read+write) MSHR misses 938system.cpu.l2cache.overall_mshr_misses::cpu.inst 13294 # number of overall MSHR misses 939system.cpu.l2cache.overall_mshr_misses::cpu.data 388805 # number of overall MSHR misses 940system.cpu.l2cache.overall_mshr_misses::total 402099 # number of overall MSHR misses 941system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 802368000 # number of ReadReq MSHR miss cycles 942system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14293948000 # number of ReadReq MSHR miss cycles 943system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15096316000 # number of ReadReq MSHR miss cycles 944system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 130013 # number of UpgradeReq MSHR miss cycles 945system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 130013 # number of UpgradeReq MSHR miss cycles 946system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6622079619 # number of ReadExReq MSHR miss cycles 947system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6622079619 # number of ReadExReq MSHR miss cycles 948system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802368000 # number of demand (read+write) MSHR miss cycles 949system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20916027619 # number of demand (read+write) MSHR miss cycles 950system.cpu.l2cache.demand_mshr_miss_latency::total 21718395619 # number of demand (read+write) MSHR miss cycles 951system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802368000 # number of overall MSHR miss cycles 952system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20916027619 # number of overall MSHR miss cycles 953system.cpu.l2cache.overall_mshr_miss_latency::total 21718395619 # number of overall MSHR miss cycles | 828system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116842 # number of ReadExReq MSHR misses 829system.cpu.l2cache.ReadExReq_mshr_misses::total 116842 # number of ReadExReq MSHR misses 830system.cpu.l2cache.demand_mshr_misses::cpu.inst 13293 # number of demand (read+write) MSHR misses 831system.cpu.l2cache.demand_mshr_misses::cpu.data 388801 # number of demand (read+write) MSHR misses 832system.cpu.l2cache.demand_mshr_misses::total 402094 # number of demand (read+write) MSHR misses 833system.cpu.l2cache.overall_mshr_misses::cpu.inst 13293 # number of overall MSHR misses 834system.cpu.l2cache.overall_mshr_misses::cpu.data 388801 # number of overall MSHR misses 835system.cpu.l2cache.overall_mshr_misses::total 402094 # number of overall MSHR misses 836system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 800925500 # number of ReadReq MSHR miss cycles 837system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14301564750 # number of ReadReq MSHR miss cycles 838system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15102490250 # number of ReadReq MSHR miss cycles 839system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles 840system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles 841system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6615159119 # number of ReadExReq MSHR miss cycles 842system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6615159119 # number of ReadExReq MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 800925500 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20916723869 # number of demand (read+write) MSHR miss cycles 845system.cpu.l2cache.demand_mshr_miss_latency::total 21717649369 # number of demand (read+write) MSHR miss cycles 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 800925500 # number of overall MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20916723869 # number of overall MSHR miss cycles 848system.cpu.l2cache.overall_mshr_miss_latency::total 21717649369 # number of overall MSHR miss cycles |
| 954system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334183000 # number of ReadReq MSHR uncacheable cycles 955system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334183000 # number of ReadReq MSHR uncacheable cycles | 849system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334183000 # number of ReadReq MSHR uncacheable cycles 850system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334183000 # number of ReadReq MSHR uncacheable cycles |
| 956system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893390000 # number of WriteReq MSHR uncacheable cycles 957system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893390000 # number of WriteReq MSHR uncacheable cycles 958system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227573000 # number of overall MSHR uncacheable cycles 959system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227573000 # number of overall MSHR uncacheable cycles 960system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for ReadReq accesses 961system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250343 # mshr miss rate for ReadReq accesses 962system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141590 # mshr miss rate for ReadReq accesses | 851system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893600000 # number of WriteReq MSHR uncacheable cycles 852system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893600000 # number of WriteReq MSHR uncacheable cycles 853system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227783000 # number of overall MSHR uncacheable cycles 854system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227783000 # number of overall MSHR uncacheable cycles 855system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for ReadReq accesses 856system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250318 # mshr miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141560 # mshr miss rate for ReadReq accesses |
| 963system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 964system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses | 858system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 859system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses |
| 965system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384120 # mshr miss rate for ReadExReq accesses 966system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384120 # mshr miss rate for ReadExReq accesses 967system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for demand accesses 968system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for demand accesses 969system.cpu.l2cache.demand_mshr_miss_rate::total 0.173405 # mshr miss rate for demand accesses 970system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for overall accesses 971system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for overall accesses 972system.cpu.l2cache.overall_mshr_miss_rate::total 0.173405 # mshr miss rate for overall accesses 973system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60355.649165 # average ReadReq mshr miss latency 974system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52559.008678 # average ReadReq mshr miss latency 975system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52922.363928 # average ReadReq mshr miss latency 976system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 977system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 978system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56674.052112 # average ReadExReq mshr miss latency 979system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56674.052112 # average ReadExReq mshr miss latency 980system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency 981system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency 982system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency 983system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency 984system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency 985system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency | 860system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384101 # mshr miss rate for ReadExReq accesses 861system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384101 # mshr miss rate for ReadExReq accesses 862system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for demand accesses 863system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279582 # mshr miss rate for demand accesses 864system.cpu.l2cache.demand_mshr_miss_rate::total 0.173372 # mshr miss rate for demand accesses 865system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for overall accesses 866system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279582 # mshr miss rate for overall accesses 867system.cpu.l2cache.overall_mshr_miss_rate::total 0.173372 # mshr miss rate for overall accesses 868system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60251.673813 # average ReadReq mshr miss latency 869system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52587.208918 # average ReadReq mshr miss latency 870system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52944.379882 # average ReadReq mshr miss latency 871system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency 872system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency 873system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56616.277700 # average ReadExReq mshr miss latency 874system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56616.277700 # average ReadExReq mshr miss latency 875system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60251.673813 # average overall mshr miss latency 876system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53798.019730 # average overall mshr miss latency 877system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54011.373880 # average overall mshr miss latency 878system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60251.673813 # average overall mshr miss latency 879system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53798.019730 # average overall mshr miss latency 880system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54011.373880 # average overall mshr miss latency |
| 986system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 987system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 988system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 989system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 990system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 991system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 992system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 881system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 882system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 883system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 884system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 885system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 886system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 887system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 993system.cpu.dcache.tags.replacements 1390025 # number of replacements 994system.cpu.dcache.tags.tagsinuse 511.978881 # Cycle average of tags in use 995system.cpu.dcache.tags.total_refs 14030084 # Total number of references to valid blocks. 996system.cpu.dcache.tags.sampled_refs 1390537 # Sample count of references to valid blocks. 997system.cpu.dcache.tags.avg_refs 10.089688 # Average number of references to valid blocks. 998system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. 999system.cpu.dcache.tags.occ_blocks::cpu.data 511.978881 # Average occupied blocks per requestor 1000system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy 1001system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy 1002system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1003system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 1004system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 1005system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 1006system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1007system.cpu.dcache.tags.tag_accesses 63073026 # Number of tag accesses 1008system.cpu.dcache.tags.data_accesses 63073026 # Number of data accesses 1009system.cpu.dcache.ReadReq_hits::cpu.data 7802461 # number of ReadReq hits 1010system.cpu.dcache.ReadReq_hits::total 7802461 # number of ReadReq hits 1011system.cpu.dcache.WriteReq_hits::cpu.data 5845351 # number of WriteReq hits 1012system.cpu.dcache.WriteReq_hits::total 5845351 # number of WriteReq hits 1013system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits 1014system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits 1015system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits 1016system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits 1017system.cpu.dcache.demand_hits::cpu.data 13647812 # number of demand (read+write) hits 1018system.cpu.dcache.demand_hits::total 13647812 # number of demand (read+write) hits 1019system.cpu.dcache.overall_hits::cpu.data 13647812 # number of overall hits 1020system.cpu.dcache.overall_hits::total 13647812 # number of overall hits 1021system.cpu.dcache.ReadReq_misses::cpu.data 1069134 # number of ReadReq misses 1022system.cpu.dcache.ReadReq_misses::total 1069134 # number of ReadReq misses 1023system.cpu.dcache.WriteReq_misses::cpu.data 304206 # number of WriteReq misses 1024system.cpu.dcache.WriteReq_misses::total 304206 # number of WriteReq misses 1025system.cpu.dcache.LoadLockedReq_misses::cpu.data 17215 # number of LoadLockedReq misses 1026system.cpu.dcache.LoadLockedReq_misses::total 17215 # number of LoadLockedReq misses 1027system.cpu.dcache.demand_misses::cpu.data 1373340 # number of demand (read+write) misses 1028system.cpu.dcache.demand_misses::total 1373340 # number of demand (read+write) misses 1029system.cpu.dcache.overall_misses::cpu.data 1373340 # number of overall misses 1030system.cpu.dcache.overall_misses::total 1373340 # number of overall misses 1031system.cpu.dcache.ReadReq_miss_latency::cpu.data 28994287250 # number of ReadReq miss cycles 1032system.cpu.dcache.ReadReq_miss_latency::total 28994287250 # number of ReadReq miss cycles 1033system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922192632 # number of WriteReq miss cycles 1034system.cpu.dcache.WriteReq_miss_latency::total 10922192632 # number of WriteReq miss cycles 1035system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228270750 # number of LoadLockedReq miss cycles 1036system.cpu.dcache.LoadLockedReq_miss_latency::total 228270750 # number of LoadLockedReq miss cycles 1037system.cpu.dcache.demand_miss_latency::cpu.data 39916479882 # number of demand (read+write) miss cycles 1038system.cpu.dcache.demand_miss_latency::total 39916479882 # number of demand (read+write) miss cycles 1039system.cpu.dcache.overall_miss_latency::cpu.data 39916479882 # number of overall miss cycles 1040system.cpu.dcache.overall_miss_latency::total 39916479882 # number of overall miss cycles 1041system.cpu.dcache.ReadReq_accesses::cpu.data 8871595 # number of ReadReq accesses(hits+misses) 1042system.cpu.dcache.ReadReq_accesses::total 8871595 # number of ReadReq accesses(hits+misses) 1043system.cpu.dcache.WriteReq_accesses::cpu.data 6149557 # number of WriteReq accesses(hits+misses) 1044system.cpu.dcache.WriteReq_accesses::total 6149557 # number of WriteReq accesses(hits+misses) 1045system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses) 1046system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses) 1047system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses) 1048system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses) 1049system.cpu.dcache.demand_accesses::cpu.data 15021152 # number of demand (read+write) accesses 1050system.cpu.dcache.demand_accesses::total 15021152 # number of demand (read+write) accesses 1051system.cpu.dcache.overall_accesses::cpu.data 15021152 # number of overall (read+write) accesses 1052system.cpu.dcache.overall_accesses::total 15021152 # number of overall (read+write) accesses 1053system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120512 # miss rate for ReadReq accesses 1054system.cpu.dcache.ReadReq_miss_rate::total 0.120512 # miss rate for ReadReq accesses 1055system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses 1056system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses 1057system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses 1058system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses 1059system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses 1060system.cpu.dcache.demand_miss_rate::total 0.091427 # miss rate for demand accesses 1061system.cpu.dcache.overall_miss_rate::cpu.data 0.091427 # miss rate for overall accesses 1062system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses 1063system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27119.413703 # average ReadReq miss latency 1064system.cpu.dcache.ReadReq_avg_miss_latency::total 27119.413703 # average ReadReq miss latency 1065system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35903.935596 # average WriteReq miss latency 1066system.cpu.dcache.WriteReq_avg_miss_latency::total 35903.935596 # average WriteReq miss latency 1067system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13259.991287 # average LoadLockedReq miss latency 1068system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13259.991287 # average LoadLockedReq miss latency 1069system.cpu.dcache.demand_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency 1070system.cpu.dcache.demand_avg_miss_latency::total 29065.256879 # average overall miss latency 1071system.cpu.dcache.overall_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency 1072system.cpu.dcache.overall_avg_miss_latency::total 29065.256879 # average overall miss latency 1073system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1074system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1075system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1076system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1077system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1078system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1079system.cpu.dcache.fast_writes 0 # number of fast writes performed 1080system.cpu.dcache.cache_copies 0 # number of cache copies performed 1081system.cpu.dcache.writebacks::writebacks 834448 # number of writebacks 1082system.cpu.dcache.writebacks::total 834448 # number of writebacks 1083system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069134 # number of ReadReq MSHR misses 1084system.cpu.dcache.ReadReq_mshr_misses::total 1069134 # number of ReadReq MSHR misses 1085system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304206 # number of WriteReq MSHR misses 1086system.cpu.dcache.WriteReq_mshr_misses::total 304206 # number of WriteReq MSHR misses 1087system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17215 # number of LoadLockedReq MSHR misses 1088system.cpu.dcache.LoadLockedReq_mshr_misses::total 17215 # number of LoadLockedReq MSHR misses 1089system.cpu.dcache.demand_mshr_misses::cpu.data 1373340 # number of demand (read+write) MSHR misses 1090system.cpu.dcache.demand_mshr_misses::total 1373340 # number of demand (read+write) MSHR misses 1091system.cpu.dcache.overall_mshr_misses::cpu.data 1373340 # number of overall MSHR misses 1092system.cpu.dcache.overall_mshr_misses::total 1373340 # number of overall MSHR misses 1093system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26730348750 # number of ReadReq MSHR miss cycles 1094system.cpu.dcache.ReadReq_mshr_miss_latency::total 26730348750 # number of ReadReq MSHR miss cycles 1095system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10261067368 # number of WriteReq MSHR miss cycles 1096system.cpu.dcache.WriteReq_mshr_miss_latency::total 10261067368 # number of WriteReq MSHR miss cycles 1097system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193828250 # number of LoadLockedReq MSHR miss cycles 1098system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193828250 # number of LoadLockedReq MSHR miss cycles 1099system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36991416118 # number of demand (read+write) MSHR miss cycles 1100system.cpu.dcache.demand_mshr_miss_latency::total 36991416118 # number of demand (read+write) MSHR miss cycles 1101system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36991416118 # number of overall MSHR miss cycles 1102system.cpu.dcache.overall_mshr_miss_latency::total 36991416118 # number of overall MSHR miss cycles 1103system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424273000 # number of ReadReq MSHR uncacheable cycles 1104system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles 1105system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009178000 # number of WriteReq MSHR uncacheable cycles 1106system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009178000 # number of WriteReq MSHR uncacheable cycles 1107system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433451000 # number of overall MSHR uncacheable cycles 1108system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433451000 # number of overall MSHR uncacheable cycles 1109system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120512 # mshr miss rate for ReadReq accesses 1110system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120512 # mshr miss rate for ReadReq accesses 1111system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049468 # mshr miss rate for WriteReq accesses 1112system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049468 # mshr miss rate for WriteReq accesses 1113system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses 1114system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses 1115system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses 1116system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses 1117system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses 1118system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses 1119system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25001.869504 # average ReadReq mshr miss latency 1120system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25001.869504 # average ReadReq mshr miss latency 1121system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33730.654123 # average WriteReq mshr miss latency 1122system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33730.654123 # average WriteReq mshr miss latency 1123system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11259.265176 # average LoadLockedReq mshr miss latency 1124system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11259.265176 # average LoadLockedReq mshr miss latency 1125system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency 1126system.cpu.dcache.demand_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency 1127system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency 1128system.cpu.dcache.overall_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency 1129system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1130system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1131system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1132system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1133system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1134system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1135system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1136system.cpu.toL2Bus.trans_dist::ReadReq 2021774 # Transaction distribution 1137system.cpu.toL2Bus.trans_dist::ReadResp 2021757 # Transaction distribution 1138system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution 1139system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution 1140system.cpu.toL2Bus.trans_dist::Writeback 834448 # Transaction distribution 1141system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41564 # Transaction distribution | 888system.cpu.toL2Bus.trans_dist::ReadReq 2022188 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::ReadResp 2022171 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution 891system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution 892system.cpu.toL2Bus.trans_dist::Writeback 834534 # Transaction distribution 893system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution |
| 1142system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution | 894system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 895system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution |
| 1144system.cpu.toL2Bus.trans_dist::ReadExReq 304189 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::ReadExResp 304189 # Transaction distribution 1146system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856624 # Packet count per connected master and slave (bytes) 1147system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648872 # Packet count per connected master and slave (bytes) 1148system.cpu.toL2Bus.pkt_count::total 5505496 # Packet count per connected master and slave (bytes) 1149system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59411328 # Cumulative packet size per connected master and slave (bytes) 1150system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142453644 # Cumulative packet size per connected master and slave (bytes) 1151system.cpu.toL2Bus.pkt_size::total 201864972 # Cumulative packet size per connected master and slave (bytes) 1152system.cpu.toL2Bus.snoops 41913 # Total snoops (count) 1153system.cpu.toL2Bus.snoop_fanout::samples 3195062 # Request fanout histogram 1154system.cpu.toL2Bus.snoop_fanout::mean 1.013063 # Request fanout histogram 1155system.cpu.toL2Bus.snoop_fanout::stdev 0.113544 # Request fanout histogram | 896system.cpu.toL2Bus.trans_dist::ReadExReq 304196 # Transaction distribution 897system.cpu.toL2Bus.trans_dist::ReadExResp 304196 # Transaction distribution 898system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857238 # Packet count per connected master and slave (bytes) 899system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649188 # Packet count per connected master and slave (bytes) 900system.cpu.toL2Bus.pkt_count::total 5506426 # Packet count per connected master and slave (bytes) 901system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59430976 # Cumulative packet size per connected master and slave (bytes) 902system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142466452 # Cumulative packet size per connected master and slave (bytes) 903system.cpu.toL2Bus.pkt_size::total 201897428 # Cumulative packet size per connected master and slave (bytes) 904system.cpu.toL2Bus.snoops 41901 # Total snoops (count) 905system.cpu.toL2Bus.snoop_fanout::samples 3195557 # Request fanout histogram 906system.cpu.toL2Bus.snoop_fanout::mean 1.013057 # Request fanout histogram 907system.cpu.toL2Bus.snoop_fanout::stdev 0.113520 # Request fanout histogram |
| 1156system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 908system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1158system.cpu.toL2Bus.snoop_fanout::1 3153325 98.69% 98.69% # Request fanout histogram 1159system.cpu.toL2Bus.snoop_fanout::2 41737 1.31% 100.00% # Request fanout histogram | 910system.cpu.toL2Bus.snoop_fanout::1 3153832 98.69% 98.69% # Request fanout histogram 911system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram |
| 1160system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1162system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 912system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 913system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 914system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1163system.cpu.toL2Bus.snoop_fanout::total 3195062 # Request fanout histogram 1164system.cpu.toL2Bus.reqLayer0.occupancy 2424224500 # Layer occupancy (ticks) | 915system.cpu.toL2Bus.snoop_fanout::total 3195557 # Request fanout histogram 916system.cpu.toL2Bus.reqLayer0.occupancy 2424565000 # Layer occupancy (ticks) |
| 1165system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1166system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 1167system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 917system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 918system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) 919system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1168system.cpu.toL2Bus.respLayer0.occupancy 1395050000 # Layer occupancy (ticks) | 920system.cpu.toL2Bus.respLayer0.occupancy 1395517500 # Layer occupancy (ticks) |
| 1169system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 921system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1170system.cpu.toL2Bus.respLayer1.occupancy 2186768132 # Layer occupancy (ticks) | 922system.cpu.toL2Bus.respLayer1.occupancy 2186897880 # Layer occupancy (ticks) |
| 1171system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 923system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 924system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 925system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 926system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 927system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 928system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 929system.disk0.dma_write_txs 395 # Number of DMA write transactions. 930system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 931system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 932system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 933system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 934system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 935system.disk2.dma_write_txs 1 # Number of DMA write transactions. 936system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 937system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 938system.iobus.trans_dist::WriteReq 51202 # Transaction distribution 939system.iobus.trans_dist::WriteResp 9650 # Transaction distribution 940system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 941system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) 942system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 943system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 944system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 945system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 946system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 947system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 948system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 949system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 950system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 951system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 952system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 953system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) 954system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 955system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 956system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) 957system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) 958system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 959system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 960system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 961system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 962system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 963system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 964system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 965system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 966system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 967system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 968system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 969system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) 970system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 971system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 972system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) 973system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) 974system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 975system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 976system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 977system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 978system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 979system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 980system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 981system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 982system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 983system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 984system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 985system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 986system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 987system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 988system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 989system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 990system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 991system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 992system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 993system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 994system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 995system.iobus.reqLayer29.occupancy 406189794 # Layer occupancy (ticks) 996system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 997system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 998system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 999system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) 1000system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1001system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) 1002system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1003system.iocache.tags.replacements 41685 # number of replacements 1004system.iocache.tags.tagsinuse 1.352352 # Cycle average of tags in use 1005system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1006system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1007system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1008system.iocache.tags.warmup_cycle 1753525032000 # Cycle when the warmup percentage was hit. 1009system.iocache.tags.occ_blocks::tsunami.ide 1.352352 # Average occupied blocks per requestor 1010system.iocache.tags.occ_percent::tsunami.ide 0.084522 # Average percentage of cache occupancy 1011system.iocache.tags.occ_percent::total 0.084522 # Average percentage of cache occupancy 1012system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1013system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1014system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1015system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1016system.iocache.tags.data_accesses 375525 # Number of data accesses 1017system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1018system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1019system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 1020system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 1021system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 1022system.iocache.demand_misses::total 173 # number of demand (read+write) misses 1023system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 1024system.iocache.overall_misses::total 173 # number of overall misses 1025system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 1026system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 1027system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634918911 # number of WriteInvalidateReq miss cycles 1028system.iocache.WriteInvalidateReq_miss_latency::total 13634918911 # number of WriteInvalidateReq miss cycles 1029system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 1030system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 1031system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 1032system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles 1033system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 1034system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 1035system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1036system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 1037system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 1038system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 1039system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 1040system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses 1041system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1042system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1043system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1044system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1045system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1046system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1047system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1048system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1049system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 1050system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 1051system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328141.098166 # average WriteInvalidateReq miss latency 1052system.iocache.WriteInvalidateReq_avg_miss_latency::total 328141.098166 # average WriteInvalidateReq miss latency 1053system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 1054system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency 1055system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 1056system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency 1057system.iocache.blocked_cycles::no_mshrs 206323 # number of cycles access was blocked 1058system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1059system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked 1060system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1061system.iocache.avg_blocked_cycles::no_mshrs 8.756971 # average number of cycles each access was blocked 1062system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1063system.iocache.fast_writes 0 # number of fast writes performed 1064system.iocache.cache_copies 0 # number of cache copies performed 1065system.iocache.writebacks::writebacks 41512 # number of writebacks 1066system.iocache.writebacks::total 41512 # number of writebacks 1067system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 1068system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 1069system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1070system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 1071system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 1072system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 1073system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 1074system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 1075system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 1076system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 1077system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474214911 # number of WriteInvalidateReq MSHR miss cycles 1078system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474214911 # number of WriteInvalidateReq MSHR miss cycles 1079system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 1080system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 1081system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 1082system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles 1083system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1084system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1085system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1086system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1087system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1088system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1089system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1090system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1091system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 1092system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency 1093system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276141.098166 # average WriteInvalidateReq mshr miss latency 1094system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276141.098166 # average WriteInvalidateReq mshr miss latency 1095system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 1096system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 1097system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 1098system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 1099system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1100system.membus.trans_dist::ReadReq 292355 # Transaction distribution 1101system.membus.trans_dist::ReadResp 292355 # Transaction distribution 1102system.membus.trans_dist::WriteReq 9650 # Transaction distribution 1103system.membus.trans_dist::WriteResp 9650 # Transaction distribution 1104system.membus.trans_dist::Writeback 115689 # Transaction distribution 1105system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1106system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 1107system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 1108system.membus.trans_dist::UpgradeResp 132 # Transaction distribution 1109system.membus.trans_dist::ReadExReq 116723 # Transaction distribution 1110system.membus.trans_dist::ReadExResp 116723 # Transaction distribution 1111system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) 1112system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878118 # Packet count per connected master and slave (bytes) 1113system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911278 # Packet count per connected master and slave (bytes) 1114system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) 1115system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) 1116system.membus.pkt_count::total 1036082 # Packet count per connected master and slave (bytes) 1117system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) 1118system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456384 # Cumulative packet size per connected master and slave (bytes) 1119system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30500948 # Cumulative packet size per connected master and slave (bytes) 1120system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) 1121system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) 1122system.membus.pkt_size::total 35818004 # Cumulative packet size per connected master and slave (bytes) 1123system.membus.snoops 431 # Total snoops (count) 1124system.membus.snoop_fanout::samples 559521 # Request fanout histogram 1125system.membus.snoop_fanout::mean 1 # Request fanout histogram 1126system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1127system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1128system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1129system.membus.snoop_fanout::1 559521 100.00% 100.00% # Request fanout histogram 1130system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1131system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1132system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1133system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1134system.membus.snoop_fanout::total 559521 # Request fanout histogram 1135system.membus.reqLayer0.occupancy 30373000 # Layer occupancy (ticks) 1136system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1137system.membus.reqLayer1.occupancy 1824623000 # Layer occupancy (ticks) 1138system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1139system.membus.respLayer1.occupancy 3751921620 # Layer occupancy (ticks) 1140system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1141system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) 1142system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1143system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1144system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1145system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1146system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1147system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1148system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1149system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1150system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1151system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1152system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1153system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1154system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1155system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1156system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1157system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1158system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1159system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1160system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1161system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1162system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1163system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1164system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1165system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1166system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1167system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1168system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1169system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1170system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1171system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1172system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1173system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
|
| 1172 1173---------- End Simulation Statistics ---------- | 1174 1175---------- End Simulation Statistics ---------- |