| stats.txt (10433:821cbe4a183b) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.919439 # Number of seconds simulated 4sim_ticks 1919439025000 # Number of ticks simulated 5final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.919439 # Number of seconds simulated 4sim_ticks 1919439025000 # Number of ticks simulated 5final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 960719 # Simulator instruction rate (inst/s) 8host_op_rate 960718 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32869301826 # Simulator tick rate (ticks/s) 10host_mem_usage 317196 # Number of bytes of host memory used 11host_seconds 58.40 # Real time elapsed on the host | 7host_inst_rate 1406989 # Simulator instruction rate (inst/s) 8host_op_rate 1406988 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 48137648137 # Simulator tick rate (ticks/s) 10host_mem_usage 309300 # Number of bytes of host memory used 11host_seconds 39.87 # Real time elapsed on the host |
| 12sim_insts 56102180 # Number of instructions simulated 13sim_ops 56102180 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory --- 387 unchanged lines hidden (view full) --- 407system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 408system.iocache.blocked::no_targets 0 # number of cycles access was blocked 409system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 410system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 411system.iocache.fast_writes 41552 # number of fast writes performed 412system.iocache.cache_copies 0 # number of cache copies performed 413system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 414system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses | 12sim_insts 56102180 # Number of instructions simulated 13sim_ops 56102180 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory --- 387 unchanged lines hidden (view full) --- 407system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 408system.iocache.blocked::no_targets 0 # number of cycles access was blocked 409system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 410system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 411system.iocache.fast_writes 41552 # number of fast writes performed 412system.iocache.cache_copies 0 # number of cache copies performed 413system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 414system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses |
| 415system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 416system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses | |
| 417system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 418system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 419system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 420system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 421system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles 422system.iocache.ReadReq_mshr_miss_latency::total 15526633 # number of ReadReq MSHR miss cycles 423system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512178304 # number of WriteInvalidateReq MSHR miss cycles 424system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512178304 # number of WriteInvalidateReq MSHR miss cycles 425system.iocache.demand_mshr_miss_latency::tsunami.ide 15526633 # number of demand (read+write) MSHR miss cycles 426system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles 427system.iocache.overall_mshr_miss_latency::tsunami.ide 15526633 # number of overall MSHR miss cycles 428system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles 429system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 430system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 415system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 416system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 417system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 418system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 419system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles 420system.iocache.ReadReq_mshr_miss_latency::total 15526633 # number of ReadReq MSHR miss cycles 421system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512178304 # number of WriteInvalidateReq MSHR miss cycles 422system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512178304 # number of WriteInvalidateReq MSHR miss cycles 423system.iocache.demand_mshr_miss_latency::tsunami.ide 15526633 # number of demand (read+write) MSHR miss cycles 424system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles 425system.iocache.overall_mshr_miss_latency::tsunami.ide 15526633 # number of overall MSHR miss cycles 426system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles 427system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 428system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 431system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999904 # mshr miss rate for WriteInvalidateReq accesses 432system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999904 # mshr miss rate for WriteInvalidateReq accesses | |
| 433system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 434system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 435system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 436system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 437system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency 438system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency | 429system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 431system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 433system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency 434system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency |
| 439system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60458.661533 # average WriteInvalidateReq mshr miss latency 440system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60458.661533 # average WriteInvalidateReq mshr miss latency | 435system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency 436system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 441system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency 442system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency 443system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency 444system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency 445system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 446system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 447system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 448system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 729 unchanged lines hidden --- | 437system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency 438system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency 439system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency 440system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency 441system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 443system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 444system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 729 unchanged lines hidden --- |