| stats.txt (10220:9eab5efc02e8) | stats.txt (10352:5f1f92bf76ee) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.919447 # Number of seconds simulated 4sim_ticks 1919446558000 # Number of ticks simulated 5final_tick 1919446558000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.919439 # Number of seconds simulated 4sim_ticks 1919438772000 # Number of ticks simulated 5final_tick 1919438772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 885398 # Simulator instruction rate (inst/s) 8host_op_rate 885398 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 30291378157 # Simulator tick rate (ticks/s) 10host_mem_usage 344696 # Number of bytes of host memory used 11host_seconds 63.37 # Real time elapsed on the host 12sim_insts 56104177 # Number of instructions simulated 13sim_ops 56104177 # Number of ops (including micro ops) simulated | 7host_inst_rate 1398299 # Simulator instruction rate (inst/s) 8host_op_rate 1398299 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47840414078 # Simulator tick rate (ticks/s) 10host_mem_usage 314348 # Number of bytes of host memory used 11host_seconds 40.12 # Real time elapsed on the host 12sim_insts 56102112 # Number of instructions simulated 13sim_ops 56102112 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24858240 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7404032 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7404032 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388410 # Number of read requests responded to by this memory 26system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115688 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115688 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 443228 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 12950733 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 1381832 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 14775792 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 443228 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 443228 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 3857379 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 3857379 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 3857379 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 443228 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 12950733 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 1381832 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 18633171 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 443146 # Number of read requests accepted 44system.physmem.writeReqs 115688 # Number of write requests accepted 45system.physmem.readBursts 443146 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 115688 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 28353856 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7402304 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 28361344 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7404032 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24875968 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 25727744 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4747712 # Number of bytes written to this memory 23system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7407040 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 388687 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 401996 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 74183 # Number of write requests responded to by this memory 30system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 115735 # Number of write requests responded to by this memory 32system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.data 12960022 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::total 13403785 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s) 38system.physmem.bw_write::writebacks 2473490 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_write::tsunami.ide 1385472 # Write bandwidth from this memory (bytes/s) 40system.physmem.bw_write::total 3858961 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_total::writebacks 2473490 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 12960022 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::total 17262746 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.readReqs 401996 # Number of read requests accepted 47system.physmem.writeReqs 115735 # Number of write requests accepted 48system.physmem.readBursts 401996 # Number of DRAM read bursts, including those serviced by the write queue 49system.physmem.writeBursts 115735 # Number of DRAM write bursts, including those merged in the write queue 50system.physmem.bytesReadDRAM 25716224 # Total number of bytes read from DRAM 51system.physmem.bytesReadWrQ 11520 # Total number of bytes read from write queue 52system.physmem.bytesWritten 7405312 # Total number of bytes written to DRAM 53system.physmem.bytesReadSys 25727744 # Total read bytes from the system interface side 54system.physmem.bytesWrittenSys 7407040 # Total written bytes from the system interface side 55system.physmem.servicedByWrQ 180 # Number of DRAM read bursts serviced by the write queue |
| 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 56system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 54system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 27768 # Per bank write bursts 56system.physmem.perBankRdBursts::1 28019 # Per bank write bursts 57system.physmem.perBankRdBursts::2 28336 # Per bank write bursts 58system.physmem.perBankRdBursts::3 28020 # Per bank write bursts 59system.physmem.perBankRdBursts::4 27518 # Per bank write bursts 60system.physmem.perBankRdBursts::5 27546 # Per bank write bursts 61system.physmem.perBankRdBursts::6 26737 # Per bank write bursts 62system.physmem.perBankRdBursts::7 26852 # Per bank write bursts 63system.physmem.perBankRdBursts::8 27860 # Per bank write bursts 64system.physmem.perBankRdBursts::9 27104 # Per bank write bursts 65system.physmem.perBankRdBursts::10 27841 # Per bank write bursts 66system.physmem.perBankRdBursts::11 27413 # Per bank write bursts 67system.physmem.perBankRdBursts::12 27378 # Per bank write bursts 68system.physmem.perBankRdBursts::13 28201 # Per bank write bursts 69system.physmem.perBankRdBursts::14 28236 # Per bank write bursts 70system.physmem.perBankRdBursts::15 28200 # Per bank write bursts | 57system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write 58system.physmem.perBankRdBursts::0 25161 # Per bank write bursts 59system.physmem.perBankRdBursts::1 25541 # Per bank write bursts 60system.physmem.perBankRdBursts::2 25618 # Per bank write bursts 61system.physmem.perBankRdBursts::3 25537 # Per bank write bursts 62system.physmem.perBankRdBursts::4 24981 # Per bank write bursts 63system.physmem.perBankRdBursts::5 24976 # Per bank write bursts 64system.physmem.perBankRdBursts::6 24228 # Per bank write bursts 65system.physmem.perBankRdBursts::7 24506 # Per bank write bursts 66system.physmem.perBankRdBursts::8 25159 # Per bank write bursts 67system.physmem.perBankRdBursts::9 24820 # Per bank write bursts 68system.physmem.perBankRdBursts::10 25363 # Per bank write bursts 69system.physmem.perBankRdBursts::11 24840 # Per bank write bursts 70system.physmem.perBankRdBursts::12 24420 # Per bank write bursts 71system.physmem.perBankRdBursts::13 25388 # Per bank write bursts 72system.physmem.perBankRdBursts::14 25795 # Per bank write bursts 73system.physmem.perBankRdBursts::15 25483 # Per bank write bursts |
| 71system.physmem.perBankWrBursts::0 7550 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7529 # Per bank write bursts | 74system.physmem.perBankWrBursts::0 7550 # Per bank write bursts 75system.physmem.perBankWrBursts::1 7529 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::2 7869 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7540 # Per bank write bursts | 76system.physmem.perBankWrBursts::2 7880 # Per bank write bursts 77system.physmem.perBankWrBursts::3 7553 # Per bank write bursts |
| 75system.physmem.perBankWrBursts::4 7115 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6983 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6321 # Per bank write bursts | 78system.physmem.perBankWrBursts::4 7115 # Per bank write bursts 79system.physmem.perBankWrBursts::5 6983 # Per bank write bursts 80system.physmem.perBankWrBursts::6 6321 # Per bank write bursts |
| 78system.physmem.perBankWrBursts::7 6313 # Per bank write bursts | 81system.physmem.perBankWrBursts::7 6319 # Per bank write bursts |
| 79system.physmem.perBankWrBursts::8 7293 # Per bank write bursts | 82system.physmem.perBankWrBursts::8 7293 # Per bank write bursts |
| 80system.physmem.perBankWrBursts::9 6538 # Per bank write bursts | 83system.physmem.perBankWrBursts::9 6554 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::10 7205 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6861 # Per bank write bursts 83system.physmem.perBankWrBursts::12 6964 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7821 # Per bank write bursts | 84system.physmem.perBankWrBursts::10 7205 # Per bank write bursts 85system.physmem.perBankWrBursts::11 6861 # Per bank write bursts 86system.physmem.perBankWrBursts::12 6964 # Per bank write bursts 87system.physmem.perBankWrBursts::13 7821 # Per bank write bursts |
| 85system.physmem.perBankWrBursts::14 7979 # Per bank write bursts | 88system.physmem.perBankWrBursts::14 7980 # Per bank write bursts |
| 86system.physmem.perBankWrBursts::15 7780 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 11 # Number of times write queue was full causing retry | 89system.physmem.perBankWrBursts::15 7780 # Per bank write bursts 90system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 91system.physmem.numWrRetry 11 # Number of times write queue was full causing retry |
| 89system.physmem.totGap 1919434637000 # Total gap between requests | 92system.physmem.totGap 1919426851000 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 93system.physmem.readPktSize::0 0 # Read request sizes (log2) 94system.physmem.readPktSize::1 0 # Read request sizes (log2) 95system.physmem.readPktSize::2 0 # Read request sizes (log2) 96system.physmem.readPktSize::3 0 # Read request sizes (log2) 97system.physmem.readPktSize::4 0 # Read request sizes (log2) 98system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 443146 # Read request sizes (log2) | 99system.physmem.readPktSize::6 401996 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 100system.physmem.writePktSize::0 0 # Write request sizes (log2) 101system.physmem.writePktSize::1 0 # Write request sizes (log2) 102system.physmem.writePktSize::2 0 # Write request sizes (log2) 103system.physmem.writePktSize::3 0 # Write request sizes (log2) 104system.physmem.writePktSize::4 0 # Write request sizes (log2) 105system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 115688 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 401962 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 1642 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 2685 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 1248 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1966 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 3974 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 2507 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 2187 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 2134 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2102 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1622 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1616 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1907 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 1876 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 2136 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 1224 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 966 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 883 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see | 106system.physmem.writePktSize::6 115735 # Write request sizes (log2) 107system.physmem.rdQLenPdf::0 401802 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see |
| 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 128system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 146system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1478 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 4562 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 4579 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 4593 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4592 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 4608 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4699 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4858 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4946 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 5128 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5326 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 5448 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 5540 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 5685 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 5621 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5715 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 897 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 915 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 934 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 861 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 945 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1033 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 949 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1139 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1162 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1146 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1232 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 1390 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 1625 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 1897 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 2098 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 1909 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 1878 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 1683 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 1684 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 1800 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 1629 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 867 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 418 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 235 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 155 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 538.261302 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 328.855989 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 417.099114 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 14887 22.41% 22.41% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 11472 17.27% 39.68% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4684 7.05% 46.73% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3132 4.71% 51.45% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 3072 4.62% 56.07% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1874 2.82% 58.89% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1342 2.02% 60.91% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1444 2.17% 63.09% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 24522 36.91% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 6775 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 65.389077 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 16.529238 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2564.130292 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 6772 99.96% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 6775 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 6775 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 17.071734 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 16.848509 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 3.695111 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16 5062 74.72% 74.72% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::17 127 1.87% 76.59% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::18 1207 17.82% 94.41% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::19 25 0.37% 94.77% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::20 12 0.18% 94.95% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::21 16 0.24% 95.19% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::22 18 0.27% 95.45% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::23 98 1.45% 96.90% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::25 41 0.61% 97.83% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::26 20 0.30% 98.13% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::27 8 0.12% 98.24% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28 7 0.10% 98.35% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::29 8 0.12% 98.46% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::30 7 0.10% 98.57% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::31 15 0.22% 98.79% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::32 9 0.13% 98.92% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::33 1 0.01% 98.94% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::34 1 0.01% 98.95% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::35 1 0.01% 98.97% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::37 1 0.01% 98.98% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::38 1 0.01% 99.00% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::39 4 0.06% 99.06% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::40 9 0.13% 99.19% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::41 8 0.12% 99.31% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::42 2 0.03% 99.34% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::43 2 0.03% 99.37% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::44 2 0.03% 99.39% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::45 1 0.01% 99.41% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::47 8 0.12% 99.54% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::48 7 0.10% 99.65% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::49 1 0.01% 99.66% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::50 2 0.03% 99.69% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::51 2 0.03% 99.72% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::52 1 0.01% 99.73% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::54 1 0.01% 99.75% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::56 7 0.10% 99.85% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::57 9 0.13% 99.99% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::59 1 0.01% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 6775 # Writes before turning the bus around for reads 268system.physmem.totQLat 7315796250 # Total ticks spent queuing 269system.physmem.totMemAccLat 15622590000 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 2215145000 # Total ticks spent in databus transfers 271system.physmem.avgQLat 16513.13 # Average queueing delay per DRAM burst | 154system.physmem.wrQLenPdf::15 1859 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 2606 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 5607 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 5735 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 5978 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6706 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 6976 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 8149 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::23 8460 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 8432 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 8109 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 8281 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 6824 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 6355 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 5592 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::30 5334 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::31 5330 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::32 5306 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::33 213 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::35 175 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::40 128 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::46 205 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::49 146 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::51 111 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::52 104 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::59 70 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see 203system.physmem.bytesPerActivate::samples 63869 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::mean 518.585480 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::gmean 313.979775 # Bytes accessed per row activation 206system.physmem.bytesPerActivate::stdev 413.923527 # Bytes accessed per row activation 207system.physmem.bytesPerActivate::0-127 14875 23.29% 23.29% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::128-255 11515 18.03% 41.32% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::256-383 4721 7.39% 48.71% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::384-511 3142 4.92% 53.63% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::512-639 3018 4.73% 58.36% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::640-767 1863 2.92% 61.27% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::768-895 1301 2.04% 63.31% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::896-1023 1404 2.20% 65.51% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::1024-1151 22030 34.49% 100.00% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::total 63869 # Bytes accessed per row activation 217system.physmem.rdPerTurnAround::samples 5101 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::mean 78.768477 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::stdev 2955.016496 # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::0-8191 5098 99.94% 99.94% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::total 5101 # Reads before turning the bus around for writes 225system.physmem.wrPerTurnAround::samples 5101 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::mean 22.683395 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::gmean 19.235797 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::stdev 21.276820 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::16-19 4452 87.28% 87.28% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20-23 22 0.43% 87.71% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::24-27 15 0.29% 88.00% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::28-31 224 4.39% 92.39% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::32-35 41 0.80% 93.20% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::36-39 6 0.12% 93.32% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::40-43 9 0.18% 93.49% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::44-47 7 0.14% 93.63% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::48-51 19 0.37% 94.00% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::52-55 2 0.04% 94.04% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::56-59 4 0.08% 94.12% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::60-63 2 0.04% 94.16% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::64-67 11 0.22% 94.37% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::68-71 3 0.06% 94.43% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-75 7 0.14% 94.57% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-83 30 0.59% 95.16% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::84-87 13 0.25% 95.41% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::88-91 3 0.06% 95.47% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::92-95 1 0.02% 95.49% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::96-99 166 3.25% 98.75% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::100-103 10 0.20% 98.94% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::112-115 2 0.04% 98.98% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::120-123 6 0.12% 99.10% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::128-131 4 0.08% 99.18% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::132-135 2 0.04% 99.22% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::136-139 6 0.12% 99.33% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::140-143 9 0.18% 99.51% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::144-147 9 0.18% 99.69% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::148-151 1 0.02% 99.71% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::152-155 3 0.06% 99.76% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::156-159 2 0.04% 99.80% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::160-163 3 0.06% 99.86% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::164-167 1 0.02% 99.88% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::168-171 1 0.02% 99.90% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::220-223 1 0.02% 99.92% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::224-227 4 0.08% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::total 5101 # Writes before turning the bus around for reads 266system.physmem.totQLat 2117396500 # Total ticks spent queuing 267system.physmem.totMemAccLat 9651446500 # Total ticks spent from burst creation until serviced by the DRAM 268system.physmem.totBusLat 2009080000 # Total ticks spent in databus transfers 269system.physmem.avgQLat 5269.57 # Average queueing delay per DRAM burst |
| 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 270system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 273system.physmem.avgMemAccLat 35263.13 # Average memory access latency per DRAM burst 274system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s | 271system.physmem.avgMemAccLat 24019.57 # Average memory access latency per DRAM burst 272system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s |
| 275system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s | 273system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s |
| 276system.physmem.avgRdBWSys 14.78 # Average system read bandwidth in MiByte/s | 274system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s |
| 277system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 275system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s 276system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 279system.physmem.busUtil 0.15 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads | 277system.physmem.busUtil 0.13 # Data bus utilization in percentage 278system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads |
| 281system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 279system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 282system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 283system.physmem.avgWrQLen 23.40 # Average write queue length when enqueuing 284system.physmem.readRowHits 398273 # Number of row buffer hits during reads 285system.physmem.writeRowHits 93988 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 81.24 # Row buffer hit rate for writes 288system.physmem.avgGap 3434713.42 # Average gap between requests 289system.physmem.pageHitRate 88.11 # Row buffer hit rate, read and write combined 290system.physmem.memoryStateTime::IDLE 1800016178000 # Time in different power states 291system.physmem.memoryStateTime::REF 64094420000 # Time in different power states | 280system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 281system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing 282system.physmem.readRowHits 360116 # Number of row buffer hits during reads 283system.physmem.writeRowHits 93539 # Number of row buffer hits during writes 284system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads 285system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes 286system.physmem.avgGap 3707382.50 # Average gap between requests 287system.physmem.pageHitRate 87.65 # Row buffer hit rate, read and write combined 288system.physmem.memoryStateTime::IDLE 1800046548500 # Time in different power states 289system.physmem.memoryStateTime::REF 64094160000 # Time in different power states |
| 292system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 290system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 293system.physmem.memoryStateTime::ACT 55332653250 # Time in different power states | 291system.physmem.memoryStateTime::ACT 55294756500 # Time in different power states |
| 294system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 292system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 295system.membus.throughput 18674823 # Throughput (bytes/s) 296system.membus.trans_dist::ReadReq 292356 # Transaction distribution 297system.membus.trans_dist::ReadResp 292356 # Transaction distribution | 293system.membus.throughput 17291227 # Throughput (bytes/s) 294system.membus.trans_dist::ReadReq 292357 # Transaction distribution 295system.membus.trans_dist::ReadResp 292357 # Transaction distribution |
| 298system.membus.trans_dist::WriteReq 9649 # Transaction distribution 299system.membus.trans_dist::WriteResp 9649 # Transaction distribution | 296system.membus.trans_dist::WriteReq 9649 # Transaction distribution 297system.membus.trans_dist::WriteResp 9649 # Transaction distribution |
| 300system.membus.trans_dist::Writeback 115688 # Transaction distribution | 298system.membus.trans_dist::Writeback 74183 # Transaction distribution 299system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 300system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution |
| 301system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 302system.membus.trans_dist::UpgradeResp 132 # Transaction distribution | 301system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 302system.membus.trans_dist::UpgradeResp 132 # Transaction distribution |
| 303system.membus.trans_dist::ReadExReq 158273 # Transaction distribution 304system.membus.trans_dist::ReadExResp 158273 # Transaction distribution | 303system.membus.trans_dist::ReadExReq 116727 # Transaction distribution 304system.membus.trans_dist::ReadExResp 116727 # Transaction distribution |
| 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) | 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) |
| 306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878115 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911273 # Packet count per connected master and slave (bytes) 308system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) 310system.membus.pkt_count::total 1035953 # Packet count per connected master and slave (bytes) | 306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878409 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911567 # Packet count per connected master and slave (bytes) 308system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) 310system.membus.pkt_count::total 994859 # Packet count per connected master and slave (bytes) |
| 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) | 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) |
| 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456256 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30500812 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) 315system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) 316system.membus.tot_pkt_size::total 35809932 # Cumulative packet size per connected master and slave (bytes) 317system.membus.data_through_bus 35809932 # Total data (bytes) 318system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) 319system.membus.reqLayer0.occupancy 32376000 # Layer occupancy (ticks) | 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474496 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30519052 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 315system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 316system.membus.tot_pkt_size::total 33179340 # Cumulative packet size per connected master and slave (bytes) 317system.membus.data_through_bus 33179340 # Total data (bytes) 318system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) 319system.membus.reqLayer0.occupancy 32375500 # Layer occupancy (ticks) |
| 320system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 320system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 321system.membus.reqLayer1.occupancy 1491996000 # Layer occupancy (ticks) | 321system.membus.reqLayer1.occupancy 1450892000 # Layer occupancy (ticks) |
| 322system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 322system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 323system.membus.respLayer1.occupancy 3751677600 # Layer occupancy (ticks) | 323system.membus.respLayer1.occupancy 3751806368 # Layer occupancy (ticks) |
| 324system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 324system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 325system.membus.respLayer2.occupancy 376660500 # Layer occupancy (ticks) | 325system.membus.respLayer2.occupancy 43113000 # Layer occupancy (ticks) |
| 326system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 327system.iocache.tags.replacements 41685 # number of replacements | 326system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 327system.iocache.tags.replacements 41685 # number of replacements |
| 328system.iocache.tags.tagsinuse 1.344872 # Cycle average of tags in use | 328system.iocache.tags.tagsinuse 1.344805 # Cycle average of tags in use |
| 329system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 330system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 331system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 329system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 330system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 331system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 332system.iocache.tags.warmup_cycle 1753525004000 # Cycle when the warmup percentage was hit. 333system.iocache.tags.occ_blocks::tsunami.ide 1.344872 # Average occupied blocks per requestor 334system.iocache.tags.occ_percent::tsunami.ide 0.084054 # Average percentage of cache occupancy 335system.iocache.tags.occ_percent::total 0.084054 # Average percentage of cache occupancy | 332system.iocache.tags.warmup_cycle 1753524887000 # Cycle when the warmup percentage was hit. 333system.iocache.tags.occ_blocks::tsunami.ide 1.344805 # Average occupied blocks per requestor 334system.iocache.tags.occ_percent::tsunami.ide 0.084050 # Average percentage of cache occupancy 335system.iocache.tags.occ_percent::total 0.084050 # Average percentage of cache occupancy |
| 336system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 337system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 338system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 339system.iocache.tags.tag_accesses 375525 # Number of tag accesses 340system.iocache.tags.data_accesses 375525 # Number of data accesses | 336system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 337system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 338system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 339system.iocache.tags.tag_accesses 375525 # Number of tag accesses 340system.iocache.tags.data_accesses 375525 # Number of data accesses |
| 341system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 342system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits |
|
| 341system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 342system.iocache.ReadReq_misses::total 173 # number of ReadReq misses | 343system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 344system.iocache.ReadReq_misses::total 173 # number of ReadReq misses |
| 343system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 344system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 345system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 346system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 347system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 348system.iocache.overall_misses::total 41725 # number of overall misses 349system.iocache.ReadReq_miss_latency::tsunami.ide 21253133 # number of ReadReq miss cycles 350system.iocache.ReadReq_miss_latency::total 21253133 # number of ReadReq miss cycles 351system.iocache.WriteReq_miss_latency::tsunami.ide 12447285431 # number of WriteReq miss cycles 352system.iocache.WriteReq_miss_latency::total 12447285431 # number of WriteReq miss cycles 353system.iocache.demand_miss_latency::tsunami.ide 12468538564 # number of demand (read+write) miss cycles 354system.iocache.demand_miss_latency::total 12468538564 # number of demand (read+write) miss cycles 355system.iocache.overall_miss_latency::tsunami.ide 12468538564 # number of overall miss cycles 356system.iocache.overall_miss_latency::total 12468538564 # number of overall miss cycles | 345system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses 346system.iocache.demand_misses::total 173 # number of demand (read+write) misses 347system.iocache.overall_misses::tsunami.ide 173 # number of overall misses 348system.iocache.overall_misses::total 173 # number of overall misses 349system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles 350system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles 351system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles 352system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles 353system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles 354system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles |
| 357system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 358system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) | 355system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 356system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) |
| 359system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 360system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 361system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 362system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 363system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 364system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses | 357system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 358system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 359system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses 360system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses 361system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses 362system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses |
| 365system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 366system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 363system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 364system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 367system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 368system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses | |
| 369system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 370system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 371system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 372system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 365system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 366system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 367system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 368system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 373system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122850.479769 # average ReadReq miss latency 374system.iocache.ReadReq_avg_miss_latency::total 122850.479769 # average ReadReq miss latency 375system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299559.237365 # average WriteReq miss latency 376system.iocache.WriteReq_avg_miss_latency::total 299559.237365 # average WriteReq miss latency 377system.iocache.demand_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency 378system.iocache.demand_avg_miss_latency::total 298826.568340 # average overall miss latency 379system.iocache.overall_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency 380system.iocache.overall_avg_miss_latency::total 298826.568340 # average overall miss latency 381system.iocache.blocked_cycles::no_mshrs 365803 # number of cycles access was blocked | 369system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency 370system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency 371system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 372system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency 373system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency 374system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency 375system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 382system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 376system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 383system.iocache.blocked::no_mshrs 28265 # number of cycles access was blocked | 377system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 384system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 378system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 385system.iocache.avg_blocked_cycles::no_mshrs 12.941907 # average number of cycles each access was blocked | 379system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 386system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 380system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 387system.iocache.fast_writes 0 # number of fast writes performed | 381system.iocache.fast_writes 41552 # number of fast writes performed |
| 388system.iocache.cache_copies 0 # number of cache copies performed | 382system.iocache.cache_copies 0 # number of cache copies performed |
| 389system.iocache.writebacks::writebacks 41512 # number of writebacks 390system.iocache.writebacks::total 41512 # number of writebacks | |
| 391system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 392system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses | 383system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 384system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses |
| 393system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 394system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 395system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 396system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 397system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 398system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 399system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12255133 # number of ReadReq MSHR miss cycles 400system.iocache.ReadReq_mshr_miss_latency::total 12255133 # number of ReadReq MSHR miss cycles 401system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10284312431 # number of WriteReq MSHR miss cycles 402system.iocache.WriteReq_mshr_miss_latency::total 10284312431 # number of WriteReq MSHR miss cycles 403system.iocache.demand_mshr_miss_latency::tsunami.ide 10296567564 # number of demand (read+write) MSHR miss cycles 404system.iocache.demand_mshr_miss_latency::total 10296567564 # number of demand (read+write) MSHR miss cycles 405system.iocache.overall_mshr_miss_latency::tsunami.ide 10296567564 # number of overall MSHR miss cycles 406system.iocache.overall_mshr_miss_latency::total 10296567564 # number of overall MSHR miss cycles | 385system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 386system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 387system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses 388system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 389system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses 390system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses 391system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles 392system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles 393system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2506570306 # number of WriteInvalidateReq MSHR miss cycles 394system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2506570306 # number of WriteInvalidateReq MSHR miss cycles 395system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles 396system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles 397system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles 398system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles |
| 407system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 408system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 399system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 400system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 409system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 410system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses | 401system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 402system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses |
| 411system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 412system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 413system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 414system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 403system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 404system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 405system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 406system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 415system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70838.919075 # average ReadReq mshr miss latency 416system.iocache.ReadReq_avg_mshr_miss_latency::total 70838.919075 # average ReadReq mshr miss latency 417system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247504.631089 # average WriteReq mshr miss latency 418system.iocache.WriteReq_avg_mshr_miss_latency::total 247504.631089 # average WriteReq mshr miss latency 419system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency 420system.iocache.demand_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency 421system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency 422system.iocache.overall_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency | 407system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency 408system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency 409system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60323.698161 # average WriteInvalidateReq mshr miss latency 410system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60323.698161 # average WriteInvalidateReq mshr miss latency 411system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 412system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency 413system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency 414system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency |
| 423system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 424system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 425system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 426system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 427system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 428system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 429system.disk0.dma_write_txs 395 # Number of DMA write transactions. 430system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 431system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 432system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 433system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 434system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 435system.disk2.dma_write_txs 1 # Number of DMA write transactions. 436system.cpu_clk_domain.clock 500 # Clock period in ticks 437system.cpu.dtb.fetch_hits 0 # ITB hits 438system.cpu.dtb.fetch_misses 0 # ITB misses 439system.cpu.dtb.fetch_acv 0 # ITB acv 440system.cpu.dtb.fetch_accesses 0 # ITB accesses | 415system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 416system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 417system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 418system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 419system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 420system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 421system.disk0.dma_write_txs 395 # Number of DMA write transactions. 422system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 423system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 424system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 425system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 426system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 427system.disk2.dma_write_txs 1 # Number of DMA write transactions. 428system.cpu_clk_domain.clock 500 # Clock period in ticks 429system.cpu.dtb.fetch_hits 0 # ITB hits 430system.cpu.dtb.fetch_misses 0 # ITB misses 431system.cpu.dtb.fetch_acv 0 # ITB acv 432system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 441system.cpu.dtb.read_hits 9052923 # DTB read hits 442system.cpu.dtb.read_misses 10354 # DTB read misses | 433system.cpu.dtb.read_hits 9052614 # DTB read hits 434system.cpu.dtb.read_misses 10356 # DTB read misses |
| 443system.cpu.dtb.read_acv 210 # DTB read access violations | 435system.cpu.dtb.read_acv 210 # DTB read access violations |
| 444system.cpu.dtb.read_accesses 728911 # DTB read accesses 445system.cpu.dtb.write_hits 6349403 # DTB write hits 446system.cpu.dtb.write_misses 1143 # DTB write misses | 436system.cpu.dtb.read_accesses 728915 # DTB read accesses 437system.cpu.dtb.write_hits 6349217 # DTB write hits 438system.cpu.dtb.write_misses 1144 # DTB write misses |
| 447system.cpu.dtb.write_acv 157 # DTB write access violations | 439system.cpu.dtb.write_acv 157 # DTB write access violations |
| 448system.cpu.dtb.write_accesses 291932 # DTB write accesses 449system.cpu.dtb.data_hits 15402326 # DTB hits 450system.cpu.dtb.data_misses 11497 # DTB misses | 440system.cpu.dtb.write_accesses 291933 # DTB write accesses 441system.cpu.dtb.data_hits 15401831 # DTB hits 442system.cpu.dtb.data_misses 11500 # DTB misses |
| 451system.cpu.dtb.data_acv 367 # DTB access violations | 443system.cpu.dtb.data_acv 367 # DTB access violations |
| 452system.cpu.dtb.data_accesses 1020843 # DTB accesses 453system.cpu.itb.fetch_hits 4974965 # ITB hits | 444system.cpu.dtb.data_accesses 1020848 # DTB accesses 445system.cpu.itb.fetch_hits 4974960 # ITB hits |
| 454system.cpu.itb.fetch_misses 5010 # ITB misses 455system.cpu.itb.fetch_acv 184 # ITB acv | 446system.cpu.itb.fetch_misses 5010 # ITB misses 447system.cpu.itb.fetch_acv 184 # ITB acv |
| 456system.cpu.itb.fetch_accesses 4979975 # ITB accesses | 448system.cpu.itb.fetch_accesses 4979970 # ITB accesses |
| 457system.cpu.itb.read_hits 0 # DTB read hits 458system.cpu.itb.read_misses 0 # DTB read misses 459system.cpu.itb.read_acv 0 # DTB read access violations 460system.cpu.itb.read_accesses 0 # DTB read accesses 461system.cpu.itb.write_hits 0 # DTB write hits 462system.cpu.itb.write_misses 0 # DTB write misses 463system.cpu.itb.write_acv 0 # DTB write access violations 464system.cpu.itb.write_accesses 0 # DTB write accesses 465system.cpu.itb.data_hits 0 # DTB hits 466system.cpu.itb.data_misses 0 # DTB misses 467system.cpu.itb.data_acv 0 # DTB access violations 468system.cpu.itb.data_accesses 0 # DTB accesses | 449system.cpu.itb.read_hits 0 # DTB read hits 450system.cpu.itb.read_misses 0 # DTB read misses 451system.cpu.itb.read_acv 0 # DTB read access violations 452system.cpu.itb.read_accesses 0 # DTB read accesses 453system.cpu.itb.write_hits 0 # DTB write hits 454system.cpu.itb.write_misses 0 # DTB write misses 455system.cpu.itb.write_acv 0 # DTB write access violations 456system.cpu.itb.write_accesses 0 # DTB write accesses 457system.cpu.itb.data_hits 0 # DTB hits 458system.cpu.itb.data_misses 0 # DTB misses 459system.cpu.itb.data_acv 0 # DTB access violations 460system.cpu.itb.data_accesses 0 # DTB accesses |
| 469system.cpu.numCycles 3838893116 # number of cpu cycles simulated | 461system.cpu.numCycles 3838877544 # number of cpu cycles simulated |
| 470system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 471system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 462system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 463system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 472system.cpu.committedInsts 56104177 # Number of instructions committed 473system.cpu.committedOps 56104177 # Number of ops (including micro ops) committed 474system.cpu.num_int_alu_accesses 51979169 # Number of integer alu accesses 475system.cpu.num_fp_alu_accesses 324594 # Number of float alu accesses 476system.cpu.num_func_calls 1481286 # number of times a function call or return occured 477system.cpu.num_conditional_control_insts 6461218 # number of instructions that are conditional controls 478system.cpu.num_int_insts 51979169 # number of integer instructions 479system.cpu.num_fp_insts 324594 # number of float instructions 480system.cpu.num_int_register_reads 71209746 # number of times the integer registers were read 481system.cpu.num_int_register_writes 38460532 # number of times the integer registers were written 482system.cpu.num_fp_register_reads 163708 # number of times the floating registers were read 483system.cpu.num_fp_register_writes 166588 # number of times the floating registers were written 484system.cpu.num_mem_refs 15454993 # number of memory refs 485system.cpu.num_load_insts 9089820 # Number of load instructions 486system.cpu.num_store_insts 6365173 # Number of store instructions 487system.cpu.num_idle_cycles 3587243859.498131 # Number of idle cycles 488system.cpu.num_busy_cycles 251649256.501869 # Number of busy cycles 489system.cpu.not_idle_fraction 0.065553 # Percentage of non-idle cycles 490system.cpu.idle_fraction 0.934447 # Percentage of idle cycles 491system.cpu.Branches 8413035 # Number of branches fetched 492system.cpu.op_class::No_OpClass 3197761 5.70% 5.70% # Class of executed instruction 493system.cpu.op_class::IntAlu 36186344 64.48% 70.18% # Class of executed instruction 494system.cpu.op_class::IntMult 61011 0.11% 70.29% # Class of executed instruction 495system.cpu.op_class::IntDiv 0 0.00% 70.29% # Class of executed instruction 496system.cpu.op_class::FloatAdd 25613 0.05% 70.34% # Class of executed instruction | 464system.cpu.committedInsts 56102112 # Number of instructions committed 465system.cpu.committedOps 56102112 # Number of ops (including micro ops) committed 466system.cpu.num_int_alu_accesses 51977185 # Number of integer alu accesses 467system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 468system.cpu.num_func_calls 1481236 # number of times a function call or return occured 469system.cpu.num_conditional_control_insts 6460933 # number of instructions that are conditional controls 470system.cpu.num_int_insts 51977185 # number of integer instructions 471system.cpu.num_fp_insts 324460 # number of float instructions 472system.cpu.num_int_register_reads 71206533 # number of times the integer registers were read 473system.cpu.num_int_register_writes 38459103 # number of times the integer registers were written 474system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 475system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 476system.cpu.num_mem_refs 15454487 # number of memory refs 477system.cpu.num_load_insts 9089505 # Number of load instructions 478system.cpu.num_store_insts 6364982 # Number of store instructions 479system.cpu.num_idle_cycles 3587234430.998131 # Number of idle cycles 480system.cpu.num_busy_cycles 251643113.001869 # Number of busy cycles 481system.cpu.not_idle_fraction 0.065551 # Percentage of non-idle cycles 482system.cpu.idle_fraction 0.934449 # Percentage of idle cycles 483system.cpu.Branches 8412678 # Number of branches fetched 484system.cpu.op_class::No_OpClass 3197715 5.70% 5.70% # Class of executed instruction 485system.cpu.op_class::IntAlu 36172357 64.46% 70.16% # Class of executed instruction 486system.cpu.op_class::IntMult 61004 0.11% 70.27% # Class of executed instruction 487system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction 488system.cpu.op_class::FloatAdd 38087 0.07% 70.34% # Class of executed instruction |
| 497system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction 498system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction 499system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction 500system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction 501system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction 502system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction 503system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction 504system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction --- 9 unchanged lines hidden (view full) --- 514system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction 515system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction 516system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction 517system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction 518system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction 519system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction 520system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction 521system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction | 489system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction 490system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction 491system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction 492system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction 493system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction 494system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction 495system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction 496system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction --- 9 unchanged lines hidden (view full) --- 506system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction 507system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction 508system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction 509system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction 510system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction 511system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction 512system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction 513system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction |
| 522system.cpu.op_class::MemRead 9316905 16.60% 86.95% # Class of executed instruction 523system.cpu.op_class::MemWrite 6371245 11.35% 98.30% # Class of executed instruction 524system.cpu.op_class::IprAccess 953526 1.70% 100.00% # Class of executed instruction | 514system.cpu.op_class::MemRead 9316582 16.60% 86.95% # Class of executed instruction 515system.cpu.op_class::MemWrite 6371054 11.35% 98.30% # Class of executed instruction 516system.cpu.op_class::IprAccess 953544 1.70% 100.00% # Class of executed instruction |
| 525system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 517system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 526system.cpu.op_class::total 56116041 # Class of executed instruction | 518system.cpu.op_class::total 56113979 # Class of executed instruction |
| 527system.cpu.kern.inst.arm 0 # number of arm instructions executed 528system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed | 519system.cpu.kern.inst.arm 0 # number of arm instructions executed 520system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed |
| 529system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed | 521system.cpu.kern.inst.hwrei 212019 # number of hwrei instructions executed |
| 530system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl 531system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 532system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl | 522system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl 523system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 524system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl |
| 533system.cpu.kern.ipl_count::31 106210 57.99% 100.00% # number of times we switched to this ipl 534system.cpu.kern.ipl_count::total 183167 # number of times we switched to this ipl | 525system.cpu.kern.ipl_count::31 106211 57.99% 100.00% # number of times we switched to this ipl 526system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl |
| 535system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl 536system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 537system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl 538system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl 539system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl | 527system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl 528system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 529system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl 530system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl 531system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl |
| 540system.cpu.kern.ipl_ticks::0 1857252195000 96.76% 96.76% # number of cycles we spent at this ipl 541system.cpu.kern.ipl_ticks::21 91387500 0.00% 96.76% # number of cycles we spent at this ipl 542system.cpu.kern.ipl_ticks::22 737178000 0.04% 96.80% # number of cycles we spent at this ipl 543system.cpu.kern.ipl_ticks::31 61365063500 3.20% 100.00% # number of cycles we spent at this ipl 544system.cpu.kern.ipl_ticks::total 1919445824000 # number of cycles we spent at this ipl | 532system.cpu.kern.ipl_ticks::0 1857248521000 96.76% 96.76% # number of cycles we spent at this ipl 533system.cpu.kern.ipl_ticks::21 91287500 0.00% 96.76% # number of cycles we spent at this ipl 534system.cpu.kern.ipl_ticks::22 737179000 0.04% 96.80% # number of cycles we spent at this ipl 535system.cpu.kern.ipl_ticks::31 61361050500 3.20% 100.00% # number of cycles we spent at this ipl 536system.cpu.kern.ipl_ticks::total 1919438038000 # number of cycles we spent at this ipl |
| 545system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl 546system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 547system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 537system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl 538system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 539system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 548system.cpu.kern.ipl_used::31 0.692289 # fraction of swpipl calls that actually changed the ipl 549system.cpu.kern.ipl_used::total 0.814110 # fraction of swpipl calls that actually changed the ipl | 540system.cpu.kern.ipl_used::31 0.692282 # fraction of swpipl calls that actually changed the ipl 541system.cpu.kern.ipl_used::total 0.814105 # fraction of swpipl calls that actually changed the ipl |
| 550system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 551system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 552system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 553system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 554system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 555system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 556system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 557system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 577system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 578system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 579system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 580system.cpu.kern.syscall::total 326 # number of syscalls executed 581system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 582system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 583system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 584system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 542system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 543system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 544system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 545system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 546system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 547system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 548system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 549system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 569system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 570system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 571system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 572system.cpu.kern.syscall::total 326 # number of syscalls executed 573system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 574system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 575system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 576system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 585system.cpu.kern.callpal::swpctx 4179 2.17% 2.17% # number of callpals executed | 577system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed |
| 586system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 587system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 578system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 579system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 588system.cpu.kern.callpal::swpipl 175948 91.21% 93.41% # number of callpals executed | 580system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed |
| 589system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed 590system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 591system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 592system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 593system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 594system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed 595system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 596system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 581system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed 582system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 583system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 584system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed 585system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 586system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed 587system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 588system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 597system.cpu.kern.callpal::total 192895 # number of callpals executed 598system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches 599system.cpu.kern.mode_switch::user 1741 # number of protection mode switches | 589system.cpu.kern.callpal::total 192894 # number of callpals executed 590system.cpu.kern.mode_switch::kernel 5902 # number of protection mode switches 591system.cpu.kern.mode_switch::user 1742 # number of protection mode switches |
| 600system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 601system.cpu.kern.mode_good::kernel 1912 | 592system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 593system.cpu.kern.mode_good::kernel 1912 |
| 602system.cpu.kern.mode_good::user 1741 603system.cpu.kern.mode_good::idle 171 604system.cpu.kern.mode_switch_good::kernel 0.323848 # fraction of useful protection mode switches | 594system.cpu.kern.mode_good::user 1742 595system.cpu.kern.mode_good::idle 170 596system.cpu.kern.mode_switch_good::kernel 0.323958 # fraction of useful protection mode switches |
| 605system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 597system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 606system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 607system.cpu.kern.mode_switch_good::total 0.392527 # fraction of useful protection mode switches 608system.cpu.kern.mode_ticks::kernel 46108525500 2.40% 2.40% # number of ticks spent at the given mode 609system.cpu.kern.mode_ticks::user 5189217000 0.27% 2.67% # number of ticks spent at the given mode 610system.cpu.kern.mode_ticks::idle 1868148079500 97.33% 100.00% # number of ticks spent at the given mode 611system.cpu.kern.swap_context 4180 # number of times the context was actually changed | 598system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches 599system.cpu.kern.mode_switch_good::total 0.392567 # fraction of useful protection mode switches 600system.cpu.kern.mode_ticks::kernel 46116573000 2.40% 2.40% # number of ticks spent at the given mode 601system.cpu.kern.mode_ticks::user 5192895500 0.27% 2.67% # number of ticks spent at the given mode 602system.cpu.kern.mode_ticks::idle 1868128567500 97.33% 100.00% # number of ticks spent at the given mode 603system.cpu.kern.swap_context 4178 # number of times the context was actually changed |
| 612system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 613system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 614system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 615system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 616system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 617system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 618system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 619system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 635system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 636system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 637system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 638system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 639system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 640system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 641system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 642system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 604system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 605system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 606system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 607system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 608system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 609system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 610system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 611system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 627system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 628system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 629system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 630system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 631system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 632system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 633system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 634system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 643system.iobus.throughput 1409867 # Throughput (bytes/s) | 635system.iobus.throughput 1409873 # Throughput (bytes/s) |
| 644system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 645system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 646system.iobus.trans_dist::WriteReq 51201 # Transaction distribution 647system.iobus.trans_dist::WriteResp 51201 # Transaction distribution 648system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) 649system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 650system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 651system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 43 unchanged lines hidden (view full) --- 695system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 696system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 697system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 698system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 699system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 700system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 701system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 702system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 636system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 637system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 638system.iobus.trans_dist::WriteReq 51201 # Transaction distribution 639system.iobus.trans_dist::WriteResp 51201 # Transaction distribution 640system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) 641system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 642system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 643system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 43 unchanged lines hidden (view full) --- 687system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 688system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 689system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 690system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 691system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 692system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 693system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 694system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 703system.iobus.reqLayer29.occupancy 380199064 # Layer occupancy (ticks) | 695system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks) |
| 704system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 705system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 706system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 707system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) 708system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 696system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 697system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 698system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 699system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) 700system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 709system.iobus.respLayer1.occupancy 43233500 # Layer occupancy (ticks) | 701system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) |
| 710system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 702system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 711system.cpu.icache.tags.replacements 927875 # number of replacements 712system.cpu.icache.tags.tagsinuse 508.303976 # Cycle average of tags in use 713system.cpu.icache.tags.total_refs 55187496 # Total number of references to valid blocks. 714system.cpu.icache.tags.sampled_refs 928386 # Sample count of references to valid blocks. 715system.cpu.icache.tags.avg_refs 59.444559 # Average number of references to valid blocks. | 703system.cpu.icache.tags.replacements 927724 # number of replacements 704system.cpu.icache.tags.tagsinuse 508.304001 # Cycle average of tags in use 705system.cpu.icache.tags.total_refs 55185585 # Total number of references to valid blocks. 706system.cpu.icache.tags.sampled_refs 928235 # Sample count of references to valid blocks. 707system.cpu.icache.tags.avg_refs 59.452170 # Average number of references to valid blocks. |
| 716system.cpu.icache.tags.warmup_cycle 39855277250 # Cycle when the warmup percentage was hit. | 708system.cpu.icache.tags.warmup_cycle 39855277250 # Cycle when the warmup percentage was hit. |
| 717system.cpu.icache.tags.occ_blocks::cpu.inst 508.303976 # Average occupied blocks per requestor | 709system.cpu.icache.tags.occ_blocks::cpu.inst 508.304001 # Average occupied blocks per requestor |
| 718system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy 719system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy 720system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 721system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 722system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 723system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 724system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 725system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 710system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy 711system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy 712system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 713system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 714system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 715system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 716system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 717system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 726system.cpu.icache.tags.tag_accesses 57044588 # Number of tag accesses 727system.cpu.icache.tags.data_accesses 57044588 # Number of data accesses 728system.cpu.icache.ReadReq_hits::cpu.inst 55187496 # number of ReadReq hits 729system.cpu.icache.ReadReq_hits::total 55187496 # number of ReadReq hits 730system.cpu.icache.demand_hits::cpu.inst 55187496 # number of demand (read+write) hits 731system.cpu.icache.demand_hits::total 55187496 # number of demand (read+write) hits 732system.cpu.icache.overall_hits::cpu.inst 55187496 # number of overall hits 733system.cpu.icache.overall_hits::total 55187496 # number of overall hits 734system.cpu.icache.ReadReq_misses::cpu.inst 928546 # number of ReadReq misses 735system.cpu.icache.ReadReq_misses::total 928546 # number of ReadReq misses 736system.cpu.icache.demand_misses::cpu.inst 928546 # number of demand (read+write) misses 737system.cpu.icache.demand_misses::total 928546 # number of demand (read+write) misses 738system.cpu.icache.overall_misses::cpu.inst 928546 # number of overall misses 739system.cpu.icache.overall_misses::total 928546 # number of overall misses 740system.cpu.icache.ReadReq_miss_latency::cpu.inst 12910342260 # number of ReadReq miss cycles 741system.cpu.icache.ReadReq_miss_latency::total 12910342260 # number of ReadReq miss cycles 742system.cpu.icache.demand_miss_latency::cpu.inst 12910342260 # number of demand (read+write) miss cycles 743system.cpu.icache.demand_miss_latency::total 12910342260 # number of demand (read+write) miss cycles 744system.cpu.icache.overall_miss_latency::cpu.inst 12910342260 # number of overall miss cycles 745system.cpu.icache.overall_miss_latency::total 12910342260 # number of overall miss cycles 746system.cpu.icache.ReadReq_accesses::cpu.inst 56116042 # number of ReadReq accesses(hits+misses) 747system.cpu.icache.ReadReq_accesses::total 56116042 # number of ReadReq accesses(hits+misses) 748system.cpu.icache.demand_accesses::cpu.inst 56116042 # number of demand (read+write) accesses 749system.cpu.icache.demand_accesses::total 56116042 # number of demand (read+write) accesses 750system.cpu.icache.overall_accesses::cpu.inst 56116042 # number of overall (read+write) accesses 751system.cpu.icache.overall_accesses::total 56116042 # number of overall (read+write) accesses 752system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016547 # miss rate for ReadReq accesses 753system.cpu.icache.ReadReq_miss_rate::total 0.016547 # miss rate for ReadReq accesses 754system.cpu.icache.demand_miss_rate::cpu.inst 0.016547 # miss rate for demand accesses 755system.cpu.icache.demand_miss_rate::total 0.016547 # miss rate for demand accesses 756system.cpu.icache.overall_miss_rate::cpu.inst 0.016547 # miss rate for overall accesses 757system.cpu.icache.overall_miss_rate::total 0.016547 # miss rate for overall accesses 758system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.826262 # average ReadReq miss latency 759system.cpu.icache.ReadReq_avg_miss_latency::total 13903.826262 # average ReadReq miss latency 760system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency 761system.cpu.icache.demand_avg_miss_latency::total 13903.826262 # average overall miss latency 762system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency 763system.cpu.icache.overall_avg_miss_latency::total 13903.826262 # average overall miss latency | 718system.cpu.icache.tags.tag_accesses 57042375 # Number of tag accesses 719system.cpu.icache.tags.data_accesses 57042375 # Number of data accesses 720system.cpu.icache.ReadReq_hits::cpu.inst 55185585 # number of ReadReq hits 721system.cpu.icache.ReadReq_hits::total 55185585 # number of ReadReq hits 722system.cpu.icache.demand_hits::cpu.inst 55185585 # number of demand (read+write) hits 723system.cpu.icache.demand_hits::total 55185585 # number of demand (read+write) hits 724system.cpu.icache.overall_hits::cpu.inst 55185585 # number of overall hits 725system.cpu.icache.overall_hits::total 55185585 # number of overall hits 726system.cpu.icache.ReadReq_misses::cpu.inst 928395 # number of ReadReq misses 727system.cpu.icache.ReadReq_misses::total 928395 # number of ReadReq misses 728system.cpu.icache.demand_misses::cpu.inst 928395 # number of demand (read+write) misses 729system.cpu.icache.demand_misses::total 928395 # number of demand (read+write) misses 730system.cpu.icache.overall_misses::cpu.inst 928395 # number of overall misses 731system.cpu.icache.overall_misses::total 928395 # number of overall misses 732system.cpu.icache.ReadReq_miss_latency::cpu.inst 12914246500 # number of ReadReq miss cycles 733system.cpu.icache.ReadReq_miss_latency::total 12914246500 # number of ReadReq miss cycles 734system.cpu.icache.demand_miss_latency::cpu.inst 12914246500 # number of demand (read+write) miss cycles 735system.cpu.icache.demand_miss_latency::total 12914246500 # number of demand (read+write) miss cycles 736system.cpu.icache.overall_miss_latency::cpu.inst 12914246500 # number of overall miss cycles 737system.cpu.icache.overall_miss_latency::total 12914246500 # number of overall miss cycles 738system.cpu.icache.ReadReq_accesses::cpu.inst 56113980 # number of ReadReq accesses(hits+misses) 739system.cpu.icache.ReadReq_accesses::total 56113980 # number of ReadReq accesses(hits+misses) 740system.cpu.icache.demand_accesses::cpu.inst 56113980 # number of demand (read+write) accesses 741system.cpu.icache.demand_accesses::total 56113980 # number of demand (read+write) accesses 742system.cpu.icache.overall_accesses::cpu.inst 56113980 # number of overall (read+write) accesses 743system.cpu.icache.overall_accesses::total 56113980 # number of overall (read+write) accesses 744system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016545 # miss rate for ReadReq accesses 745system.cpu.icache.ReadReq_miss_rate::total 0.016545 # miss rate for ReadReq accesses 746system.cpu.icache.demand_miss_rate::cpu.inst 0.016545 # miss rate for demand accesses 747system.cpu.icache.demand_miss_rate::total 0.016545 # miss rate for demand accesses 748system.cpu.icache.overall_miss_rate::cpu.inst 0.016545 # miss rate for overall accesses 749system.cpu.icache.overall_miss_rate::total 0.016545 # miss rate for overall accesses 750system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13910.293033 # average ReadReq miss latency 751system.cpu.icache.ReadReq_avg_miss_latency::total 13910.293033 # average ReadReq miss latency 752system.cpu.icache.demand_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency 753system.cpu.icache.demand_avg_miss_latency::total 13910.293033 # average overall miss latency 754system.cpu.icache.overall_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency 755system.cpu.icache.overall_avg_miss_latency::total 13910.293033 # average overall miss latency |
| 764system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 765system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 766system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 767system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 768system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 769system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 770system.cpu.icache.fast_writes 0 # number of fast writes performed 771system.cpu.icache.cache_copies 0 # number of cache copies performed | 756system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 757system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 758system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 759system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 760system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 761system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 762system.cpu.icache.fast_writes 0 # number of fast writes performed 763system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 772system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928546 # number of ReadReq MSHR misses 773system.cpu.icache.ReadReq_mshr_misses::total 928546 # number of ReadReq MSHR misses 774system.cpu.icache.demand_mshr_misses::cpu.inst 928546 # number of demand (read+write) MSHR misses 775system.cpu.icache.demand_mshr_misses::total 928546 # number of demand (read+write) MSHR misses 776system.cpu.icache.overall_mshr_misses::cpu.inst 928546 # number of overall MSHR misses 777system.cpu.icache.overall_mshr_misses::total 928546 # number of overall MSHR misses 778system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048086740 # number of ReadReq MSHR miss cycles 779system.cpu.icache.ReadReq_mshr_miss_latency::total 11048086740 # number of ReadReq MSHR miss cycles 780system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048086740 # number of demand (read+write) MSHR miss cycles 781system.cpu.icache.demand_mshr_miss_latency::total 11048086740 # number of demand (read+write) MSHR miss cycles 782system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11048086740 # number of overall MSHR miss cycles 783system.cpu.icache.overall_mshr_miss_latency::total 11048086740 # number of overall MSHR miss cycles 784system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for ReadReq accesses 785system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016547 # mshr miss rate for ReadReq accesses 786system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for demand accesses 787system.cpu.icache.demand_mshr_miss_rate::total 0.016547 # mshr miss rate for demand accesses 788system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for overall accesses 789system.cpu.icache.overall_mshr_miss_rate::total 0.016547 # mshr miss rate for overall accesses 790system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.265396 # average ReadReq mshr miss latency 791system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.265396 # average ReadReq mshr miss latency 792system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency 793system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency 794system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency 795system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency | 764system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928395 # number of ReadReq MSHR misses 765system.cpu.icache.ReadReq_mshr_misses::total 928395 # number of ReadReq MSHR misses 766system.cpu.icache.demand_mshr_misses::cpu.inst 928395 # number of demand (read+write) MSHR misses 767system.cpu.icache.demand_mshr_misses::total 928395 # number of demand (read+write) MSHR misses 768system.cpu.icache.overall_mshr_misses::cpu.inst 928395 # number of overall MSHR misses 769system.cpu.icache.overall_mshr_misses::total 928395 # number of overall MSHR misses 770system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11052282500 # number of ReadReq MSHR miss cycles 771system.cpu.icache.ReadReq_mshr_miss_latency::total 11052282500 # number of ReadReq MSHR miss cycles 772system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11052282500 # number of demand (read+write) MSHR miss cycles 773system.cpu.icache.demand_mshr_miss_latency::total 11052282500 # number of demand (read+write) MSHR miss cycles 774system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11052282500 # number of overall MSHR miss cycles 775system.cpu.icache.overall_mshr_miss_latency::total 11052282500 # number of overall MSHR miss cycles 776system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for ReadReq accesses 777system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016545 # mshr miss rate for ReadReq accesses 778system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for demand accesses 779system.cpu.icache.demand_mshr_miss_rate::total 0.016545 # mshr miss rate for demand accesses 780system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for overall accesses 781system.cpu.icache.overall_mshr_miss_rate::total 0.016545 # mshr miss rate for overall accesses 782system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.719974 # average ReadReq mshr miss latency 783system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.719974 # average ReadReq mshr miss latency 784system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.719974 # average overall mshr miss latency 785system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.719974 # average overall mshr miss latency 786system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.719974 # average overall mshr miss latency 787system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.719974 # average overall mshr miss latency |
| 796system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 788system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 797system.cpu.l2cache.tags.replacements 336232 # number of replacements 798system.cpu.l2cache.tags.tagsinuse 65296.289611 # Cycle average of tags in use 799system.cpu.l2cache.tags.total_refs 2446119 # Total number of references to valid blocks. 800system.cpu.l2cache.tags.sampled_refs 401393 # Sample count of references to valid blocks. 801system.cpu.l2cache.tags.avg_refs 6.094075 # Average number of references to valid blocks. | 789system.cpu.l2cache.tags.replacements 336239 # number of replacements 790system.cpu.l2cache.tags.tagsinuse 65296.333666 # Cycle average of tags in use 791system.cpu.l2cache.tags.total_refs 2445823 # Total number of references to valid blocks. 792system.cpu.l2cache.tags.sampled_refs 401400 # Sample count of references to valid blocks. 793system.cpu.l2cache.tags.avg_refs 6.093231 # Average number of references to valid blocks. |
| 802system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit. | 794system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit. |
| 803system.cpu.l2cache.tags.occ_blocks::writebacks 55555.447127 # Average occupied blocks per requestor 804system.cpu.l2cache.tags.occ_blocks::cpu.inst 4766.385283 # Average occupied blocks per requestor 805system.cpu.l2cache.tags.occ_blocks::cpu.data 4974.457201 # Average occupied blocks per requestor 806system.cpu.l2cache.tags.occ_percent::writebacks 0.847709 # Average percentage of cache occupancy 807system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072729 # Average percentage of cache occupancy 808system.cpu.l2cache.tags.occ_percent::cpu.data 0.075904 # Average percentage of cache occupancy 809system.cpu.l2cache.tags.occ_percent::total 0.996342 # Average percentage of cache occupancy | 795system.cpu.l2cache.tags.occ_blocks::writebacks 55553.405547 # Average occupied blocks per requestor 796system.cpu.l2cache.tags.occ_blocks::cpu.inst 4767.094279 # Average occupied blocks per requestor 797system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.833840 # Average occupied blocks per requestor 798system.cpu.l2cache.tags.occ_percent::writebacks 0.847678 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072740 # Average percentage of cache occupancy 800system.cpu.l2cache.tags.occ_percent::cpu.data 0.075925 # Average percentage of cache occupancy 801system.cpu.l2cache.tags.occ_percent::total 0.996343 # Average percentage of cache occupancy |
| 810system.cpu.l2cache.tags.occ_task_id_blocks::1024 65161 # Occupied blocks per task id 811system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 812system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id | 802system.cpu.l2cache.tags.occ_task_id_blocks::1024 65161 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 804system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id |
| 813system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4875 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3257 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55778 # Occupied blocks per task id | 805system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id 806system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3266 # Occupied blocks per task id 807system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55772 # Occupied blocks per task id |
| 816system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994278 # Percentage of cache occupancy per task id | 808system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994278 # Percentage of cache occupancy per task id |
| 817system.cpu.l2cache.tags.tag_accesses 25936539 # Number of tag accesses 818system.cpu.l2cache.tags.data_accesses 25936539 # Number of data accesses 819system.cpu.l2cache.ReadReq_hits::cpu.inst 915233 # number of ReadReq hits 820system.cpu.l2cache.ReadReq_hits::cpu.data 814520 # number of ReadReq hits 821system.cpu.l2cache.ReadReq_hits::total 1729753 # number of ReadReq hits 822system.cpu.l2cache.Writeback_hits::writebacks 834591 # number of Writeback hits 823system.cpu.l2cache.Writeback_hits::total 834591 # number of Writeback hits | 809system.cpu.l2cache.tags.tag_accesses 25933937 # Number of tag accesses 810system.cpu.l2cache.tags.data_accesses 25933937 # Number of data accesses 811system.cpu.l2cache.ReadReq_hits::cpu.inst 915081 # number of ReadReq hits 812system.cpu.l2cache.ReadReq_hits::cpu.data 814447 # number of ReadReq hits 813system.cpu.l2cache.ReadReq_hits::total 1729528 # number of ReadReq hits 814system.cpu.l2cache.Writeback_hits::writebacks 834526 # number of Writeback hits 815system.cpu.l2cache.Writeback_hits::total 834526 # number of Writeback hits |
| 824system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 825system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 816system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 817system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 826system.cpu.l2cache.ReadExReq_hits::cpu.data 187383 # number of ReadExReq hits 827system.cpu.l2cache.ReadExReq_hits::total 187383 # number of ReadExReq hits 828system.cpu.l2cache.demand_hits::cpu.inst 915233 # number of demand (read+write) hits 829system.cpu.l2cache.demand_hits::cpu.data 1001903 # number of demand (read+write) hits 830system.cpu.l2cache.demand_hits::total 1917136 # number of demand (read+write) hits 831system.cpu.l2cache.overall_hits::cpu.inst 915233 # number of overall hits 832system.cpu.l2cache.overall_hits::cpu.data 1001903 # number of overall hits 833system.cpu.l2cache.overall_hits::total 1917136 # number of overall hits 834system.cpu.l2cache.ReadReq_misses::cpu.inst 13293 # number of ReadReq misses | 818system.cpu.l2cache.ReadExReq_hits::cpu.data 187344 # number of ReadExReq hits 819system.cpu.l2cache.ReadExReq_hits::total 187344 # number of ReadExReq hits 820system.cpu.l2cache.demand_hits::cpu.inst 915081 # number of demand (read+write) hits 821system.cpu.l2cache.demand_hits::cpu.data 1001791 # number of demand (read+write) hits 822system.cpu.l2cache.demand_hits::total 1916872 # number of demand (read+write) hits 823system.cpu.l2cache.overall_hits::cpu.inst 915081 # number of overall hits 824system.cpu.l2cache.overall_hits::cpu.data 1001791 # number of overall hits 825system.cpu.l2cache.overall_hits::total 1916872 # number of overall hits 826system.cpu.l2cache.ReadReq_misses::cpu.inst 13294 # number of ReadReq misses |
| 835system.cpu.l2cache.ReadReq_misses::cpu.data 271960 # number of ReadReq misses | 827system.cpu.l2cache.ReadReq_misses::cpu.data 271960 # number of ReadReq misses |
| 836system.cpu.l2cache.ReadReq_misses::total 285253 # number of ReadReq misses | 828system.cpu.l2cache.ReadReq_misses::total 285254 # number of ReadReq misses |
| 837system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 838system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses | 829system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 830system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses |
| 839system.cpu.l2cache.ReadExReq_misses::cpu.data 116840 # number of ReadExReq misses 840system.cpu.l2cache.ReadExReq_misses::total 116840 # number of ReadExReq misses 841system.cpu.l2cache.demand_misses::cpu.inst 13293 # number of demand (read+write) misses 842system.cpu.l2cache.demand_misses::cpu.data 388800 # number of demand (read+write) misses 843system.cpu.l2cache.demand_misses::total 402093 # number of demand (read+write) misses 844system.cpu.l2cache.overall_misses::cpu.inst 13293 # number of overall misses 845system.cpu.l2cache.overall_misses::cpu.data 388800 # number of overall misses 846system.cpu.l2cache.overall_misses::total 402093 # number of overall misses 847system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 967190740 # number of ReadReq miss cycles 848system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17699357246 # number of ReadReq miss cycles 849system.cpu.l2cache.ReadReq_miss_latency::total 18666547986 # number of ReadReq miss cycles 850system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles 851system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles 852system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8068029125 # number of ReadExReq miss cycles 853system.cpu.l2cache.ReadExReq_miss_latency::total 8068029125 # number of ReadExReq miss cycles 854system.cpu.l2cache.demand_miss_latency::cpu.inst 967190740 # number of demand (read+write) miss cycles 855system.cpu.l2cache.demand_miss_latency::cpu.data 25767386371 # number of demand (read+write) miss cycles 856system.cpu.l2cache.demand_miss_latency::total 26734577111 # number of demand (read+write) miss cycles 857system.cpu.l2cache.overall_miss_latency::cpu.inst 967190740 # number of overall miss cycles 858system.cpu.l2cache.overall_miss_latency::cpu.data 25767386371 # number of overall miss cycles 859system.cpu.l2cache.overall_miss_latency::total 26734577111 # number of overall miss cycles 860system.cpu.l2cache.ReadReq_accesses::cpu.inst 928526 # number of ReadReq accesses(hits+misses) 861system.cpu.l2cache.ReadReq_accesses::cpu.data 1086480 # number of ReadReq accesses(hits+misses) 862system.cpu.l2cache.ReadReq_accesses::total 2015006 # number of ReadReq accesses(hits+misses) 863system.cpu.l2cache.Writeback_accesses::writebacks 834591 # number of Writeback accesses(hits+misses) 864system.cpu.l2cache.Writeback_accesses::total 834591 # number of Writeback accesses(hits+misses) | 831system.cpu.l2cache.ReadExReq_misses::cpu.data 116846 # number of ReadExReq misses 832system.cpu.l2cache.ReadExReq_misses::total 116846 # number of ReadExReq misses 833system.cpu.l2cache.demand_misses::cpu.inst 13294 # number of demand (read+write) misses 834system.cpu.l2cache.demand_misses::cpu.data 388806 # number of demand (read+write) misses 835system.cpu.l2cache.demand_misses::total 402100 # number of demand (read+write) misses 836system.cpu.l2cache.overall_misses::cpu.inst 13294 # number of overall misses 837system.cpu.l2cache.overall_misses::cpu.data 388806 # number of overall misses 838system.cpu.l2cache.overall_misses::total 402100 # number of overall misses 839system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 973057500 # number of ReadReq miss cycles 840system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17696986250 # number of ReadReq miss cycles 841system.cpu.l2cache.ReadReq_miss_latency::total 18670043750 # number of ReadReq miss cycles 842system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 93496 # number of UpgradeReq miss cycles 843system.cpu.l2cache.UpgradeReq_miss_latency::total 93496 # number of UpgradeReq miss cycles 844system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8067144131 # number of ReadExReq miss cycles 845system.cpu.l2cache.ReadExReq_miss_latency::total 8067144131 # number of ReadExReq miss cycles 846system.cpu.l2cache.demand_miss_latency::cpu.inst 973057500 # number of demand (read+write) miss cycles 847system.cpu.l2cache.demand_miss_latency::cpu.data 25764130381 # number of demand (read+write) miss cycles 848system.cpu.l2cache.demand_miss_latency::total 26737187881 # number of demand (read+write) miss cycles 849system.cpu.l2cache.overall_miss_latency::cpu.inst 973057500 # number of overall miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.data 25764130381 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::total 26737187881 # number of overall miss cycles 852system.cpu.l2cache.ReadReq_accesses::cpu.inst 928375 # number of ReadReq accesses(hits+misses) 853system.cpu.l2cache.ReadReq_accesses::cpu.data 1086407 # number of ReadReq accesses(hits+misses) 854system.cpu.l2cache.ReadReq_accesses::total 2014782 # number of ReadReq accesses(hits+misses) 855system.cpu.l2cache.Writeback_accesses::writebacks 834526 # number of Writeback accesses(hits+misses) 856system.cpu.l2cache.Writeback_accesses::total 834526 # number of Writeback accesses(hits+misses) |
| 865system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 866system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) | 857system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 858system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) |
| 867system.cpu.l2cache.ReadExReq_accesses::cpu.data 304223 # number of ReadExReq accesses(hits+misses) 868system.cpu.l2cache.ReadExReq_accesses::total 304223 # number of ReadExReq accesses(hits+misses) 869system.cpu.l2cache.demand_accesses::cpu.inst 928526 # number of demand (read+write) accesses 870system.cpu.l2cache.demand_accesses::cpu.data 1390703 # number of demand (read+write) accesses 871system.cpu.l2cache.demand_accesses::total 2319229 # number of demand (read+write) accesses 872system.cpu.l2cache.overall_accesses::cpu.inst 928526 # number of overall (read+write) accesses 873system.cpu.l2cache.overall_accesses::cpu.data 1390703 # number of overall (read+write) accesses 874system.cpu.l2cache.overall_accesses::total 2319229 # number of overall (read+write) accesses 875system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014316 # miss rate for ReadReq accesses 876system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250313 # miss rate for ReadReq accesses 877system.cpu.l2cache.ReadReq_miss_rate::total 0.141564 # miss rate for ReadReq accesses | 859system.cpu.l2cache.ReadExReq_accesses::cpu.data 304190 # number of ReadExReq accesses(hits+misses) 860system.cpu.l2cache.ReadExReq_accesses::total 304190 # number of ReadExReq accesses(hits+misses) 861system.cpu.l2cache.demand_accesses::cpu.inst 928375 # number of demand (read+write) accesses 862system.cpu.l2cache.demand_accesses::cpu.data 1390597 # number of demand (read+write) accesses 863system.cpu.l2cache.demand_accesses::total 2318972 # number of demand (read+write) accesses 864system.cpu.l2cache.overall_accesses::cpu.inst 928375 # number of overall (read+write) accesses 865system.cpu.l2cache.overall_accesses::cpu.data 1390597 # number of overall (read+write) accesses 866system.cpu.l2cache.overall_accesses::total 2318972 # number of overall (read+write) accesses 867system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014320 # miss rate for ReadReq accesses 868system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250330 # miss rate for ReadReq accesses 869system.cpu.l2cache.ReadReq_miss_rate::total 0.141581 # miss rate for ReadReq accesses |
| 878system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 879system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses | 870system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 871system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses |
| 880system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384060 # miss rate for ReadExReq accesses 881system.cpu.l2cache.ReadExReq_miss_rate::total 0.384060 # miss rate for ReadExReq accesses 882system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014316 # miss rate for demand accesses 883system.cpu.l2cache.demand_miss_rate::cpu.data 0.279571 # miss rate for demand accesses 884system.cpu.l2cache.demand_miss_rate::total 0.173374 # miss rate for demand accesses 885system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014316 # miss rate for overall accesses 886system.cpu.l2cache.overall_miss_rate::cpu.data 0.279571 # miss rate for overall accesses 887system.cpu.l2cache.overall_miss_rate::total 0.173374 # miss rate for overall accesses 888system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72759.402693 # average ReadReq miss latency 889system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65080.737042 # average ReadReq miss latency 890system.cpu.l2cache.ReadReq_avg_miss_latency::total 65438.568520 # average ReadReq miss latency 891system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency 892system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency 893system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69051.943898 # average ReadExReq miss latency 894system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69051.943898 # average ReadExReq miss latency 895system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72759.402693 # average overall miss latency 896system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66274.141901 # average overall miss latency 897system.cpu.l2cache.demand_avg_miss_latency::total 66488.541484 # average overall miss latency 898system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72759.402693 # average overall miss latency 899system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66274.141901 # average overall miss latency 900system.cpu.l2cache.overall_avg_miss_latency::total 66488.541484 # average overall miss latency | 872system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384122 # miss rate for ReadExReq accesses 873system.cpu.l2cache.ReadExReq_miss_rate::total 0.384122 # miss rate for ReadExReq accesses 874system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014320 # miss rate for demand accesses 875system.cpu.l2cache.demand_miss_rate::cpu.data 0.279596 # miss rate for demand accesses 876system.cpu.l2cache.demand_miss_rate::total 0.173396 # miss rate for demand accesses 877system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014320 # miss rate for overall accesses 878system.cpu.l2cache.overall_miss_rate::cpu.data 0.279596 # miss rate for overall accesses 879system.cpu.l2cache.overall_miss_rate::total 0.173396 # miss rate for overall accesses 880system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73195.238453 # average ReadReq miss latency 881system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65072.018863 # average ReadReq miss latency 882system.cpu.l2cache.ReadReq_avg_miss_latency::total 65450.594032 # average ReadReq miss latency 883system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7192 # average UpgradeReq miss latency 884system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7192 # average UpgradeReq miss latency 885system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69040.824085 # average ReadExReq miss latency 886system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69040.824085 # average ReadExReq miss latency 887system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73195.238453 # average overall miss latency 888system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66264.744837 # average overall miss latency 889system.cpu.l2cache.demand_avg_miss_latency::total 66493.876849 # average overall miss latency 890system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73195.238453 # average overall miss latency 891system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66264.744837 # average overall miss latency 892system.cpu.l2cache.overall_avg_miss_latency::total 66493.876849 # average overall miss latency |
| 901system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 902system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 904system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 906system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu.l2cache.fast_writes 0 # number of fast writes performed 908system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 893system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 894system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 895system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 896system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 897system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 898system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 899system.cpu.l2cache.fast_writes 0 # number of fast writes performed 900system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 909system.cpu.l2cache.writebacks::writebacks 74176 # number of writebacks 910system.cpu.l2cache.writebacks::total 74176 # number of writebacks 911system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13293 # number of ReadReq MSHR misses | 901system.cpu.l2cache.writebacks::writebacks 74183 # number of writebacks 902system.cpu.l2cache.writebacks::total 74183 # number of writebacks 903system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13294 # number of ReadReq MSHR misses |
| 912system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271960 # number of ReadReq MSHR misses | 904system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271960 # number of ReadReq MSHR misses |
| 913system.cpu.l2cache.ReadReq_mshr_misses::total 285253 # number of ReadReq MSHR misses | 905system.cpu.l2cache.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses |
| 914system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 915system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses | 906system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 907system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses |
| 916system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116840 # number of ReadExReq MSHR misses 917system.cpu.l2cache.ReadExReq_mshr_misses::total 116840 # number of ReadExReq MSHR misses 918system.cpu.l2cache.demand_mshr_misses::cpu.inst 13293 # number of demand (read+write) MSHR misses 919system.cpu.l2cache.demand_mshr_misses::cpu.data 388800 # number of demand (read+write) MSHR misses 920system.cpu.l2cache.demand_mshr_misses::total 402093 # number of demand (read+write) MSHR misses 921system.cpu.l2cache.overall_mshr_misses::cpu.inst 13293 # number of overall MSHR misses 922system.cpu.l2cache.overall_mshr_misses::cpu.data 388800 # number of overall MSHR misses 923system.cpu.l2cache.overall_mshr_misses::total 402093 # number of overall MSHR misses 924system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 800656260 # number of ReadReq MSHR miss cycles 925system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14299493254 # number of ReadReq MSHR miss cycles 926system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15100149514 # number of ReadReq MSHR miss cycles 927system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles 928system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles 929system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607242375 # number of ReadExReq MSHR miss cycles 930system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607242375 # number of ReadExReq MSHR miss cycles 931system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 800656260 # number of demand (read+write) MSHR miss cycles 932system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20906735629 # number of demand (read+write) MSHR miss cycles 933system.cpu.l2cache.demand_mshr_miss_latency::total 21707391889 # number of demand (read+write) MSHR miss cycles 934system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 800656260 # number of overall MSHR miss cycles 935system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20906735629 # number of overall MSHR miss cycles 936system.cpu.l2cache.overall_mshr_miss_latency::total 21707391889 # number of overall MSHR miss cycles 937system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles 938system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles 939system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895432500 # number of WriteReq MSHR uncacheable cycles 940system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895432500 # number of WriteReq MSHR uncacheable cycles 941system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229578000 # number of overall MSHR uncacheable cycles 942system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229578000 # number of overall MSHR uncacheable cycles 943system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses 944system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250313 # mshr miss rate for ReadReq accesses 945system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141564 # mshr miss rate for ReadReq accesses | 908system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116846 # number of ReadExReq MSHR misses 909system.cpu.l2cache.ReadExReq_mshr_misses::total 116846 # number of ReadExReq MSHR misses 910system.cpu.l2cache.demand_mshr_misses::cpu.inst 13294 # number of demand (read+write) MSHR misses 911system.cpu.l2cache.demand_mshr_misses::cpu.data 388806 # number of demand (read+write) MSHR misses 912system.cpu.l2cache.demand_mshr_misses::total 402100 # number of demand (read+write) MSHR misses 913system.cpu.l2cache.overall_mshr_misses::cpu.inst 13294 # number of overall MSHR misses 914system.cpu.l2cache.overall_mshr_misses::cpu.data 388806 # number of overall MSHR misses 915system.cpu.l2cache.overall_mshr_misses::total 402100 # number of overall MSHR misses 916system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 806506000 # number of ReadReq MSHR miss cycles 917system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14297020250 # number of ReadReq MSHR miss cycles 918system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15103526250 # number of ReadReq MSHR miss cycles 919system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 130013 # number of UpgradeReq MSHR miss cycles 920system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 130013 # number of UpgradeReq MSHR miss cycles 921system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6606288869 # number of ReadExReq MSHR miss cycles 922system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6606288869 # number of ReadExReq MSHR miss cycles 923system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 806506000 # number of demand (read+write) MSHR miss cycles 924system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20903309119 # number of demand (read+write) MSHR miss cycles 925system.cpu.l2cache.demand_mshr_miss_latency::total 21709815119 # number of demand (read+write) MSHR miss cycles 926system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 806506000 # number of overall MSHR miss cycles 927system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20903309119 # number of overall MSHR miss cycles 928system.cpu.l2cache.overall_mshr_miss_latency::total 21709815119 # number of overall MSHR miss cycles 929system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles 930system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles 931system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895431500 # number of WriteReq MSHR uncacheable cycles 932system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895431500 # number of WriteReq MSHR uncacheable cycles 933system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229577500 # number of overall MSHR uncacheable cycles 934system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229577500 # number of overall MSHR uncacheable cycles 935system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for ReadReq accesses 936system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250330 # mshr miss rate for ReadReq accesses 937system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141581 # mshr miss rate for ReadReq accesses |
| 946system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 947system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses | 938system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 939system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses |
| 948system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384060 # mshr miss rate for ReadExReq accesses 949system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384060 # mshr miss rate for ReadExReq accesses 950system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses 951system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for demand accesses 952system.cpu.l2cache.demand_mshr_miss_rate::total 0.173374 # mshr miss rate for demand accesses 953system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses 954system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for overall accesses 955system.cpu.l2cache.overall_mshr_miss_rate::total 0.173374 # mshr miss rate for overall accesses 956system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60231.419544 # average ReadReq mshr miss latency 957system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52579.398640 # average ReadReq mshr miss latency 958system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52935.988452 # average ReadReq mshr miss latency 959system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency 960system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency 961system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56549.489687 # average ReadExReq mshr miss latency 962system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56549.489687 # average ReadExReq mshr miss latency 963system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency 964system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency 965system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency 966system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency 967system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency 968system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency | 940system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384122 # mshr miss rate for ReadExReq accesses 941system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384122 # mshr miss rate for ReadExReq accesses 942system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for demand accesses 943system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for demand accesses 944system.cpu.l2cache.demand_mshr_miss_rate::total 0.173396 # mshr miss rate for demand accesses 945system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for overall accesses 946system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for overall accesses 947system.cpu.l2cache.overall_mshr_miss_rate::total 0.173396 # mshr miss rate for overall accesses 948system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60666.917406 # average ReadReq mshr miss latency 949system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52570.305376 # average ReadReq mshr miss latency 950system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52947.640524 # average ReadReq mshr miss latency 951system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 952system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 953system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56538.425526 # average ReadExReq mshr miss latency 954system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.425526 # average ReadExReq mshr miss latency 955system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency 956system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency 957system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency 958system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency 959system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency 960system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency |
| 969system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 970system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 971system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 972system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 973system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 974system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 975system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 961system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 962system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 963system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 964system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 965system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 966system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 967system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 976system.cpu.dcache.tags.replacements 1390190 # number of replacements 977system.cpu.dcache.tags.tagsinuse 511.978877 # Cycle average of tags in use 978system.cpu.dcache.tags.total_refs 14030691 # Total number of references to valid blocks. 979system.cpu.dcache.tags.sampled_refs 1390702 # Sample count of references to valid blocks. 980system.cpu.dcache.tags.avg_refs 10.088927 # Average number of references to valid blocks. | 968system.cpu.dcache.tags.replacements 1390084 # number of replacements 969system.cpu.dcache.tags.tagsinuse 511.978881 # Cycle average of tags in use 970system.cpu.dcache.tags.total_refs 14030288 # Total number of references to valid blocks. 971system.cpu.dcache.tags.sampled_refs 1390596 # Sample count of references to valid blocks. 972system.cpu.dcache.tags.avg_refs 10.089406 # Average number of references to valid blocks. |
| 981system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. | 973system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. |
| 982system.cpu.dcache.tags.occ_blocks::cpu.data 511.978877 # Average occupied blocks per requestor | 974system.cpu.dcache.tags.occ_blocks::cpu.data 511.978881 # Average occupied blocks per requestor |
| 983system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy 984system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy 985system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 986system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 987system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 988system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 989system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 975system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy 976system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy 977system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 978system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 979system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 980system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 981system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 990system.cpu.dcache.tags.tag_accesses 63076279 # Number of tag accesses 991system.cpu.dcache.tags.data_accesses 63076279 # Number of data accesses 992system.cpu.dcache.ReadReq_hits::cpu.data 7802806 # number of ReadReq hits 993system.cpu.dcache.ReadReq_hits::total 7802806 # number of ReadReq hits 994system.cpu.dcache.WriteReq_hits::cpu.data 5845593 # number of WriteReq hits 995system.cpu.dcache.WriteReq_hits::total 5845593 # number of WriteReq hits 996system.cpu.dcache.LoadLockedReq_hits::cpu.data 183040 # number of LoadLockedReq hits 997system.cpu.dcache.LoadLockedReq_hits::total 183040 # number of LoadLockedReq hits 998system.cpu.dcache.StoreCondReq_hits::cpu.data 199235 # number of StoreCondReq hits 999system.cpu.dcache.StoreCondReq_hits::total 199235 # number of StoreCondReq hits 1000system.cpu.dcache.demand_hits::cpu.data 13648399 # number of demand (read+write) hits 1001system.cpu.dcache.demand_hits::total 13648399 # number of demand (read+write) hits 1002system.cpu.dcache.overall_hits::cpu.data 13648399 # number of overall hits 1003system.cpu.dcache.overall_hits::total 13648399 # number of overall hits 1004system.cpu.dcache.ReadReq_misses::cpu.data 1069264 # number of ReadReq misses 1005system.cpu.dcache.ReadReq_misses::total 1069264 # number of ReadReq misses 1006system.cpu.dcache.WriteReq_misses::cpu.data 304240 # number of WriteReq misses 1007system.cpu.dcache.WriteReq_misses::total 304240 # number of WriteReq misses 1008system.cpu.dcache.LoadLockedReq_misses::cpu.data 17216 # number of LoadLockedReq misses 1009system.cpu.dcache.LoadLockedReq_misses::total 17216 # number of LoadLockedReq misses 1010system.cpu.dcache.demand_misses::cpu.data 1373504 # number of demand (read+write) misses 1011system.cpu.dcache.demand_misses::total 1373504 # number of demand (read+write) misses 1012system.cpu.dcache.overall_misses::cpu.data 1373504 # number of overall misses 1013system.cpu.dcache.overall_misses::total 1373504 # number of overall misses 1014system.cpu.dcache.ReadReq_miss_latency::cpu.data 29001409504 # number of ReadReq miss cycles 1015system.cpu.dcache.ReadReq_miss_latency::total 29001409504 # number of ReadReq miss cycles 1016system.cpu.dcache.WriteReq_miss_latency::cpu.data 10907701386 # number of WriteReq miss cycles 1017system.cpu.dcache.WriteReq_miss_latency::total 10907701386 # number of WriteReq miss cycles 1018system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228213250 # number of LoadLockedReq miss cycles 1019system.cpu.dcache.LoadLockedReq_miss_latency::total 228213250 # number of LoadLockedReq miss cycles 1020system.cpu.dcache.demand_miss_latency::cpu.data 39909110890 # number of demand (read+write) miss cycles 1021system.cpu.dcache.demand_miss_latency::total 39909110890 # number of demand (read+write) miss cycles 1022system.cpu.dcache.overall_miss_latency::cpu.data 39909110890 # number of overall miss cycles 1023system.cpu.dcache.overall_miss_latency::total 39909110890 # number of overall miss cycles 1024system.cpu.dcache.ReadReq_accesses::cpu.data 8872070 # number of ReadReq accesses(hits+misses) 1025system.cpu.dcache.ReadReq_accesses::total 8872070 # number of ReadReq accesses(hits+misses) 1026system.cpu.dcache.WriteReq_accesses::cpu.data 6149833 # number of WriteReq accesses(hits+misses) 1027system.cpu.dcache.WriteReq_accesses::total 6149833 # number of WriteReq accesses(hits+misses) 1028system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200256 # number of LoadLockedReq accesses(hits+misses) 1029system.cpu.dcache.LoadLockedReq_accesses::total 200256 # number of LoadLockedReq accesses(hits+misses) 1030system.cpu.dcache.StoreCondReq_accesses::cpu.data 199235 # number of StoreCondReq accesses(hits+misses) 1031system.cpu.dcache.StoreCondReq_accesses::total 199235 # number of StoreCondReq accesses(hits+misses) 1032system.cpu.dcache.demand_accesses::cpu.data 15021903 # number of demand (read+write) accesses 1033system.cpu.dcache.demand_accesses::total 15021903 # number of demand (read+write) accesses 1034system.cpu.dcache.overall_accesses::cpu.data 15021903 # number of overall (read+write) accesses 1035system.cpu.dcache.overall_accesses::total 15021903 # number of overall (read+write) accesses 1036system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120520 # miss rate for ReadReq accesses 1037system.cpu.dcache.ReadReq_miss_rate::total 0.120520 # miss rate for ReadReq accesses 1038system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049471 # miss rate for WriteReq accesses 1039system.cpu.dcache.WriteReq_miss_rate::total 0.049471 # miss rate for WriteReq accesses 1040system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses 1041system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses 1042system.cpu.dcache.demand_miss_rate::cpu.data 0.091433 # miss rate for demand accesses 1043system.cpu.dcache.demand_miss_rate::total 0.091433 # miss rate for demand accesses 1044system.cpu.dcache.overall_miss_rate::cpu.data 0.091433 # miss rate for overall accesses 1045system.cpu.dcache.overall_miss_rate::total 0.091433 # miss rate for overall accesses 1046system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27122.777447 # average ReadReq miss latency 1047system.cpu.dcache.ReadReq_avg_miss_latency::total 27122.777447 # average ReadReq miss latency 1048system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35852.292223 # average WriteReq miss latency 1049system.cpu.dcache.WriteReq_avg_miss_latency::total 35852.292223 # average WriteReq miss latency 1050system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.881157 # average LoadLockedReq miss latency 1051system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.881157 # average LoadLockedReq miss latency 1052system.cpu.dcache.demand_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency 1053system.cpu.dcache.demand_avg_miss_latency::total 29056.421306 # average overall miss latency 1054system.cpu.dcache.overall_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency 1055system.cpu.dcache.overall_avg_miss_latency::total 29056.421306 # average overall miss latency | 982system.cpu.dcache.tags.tag_accesses 63074137 # Number of tag accesses 983system.cpu.dcache.tags.data_accesses 63074137 # Number of data accesses 984system.cpu.dcache.ReadReq_hits::cpu.data 7802568 # number of ReadReq hits 985system.cpu.dcache.ReadReq_hits::total 7802568 # number of ReadReq hits 986system.cpu.dcache.WriteReq_hits::cpu.data 5845442 # number of WriteReq hits 987system.cpu.dcache.WriteReq_hits::total 5845442 # number of WriteReq hits 988system.cpu.dcache.LoadLockedReq_hits::cpu.data 183034 # number of LoadLockedReq hits 989system.cpu.dcache.LoadLockedReq_hits::total 183034 # number of LoadLockedReq hits 990system.cpu.dcache.StoreCondReq_hits::cpu.data 199227 # number of StoreCondReq hits 991system.cpu.dcache.StoreCondReq_hits::total 199227 # number of StoreCondReq hits 992system.cpu.dcache.demand_hits::cpu.data 13648010 # number of demand (read+write) hits 993system.cpu.dcache.demand_hits::total 13648010 # number of demand (read+write) hits 994system.cpu.dcache.overall_hits::cpu.data 13648010 # number of overall hits 995system.cpu.dcache.overall_hits::total 13648010 # number of overall hits 996system.cpu.dcache.ReadReq_misses::cpu.data 1069193 # number of ReadReq misses 997system.cpu.dcache.ReadReq_misses::total 1069193 # number of ReadReq misses 998system.cpu.dcache.WriteReq_misses::cpu.data 304207 # number of WriteReq misses 999system.cpu.dcache.WriteReq_misses::total 304207 # number of WriteReq misses 1000system.cpu.dcache.LoadLockedReq_misses::cpu.data 17214 # number of LoadLockedReq misses 1001system.cpu.dcache.LoadLockedReq_misses::total 17214 # number of LoadLockedReq misses 1002system.cpu.dcache.demand_misses::cpu.data 1373400 # number of demand (read+write) misses 1003system.cpu.dcache.demand_misses::total 1373400 # number of demand (read+write) misses 1004system.cpu.dcache.overall_misses::cpu.data 1373400 # number of overall misses 1005system.cpu.dcache.overall_misses::total 1373400 # number of overall misses 1006system.cpu.dcache.ReadReq_miss_latency::cpu.data 28998201750 # number of ReadReq miss cycles 1007system.cpu.dcache.ReadReq_miss_latency::total 28998201750 # number of ReadReq miss cycles 1008system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906246382 # number of WriteReq miss cycles 1009system.cpu.dcache.WriteReq_miss_latency::total 10906246382 # number of WriteReq miss cycles 1010system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228174000 # number of LoadLockedReq miss cycles 1011system.cpu.dcache.LoadLockedReq_miss_latency::total 228174000 # number of LoadLockedReq miss cycles 1012system.cpu.dcache.demand_miss_latency::cpu.data 39904448132 # number of demand (read+write) miss cycles 1013system.cpu.dcache.demand_miss_latency::total 39904448132 # number of demand (read+write) miss cycles 1014system.cpu.dcache.overall_miss_latency::cpu.data 39904448132 # number of overall miss cycles 1015system.cpu.dcache.overall_miss_latency::total 39904448132 # number of overall miss cycles 1016system.cpu.dcache.ReadReq_accesses::cpu.data 8871761 # number of ReadReq accesses(hits+misses) 1017system.cpu.dcache.ReadReq_accesses::total 8871761 # number of ReadReq accesses(hits+misses) 1018system.cpu.dcache.WriteReq_accesses::cpu.data 6149649 # number of WriteReq accesses(hits+misses) 1019system.cpu.dcache.WriteReq_accesses::total 6149649 # number of WriteReq accesses(hits+misses) 1020system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) 1021system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) 1022system.cpu.dcache.StoreCondReq_accesses::cpu.data 199227 # number of StoreCondReq accesses(hits+misses) 1023system.cpu.dcache.StoreCondReq_accesses::total 199227 # number of StoreCondReq accesses(hits+misses) 1024system.cpu.dcache.demand_accesses::cpu.data 15021410 # number of demand (read+write) accesses 1025system.cpu.dcache.demand_accesses::total 15021410 # number of demand (read+write) accesses 1026system.cpu.dcache.overall_accesses::cpu.data 15021410 # number of overall (read+write) accesses 1027system.cpu.dcache.overall_accesses::total 15021410 # number of overall (read+write) accesses 1028system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120516 # miss rate for ReadReq accesses 1029system.cpu.dcache.ReadReq_miss_rate::total 0.120516 # miss rate for ReadReq accesses 1030system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049467 # miss rate for WriteReq accesses 1031system.cpu.dcache.WriteReq_miss_rate::total 0.049467 # miss rate for WriteReq accesses 1032system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085963 # miss rate for LoadLockedReq accesses 1033system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085963 # miss rate for LoadLockedReq accesses 1034system.cpu.dcache.demand_miss_rate::cpu.data 0.091429 # miss rate for demand accesses 1035system.cpu.dcache.demand_miss_rate::total 0.091429 # miss rate for demand accesses 1036system.cpu.dcache.overall_miss_rate::cpu.data 0.091429 # miss rate for overall accesses 1037system.cpu.dcache.overall_miss_rate::total 0.091429 # miss rate for overall accesses 1038system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27121.578377 # average ReadReq miss latency 1039system.cpu.dcache.ReadReq_avg_miss_latency::total 27121.578377 # average ReadReq miss latency 1040system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35851.398495 # average WriteReq miss latency 1041system.cpu.dcache.WriteReq_avg_miss_latency::total 35851.398495 # average WriteReq miss latency 1042system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.141164 # average LoadLockedReq miss latency 1043system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.141164 # average LoadLockedReq miss latency 1044system.cpu.dcache.demand_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency 1045system.cpu.dcache.demand_avg_miss_latency::total 29055.226541 # average overall miss latency 1046system.cpu.dcache.overall_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency 1047system.cpu.dcache.overall_avg_miss_latency::total 29055.226541 # average overall miss latency |
| 1056system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1057system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1058system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1059system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1060system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1061system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1062system.cpu.dcache.fast_writes 0 # number of fast writes performed 1063system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1048system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1049system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1050system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1051system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1052system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1053system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1054system.cpu.dcache.fast_writes 0 # number of fast writes performed 1055system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1064system.cpu.dcache.writebacks::writebacks 834591 # number of writebacks 1065system.cpu.dcache.writebacks::total 834591 # number of writebacks 1066system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069264 # number of ReadReq MSHR misses 1067system.cpu.dcache.ReadReq_mshr_misses::total 1069264 # number of ReadReq MSHR misses 1068system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304240 # number of WriteReq MSHR misses 1069system.cpu.dcache.WriteReq_mshr_misses::total 304240 # number of WriteReq MSHR misses 1070system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17216 # number of LoadLockedReq MSHR misses 1071system.cpu.dcache.LoadLockedReq_mshr_misses::total 17216 # number of LoadLockedReq MSHR misses 1072system.cpu.dcache.demand_mshr_misses::cpu.data 1373504 # number of demand (read+write) MSHR misses 1073system.cpu.dcache.demand_mshr_misses::total 1373504 # number of demand (read+write) MSHR misses 1074system.cpu.dcache.overall_mshr_misses::cpu.data 1373504 # number of overall MSHR misses 1075system.cpu.dcache.overall_mshr_misses::total 1373504 # number of overall MSHR misses 1076system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26737269496 # number of ReadReq MSHR miss cycles 1077system.cpu.dcache.ReadReq_mshr_miss_latency::total 26737269496 # number of ReadReq MSHR miss cycles 1078system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10246531614 # number of WriteReq MSHR miss cycles 1079system.cpu.dcache.WriteReq_mshr_miss_latency::total 10246531614 # number of WriteReq MSHR miss cycles 1080system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193767750 # number of LoadLockedReq MSHR miss cycles 1081system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193767750 # number of LoadLockedReq MSHR miss cycles 1082system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36983801110 # number of demand (read+write) MSHR miss cycles 1083system.cpu.dcache.demand_mshr_miss_latency::total 36983801110 # number of demand (read+write) MSHR miss cycles 1084system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36983801110 # number of overall MSHR miss cycles 1085system.cpu.dcache.overall_mshr_miss_latency::total 36983801110 # number of overall MSHR miss cycles 1086system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles 1087system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles 1088system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011220500 # number of WriteReq MSHR uncacheable cycles 1089system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011220500 # number of WriteReq MSHR uncacheable cycles 1090system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435456000 # number of overall MSHR uncacheable cycles 1091system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435456000 # number of overall MSHR uncacheable cycles 1092system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120520 # mshr miss rate for ReadReq accesses 1093system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120520 # mshr miss rate for ReadReq accesses 1094system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049471 # mshr miss rate for WriteReq accesses 1095system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses 1096system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses 1097system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses 1098system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for demand accesses 1099system.cpu.dcache.demand_mshr_miss_rate::total 0.091433 # mshr miss rate for demand accesses 1100system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for overall accesses 1101system.cpu.dcache.overall_mshr_miss_rate::total 0.091433 # mshr miss rate for overall accesses 1102system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25005.302242 # average ReadReq mshr miss latency 1103system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25005.302242 # average ReadReq mshr miss latency 1104system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33679.107330 # average WriteReq mshr miss latency 1105system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33679.107330 # average WriteReq mshr miss latency 1106system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11255.097003 # average LoadLockedReq mshr miss latency 1107system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11255.097003 # average LoadLockedReq mshr miss latency 1108system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency 1109system.cpu.dcache.demand_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency 1110system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency 1111system.cpu.dcache.overall_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency | 1056system.cpu.dcache.writebacks::writebacks 834526 # number of writebacks 1057system.cpu.dcache.writebacks::total 834526 # number of writebacks 1058system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069193 # number of ReadReq MSHR misses 1059system.cpu.dcache.ReadReq_mshr_misses::total 1069193 # number of ReadReq MSHR misses 1060system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304207 # number of WriteReq MSHR misses 1061system.cpu.dcache.WriteReq_mshr_misses::total 304207 # number of WriteReq MSHR misses 1062system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17214 # number of LoadLockedReq MSHR misses 1063system.cpu.dcache.LoadLockedReq_mshr_misses::total 17214 # number of LoadLockedReq MSHR misses 1064system.cpu.dcache.demand_mshr_misses::cpu.data 1373400 # number of demand (read+write) MSHR misses 1065system.cpu.dcache.demand_mshr_misses::total 1373400 # number of demand (read+write) MSHR misses 1066system.cpu.dcache.overall_mshr_misses::cpu.data 1373400 # number of overall MSHR misses 1067system.cpu.dcache.overall_mshr_misses::total 1373400 # number of overall MSHR misses 1068system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26734131250 # number of ReadReq MSHR miss cycles 1069system.cpu.dcache.ReadReq_mshr_miss_latency::total 26734131250 # number of ReadReq MSHR miss cycles 1070system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245126618 # number of WriteReq MSHR miss cycles 1071system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245126618 # number of WriteReq MSHR miss cycles 1072system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles 1073system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles 1074system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36979257868 # number of demand (read+write) MSHR miss cycles 1075system.cpu.dcache.demand_mshr_miss_latency::total 36979257868 # number of demand (read+write) MSHR miss cycles 1076system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36979257868 # number of overall MSHR miss cycles 1077system.cpu.dcache.overall_mshr_miss_latency::total 36979257868 # number of overall MSHR miss cycles 1078system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles 1079system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles 1080system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles 1081system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles 1082system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435455500 # number of overall MSHR uncacheable cycles 1083system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435455500 # number of overall MSHR uncacheable cycles 1084system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120516 # mshr miss rate for ReadReq accesses 1085system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120516 # mshr miss rate for ReadReq accesses 1086system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049467 # mshr miss rate for WriteReq accesses 1087system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049467 # mshr miss rate for WriteReq accesses 1088system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085963 # mshr miss rate for LoadLockedReq accesses 1089system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085963 # mshr miss rate for LoadLockedReq accesses 1090system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for demand accesses 1091system.cpu.dcache.demand_mshr_miss_rate::total 0.091429 # mshr miss rate for demand accesses 1092system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for overall accesses 1093system.cpu.dcache.overall_mshr_miss_rate::total 0.091429 # mshr miss rate for overall accesses 1094system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25004.027570 # average ReadReq mshr miss latency 1095system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25004.027570 # average ReadReq mshr miss latency 1096system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33678.142245 # average WriteReq mshr miss latency 1097system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33678.142245 # average WriteReq mshr miss latency 1098system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11254.327873 # average LoadLockedReq mshr miss latency 1099system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11254.327873 # average LoadLockedReq mshr miss latency 1100system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency 1101system.cpu.dcache.demand_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency 1102system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency 1103system.cpu.dcache.overall_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency |
| 1112system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1113system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1114system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1115system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1116system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1117system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1118system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1104system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1105system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1106system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1107system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1108system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1109system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1110system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1119system.cpu.toL2Bus.throughput 105186760 # Throughput (bytes/s) 1120system.cpu.toL2Bus.trans_dist::ReadReq 2022129 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::ReadResp 2022112 # Transaction distribution | 1111system.cpu.toL2Bus.throughput 106562255 # Throughput (bytes/s) 1112system.cpu.toL2Bus.trans_dist::ReadReq 2021905 # Transaction distribution 1113system.cpu.toL2Bus.trans_dist::ReadResp 2021888 # Transaction distribution |
| 1122system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution | 1114system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution 1115system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution |
| 1124system.cpu.toL2Bus.trans_dist::Writeback 834591 # Transaction distribution | 1116system.cpu.toL2Bus.trans_dist::Writeback 834526 # Transaction distribution 1117system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41563 # Transaction distribution |
| 1125system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution | 1118system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1119system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution |
| 1127system.cpu.toL2Bus.trans_dist::ReadExReq 345775 # Transaction distribution 1128system.cpu.toL2Bus.trans_dist::ReadExResp 304224 # Transaction distribution 1129system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857072 # Packet count per connected master and slave (bytes) 1130system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649346 # Packet count per connected master and slave (bytes) 1131system.cpu.toL2Bus.pkt_count::total 5506418 # Packet count per connected master and slave (bytes) 1132system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59425664 # Cumulative packet size per connected master and slave (bytes) 1133system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142473420 # Cumulative packet size per connected master and slave (bytes) 1134system.cpu.toL2Bus.tot_pkt_size::total 201899084 # Cumulative packet size per connected master and slave (bytes) 1135system.cpu.toL2Bus.data_through_bus 201889036 # Total data (bytes) 1136system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) 1137system.cpu.toL2Bus.reqLayer0.occupancy 2424633500 # Layer occupancy (ticks) | 1120system.cpu.toL2Bus.trans_dist::ReadExReq 304190 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::ReadExResp 304190 # Transaction distribution 1122system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856770 # Packet count per connected master and slave (bytes) 1123system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649068 # Packet count per connected master and slave (bytes) 1124system.cpu.toL2Bus.pkt_count::total 5505838 # Packet count per connected master and slave (bytes) 1125system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59416000 # Cumulative packet size per connected master and slave (bytes) 1126system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142462412 # Cumulative packet size per connected master and slave (bytes) 1127system.cpu.toL2Bus.tot_pkt_size::total 201878412 # Cumulative packet size per connected master and slave (bytes) 1128system.cpu.toL2Bus.data_through_bus 201868428 # Total data (bytes) 1129system.cpu.toL2Bus.snoop_data_through_bus 2671296 # Total snoop data (bytes) 1130system.cpu.toL2Bus.reqLayer0.occupancy 2424407500 # Layer occupancy (ticks) |
| 1138system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1131system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1139system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) | 1132system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) |
| 1140system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1133system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1141system.cpu.toL2Bus.respLayer0.occupancy 1395400760 # Layer occupancy (ticks) | 1134system.cpu.toL2Bus.respLayer0.occupancy 1395179500 # Layer occupancy (ticks) |
| 1142system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1135system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1143system.cpu.toL2Bus.respLayer1.occupancy 2186975140 # Layer occupancy (ticks) | 1136system.cpu.toL2Bus.respLayer1.occupancy 2186860632 # Layer occupancy (ticks) |
| 1144system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1145 1146---------- End Simulation Statistics ---------- | 1137system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1138 1139---------- End Simulation Statistics ---------- |