| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.920416 # Number of seconds simulated 4sim_ticks 1920416181000 # Number of ticks simulated 5final_tick 1920416181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.919447 # Number of seconds simulated 4sim_ticks 1919446558000 # Number of ticks simulated 5final_tick 1919446558000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1752736 # Simulator instruction rate (inst/s) 8host_op_rate 1752735 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59896862792 # Simulator tick rate (ticks/s) 10host_mem_usage 308520 # Number of bytes of host memory used 11host_seconds 32.06 # Real time elapsed on the host 12sim_insts 56196255 # Number of instructions simulated 13sim_ops 56196255 # Number of ops (including micro ops) simulated | 7host_inst_rate 885398 # Simulator instruction rate (inst/s) 8host_op_rate 885398 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 30291378157 # Simulator tick rate (ticks/s) 10host_mem_usage 344696 # Number of bytes of host memory used 11host_seconds 63.37 # Real time elapsed on the host 12sim_insts 56104177 # Number of instructions simulated 13sim_ops 56104177 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 24858240 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 28363328 # Number of bytes read from this memory | 19system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory |
| 20system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory | 20system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory |
| 22system.physmem.bytes_written::writebacks 7405888 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7405888 # Number of bytes written to this memory | 22system.physmem.bytes_written::writebacks 7404032 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7404032 # Number of bytes written to this memory |
| 24system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory | 24system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory | 25system.physmem.num_reads::cpu.data 388410 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory | 26system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::total 443177 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115717 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115717 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 443004 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 12945227 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 1381134 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 14769365 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 443004 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 443004 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 3856397 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 3856397 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 3856397 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 443004 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 12945227 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 1381134 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 18625763 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 443177 # Number of read requests accepted 44system.physmem.writeReqs 115717 # Number of write requests accepted 45system.physmem.readBursts 443177 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 115717 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 28355584 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7404416 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 28363328 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7405888 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue | 27system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115688 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115688 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 443228 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 12950733 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 1381832 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 14775792 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 443228 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 443228 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 3857379 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 3857379 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 3857379 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 443228 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 12950733 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 1381832 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 18633171 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 443146 # Number of read requests accepted 44system.physmem.writeReqs 115688 # Number of write requests accepted 45system.physmem.readBursts 443146 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 115688 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 28353856 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7402304 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 28361344 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7404032 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue |
| 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write | 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write |
| 55system.physmem.perBankRdBursts::0 27851 # Per bank write bursts 56system.physmem.perBankRdBursts::1 28132 # Per bank write bursts 57system.physmem.perBankRdBursts::2 28319 # Per bank write bursts 58system.physmem.perBankRdBursts::3 28010 # Per bank write bursts 59system.physmem.perBankRdBursts::4 27531 # Per bank write bursts 60system.physmem.perBankRdBursts::5 27552 # Per bank write bursts 61system.physmem.perBankRdBursts::6 26732 # Per bank write bursts 62system.physmem.perBankRdBursts::7 26855 # Per bank write bursts 63system.physmem.perBankRdBursts::8 27890 # Per bank write bursts 64system.physmem.perBankRdBursts::9 27110 # Per bank write bursts 65system.physmem.perBankRdBursts::10 27744 # Per bank write bursts 66system.physmem.perBankRdBursts::11 27465 # Per bank write bursts 67system.physmem.perBankRdBursts::12 27482 # Per bank write bursts 68system.physmem.perBankRdBursts::13 28199 # Per bank write bursts 69system.physmem.perBankRdBursts::14 28116 # Per bank write bursts 70system.physmem.perBankRdBursts::15 28068 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7630 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7636 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7854 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7535 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7127 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6994 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6317 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6319 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7309 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6529 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7110 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6915 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7060 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7819 # Per bank write bursts 85system.physmem.perBankWrBursts::14 7860 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7680 # Per bank write bursts | 55system.physmem.perBankRdBursts::0 27768 # Per bank write bursts 56system.physmem.perBankRdBursts::1 28019 # Per bank write bursts 57system.physmem.perBankRdBursts::2 28336 # Per bank write bursts 58system.physmem.perBankRdBursts::3 28020 # Per bank write bursts 59system.physmem.perBankRdBursts::4 27518 # Per bank write bursts 60system.physmem.perBankRdBursts::5 27546 # Per bank write bursts 61system.physmem.perBankRdBursts::6 26737 # Per bank write bursts 62system.physmem.perBankRdBursts::7 26852 # Per bank write bursts 63system.physmem.perBankRdBursts::8 27860 # Per bank write bursts 64system.physmem.perBankRdBursts::9 27104 # Per bank write bursts 65system.physmem.perBankRdBursts::10 27841 # Per bank write bursts 66system.physmem.perBankRdBursts::11 27413 # Per bank write bursts 67system.physmem.perBankRdBursts::12 27378 # Per bank write bursts 68system.physmem.perBankRdBursts::13 28201 # Per bank write bursts 69system.physmem.perBankRdBursts::14 28236 # Per bank write bursts 70system.physmem.perBankRdBursts::15 28200 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7550 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7529 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7869 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7540 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7115 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6983 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6321 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6313 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7293 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6538 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7205 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6861 # Per bank write bursts 83system.physmem.perBankWrBursts::12 6964 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7821 # Per bank write bursts 85system.physmem.perBankWrBursts::14 7979 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7780 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 11 # Number of times write queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 11 # Number of times write queue was full causing retry |
| 89system.physmem.totGap 1920404309000 # Total gap between requests | 89system.physmem.totGap 1919434637000 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 443177 # Read request sizes (log2) | 96system.physmem.readPktSize::6 443146 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 115717 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 402196 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 1714 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 1586 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 1056 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1122 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 4268 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 3790 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 3793 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3969 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 2575 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 2119 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2033 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1897 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1793 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1556 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 1524 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 1560 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 1710 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 1268 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 115688 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 401962 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 1642 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 2685 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 1248 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1966 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 3974 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 2507 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 2187 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 2134 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2102 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1622 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1616 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1907 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 1876 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 2136 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 1224 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 966 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 883 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see |
| 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 151system.physmem.wrQLenPdf::15 1547 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1870 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 2302 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 4388 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 4414 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4425 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 4435 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4520 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4492 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4550 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 6087 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 4874 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6417 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 5284 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 5514 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 5555 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5389 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 1180 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 1138 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 1092 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 1057 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 1105 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 1067 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1057 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 1183 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1517 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1561 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1644 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 1709 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 1772 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 1718 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 1911 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 1872 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 1806 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 1830 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 1705 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 1482 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 1269 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 917 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 667 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 286 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 25 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 46117 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 658.429646 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 435.074403 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 420.347464 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 7559 16.39% 16.39% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 6338 13.74% 30.13% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 2663 5.77% 35.91% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1600 3.47% 39.38% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1319 2.86% 42.24% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 861 1.87% 44.11% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 594 1.29% 45.39% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 461 1.00% 46.39% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 24722 53.61% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 46117 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 6598 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 67.149288 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2598.278449 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 6595 99.95% 99.95% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::total 6598 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 6598 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 17.534707 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 17.278859 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 3.820387 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16 4179 63.34% 63.34% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::17 322 4.88% 68.22% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::18 428 6.49% 74.70% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::19 1303 19.75% 94.45% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20 22 0.33% 94.79% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::21 17 0.26% 95.04% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::22 11 0.17% 95.21% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::23 27 0.41% 95.62% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24 43 0.65% 96.27% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::25 28 0.42% 96.70% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::26 21 0.32% 97.01% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::27 25 0.38% 97.39% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28 19 0.29% 97.68% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::29 43 0.65% 98.33% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::30 4 0.06% 98.39% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::31 12 0.18% 98.58% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::32 10 0.15% 98.73% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::33 1 0.02% 98.74% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::34 5 0.08% 98.82% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::35 4 0.06% 98.88% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::37 5 0.08% 99.01% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::38 2 0.03% 99.05% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::39 9 0.14% 99.18% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::40 4 0.06% 99.24% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::41 4 0.06% 99.30% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::42 1 0.02% 99.32% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::43 2 0.03% 99.35% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::44 3 0.05% 99.39% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::45 1 0.02% 99.41% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::46 1 0.02% 99.42% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::47 6 0.09% 99.52% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::48 8 0.12% 99.64% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::49 5 0.08% 99.71% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::50 6 0.09% 99.80% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::52 3 0.05% 99.85% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::53 1 0.02% 99.86% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::54 4 0.06% 99.92% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::55 2 0.03% 99.95% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::56 1 0.02% 99.97% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::57 1 0.02% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::58 1 0.02% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::total 6598 # Writes before turning the bus around for reads 269system.physmem.totQLat 7790286250 # Total ticks spent queuing 270system.physmem.totMemAccLat 16274878750 # Total ticks spent from burst creation until serviced by the DRAM 271system.physmem.totBusLat 2215280000 # Total ticks spent in databus transfers 272system.physmem.totBankLat 6269312500 # Total ticks spent accessing banks 273system.physmem.avgQLat 17583.07 # Average queueing delay per DRAM burst 274system.physmem.avgBankLat 14150.16 # Average bank access latency per DRAM burst | 151system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1478 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 4562 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 4579 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 4593 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4592 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 4608 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4699 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4858 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4946 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 5128 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5326 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 5448 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 5540 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 5685 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 5621 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5715 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 897 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 915 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 934 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 861 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 945 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1033 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 949 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1139 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1162 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1146 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1232 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 1390 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 1625 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 1897 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 2098 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 1909 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 1878 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 1683 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 1684 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 1800 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 1629 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 867 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 418 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 235 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 155 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 538.261302 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 328.855989 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 417.099114 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 14887 22.41% 22.41% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 11472 17.27% 39.68% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4684 7.05% 46.73% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 3132 4.71% 51.45% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 3072 4.62% 56.07% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1874 2.82% 58.89% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1342 2.02% 60.91% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1444 2.17% 63.09% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 24522 36.91% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 6775 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 65.389077 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 16.529238 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 2564.130292 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-8191 6772 99.96% 99.96% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 6775 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 6775 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 17.071734 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 16.848509 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 3.695111 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16 5062 74.72% 74.72% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::17 127 1.87% 76.59% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::18 1207 17.82% 94.41% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::19 25 0.37% 94.77% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::20 12 0.18% 94.95% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::21 16 0.24% 95.19% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::22 18 0.27% 95.45% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::23 98 1.45% 96.90% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::25 41 0.61% 97.83% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::26 20 0.30% 98.13% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::27 8 0.12% 98.24% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28 7 0.10% 98.35% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::29 8 0.12% 98.46% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::30 7 0.10% 98.57% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::31 15 0.22% 98.79% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::32 9 0.13% 98.92% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::33 1 0.01% 98.94% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::34 1 0.01% 98.95% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::35 1 0.01% 98.97% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::37 1 0.01% 98.98% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::38 1 0.01% 99.00% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::39 4 0.06% 99.06% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::40 9 0.13% 99.19% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::41 8 0.12% 99.31% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::42 2 0.03% 99.34% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::43 2 0.03% 99.37% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::44 2 0.03% 99.39% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::45 1 0.01% 99.41% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::47 8 0.12% 99.54% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::48 7 0.10% 99.65% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::49 1 0.01% 99.66% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::50 2 0.03% 99.69% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::51 2 0.03% 99.72% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::52 1 0.01% 99.73% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::54 1 0.01% 99.75% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::56 7 0.10% 99.85% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::57 9 0.13% 99.99% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::59 1 0.01% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 6775 # Writes before turning the bus around for reads 268system.physmem.totQLat 7315796250 # Total ticks spent queuing 269system.physmem.totMemAccLat 15622590000 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 2215145000 # Total ticks spent in databus transfers 271system.physmem.avgQLat 16513.13 # Average queueing delay per DRAM burst |
| 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 276system.physmem.avgMemAccLat 36733.23 # Average memory access latency per DRAM burst | 273system.physmem.avgMemAccLat 35263.13 # Average memory access latency per DRAM burst |
| 277system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s | 274system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s 275system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s |
| 279system.physmem.avgRdBWSys 14.77 # Average system read bandwidth in MiByte/s | 276system.physmem.avgRdBWSys 14.78 # Average system read bandwidth in MiByte/s |
| 280system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 282system.physmem.busUtil 0.15 # Data bus utilization in percentage 283system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 285system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing | 277system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 279system.physmem.busUtil 0.15 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 281system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 282system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing |
| 286system.physmem.avgWrQLen 24.59 # Average write queue length when enqueuing 287system.physmem.readRowHits 398457 # Number of row buffer hits during reads 288system.physmem.writeRowHits 94179 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 81.39 # Row buffer hit rate for writes 291system.physmem.avgGap 3436079.67 # Average gap between requests 292system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined 293system.physmem.prechargeAllPercent 0.57 # Percentage of time for which DRAM has all the banks in precharge state 294system.membus.throughput 18667397 # Throughput (bytes/s) 295system.membus.trans_dist::ReadReq 292363 # Transaction distribution 296system.membus.trans_dist::ReadResp 292363 # Transaction distribution 297system.membus.trans_dist::WriteReq 9650 # Transaction distribution 298system.membus.trans_dist::WriteResp 9650 # Transaction distribution 299system.membus.trans_dist::Writeback 115717 # Transaction distribution | 283system.physmem.avgWrQLen 23.40 # Average write queue length when enqueuing 284system.physmem.readRowHits 398273 # Number of row buffer hits during reads 285system.physmem.writeRowHits 93988 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 81.24 # Row buffer hit rate for writes 288system.physmem.avgGap 3434713.42 # Average gap between requests 289system.physmem.pageHitRate 88.11 # Row buffer hit rate, read and write combined 290system.physmem.memoryStateTime::IDLE 1800016178000 # Time in different power states 291system.physmem.memoryStateTime::REF 64094420000 # Time in different power states 292system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 293system.physmem.memoryStateTime::ACT 55332653250 # Time in different power states 294system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 295system.membus.throughput 18674823 # Throughput (bytes/s) 296system.membus.trans_dist::ReadReq 292356 # Transaction distribution 297system.membus.trans_dist::ReadResp 292356 # Transaction distribution 298system.membus.trans_dist::WriteReq 9649 # Transaction distribution 299system.membus.trans_dist::WriteResp 9649 # Transaction distribution 300system.membus.trans_dist::Writeback 115688 # Transaction distribution |
| 300system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 301system.membus.trans_dist::UpgradeResp 132 # Transaction distribution | 301system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 302system.membus.trans_dist::UpgradeResp 132 # Transaction distribution |
| 302system.membus.trans_dist::ReadExReq 158297 # Transaction distribution 303system.membus.trans_dist::ReadExResp 158297 # Transaction distribution 304system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878206 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911366 # Packet count per connected master and slave (bytes) | 303system.membus.trans_dist::ReadExReq 158273 # Transaction distribution 304system.membus.trans_dist::ReadExResp 158273 # Transaction distribution 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878115 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911273 # Packet count per connected master and slave (bytes) |
| 307system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) 308system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) | 308system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) |
| 309system.membus.pkt_count::total 1036046 # Packet count per connected master and slave (bytes) 310system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30460096 # Cumulative packet size per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30504660 # Cumulative packet size per connected master and slave (bytes) | 310system.membus.pkt_count::total 1035953 # Packet count per connected master and slave (bytes) 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456256 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30500812 # Cumulative packet size per connected master and slave (bytes) |
| 313system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) | 314system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) 315system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) |
| 315system.membus.tot_pkt_size::total 35813780 # Cumulative packet size per connected master and slave (bytes) 316system.membus.data_through_bus 35813780 # Total data (bytes) | 316system.membus.tot_pkt_size::total 35809932 # Cumulative packet size per connected master and slave (bytes) 317system.membus.data_through_bus 35809932 # Total data (bytes) |
| 317system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) | 318system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) |
| 318system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) | 319system.membus.reqLayer0.occupancy 32376000 # Layer occupancy (ticks) |
| 319system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 320system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 320system.membus.reqLayer1.occupancy 1492987250 # Layer occupancy (ticks) | 321system.membus.reqLayer1.occupancy 1491996000 # Layer occupancy (ticks) |
| 321system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 322system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 322system.membus.respLayer1.occupancy 3752965347 # Layer occupancy (ticks) | 323system.membus.respLayer1.occupancy 3751677600 # Layer occupancy (ticks) |
| 323system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 324system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 324system.membus.respLayer2.occupancy 376688000 # Layer occupancy (ticks) | 325system.membus.respLayer2.occupancy 376660500 # Layer occupancy (ticks) |
| 325system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 326system.iocache.tags.replacements 41685 # number of replacements | 326system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 327system.iocache.tags.replacements 41685 # number of replacements |
| 327system.iocache.tags.tagsinuse 1.344147 # Cycle average of tags in use | 328system.iocache.tags.tagsinuse 1.344872 # Cycle average of tags in use |
| 328system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 329system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 330system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 329system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 330system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 331system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 331system.iocache.tags.warmup_cycle 1754500427000 # Cycle when the warmup percentage was hit. 332system.iocache.tags.occ_blocks::tsunami.ide 1.344147 # Average occupied blocks per requestor 333system.iocache.tags.occ_percent::tsunami.ide 0.084009 # Average percentage of cache occupancy 334system.iocache.tags.occ_percent::total 0.084009 # Average percentage of cache occupancy | 332system.iocache.tags.warmup_cycle 1753525004000 # Cycle when the warmup percentage was hit. 333system.iocache.tags.occ_blocks::tsunami.ide 1.344872 # Average occupied blocks per requestor 334system.iocache.tags.occ_percent::tsunami.ide 0.084054 # Average percentage of cache occupancy 335system.iocache.tags.occ_percent::total 0.084054 # Average percentage of cache occupancy |
| 335system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 336system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 337system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 338system.iocache.tags.tag_accesses 375525 # Number of tag accesses 339system.iocache.tags.data_accesses 375525 # Number of data accesses 340system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 341system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 342system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 343system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 344system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 345system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 346system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 347system.iocache.overall_misses::total 41725 # number of overall misses | 336system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 337system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 338system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 339system.iocache.tags.tag_accesses 375525 # Number of tag accesses 340system.iocache.tags.data_accesses 375525 # Number of data accesses 341system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 342system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 343system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 344system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 345system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 346system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 347system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 348system.iocache.overall_misses::total 41725 # number of overall misses |
| 348system.iocache.ReadReq_miss_latency::tsunami.ide 21134633 # number of ReadReq miss cycles 349system.iocache.ReadReq_miss_latency::total 21134633 # number of ReadReq miss cycles 350system.iocache.WriteReq_miss_latency::tsunami.ide 13148459442 # number of WriteReq miss cycles 351system.iocache.WriteReq_miss_latency::total 13148459442 # number of WriteReq miss cycles 352system.iocache.demand_miss_latency::tsunami.ide 13169594075 # number of demand (read+write) miss cycles 353system.iocache.demand_miss_latency::total 13169594075 # number of demand (read+write) miss cycles 354system.iocache.overall_miss_latency::tsunami.ide 13169594075 # number of overall miss cycles 355system.iocache.overall_miss_latency::total 13169594075 # number of overall miss cycles | 349system.iocache.ReadReq_miss_latency::tsunami.ide 21253133 # number of ReadReq miss cycles 350system.iocache.ReadReq_miss_latency::total 21253133 # number of ReadReq miss cycles 351system.iocache.WriteReq_miss_latency::tsunami.ide 12447285431 # number of WriteReq miss cycles 352system.iocache.WriteReq_miss_latency::total 12447285431 # number of WriteReq miss cycles 353system.iocache.demand_miss_latency::tsunami.ide 12468538564 # number of demand (read+write) miss cycles 354system.iocache.demand_miss_latency::total 12468538564 # number of demand (read+write) miss cycles 355system.iocache.overall_miss_latency::tsunami.ide 12468538564 # number of overall miss cycles 356system.iocache.overall_miss_latency::total 12468538564 # number of overall miss cycles |
| 356system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 357system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 358system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 359system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 360system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 361system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 362system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 363system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 364system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 365system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 366system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 367system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 368system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 369system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 370system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 371system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 357system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 358system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 359system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 360system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 361system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 362system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 363system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 364system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 365system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 366system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 367system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 368system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 369system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 370system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 371system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 372system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 372system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122165.508671 # average ReadReq miss latency 373system.iocache.ReadReq_avg_miss_latency::total 122165.508671 # average ReadReq miss latency 374system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316433.852570 # average WriteReq miss latency 375system.iocache.WriteReq_avg_miss_latency::total 316433.852570 # average WriteReq miss latency 376system.iocache.demand_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency 377system.iocache.demand_avg_miss_latency::total 315628.378071 # average overall miss latency 378system.iocache.overall_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency 379system.iocache.overall_avg_miss_latency::total 315628.378071 # average overall miss latency 380system.iocache.blocked_cycles::no_mshrs 393896 # number of cycles access was blocked | 373system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122850.479769 # average ReadReq miss latency 374system.iocache.ReadReq_avg_miss_latency::total 122850.479769 # average ReadReq miss latency 375system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299559.237365 # average WriteReq miss latency 376system.iocache.WriteReq_avg_miss_latency::total 299559.237365 # average WriteReq miss latency 377system.iocache.demand_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency 378system.iocache.demand_avg_miss_latency::total 298826.568340 # average overall miss latency 379system.iocache.overall_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency 380system.iocache.overall_avg_miss_latency::total 298826.568340 # average overall miss latency 381system.iocache.blocked_cycles::no_mshrs 365803 # number of cycles access was blocked |
| 381system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 382system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 382system.iocache.blocked::no_mshrs 28296 # number of cycles access was blocked | 383system.iocache.blocked::no_mshrs 28265 # number of cycles access was blocked |
| 383system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 384system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 384system.iocache.avg_blocked_cycles::no_mshrs 13.920554 # average number of cycles each access was blocked | 385system.iocache.avg_blocked_cycles::no_mshrs 12.941907 # average number of cycles each access was blocked |
| 385system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 386system.iocache.fast_writes 0 # number of fast writes performed 387system.iocache.cache_copies 0 # number of cache copies performed 388system.iocache.writebacks::writebacks 41512 # number of writebacks 389system.iocache.writebacks::total 41512 # number of writebacks 390system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 391system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 392system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 393system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 394system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 395system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 396system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 397system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 386system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 387system.iocache.fast_writes 0 # number of fast writes performed 388system.iocache.cache_copies 0 # number of cache copies performed 389system.iocache.writebacks::writebacks 41512 # number of writebacks 390system.iocache.writebacks::total 41512 # number of writebacks 391system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 392system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 393system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 394system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 395system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 396system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 397system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 398system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 398system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137633 # number of ReadReq MSHR miss cycles 399system.iocache.ReadReq_mshr_miss_latency::total 12137633 # number of ReadReq MSHR miss cycles 400system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10985430442 # number of WriteReq MSHR miss cycles 401system.iocache.WriteReq_mshr_miss_latency::total 10985430442 # number of WriteReq MSHR miss cycles 402system.iocache.demand_mshr_miss_latency::tsunami.ide 10997568075 # number of demand (read+write) MSHR miss cycles 403system.iocache.demand_mshr_miss_latency::total 10997568075 # number of demand (read+write) MSHR miss cycles 404system.iocache.overall_mshr_miss_latency::tsunami.ide 10997568075 # number of overall MSHR miss cycles 405system.iocache.overall_mshr_miss_latency::total 10997568075 # number of overall MSHR miss cycles | 399system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12255133 # number of ReadReq MSHR miss cycles 400system.iocache.ReadReq_mshr_miss_latency::total 12255133 # number of ReadReq MSHR miss cycles 401system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10284312431 # number of WriteReq MSHR miss cycles 402system.iocache.WriteReq_mshr_miss_latency::total 10284312431 # number of WriteReq MSHR miss cycles 403system.iocache.demand_mshr_miss_latency::tsunami.ide 10296567564 # number of demand (read+write) MSHR miss cycles 404system.iocache.demand_mshr_miss_latency::total 10296567564 # number of demand (read+write) MSHR miss cycles 405system.iocache.overall_mshr_miss_latency::tsunami.ide 10296567564 # number of overall MSHR miss cycles 406system.iocache.overall_mshr_miss_latency::total 10296567564 # number of overall MSHR miss cycles |
| 406system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 407system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 408system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 409system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 410system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 411system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 412system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 413system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 407system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 408system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 409system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 410system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 411system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 412system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 413system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 414system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 414system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70159.728324 # average ReadReq mshr miss latency 415system.iocache.ReadReq_avg_mshr_miss_latency::total 70159.728324 # average ReadReq mshr miss latency 416system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264377.898585 # average WriteReq mshr miss latency 417system.iocache.WriteReq_avg_mshr_miss_latency::total 264377.898585 # average WriteReq mshr miss latency 418system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency 419system.iocache.demand_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency 420system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency 421system.iocache.overall_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency | 415system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70838.919075 # average ReadReq mshr miss latency 416system.iocache.ReadReq_avg_mshr_miss_latency::total 70838.919075 # average ReadReq mshr miss latency 417system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247504.631089 # average WriteReq mshr miss latency 418system.iocache.WriteReq_avg_mshr_miss_latency::total 247504.631089 # average WriteReq mshr miss latency 419system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency 420system.iocache.demand_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency 421system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency 422system.iocache.overall_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency |
| 422system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 423system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 424system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 425system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 426system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 427system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 428system.disk0.dma_write_txs 395 # Number of DMA write transactions. 429system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 430system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 431system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 432system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 433system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 434system.disk2.dma_write_txs 1 # Number of DMA write transactions. 435system.cpu_clk_domain.clock 500 # Clock period in ticks 436system.cpu.dtb.fetch_hits 0 # ITB hits 437system.cpu.dtb.fetch_misses 0 # ITB misses 438system.cpu.dtb.fetch_acv 0 # ITB acv 439system.cpu.dtb.fetch_accesses 0 # ITB accesses | 423system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 424system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 425system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 426system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 427system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 428system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 429system.disk0.dma_write_txs 395 # Number of DMA write transactions. 430system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 431system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 432system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 433system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 434system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 435system.disk2.dma_write_txs 1 # Number of DMA write transactions. 436system.cpu_clk_domain.clock 500 # Clock period in ticks 437system.cpu.dtb.fetch_hits 0 # ITB hits 438system.cpu.dtb.fetch_misses 0 # ITB misses 439system.cpu.dtb.fetch_acv 0 # ITB acv 440system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 440system.cpu.dtb.read_hits 9066711 # DTB read hits 441system.cpu.dtb.read_misses 10324 # DTB read misses | 441system.cpu.dtb.read_hits 9052923 # DTB read hits 442system.cpu.dtb.read_misses 10354 # DTB read misses |
| 442system.cpu.dtb.read_acv 210 # DTB read access violations | 443system.cpu.dtb.read_acv 210 # DTB read access violations |
| 443system.cpu.dtb.read_accesses 728853 # DTB read accesses 444system.cpu.dtb.write_hits 6357503 # DTB write hits 445system.cpu.dtb.write_misses 1142 # DTB write misses | 444system.cpu.dtb.read_accesses 728911 # DTB read accesses 445system.cpu.dtb.write_hits 6349403 # DTB write hits 446system.cpu.dtb.write_misses 1143 # DTB write misses |
| 446system.cpu.dtb.write_acv 157 # DTB write access violations | 447system.cpu.dtb.write_acv 157 # DTB write access violations |
| 447system.cpu.dtb.write_accesses 291931 # DTB write accesses 448system.cpu.dtb.data_hits 15424214 # DTB hits 449system.cpu.dtb.data_misses 11466 # DTB misses | 448system.cpu.dtb.write_accesses 291932 # DTB write accesses 449system.cpu.dtb.data_hits 15402326 # DTB hits 450system.cpu.dtb.data_misses 11497 # DTB misses |
| 450system.cpu.dtb.data_acv 367 # DTB access violations | 451system.cpu.dtb.data_acv 367 # DTB access violations |
| 451system.cpu.dtb.data_accesses 1020784 # DTB accesses 452system.cpu.itb.fetch_hits 4974520 # ITB hits | 452system.cpu.dtb.data_accesses 1020843 # DTB accesses 453system.cpu.itb.fetch_hits 4974965 # ITB hits |
| 453system.cpu.itb.fetch_misses 5010 # ITB misses 454system.cpu.itb.fetch_acv 184 # ITB acv | 454system.cpu.itb.fetch_misses 5010 # ITB misses 455system.cpu.itb.fetch_acv 184 # ITB acv |
| 455system.cpu.itb.fetch_accesses 4979530 # ITB accesses | 456system.cpu.itb.fetch_accesses 4979975 # ITB accesses |
| 456system.cpu.itb.read_hits 0 # DTB read hits 457system.cpu.itb.read_misses 0 # DTB read misses 458system.cpu.itb.read_acv 0 # DTB read access violations 459system.cpu.itb.read_accesses 0 # DTB read accesses 460system.cpu.itb.write_hits 0 # DTB write hits 461system.cpu.itb.write_misses 0 # DTB write misses 462system.cpu.itb.write_acv 0 # DTB write access violations 463system.cpu.itb.write_accesses 0 # DTB write accesses 464system.cpu.itb.data_hits 0 # DTB hits 465system.cpu.itb.data_misses 0 # DTB misses 466system.cpu.itb.data_acv 0 # DTB access violations 467system.cpu.itb.data_accesses 0 # DTB accesses | 457system.cpu.itb.read_hits 0 # DTB read hits 458system.cpu.itb.read_misses 0 # DTB read misses 459system.cpu.itb.read_acv 0 # DTB read access violations 460system.cpu.itb.read_accesses 0 # DTB read accesses 461system.cpu.itb.write_hits 0 # DTB write hits 462system.cpu.itb.write_misses 0 # DTB write misses 463system.cpu.itb.write_acv 0 # DTB write access violations 464system.cpu.itb.write_accesses 0 # DTB write accesses 465system.cpu.itb.data_hits 0 # DTB hits 466system.cpu.itb.data_misses 0 # DTB misses 467system.cpu.itb.data_acv 0 # DTB access violations 468system.cpu.itb.data_accesses 0 # DTB accesses |
| 468system.cpu.numCycles 3840832362 # number of cpu cycles simulated | 469system.cpu.numCycles 3838893116 # number of cpu cycles simulated |
| 469system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 470system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 470system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 471system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 471system.cpu.committedInsts 56196255 # Number of instructions committed 472system.cpu.committedOps 56196255 # Number of ops (including micro ops) committed 473system.cpu.num_int_alu_accesses 52067788 # Number of integer alu accesses 474system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses 475system.cpu.num_func_calls 1483738 # number of times a function call or return occured 476system.cpu.num_conditional_control_insts 6469789 # number of instructions that are conditional controls 477system.cpu.num_int_insts 52067788 # number of integer instructions 478system.cpu.num_fp_insts 324393 # number of float instructions 479system.cpu.num_int_register_reads 71342399 # number of times the integer registers were read 480system.cpu.num_int_register_writes 38531411 # number of times the integer registers were written 481system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read 482system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written 483system.cpu.num_mem_refs 15476821 # number of memory refs 484system.cpu.num_load_insts 9103557 # Number of load instructions 485system.cpu.num_store_insts 6373264 # Number of store instructions 486system.cpu.num_idle_cycles 3589010980.998131 # Number of idle cycles 487system.cpu.num_busy_cycles 251821381.001869 # Number of busy cycles 488system.cpu.not_idle_fraction 0.065564 # Percentage of non-idle cycles 489system.cpu.idle_fraction 0.934436 # Percentage of idle cycles 490system.cpu.Branches 8424076 # Number of branches fetched | 472system.cpu.committedInsts 56104177 # Number of instructions committed 473system.cpu.committedOps 56104177 # Number of ops (including micro ops) committed 474system.cpu.num_int_alu_accesses 51979169 # Number of integer alu accesses 475system.cpu.num_fp_alu_accesses 324594 # Number of float alu accesses 476system.cpu.num_func_calls 1481286 # number of times a function call or return occured 477system.cpu.num_conditional_control_insts 6461218 # number of instructions that are conditional controls 478system.cpu.num_int_insts 51979169 # number of integer instructions 479system.cpu.num_fp_insts 324594 # number of float instructions 480system.cpu.num_int_register_reads 71209746 # number of times the integer registers were read 481system.cpu.num_int_register_writes 38460532 # number of times the integer registers were written 482system.cpu.num_fp_register_reads 163708 # number of times the floating registers were read 483system.cpu.num_fp_register_writes 166588 # number of times the floating registers were written 484system.cpu.num_mem_refs 15454993 # number of memory refs 485system.cpu.num_load_insts 9089820 # Number of load instructions 486system.cpu.num_store_insts 6365173 # Number of store instructions 487system.cpu.num_idle_cycles 3587243859.498131 # Number of idle cycles 488system.cpu.num_busy_cycles 251649256.501869 # Number of busy cycles 489system.cpu.not_idle_fraction 0.065553 # Percentage of non-idle cycles 490system.cpu.idle_fraction 0.934447 # Percentage of idle cycles 491system.cpu.Branches 8413035 # Number of branches fetched 492system.cpu.op_class::No_OpClass 3197761 5.70% 5.70% # Class of executed instruction 493system.cpu.op_class::IntAlu 36186344 64.48% 70.18% # Class of executed instruction 494system.cpu.op_class::IntMult 61011 0.11% 70.29% # Class of executed instruction 495system.cpu.op_class::IntDiv 0 0.00% 70.29% # Class of executed instruction 496system.cpu.op_class::FloatAdd 25613 0.05% 70.34% # Class of executed instruction 497system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction 498system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction 499system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction 500system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction 501system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction 502system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction 503system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction 504system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction 505system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction 506system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction 507system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction 508system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction 509system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction 510system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction 511system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction 512system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction 513system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction 514system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction 515system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction 516system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction 517system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction 518system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction 519system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction 520system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction 521system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction 522system.cpu.op_class::MemRead 9316905 16.60% 86.95% # Class of executed instruction 523system.cpu.op_class::MemWrite 6371245 11.35% 98.30% # Class of executed instruction 524system.cpu.op_class::IprAccess 953526 1.70% 100.00% # Class of executed instruction 525system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 526system.cpu.op_class::total 56116041 # Class of executed instruction |
| 491system.cpu.kern.inst.arm 0 # number of arm instructions executed 492system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed | 527system.cpu.kern.inst.arm 0 # number of arm instructions executed 528system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed |
| 493system.cpu.kern.inst.hwrei 212001 # number of hwrei instructions executed 494system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl | 529system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed 530system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl |
| 495system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl | 531system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl |
| 496system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl 497system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl 498system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl 499system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl | 532system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl 533system.cpu.kern.ipl_count::31 106210 57.99% 100.00% # number of times we switched to this ipl 534system.cpu.kern.ipl_count::total 183167 # number of times we switched to this ipl 535system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl |
| 500system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl | 536system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl |
| 501system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl 502system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl 503system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl 504system.cpu.kern.ipl_ticks::0 1858066400000 96.75% 96.75% # number of cycles we spent at this ipl 505system.cpu.kern.ipl_ticks::21 91407000 0.00% 96.76% # number of cycles we spent at this ipl 506system.cpu.kern.ipl_ticks::22 737349500 0.04% 96.80% # number of cycles we spent at this ipl 507system.cpu.kern.ipl_ticks::31 61520290500 3.20% 100.00% # number of cycles we spent at this ipl 508system.cpu.kern.ipl_ticks::total 1920415447000 # number of cycles we spent at this ipl 509system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl | 537system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl 538system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl 539system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl 540system.cpu.kern.ipl_ticks::0 1857252195000 96.76% 96.76% # number of cycles we spent at this ipl 541system.cpu.kern.ipl_ticks::21 91387500 0.00% 96.76% # number of cycles we spent at this ipl 542system.cpu.kern.ipl_ticks::22 737178000 0.04% 96.80% # number of cycles we spent at this ipl 543system.cpu.kern.ipl_ticks::31 61365063500 3.20% 100.00% # number of cycles we spent at this ipl 544system.cpu.kern.ipl_ticks::total 1919445824000 # number of cycles we spent at this ipl 545system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl |
| 510system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 511system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 546system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 547system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 512system.cpu.kern.ipl_used::31 0.692248 # fraction of swpipl calls that actually changed the ipl 513system.cpu.kern.ipl_used::total 0.814083 # fraction of swpipl calls that actually changed the ipl | 548system.cpu.kern.ipl_used::31 0.692289 # fraction of swpipl calls that actually changed the ipl 549system.cpu.kern.ipl_used::total 0.814110 # fraction of swpipl calls that actually changed the ipl |
| 514system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 515system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 516system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 517system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 518system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 519system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 520system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 521system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 541system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 542system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 543system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 544system.cpu.kern.syscall::total 326 # number of syscalls executed 545system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 546system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 547system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 548system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 550system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 551system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 552system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 553system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 554system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 555system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 556system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 557system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 577system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 578system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 579system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 580system.cpu.kern.syscall::total 326 # number of syscalls executed 581system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 582system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 583system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 584system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 549system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed 550system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed | 585system.cpu.kern.callpal::swpctx 4179 2.17% 2.17% # number of callpals executed 586system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed |
| 551system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 587system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 552system.cpu.kern.callpal::swpipl 175963 91.22% 93.41% # number of callpals executed 553system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed | 588system.cpu.kern.callpal::swpipl 175948 91.21% 93.41% # number of callpals executed 589system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed |
| 554system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 555system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed | 590system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 591system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed |
| 556system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed | 592system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed |
| 557system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed | 593system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed |
| 558system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed | 594system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed |
| 559system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 560system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 595system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 596system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 561system.cpu.kern.callpal::total 192909 # number of callpals executed | 597system.cpu.kern.callpal::total 192895 # number of callpals executed |
| 562system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches 563system.cpu.kern.mode_switch::user 1741 # number of protection mode switches | 598system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches 599system.cpu.kern.mode_switch::user 1741 # number of protection mode switches |
| 564system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches 565system.cpu.kern.mode_good::kernel 1911 | 600system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 601system.cpu.kern.mode_good::kernel 1912 |
| 566system.cpu.kern.mode_good::user 1741 | 602system.cpu.kern.mode_good::user 1741 |
| 567system.cpu.kern.mode_good::idle 170 568system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches | 603system.cpu.kern.mode_good::idle 171 604system.cpu.kern.mode_switch_good::kernel 0.323848 # fraction of useful protection mode switches |
| 569system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 605system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 570system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches 571system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches 572system.cpu.kern.mode_ticks::kernel 46067941500 2.40% 2.40% # number of ticks spent at the given mode 573system.cpu.kern.mode_ticks::user 5182686000 0.27% 2.67% # number of ticks spent at the given mode 574system.cpu.kern.mode_ticks::idle 1869164817500 97.33% 100.00% # number of ticks spent at the given mode 575system.cpu.kern.swap_context 4177 # number of times the context was actually changed | 606system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 607system.cpu.kern.mode_switch_good::total 0.392527 # fraction of useful protection mode switches 608system.cpu.kern.mode_ticks::kernel 46108525500 2.40% 2.40% # number of ticks spent at the given mode 609system.cpu.kern.mode_ticks::user 5189217000 0.27% 2.67% # number of ticks spent at the given mode 610system.cpu.kern.mode_ticks::idle 1868148079500 97.33% 100.00% # number of ticks spent at the given mode 611system.cpu.kern.swap_context 4180 # number of times the context was actually changed |
| 576system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 577system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 578system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 579system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 580system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 581system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 582system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 583system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 599system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 600system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 601system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 602system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 603system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 604system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 605system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 606system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 612system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 613system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 614system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 615system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 616system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 617system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 618system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 619system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 635system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 636system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 637system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 638system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 639system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 640system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 641system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 642system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 607system.iobus.throughput 1409159 # Throughput (bytes/s) | 643system.iobus.throughput 1409867 # Throughput (bytes/s) |
| 608system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 609system.iobus.trans_dist::ReadResp 7103 # Transaction distribution | 644system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 645system.iobus.trans_dist::ReadResp 7103 # Transaction distribution |
| 610system.iobus.trans_dist::WriteReq 51202 # Transaction distribution 611system.iobus.trans_dist::WriteResp 51202 # Transaction distribution 612system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) | 646system.iobus.trans_dist::WriteReq 51201 # Transaction distribution 647system.iobus.trans_dist::WriteResp 51201 # Transaction distribution 648system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) |
| 613system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 614system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 615system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 616system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 617system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 618system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 619system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 620system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 621system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 622system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 623system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 649system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 650system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 651system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 652system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 653system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 654system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 655system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 656system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 657system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 658system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 659system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 624system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) | 660system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) |
| 625system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 626system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) | 661system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 662system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) |
| 627system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) 628system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) | 663system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) 664system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) |
| 629system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 665system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 666system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 667system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 668system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 669system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 670system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 671system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 672system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 673system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 674system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 675system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 640system.iobus.tot_pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) | 676system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) |
| 641system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 642system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) | 677system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 678system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) |
| 643system.iobus.tot_pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) 644system.iobus.data_through_bus 2706172 # Total data (bytes) 645system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) | 679system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) 680system.iobus.data_through_bus 2706164 # Total data (bytes) 681system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) |
| 646system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 647system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 648system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 649system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 650system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 651system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 652system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 653system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 659system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 660system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 662system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 663system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 664system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 665system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 666system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 682system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 683system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 684system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 685system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 686system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 687system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 688system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 689system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 695system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 696system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 697system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 698system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 699system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 700system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 701system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 702system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 667system.iobus.reqLayer29.occupancy 380034075 # Layer occupancy (ticks) | 703system.iobus.reqLayer29.occupancy 380199064 # Layer occupancy (ticks) |
| 668system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 669system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 670system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | 704system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 705system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 706system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) |
| 671system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) | 707system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) |
| 672system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 708system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 673system.iobus.respLayer1.occupancy 43162000 # Layer occupancy (ticks) | 709system.iobus.respLayer1.occupancy 43233500 # Layer occupancy (ticks) |
| 674system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 710system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 675system.cpu.icache.tags.replacements 928494 # number of replacements 676system.cpu.icache.tags.tagsinuse 508.301721 # Cycle average of tags in use 677system.cpu.icache.tags.total_refs 55278924 # Total number of references to valid blocks. 678system.cpu.icache.tags.sampled_refs 929005 # Sample count of references to valid blocks. 679system.cpu.icache.tags.avg_refs 59.503365 # Average number of references to valid blocks. 680system.cpu.icache.tags.warmup_cycle 39895254250 # Cycle when the warmup percentage was hit. 681system.cpu.icache.tags.occ_blocks::cpu.inst 508.301721 # Average occupied blocks per requestor 682system.cpu.icache.tags.occ_percent::cpu.inst 0.992777 # Average percentage of cache occupancy 683system.cpu.icache.tags.occ_percent::total 0.992777 # Average percentage of cache occupancy | 711system.cpu.icache.tags.replacements 927875 # number of replacements 712system.cpu.icache.tags.tagsinuse 508.303976 # Cycle average of tags in use 713system.cpu.icache.tags.total_refs 55187496 # Total number of references to valid blocks. 714system.cpu.icache.tags.sampled_refs 928386 # Sample count of references to valid blocks. 715system.cpu.icache.tags.avg_refs 59.444559 # Average number of references to valid blocks. 716system.cpu.icache.tags.warmup_cycle 39855277250 # Cycle when the warmup percentage was hit. 717system.cpu.icache.tags.occ_blocks::cpu.inst 508.303976 # Average occupied blocks per requestor 718system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy 719system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy |
| 684system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 685system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id | 720system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 721system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id |
| 686system.cpu.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id | 722system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 723system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id |
| 688system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 689system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 724system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 725system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 690system.cpu.icache.tags.tag_accesses 57137254 # Number of tag accesses 691system.cpu.icache.tags.data_accesses 57137254 # Number of data accesses 692system.cpu.icache.ReadReq_hits::cpu.inst 55278924 # number of ReadReq hits 693system.cpu.icache.ReadReq_hits::total 55278924 # number of ReadReq hits 694system.cpu.icache.demand_hits::cpu.inst 55278924 # number of demand (read+write) hits 695system.cpu.icache.demand_hits::total 55278924 # number of demand (read+write) hits 696system.cpu.icache.overall_hits::cpu.inst 55278924 # number of overall hits 697system.cpu.icache.overall_hits::total 55278924 # number of overall hits 698system.cpu.icache.ReadReq_misses::cpu.inst 929165 # number of ReadReq misses 699system.cpu.icache.ReadReq_misses::total 929165 # number of ReadReq misses 700system.cpu.icache.demand_misses::cpu.inst 929165 # number of demand (read+write) misses 701system.cpu.icache.demand_misses::total 929165 # number of demand (read+write) misses 702system.cpu.icache.overall_misses::cpu.inst 929165 # number of overall misses 703system.cpu.icache.overall_misses::total 929165 # number of overall misses 704system.cpu.icache.ReadReq_miss_latency::cpu.inst 12919006759 # number of ReadReq miss cycles 705system.cpu.icache.ReadReq_miss_latency::total 12919006759 # number of ReadReq miss cycles 706system.cpu.icache.demand_miss_latency::cpu.inst 12919006759 # number of demand (read+write) miss cycles 707system.cpu.icache.demand_miss_latency::total 12919006759 # number of demand (read+write) miss cycles 708system.cpu.icache.overall_miss_latency::cpu.inst 12919006759 # number of overall miss cycles 709system.cpu.icache.overall_miss_latency::total 12919006759 # number of overall miss cycles 710system.cpu.icache.ReadReq_accesses::cpu.inst 56208089 # number of ReadReq accesses(hits+misses) 711system.cpu.icache.ReadReq_accesses::total 56208089 # number of ReadReq accesses(hits+misses) 712system.cpu.icache.demand_accesses::cpu.inst 56208089 # number of demand (read+write) accesses 713system.cpu.icache.demand_accesses::total 56208089 # number of demand (read+write) accesses 714system.cpu.icache.overall_accesses::cpu.inst 56208089 # number of overall (read+write) accesses 715system.cpu.icache.overall_accesses::total 56208089 # number of overall (read+write) accesses 716system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016531 # miss rate for ReadReq accesses 717system.cpu.icache.ReadReq_miss_rate::total 0.016531 # miss rate for ReadReq accesses 718system.cpu.icache.demand_miss_rate::cpu.inst 0.016531 # miss rate for demand accesses 719system.cpu.icache.demand_miss_rate::total 0.016531 # miss rate for demand accesses 720system.cpu.icache.overall_miss_rate::cpu.inst 0.016531 # miss rate for overall accesses 721system.cpu.icache.overall_miss_rate::total 0.016531 # miss rate for overall accesses 722system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.888716 # average ReadReq miss latency 723system.cpu.icache.ReadReq_avg_miss_latency::total 13903.888716 # average ReadReq miss latency 724system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency 725system.cpu.icache.demand_avg_miss_latency::total 13903.888716 # average overall miss latency 726system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency 727system.cpu.icache.overall_avg_miss_latency::total 13903.888716 # average overall miss latency | 726system.cpu.icache.tags.tag_accesses 57044588 # Number of tag accesses 727system.cpu.icache.tags.data_accesses 57044588 # Number of data accesses 728system.cpu.icache.ReadReq_hits::cpu.inst 55187496 # number of ReadReq hits 729system.cpu.icache.ReadReq_hits::total 55187496 # number of ReadReq hits 730system.cpu.icache.demand_hits::cpu.inst 55187496 # number of demand (read+write) hits 731system.cpu.icache.demand_hits::total 55187496 # number of demand (read+write) hits 732system.cpu.icache.overall_hits::cpu.inst 55187496 # number of overall hits 733system.cpu.icache.overall_hits::total 55187496 # number of overall hits 734system.cpu.icache.ReadReq_misses::cpu.inst 928546 # number of ReadReq misses 735system.cpu.icache.ReadReq_misses::total 928546 # number of ReadReq misses 736system.cpu.icache.demand_misses::cpu.inst 928546 # number of demand (read+write) misses 737system.cpu.icache.demand_misses::total 928546 # number of demand (read+write) misses 738system.cpu.icache.overall_misses::cpu.inst 928546 # number of overall misses 739system.cpu.icache.overall_misses::total 928546 # number of overall misses 740system.cpu.icache.ReadReq_miss_latency::cpu.inst 12910342260 # number of ReadReq miss cycles 741system.cpu.icache.ReadReq_miss_latency::total 12910342260 # number of ReadReq miss cycles 742system.cpu.icache.demand_miss_latency::cpu.inst 12910342260 # number of demand (read+write) miss cycles 743system.cpu.icache.demand_miss_latency::total 12910342260 # number of demand (read+write) miss cycles 744system.cpu.icache.overall_miss_latency::cpu.inst 12910342260 # number of overall miss cycles 745system.cpu.icache.overall_miss_latency::total 12910342260 # number of overall miss cycles 746system.cpu.icache.ReadReq_accesses::cpu.inst 56116042 # number of ReadReq accesses(hits+misses) 747system.cpu.icache.ReadReq_accesses::total 56116042 # number of ReadReq accesses(hits+misses) 748system.cpu.icache.demand_accesses::cpu.inst 56116042 # number of demand (read+write) accesses 749system.cpu.icache.demand_accesses::total 56116042 # number of demand (read+write) accesses 750system.cpu.icache.overall_accesses::cpu.inst 56116042 # number of overall (read+write) accesses 751system.cpu.icache.overall_accesses::total 56116042 # number of overall (read+write) accesses 752system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016547 # miss rate for ReadReq accesses 753system.cpu.icache.ReadReq_miss_rate::total 0.016547 # miss rate for ReadReq accesses 754system.cpu.icache.demand_miss_rate::cpu.inst 0.016547 # miss rate for demand accesses 755system.cpu.icache.demand_miss_rate::total 0.016547 # miss rate for demand accesses 756system.cpu.icache.overall_miss_rate::cpu.inst 0.016547 # miss rate for overall accesses 757system.cpu.icache.overall_miss_rate::total 0.016547 # miss rate for overall accesses 758system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.826262 # average ReadReq miss latency 759system.cpu.icache.ReadReq_avg_miss_latency::total 13903.826262 # average ReadReq miss latency 760system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency 761system.cpu.icache.demand_avg_miss_latency::total 13903.826262 # average overall miss latency 762system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency 763system.cpu.icache.overall_avg_miss_latency::total 13903.826262 # average overall miss latency |
| 728system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 729system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 730system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 731system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 732system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 733system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 734system.cpu.icache.fast_writes 0 # number of fast writes performed 735system.cpu.icache.cache_copies 0 # number of cache copies performed | 764system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 765system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 766system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 767system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 768system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 769system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 770system.cpu.icache.fast_writes 0 # number of fast writes performed 771system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 736system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929165 # number of ReadReq MSHR misses 737system.cpu.icache.ReadReq_mshr_misses::total 929165 # number of ReadReq MSHR misses 738system.cpu.icache.demand_mshr_misses::cpu.inst 929165 # number of demand (read+write) MSHR misses 739system.cpu.icache.demand_mshr_misses::total 929165 # number of demand (read+write) MSHR misses 740system.cpu.icache.overall_mshr_misses::cpu.inst 929165 # number of overall MSHR misses 741system.cpu.icache.overall_mshr_misses::total 929165 # number of overall MSHR misses 742system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11055577241 # number of ReadReq MSHR miss cycles 743system.cpu.icache.ReadReq_mshr_miss_latency::total 11055577241 # number of ReadReq MSHR miss cycles 744system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11055577241 # number of demand (read+write) MSHR miss cycles 745system.cpu.icache.demand_mshr_miss_latency::total 11055577241 # number of demand (read+write) MSHR miss cycles 746system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11055577241 # number of overall MSHR miss cycles 747system.cpu.icache.overall_mshr_miss_latency::total 11055577241 # number of overall MSHR miss cycles 748system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for ReadReq accesses 749system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016531 # mshr miss rate for ReadReq accesses 750system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for demand accesses 751system.cpu.icache.demand_mshr_miss_rate::total 0.016531 # mshr miss rate for demand accesses 752system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for overall accesses 753system.cpu.icache.overall_mshr_miss_rate::total 0.016531 # mshr miss rate for overall accesses 754system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.400436 # average ReadReq mshr miss latency 755system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.400436 # average ReadReq mshr miss latency 756system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency 757system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency 758system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency 759system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency | 772system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928546 # number of ReadReq MSHR misses 773system.cpu.icache.ReadReq_mshr_misses::total 928546 # number of ReadReq MSHR misses 774system.cpu.icache.demand_mshr_misses::cpu.inst 928546 # number of demand (read+write) MSHR misses 775system.cpu.icache.demand_mshr_misses::total 928546 # number of demand (read+write) MSHR misses 776system.cpu.icache.overall_mshr_misses::cpu.inst 928546 # number of overall MSHR misses 777system.cpu.icache.overall_mshr_misses::total 928546 # number of overall MSHR misses 778system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048086740 # number of ReadReq MSHR miss cycles 779system.cpu.icache.ReadReq_mshr_miss_latency::total 11048086740 # number of ReadReq MSHR miss cycles 780system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048086740 # number of demand (read+write) MSHR miss cycles 781system.cpu.icache.demand_mshr_miss_latency::total 11048086740 # number of demand (read+write) MSHR miss cycles 782system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11048086740 # number of overall MSHR miss cycles 783system.cpu.icache.overall_mshr_miss_latency::total 11048086740 # number of overall MSHR miss cycles 784system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for ReadReq accesses 785system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016547 # mshr miss rate for ReadReq accesses 786system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for demand accesses 787system.cpu.icache.demand_mshr_miss_rate::total 0.016547 # mshr miss rate for demand accesses 788system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for overall accesses 789system.cpu.icache.overall_mshr_miss_rate::total 0.016547 # mshr miss rate for overall accesses 790system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.265396 # average ReadReq mshr miss latency 791system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.265396 # average ReadReq mshr miss latency 792system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency 793system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency 794system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency 795system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency |
| 760system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 796system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 761system.cpu.l2cache.tags.replacements 336265 # number of replacements 762system.cpu.l2cache.tags.tagsinuse 65295.577509 # Cycle average of tags in use 763system.cpu.l2cache.tags.total_refs 2447728 # Total number of references to valid blocks. 764system.cpu.l2cache.tags.sampled_refs 401427 # Sample count of references to valid blocks. 765system.cpu.l2cache.tags.avg_refs 6.097567 # Average number of references to valid blocks. 766system.cpu.l2cache.tags.warmup_cycle 6793166750 # Cycle when the warmup percentage was hit. 767system.cpu.l2cache.tags.occ_blocks::writebacks 55588.679267 # Average occupied blocks per requestor 768system.cpu.l2cache.tags.occ_blocks::cpu.inst 4757.001179 # Average occupied blocks per requestor 769system.cpu.l2cache.tags.occ_blocks::cpu.data 4949.897063 # Average occupied blocks per requestor 770system.cpu.l2cache.tags.occ_percent::writebacks 0.848216 # Average percentage of cache occupancy 771system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072586 # Average percentage of cache occupancy 772system.cpu.l2cache.tags.occ_percent::cpu.data 0.075529 # Average percentage of cache occupancy 773system.cpu.l2cache.tags.occ_percent::total 0.996331 # Average percentage of cache occupancy 774system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 775system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id | 797system.cpu.l2cache.tags.replacements 336232 # number of replacements 798system.cpu.l2cache.tags.tagsinuse 65296.289611 # Cycle average of tags in use 799system.cpu.l2cache.tags.total_refs 2446119 # Total number of references to valid blocks. 800system.cpu.l2cache.tags.sampled_refs 401393 # Sample count of references to valid blocks. 801system.cpu.l2cache.tags.avg_refs 6.094075 # Average number of references to valid blocks. 802system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit. 803system.cpu.l2cache.tags.occ_blocks::writebacks 55555.447127 # Average occupied blocks per requestor 804system.cpu.l2cache.tags.occ_blocks::cpu.inst 4766.385283 # Average occupied blocks per requestor 805system.cpu.l2cache.tags.occ_blocks::cpu.data 4974.457201 # Average occupied blocks per requestor 806system.cpu.l2cache.tags.occ_percent::writebacks 0.847709 # Average percentage of cache occupancy 807system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072729 # Average percentage of cache occupancy 808system.cpu.l2cache.tags.occ_percent::cpu.data 0.075904 # Average percentage of cache occupancy 809system.cpu.l2cache.tags.occ_percent::total 0.996342 # Average percentage of cache occupancy 810system.cpu.l2cache.tags.occ_task_id_blocks::1024 65161 # Occupied blocks per task id 811system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id |
| 776system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id | 812system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id |
| 777system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4882 # Occupied blocks per task id 778system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3251 # Occupied blocks per task id 779system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55777 # Occupied blocks per task id 780system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id 781system.cpu.l2cache.tags.tag_accesses 25952661 # Number of tag accesses 782system.cpu.l2cache.tags.data_accesses 25952661 # Number of data accesses 783system.cpu.l2cache.ReadReq_hits::cpu.inst 915852 # number of ReadReq hits 784system.cpu.l2cache.ReadReq_hits::cpu.data 814775 # number of ReadReq hits 785system.cpu.l2cache.ReadReq_hits::total 1730627 # number of ReadReq hits 786system.cpu.l2cache.Writeback_hits::writebacks 835359 # number of Writeback hits 787system.cpu.l2cache.Writeback_hits::total 835359 # number of Writeback hits | 813system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4875 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3257 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55778 # Occupied blocks per task id 816system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994278 # Percentage of cache occupancy per task id 817system.cpu.l2cache.tags.tag_accesses 25936539 # Number of tag accesses 818system.cpu.l2cache.tags.data_accesses 25936539 # Number of data accesses 819system.cpu.l2cache.ReadReq_hits::cpu.inst 915233 # number of ReadReq hits 820system.cpu.l2cache.ReadReq_hits::cpu.data 814520 # number of ReadReq hits 821system.cpu.l2cache.ReadReq_hits::total 1729753 # number of ReadReq hits 822system.cpu.l2cache.Writeback_hits::writebacks 834591 # number of Writeback hits 823system.cpu.l2cache.Writeback_hits::total 834591 # number of Writeback hits |
| 788system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 789system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 824system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 825system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 790system.cpu.l2cache.ReadExReq_hits::cpu.data 187681 # number of ReadExReq hits 791system.cpu.l2cache.ReadExReq_hits::total 187681 # number of ReadExReq hits 792system.cpu.l2cache.demand_hits::cpu.inst 915852 # number of demand (read+write) hits 793system.cpu.l2cache.demand_hits::cpu.data 1002456 # number of demand (read+write) hits 794system.cpu.l2cache.demand_hits::total 1918308 # number of demand (read+write) hits 795system.cpu.l2cache.overall_hits::cpu.inst 915852 # number of overall hits 796system.cpu.l2cache.overall_hits::cpu.data 1002456 # number of overall hits 797system.cpu.l2cache.overall_hits::total 1918308 # number of overall hits | 826system.cpu.l2cache.ReadExReq_hits::cpu.data 187383 # number of ReadExReq hits 827system.cpu.l2cache.ReadExReq_hits::total 187383 # number of ReadExReq hits 828system.cpu.l2cache.demand_hits::cpu.inst 915233 # number of demand (read+write) hits 829system.cpu.l2cache.demand_hits::cpu.data 1001903 # number of demand (read+write) hits 830system.cpu.l2cache.demand_hits::total 1917136 # number of demand (read+write) hits 831system.cpu.l2cache.overall_hits::cpu.inst 915233 # number of overall hits 832system.cpu.l2cache.overall_hits::cpu.data 1001903 # number of overall hits 833system.cpu.l2cache.overall_hits::total 1917136 # number of overall hits |
| 798system.cpu.l2cache.ReadReq_misses::cpu.inst 13293 # number of ReadReq misses | 834system.cpu.l2cache.ReadReq_misses::cpu.inst 13293 # number of ReadReq misses |
| 799system.cpu.l2cache.ReadReq_misses::cpu.data 271967 # number of ReadReq misses 800system.cpu.l2cache.ReadReq_misses::total 285260 # number of ReadReq misses | 835system.cpu.l2cache.ReadReq_misses::cpu.data 271960 # number of ReadReq misses 836system.cpu.l2cache.ReadReq_misses::total 285253 # number of ReadReq misses |
| 801system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 802system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses | 837system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 838system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses |
| 803system.cpu.l2cache.ReadExReq_misses::cpu.data 116864 # number of ReadExReq misses 804system.cpu.l2cache.ReadExReq_misses::total 116864 # number of ReadExReq misses | 839system.cpu.l2cache.ReadExReq_misses::cpu.data 116840 # number of ReadExReq misses 840system.cpu.l2cache.ReadExReq_misses::total 116840 # number of ReadExReq misses |
| 805system.cpu.l2cache.demand_misses::cpu.inst 13293 # number of demand (read+write) misses | 841system.cpu.l2cache.demand_misses::cpu.inst 13293 # number of demand (read+write) misses |
| 806system.cpu.l2cache.demand_misses::cpu.data 388831 # number of demand (read+write) misses 807system.cpu.l2cache.demand_misses::total 402124 # number of demand (read+write) misses | 842system.cpu.l2cache.demand_misses::cpu.data 388800 # number of demand (read+write) misses 843system.cpu.l2cache.demand_misses::total 402093 # number of demand (read+write) misses |
| 808system.cpu.l2cache.overall_misses::cpu.inst 13293 # number of overall misses | 844system.cpu.l2cache.overall_misses::cpu.inst 13293 # number of overall misses |
| 809system.cpu.l2cache.overall_misses::cpu.data 388831 # number of overall misses 810system.cpu.l2cache.overall_misses::total 402124 # number of overall misses 811system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 967872241 # number of ReadReq miss cycles 812system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17714808491 # number of ReadReq miss cycles 813system.cpu.l2cache.ReadReq_miss_latency::total 18682680732 # number of ReadReq miss cycles | 845system.cpu.l2cache.overall_misses::cpu.data 388800 # number of overall misses 846system.cpu.l2cache.overall_misses::total 402093 # number of overall misses 847system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 967190740 # number of ReadReq miss cycles 848system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17699357246 # number of ReadReq miss cycles 849system.cpu.l2cache.ReadReq_miss_latency::total 18666547986 # number of ReadReq miss cycles |
| 814system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles 815system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles | 850system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles 851system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles |
| 816system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8011039626 # number of ReadExReq miss cycles 817system.cpu.l2cache.ReadExReq_miss_latency::total 8011039626 # number of ReadExReq miss cycles 818system.cpu.l2cache.demand_miss_latency::cpu.inst 967872241 # number of demand (read+write) miss cycles 819system.cpu.l2cache.demand_miss_latency::cpu.data 25725848117 # number of demand (read+write) miss cycles 820system.cpu.l2cache.demand_miss_latency::total 26693720358 # number of demand (read+write) miss cycles 821system.cpu.l2cache.overall_miss_latency::cpu.inst 967872241 # number of overall miss cycles 822system.cpu.l2cache.overall_miss_latency::cpu.data 25725848117 # number of overall miss cycles 823system.cpu.l2cache.overall_miss_latency::total 26693720358 # number of overall miss cycles 824system.cpu.l2cache.ReadReq_accesses::cpu.inst 929145 # number of ReadReq accesses(hits+misses) 825system.cpu.l2cache.ReadReq_accesses::cpu.data 1086742 # number of ReadReq accesses(hits+misses) 826system.cpu.l2cache.ReadReq_accesses::total 2015887 # number of ReadReq accesses(hits+misses) 827system.cpu.l2cache.Writeback_accesses::writebacks 835359 # number of Writeback accesses(hits+misses) 828system.cpu.l2cache.Writeback_accesses::total 835359 # number of Writeback accesses(hits+misses) | 852system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8068029125 # number of ReadExReq miss cycles 853system.cpu.l2cache.ReadExReq_miss_latency::total 8068029125 # number of ReadExReq miss cycles 854system.cpu.l2cache.demand_miss_latency::cpu.inst 967190740 # number of demand (read+write) miss cycles 855system.cpu.l2cache.demand_miss_latency::cpu.data 25767386371 # number of demand (read+write) miss cycles 856system.cpu.l2cache.demand_miss_latency::total 26734577111 # number of demand (read+write) miss cycles 857system.cpu.l2cache.overall_miss_latency::cpu.inst 967190740 # number of overall miss cycles 858system.cpu.l2cache.overall_miss_latency::cpu.data 25767386371 # number of overall miss cycles 859system.cpu.l2cache.overall_miss_latency::total 26734577111 # number of overall miss cycles 860system.cpu.l2cache.ReadReq_accesses::cpu.inst 928526 # number of ReadReq accesses(hits+misses) 861system.cpu.l2cache.ReadReq_accesses::cpu.data 1086480 # number of ReadReq accesses(hits+misses) 862system.cpu.l2cache.ReadReq_accesses::total 2015006 # number of ReadReq accesses(hits+misses) 863system.cpu.l2cache.Writeback_accesses::writebacks 834591 # number of Writeback accesses(hits+misses) 864system.cpu.l2cache.Writeback_accesses::total 834591 # number of Writeback accesses(hits+misses) |
| 829system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 830system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) | 865system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 866system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) |
| 831system.cpu.l2cache.ReadExReq_accesses::cpu.data 304545 # number of ReadExReq accesses(hits+misses) 832system.cpu.l2cache.ReadExReq_accesses::total 304545 # number of ReadExReq accesses(hits+misses) 833system.cpu.l2cache.demand_accesses::cpu.inst 929145 # number of demand (read+write) accesses 834system.cpu.l2cache.demand_accesses::cpu.data 1391287 # number of demand (read+write) accesses 835system.cpu.l2cache.demand_accesses::total 2320432 # number of demand (read+write) accesses 836system.cpu.l2cache.overall_accesses::cpu.inst 929145 # number of overall (read+write) accesses 837system.cpu.l2cache.overall_accesses::cpu.data 1391287 # number of overall (read+write) accesses 838system.cpu.l2cache.overall_accesses::total 2320432 # number of overall (read+write) accesses 839system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014307 # miss rate for ReadReq accesses 840system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250259 # miss rate for ReadReq accesses 841system.cpu.l2cache.ReadReq_miss_rate::total 0.141506 # miss rate for ReadReq accesses | 867system.cpu.l2cache.ReadExReq_accesses::cpu.data 304223 # number of ReadExReq accesses(hits+misses) 868system.cpu.l2cache.ReadExReq_accesses::total 304223 # number of ReadExReq accesses(hits+misses) 869system.cpu.l2cache.demand_accesses::cpu.inst 928526 # number of demand (read+write) accesses 870system.cpu.l2cache.demand_accesses::cpu.data 1390703 # number of demand (read+write) accesses 871system.cpu.l2cache.demand_accesses::total 2319229 # number of demand (read+write) accesses 872system.cpu.l2cache.overall_accesses::cpu.inst 928526 # number of overall (read+write) accesses 873system.cpu.l2cache.overall_accesses::cpu.data 1390703 # number of overall (read+write) accesses 874system.cpu.l2cache.overall_accesses::total 2319229 # number of overall (read+write) accesses 875system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014316 # miss rate for ReadReq accesses 876system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250313 # miss rate for ReadReq accesses 877system.cpu.l2cache.ReadReq_miss_rate::total 0.141564 # miss rate for ReadReq accesses |
| 842system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 843system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses | 878system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 879system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses |
| 844system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383733 # miss rate for ReadExReq accesses 845system.cpu.l2cache.ReadExReq_miss_rate::total 0.383733 # miss rate for ReadExReq accesses 846system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014307 # miss rate for demand accesses 847system.cpu.l2cache.demand_miss_rate::cpu.data 0.279476 # miss rate for demand accesses 848system.cpu.l2cache.demand_miss_rate::total 0.173297 # miss rate for demand accesses 849system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014307 # miss rate for overall accesses 850system.cpu.l2cache.overall_miss_rate::cpu.data 0.279476 # miss rate for overall accesses 851system.cpu.l2cache.overall_miss_rate::total 0.173297 # miss rate for overall accesses 852system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72810.670353 # average ReadReq miss latency 853system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65135.874908 # average ReadReq miss latency 854system.cpu.l2cache.ReadReq_avg_miss_latency::total 65493.517254 # average ReadReq miss latency | 880system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384060 # miss rate for ReadExReq accesses 881system.cpu.l2cache.ReadExReq_miss_rate::total 0.384060 # miss rate for ReadExReq accesses 882system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014316 # miss rate for demand accesses 883system.cpu.l2cache.demand_miss_rate::cpu.data 0.279571 # miss rate for demand accesses 884system.cpu.l2cache.demand_miss_rate::total 0.173374 # miss rate for demand accesses 885system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014316 # miss rate for overall accesses 886system.cpu.l2cache.overall_miss_rate::cpu.data 0.279571 # miss rate for overall accesses 887system.cpu.l2cache.overall_miss_rate::total 0.173374 # miss rate for overall accesses 888system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72759.402693 # average ReadReq miss latency 889system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65080.737042 # average ReadReq miss latency 890system.cpu.l2cache.ReadReq_avg_miss_latency::total 65438.568520 # average ReadReq miss latency |
| 855system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency 856system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency | 891system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency 892system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency |
| 857system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68550.106329 # average ReadExReq miss latency 858system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68550.106329 # average ReadExReq miss latency 859system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72810.670353 # average overall miss latency 860system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66162.029563 # average overall miss latency 861system.cpu.l2cache.demand_avg_miss_latency::total 66381.813465 # average overall miss latency 862system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72810.670353 # average overall miss latency 863system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66162.029563 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::total 66381.813465 # average overall miss latency | 893system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69051.943898 # average ReadExReq miss latency 894system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69051.943898 # average ReadExReq miss latency 895system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72759.402693 # average overall miss latency 896system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66274.141901 # average overall miss latency 897system.cpu.l2cache.demand_avg_miss_latency::total 66488.541484 # average overall miss latency 898system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72759.402693 # average overall miss latency 899system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66274.141901 # average overall miss latency 900system.cpu.l2cache.overall_avg_miss_latency::total 66488.541484 # average overall miss latency |
| 865system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 866system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 867system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 868system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 869system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 870system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 871system.cpu.l2cache.fast_writes 0 # number of fast writes performed 872system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 901system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 902system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 904system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 906system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu.l2cache.fast_writes 0 # number of fast writes performed 908system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 873system.cpu.l2cache.writebacks::writebacks 74205 # number of writebacks 874system.cpu.l2cache.writebacks::total 74205 # number of writebacks | 909system.cpu.l2cache.writebacks::writebacks 74176 # number of writebacks 910system.cpu.l2cache.writebacks::total 74176 # number of writebacks |
| 875system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13293 # number of ReadReq MSHR misses | 911system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13293 # number of ReadReq MSHR misses |
| 876system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271967 # number of ReadReq MSHR misses 877system.cpu.l2cache.ReadReq_mshr_misses::total 285260 # number of ReadReq MSHR misses | 912system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271960 # number of ReadReq MSHR misses 913system.cpu.l2cache.ReadReq_mshr_misses::total 285253 # number of ReadReq MSHR misses |
| 878system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 879system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses | 914system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 915system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses |
| 880system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116864 # number of ReadExReq MSHR misses 881system.cpu.l2cache.ReadExReq_mshr_misses::total 116864 # number of ReadExReq MSHR misses | 916system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116840 # number of ReadExReq MSHR misses 917system.cpu.l2cache.ReadExReq_mshr_misses::total 116840 # number of ReadExReq MSHR misses |
| 882system.cpu.l2cache.demand_mshr_misses::cpu.inst 13293 # number of demand (read+write) MSHR misses | 918system.cpu.l2cache.demand_mshr_misses::cpu.inst 13293 # number of demand (read+write) MSHR misses |
| 883system.cpu.l2cache.demand_mshr_misses::cpu.data 388831 # number of demand (read+write) MSHR misses 884system.cpu.l2cache.demand_mshr_misses::total 402124 # number of demand (read+write) MSHR misses | 919system.cpu.l2cache.demand_mshr_misses::cpu.data 388800 # number of demand (read+write) MSHR misses 920system.cpu.l2cache.demand_mshr_misses::total 402093 # number of demand (read+write) MSHR misses |
| 885system.cpu.l2cache.overall_mshr_misses::cpu.inst 13293 # number of overall MSHR misses | 921system.cpu.l2cache.overall_mshr_misses::cpu.inst 13293 # number of overall MSHR misses |
| 886system.cpu.l2cache.overall_mshr_misses::cpu.data 388831 # number of overall MSHR misses 887system.cpu.l2cache.overall_mshr_misses::total 402124 # number of overall MSHR misses 888system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 801329759 # number of ReadReq MSHR miss cycles 889system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14314442009 # number of ReadReq MSHR miss cycles 890system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15115771768 # number of ReadReq MSHR miss cycles | 922system.cpu.l2cache.overall_mshr_misses::cpu.data 388800 # number of overall MSHR misses 923system.cpu.l2cache.overall_mshr_misses::total 402093 # number of overall MSHR misses 924system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 800656260 # number of ReadReq MSHR miss cycles 925system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14299493254 # number of ReadReq MSHR miss cycles 926system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15100149514 # number of ReadReq MSHR miss cycles |
| 891system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles 892system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles | 927system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles 928system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles |
| 893system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6549827374 # number of ReadExReq MSHR miss cycles 894system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6549827374 # number of ReadExReq MSHR miss cycles 895system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 801329759 # number of demand (read+write) MSHR miss cycles 896system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20864269383 # number of demand (read+write) MSHR miss cycles 897system.cpu.l2cache.demand_mshr_miss_latency::total 21665599142 # number of demand (read+write) MSHR miss cycles 898system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 801329759 # number of overall MSHR miss cycles 899system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20864269383 # number of overall MSHR miss cycles 900system.cpu.l2cache.overall_mshr_miss_latency::total 21665599142 # number of overall MSHR miss cycles 901system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles 902system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles 903system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895641500 # number of WriteReq MSHR uncacheable cycles 904system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895641500 # number of WriteReq MSHR uncacheable cycles 905system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles 906system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles 907system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for ReadReq accesses 908system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses 909system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141506 # mshr miss rate for ReadReq accesses | 929system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607242375 # number of ReadExReq MSHR miss cycles 930system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607242375 # number of ReadExReq MSHR miss cycles 931system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 800656260 # number of demand (read+write) MSHR miss cycles 932system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20906735629 # number of demand (read+write) MSHR miss cycles 933system.cpu.l2cache.demand_mshr_miss_latency::total 21707391889 # number of demand (read+write) MSHR miss cycles 934system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 800656260 # number of overall MSHR miss cycles 935system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20906735629 # number of overall MSHR miss cycles 936system.cpu.l2cache.overall_mshr_miss_latency::total 21707391889 # number of overall MSHR miss cycles 937system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles 938system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles 939system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895432500 # number of WriteReq MSHR uncacheable cycles 940system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895432500 # number of WriteReq MSHR uncacheable cycles 941system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229578000 # number of overall MSHR uncacheable cycles 942system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229578000 # number of overall MSHR uncacheable cycles 943system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses 944system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250313 # mshr miss rate for ReadReq accesses 945system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141564 # mshr miss rate for ReadReq accesses |
| 910system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 911system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses | 946system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 947system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses |
| 912system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383733 # mshr miss rate for ReadExReq accesses 913system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383733 # mshr miss rate for ReadExReq accesses 914system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for demand accesses 915system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for demand accesses 916system.cpu.l2cache.demand_mshr_miss_rate::total 0.173297 # mshr miss rate for demand accesses 917system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for overall accesses 918system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for overall accesses 919system.cpu.l2cache.overall_mshr_miss_rate::total 0.173297 # mshr miss rate for overall accesses 920system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60282.085233 # average ReadReq mshr miss latency 921system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52633.010656 # average ReadReq mshr miss latency 922system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52989.454421 # average ReadReq mshr miss latency | 948system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384060 # mshr miss rate for ReadExReq accesses 949system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384060 # mshr miss rate for ReadExReq accesses 950system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses 951system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for demand accesses 952system.cpu.l2cache.demand_mshr_miss_rate::total 0.173374 # mshr miss rate for demand accesses 953system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses 954system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for overall accesses 955system.cpu.l2cache.overall_mshr_miss_rate::total 0.173374 # mshr miss rate for overall accesses 956system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60231.419544 # average ReadReq mshr miss latency 957system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52579.398640 # average ReadReq mshr miss latency 958system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52935.988452 # average ReadReq mshr miss latency |
| 923system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency 924system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency | 959system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency 960system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency |
| 925system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56046.578707 # average ReadExReq mshr miss latency 926system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56046.578707 # average ReadExReq mshr miss latency 927system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency 928system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency 929system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency 930system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency 931system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency 932system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency | 961system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56549.489687 # average ReadExReq mshr miss latency 962system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56549.489687 # average ReadExReq mshr miss latency 963system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency 964system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency 965system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency 966system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency 967system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency 968system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency |
| 933system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 934system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 935system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 936system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 937system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 938system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 939system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 969system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 970system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 971system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 972system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 973system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 974system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 975system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 940system.cpu.dcache.tags.replacements 1390774 # number of replacements 941system.cpu.dcache.tags.tagsinuse 511.978892 # Cycle average of tags in use 942system.cpu.dcache.tags.total_refs 14051964 # Total number of references to valid blocks. 943system.cpu.dcache.tags.sampled_refs 1391286 # Sample count of references to valid blocks. 944system.cpu.dcache.tags.avg_refs 10.099982 # Average number of references to valid blocks. 945system.cpu.dcache.tags.warmup_cycle 107796250 # Cycle when the warmup percentage was hit. 946system.cpu.dcache.tags.occ_blocks::cpu.data 511.978892 # Average occupied blocks per requestor | 976system.cpu.dcache.tags.replacements 1390190 # number of replacements 977system.cpu.dcache.tags.tagsinuse 511.978877 # Cycle average of tags in use 978system.cpu.dcache.tags.total_refs 14030691 # Total number of references to valid blocks. 979system.cpu.dcache.tags.sampled_refs 1390702 # Sample count of references to valid blocks. 980system.cpu.dcache.tags.avg_refs 10.088927 # Average number of references to valid blocks. 981system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. 982system.cpu.dcache.tags.occ_blocks::cpu.data 511.978877 # Average occupied blocks per requestor |
| 947system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy 948system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy 949system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 950system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 951system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 952system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 953system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 983system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy 984system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy 985system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 986system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 987system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 988system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 989system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 954system.cpu.dcache.tags.tag_accesses 63164291 # Number of tag accesses 955system.cpu.dcache.tags.data_accesses 63164291 # Number of data accesses 956system.cpu.dcache.ReadReq_hits::cpu.data 7816324 # number of ReadReq hits 957system.cpu.dcache.ReadReq_hits::total 7816324 # number of ReadReq hits 958system.cpu.dcache.WriteReq_hits::cpu.data 5853358 # number of WriteReq hits 959system.cpu.dcache.WriteReq_hits::total 5853358 # number of WriteReq hits 960system.cpu.dcache.LoadLockedReq_hits::cpu.data 183027 # number of LoadLockedReq hits 961system.cpu.dcache.LoadLockedReq_hits::total 183027 # number of LoadLockedReq hits 962system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits 963system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits 964system.cpu.dcache.demand_hits::cpu.data 13669682 # number of demand (read+write) hits 965system.cpu.dcache.demand_hits::total 13669682 # number of demand (read+write) hits 966system.cpu.dcache.overall_hits::cpu.data 13669682 # number of overall hits 967system.cpu.dcache.overall_hits::total 13669682 # number of overall hits 968system.cpu.dcache.ReadReq_misses::cpu.data 1069509 # number of ReadReq misses 969system.cpu.dcache.ReadReq_misses::total 1069509 # number of ReadReq misses 970system.cpu.dcache.WriteReq_misses::cpu.data 304562 # number of WriteReq misses 971system.cpu.dcache.WriteReq_misses::total 304562 # number of WriteReq misses 972system.cpu.dcache.LoadLockedReq_misses::cpu.data 17233 # number of LoadLockedReq misses 973system.cpu.dcache.LoadLockedReq_misses::total 17233 # number of LoadLockedReq misses 974system.cpu.dcache.demand_misses::cpu.data 1374071 # number of demand (read+write) misses 975system.cpu.dcache.demand_misses::total 1374071 # number of demand (read+write) misses 976system.cpu.dcache.overall_misses::cpu.data 1374071 # number of overall misses 977system.cpu.dcache.overall_misses::total 1374071 # number of overall misses 978system.cpu.dcache.ReadReq_miss_latency::cpu.data 29019471009 # number of ReadReq miss cycles 979system.cpu.dcache.ReadReq_miss_latency::total 29019471009 # number of ReadReq miss cycles 980system.cpu.dcache.WriteReq_miss_latency::cpu.data 10854033885 # number of WriteReq miss cycles 981system.cpu.dcache.WriteReq_miss_latency::total 10854033885 # number of WriteReq miss cycles 982system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228736500 # number of LoadLockedReq miss cycles 983system.cpu.dcache.LoadLockedReq_miss_latency::total 228736500 # number of LoadLockedReq miss cycles 984system.cpu.dcache.demand_miss_latency::cpu.data 39873504894 # number of demand (read+write) miss cycles 985system.cpu.dcache.demand_miss_latency::total 39873504894 # number of demand (read+write) miss cycles 986system.cpu.dcache.overall_miss_latency::cpu.data 39873504894 # number of overall miss cycles 987system.cpu.dcache.overall_miss_latency::total 39873504894 # number of overall miss cycles 988system.cpu.dcache.ReadReq_accesses::cpu.data 8885833 # number of ReadReq accesses(hits+misses) 989system.cpu.dcache.ReadReq_accesses::total 8885833 # number of ReadReq accesses(hits+misses) 990system.cpu.dcache.WriteReq_accesses::cpu.data 6157920 # number of WriteReq accesses(hits+misses) 991system.cpu.dcache.WriteReq_accesses::total 6157920 # number of WriteReq accesses(hits+misses) 992system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200260 # number of LoadLockedReq accesses(hits+misses) 993system.cpu.dcache.LoadLockedReq_accesses::total 200260 # number of LoadLockedReq accesses(hits+misses) 994system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses) 995system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses) 996system.cpu.dcache.demand_accesses::cpu.data 15043753 # number of demand (read+write) accesses 997system.cpu.dcache.demand_accesses::total 15043753 # number of demand (read+write) accesses 998system.cpu.dcache.overall_accesses::cpu.data 15043753 # number of overall (read+write) accesses 999system.cpu.dcache.overall_accesses::total 15043753 # number of overall (read+write) accesses 1000system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120361 # miss rate for ReadReq accesses 1001system.cpu.dcache.ReadReq_miss_rate::total 0.120361 # miss rate for ReadReq accesses 1002system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses 1003system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses 1004system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086053 # miss rate for LoadLockedReq accesses 1005system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086053 # miss rate for LoadLockedReq accesses 1006system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses 1007system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses 1008system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses 1009system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses 1010system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27133.451901 # average ReadReq miss latency 1011system.cpu.dcache.ReadReq_avg_miss_latency::total 27133.451901 # average ReadReq miss latency 1012system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35638.175101 # average WriteReq miss latency 1013system.cpu.dcache.WriteReq_avg_miss_latency::total 35638.175101 # average WriteReq miss latency 1014system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.167760 # average LoadLockedReq miss latency 1015system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.167760 # average LoadLockedReq miss latency 1016system.cpu.dcache.demand_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency 1017system.cpu.dcache.demand_avg_miss_latency::total 29018.518617 # average overall miss latency 1018system.cpu.dcache.overall_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency 1019system.cpu.dcache.overall_avg_miss_latency::total 29018.518617 # average overall miss latency | 990system.cpu.dcache.tags.tag_accesses 63076279 # Number of tag accesses 991system.cpu.dcache.tags.data_accesses 63076279 # Number of data accesses 992system.cpu.dcache.ReadReq_hits::cpu.data 7802806 # number of ReadReq hits 993system.cpu.dcache.ReadReq_hits::total 7802806 # number of ReadReq hits 994system.cpu.dcache.WriteReq_hits::cpu.data 5845593 # number of WriteReq hits 995system.cpu.dcache.WriteReq_hits::total 5845593 # number of WriteReq hits 996system.cpu.dcache.LoadLockedReq_hits::cpu.data 183040 # number of LoadLockedReq hits 997system.cpu.dcache.LoadLockedReq_hits::total 183040 # number of LoadLockedReq hits 998system.cpu.dcache.StoreCondReq_hits::cpu.data 199235 # number of StoreCondReq hits 999system.cpu.dcache.StoreCondReq_hits::total 199235 # number of StoreCondReq hits 1000system.cpu.dcache.demand_hits::cpu.data 13648399 # number of demand (read+write) hits 1001system.cpu.dcache.demand_hits::total 13648399 # number of demand (read+write) hits 1002system.cpu.dcache.overall_hits::cpu.data 13648399 # number of overall hits 1003system.cpu.dcache.overall_hits::total 13648399 # number of overall hits 1004system.cpu.dcache.ReadReq_misses::cpu.data 1069264 # number of ReadReq misses 1005system.cpu.dcache.ReadReq_misses::total 1069264 # number of ReadReq misses 1006system.cpu.dcache.WriteReq_misses::cpu.data 304240 # number of WriteReq misses 1007system.cpu.dcache.WriteReq_misses::total 304240 # number of WriteReq misses 1008system.cpu.dcache.LoadLockedReq_misses::cpu.data 17216 # number of LoadLockedReq misses 1009system.cpu.dcache.LoadLockedReq_misses::total 17216 # number of LoadLockedReq misses 1010system.cpu.dcache.demand_misses::cpu.data 1373504 # number of demand (read+write) misses 1011system.cpu.dcache.demand_misses::total 1373504 # number of demand (read+write) misses 1012system.cpu.dcache.overall_misses::cpu.data 1373504 # number of overall misses 1013system.cpu.dcache.overall_misses::total 1373504 # number of overall misses 1014system.cpu.dcache.ReadReq_miss_latency::cpu.data 29001409504 # number of ReadReq miss cycles 1015system.cpu.dcache.ReadReq_miss_latency::total 29001409504 # number of ReadReq miss cycles 1016system.cpu.dcache.WriteReq_miss_latency::cpu.data 10907701386 # number of WriteReq miss cycles 1017system.cpu.dcache.WriteReq_miss_latency::total 10907701386 # number of WriteReq miss cycles 1018system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228213250 # number of LoadLockedReq miss cycles 1019system.cpu.dcache.LoadLockedReq_miss_latency::total 228213250 # number of LoadLockedReq miss cycles 1020system.cpu.dcache.demand_miss_latency::cpu.data 39909110890 # number of demand (read+write) miss cycles 1021system.cpu.dcache.demand_miss_latency::total 39909110890 # number of demand (read+write) miss cycles 1022system.cpu.dcache.overall_miss_latency::cpu.data 39909110890 # number of overall miss cycles 1023system.cpu.dcache.overall_miss_latency::total 39909110890 # number of overall miss cycles 1024system.cpu.dcache.ReadReq_accesses::cpu.data 8872070 # number of ReadReq accesses(hits+misses) 1025system.cpu.dcache.ReadReq_accesses::total 8872070 # number of ReadReq accesses(hits+misses) 1026system.cpu.dcache.WriteReq_accesses::cpu.data 6149833 # number of WriteReq accesses(hits+misses) 1027system.cpu.dcache.WriteReq_accesses::total 6149833 # number of WriteReq accesses(hits+misses) 1028system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200256 # number of LoadLockedReq accesses(hits+misses) 1029system.cpu.dcache.LoadLockedReq_accesses::total 200256 # number of LoadLockedReq accesses(hits+misses) 1030system.cpu.dcache.StoreCondReq_accesses::cpu.data 199235 # number of StoreCondReq accesses(hits+misses) 1031system.cpu.dcache.StoreCondReq_accesses::total 199235 # number of StoreCondReq accesses(hits+misses) 1032system.cpu.dcache.demand_accesses::cpu.data 15021903 # number of demand (read+write) accesses 1033system.cpu.dcache.demand_accesses::total 15021903 # number of demand (read+write) accesses 1034system.cpu.dcache.overall_accesses::cpu.data 15021903 # number of overall (read+write) accesses 1035system.cpu.dcache.overall_accesses::total 15021903 # number of overall (read+write) accesses 1036system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120520 # miss rate for ReadReq accesses 1037system.cpu.dcache.ReadReq_miss_rate::total 0.120520 # miss rate for ReadReq accesses 1038system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049471 # miss rate for WriteReq accesses 1039system.cpu.dcache.WriteReq_miss_rate::total 0.049471 # miss rate for WriteReq accesses 1040system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses 1041system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses 1042system.cpu.dcache.demand_miss_rate::cpu.data 0.091433 # miss rate for demand accesses 1043system.cpu.dcache.demand_miss_rate::total 0.091433 # miss rate for demand accesses 1044system.cpu.dcache.overall_miss_rate::cpu.data 0.091433 # miss rate for overall accesses 1045system.cpu.dcache.overall_miss_rate::total 0.091433 # miss rate for overall accesses 1046system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27122.777447 # average ReadReq miss latency 1047system.cpu.dcache.ReadReq_avg_miss_latency::total 27122.777447 # average ReadReq miss latency 1048system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35852.292223 # average WriteReq miss latency 1049system.cpu.dcache.WriteReq_avg_miss_latency::total 35852.292223 # average WriteReq miss latency 1050system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.881157 # average LoadLockedReq miss latency 1051system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.881157 # average LoadLockedReq miss latency 1052system.cpu.dcache.demand_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency 1053system.cpu.dcache.demand_avg_miss_latency::total 29056.421306 # average overall miss latency 1054system.cpu.dcache.overall_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency 1055system.cpu.dcache.overall_avg_miss_latency::total 29056.421306 # average overall miss latency |
| 1020system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1021system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1022system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1023system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1024system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1025system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1026system.cpu.dcache.fast_writes 0 # number of fast writes performed 1027system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1056system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1057system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1058system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1059system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1060system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1061system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1062system.cpu.dcache.fast_writes 0 # number of fast writes performed 1063system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1028system.cpu.dcache.writebacks::writebacks 835359 # number of writebacks 1029system.cpu.dcache.writebacks::total 835359 # number of writebacks 1030system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069509 # number of ReadReq MSHR misses 1031system.cpu.dcache.ReadReq_mshr_misses::total 1069509 # number of ReadReq MSHR misses 1032system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304562 # number of WriteReq MSHR misses 1033system.cpu.dcache.WriteReq_mshr_misses::total 304562 # number of WriteReq MSHR misses 1034system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17233 # number of LoadLockedReq MSHR misses 1035system.cpu.dcache.LoadLockedReq_mshr_misses::total 17233 # number of LoadLockedReq MSHR misses 1036system.cpu.dcache.demand_mshr_misses::cpu.data 1374071 # number of demand (read+write) MSHR misses 1037system.cpu.dcache.demand_mshr_misses::total 1374071 # number of demand (read+write) MSHR misses 1038system.cpu.dcache.overall_mshr_misses::cpu.data 1374071 # number of overall MSHR misses 1039system.cpu.dcache.overall_mshr_misses::total 1374071 # number of overall MSHR misses 1040system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26755042991 # number of ReadReq MSHR miss cycles 1041system.cpu.dcache.ReadReq_mshr_miss_latency::total 26755042991 # number of ReadReq MSHR miss cycles 1042system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10192844115 # number of WriteReq MSHR miss cycles 1043system.cpu.dcache.WriteReq_mshr_miss_latency::total 10192844115 # number of WriteReq MSHR miss cycles 1044system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194257500 # number of LoadLockedReq MSHR miss cycles 1045system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194257500 # number of LoadLockedReq MSHR miss cycles 1046system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36947887106 # number of demand (read+write) MSHR miss cycles 1047system.cpu.dcache.demand_mshr_miss_latency::total 36947887106 # number of demand (read+write) MSHR miss cycles 1048system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36947887106 # number of overall MSHR miss cycles 1049system.cpu.dcache.overall_mshr_miss_latency::total 36947887106 # number of overall MSHR miss cycles 1050system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles 1051system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles 1052system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011441500 # number of WriteReq MSHR uncacheable cycles 1053system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011441500 # number of WriteReq MSHR uncacheable cycles 1054system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles 1055system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles 1056system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120361 # mshr miss rate for ReadReq accesses 1057system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120361 # mshr miss rate for ReadReq accesses 1058system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses 1059system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses 1060system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086053 # mshr miss rate for LoadLockedReq accesses 1061system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086053 # mshr miss rate for LoadLockedReq accesses 1062system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses 1063system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses 1064system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses 1065system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses 1066system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25016.192469 # average ReadReq mshr miss latency 1067system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25016.192469 # average ReadReq mshr miss latency 1068system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33467.222158 # average WriteReq mshr miss latency 1069system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33467.222158 # average WriteReq mshr miss latency 1070system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.413393 # average LoadLockedReq mshr miss latency 1071system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.413393 # average LoadLockedReq mshr miss latency 1072system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency 1073system.cpu.dcache.demand_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency 1074system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency 1075system.cpu.dcache.overall_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency | 1064system.cpu.dcache.writebacks::writebacks 834591 # number of writebacks 1065system.cpu.dcache.writebacks::total 834591 # number of writebacks 1066system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069264 # number of ReadReq MSHR misses 1067system.cpu.dcache.ReadReq_mshr_misses::total 1069264 # number of ReadReq MSHR misses 1068system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304240 # number of WriteReq MSHR misses 1069system.cpu.dcache.WriteReq_mshr_misses::total 304240 # number of WriteReq MSHR misses 1070system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17216 # number of LoadLockedReq MSHR misses 1071system.cpu.dcache.LoadLockedReq_mshr_misses::total 17216 # number of LoadLockedReq MSHR misses 1072system.cpu.dcache.demand_mshr_misses::cpu.data 1373504 # number of demand (read+write) MSHR misses 1073system.cpu.dcache.demand_mshr_misses::total 1373504 # number of demand (read+write) MSHR misses 1074system.cpu.dcache.overall_mshr_misses::cpu.data 1373504 # number of overall MSHR misses 1075system.cpu.dcache.overall_mshr_misses::total 1373504 # number of overall MSHR misses 1076system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26737269496 # number of ReadReq MSHR miss cycles 1077system.cpu.dcache.ReadReq_mshr_miss_latency::total 26737269496 # number of ReadReq MSHR miss cycles 1078system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10246531614 # number of WriteReq MSHR miss cycles 1079system.cpu.dcache.WriteReq_mshr_miss_latency::total 10246531614 # number of WriteReq MSHR miss cycles 1080system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193767750 # number of LoadLockedReq MSHR miss cycles 1081system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193767750 # number of LoadLockedReq MSHR miss cycles 1082system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36983801110 # number of demand (read+write) MSHR miss cycles 1083system.cpu.dcache.demand_mshr_miss_latency::total 36983801110 # number of demand (read+write) MSHR miss cycles 1084system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36983801110 # number of overall MSHR miss cycles 1085system.cpu.dcache.overall_mshr_miss_latency::total 36983801110 # number of overall MSHR miss cycles 1086system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles 1087system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles 1088system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011220500 # number of WriteReq MSHR uncacheable cycles 1089system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011220500 # number of WriteReq MSHR uncacheable cycles 1090system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435456000 # number of overall MSHR uncacheable cycles 1091system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435456000 # number of overall MSHR uncacheable cycles 1092system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120520 # mshr miss rate for ReadReq accesses 1093system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120520 # mshr miss rate for ReadReq accesses 1094system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049471 # mshr miss rate for WriteReq accesses 1095system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses 1096system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses 1097system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses 1098system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for demand accesses 1099system.cpu.dcache.demand_mshr_miss_rate::total 0.091433 # mshr miss rate for demand accesses 1100system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for overall accesses 1101system.cpu.dcache.overall_mshr_miss_rate::total 0.091433 # mshr miss rate for overall accesses 1102system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25005.302242 # average ReadReq mshr miss latency 1103system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25005.302242 # average ReadReq mshr miss latency 1104system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33679.107330 # average WriteReq mshr miss latency 1105system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33679.107330 # average WriteReq mshr miss latency 1106system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11255.097003 # average LoadLockedReq mshr miss latency 1107system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11255.097003 # average LoadLockedReq mshr miss latency 1108system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency 1109system.cpu.dcache.demand_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency 1110system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency 1111system.cpu.dcache.overall_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency |
| 1076system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1077system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1078system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1079system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1080system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1081system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1082system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1112system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1113system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1114system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1115system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1116system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1117system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1118system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1083system.cpu.toL2Bus.throughput 105199341 # Throughput (bytes/s) 1084system.cpu.toL2Bus.trans_dist::ReadReq 2023010 # Transaction distribution 1085system.cpu.toL2Bus.trans_dist::ReadResp 2022993 # Transaction distribution 1086system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution 1087system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution 1088system.cpu.toL2Bus.trans_dist::Writeback 835359 # Transaction distribution | 1119system.cpu.toL2Bus.throughput 105186760 # Throughput (bytes/s) 1120system.cpu.toL2Bus.trans_dist::ReadReq 2022129 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::ReadResp 2022112 # Transaction distribution 1122system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::Writeback 834591 # Transaction distribution |
| 1089system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1090system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution | 1125system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution |
| 1091system.cpu.toL2Bus.trans_dist::ReadExReq 346097 # Transaction distribution 1092system.cpu.toL2Bus.trans_dist::ReadExResp 304546 # Transaction distribution 1093system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858310 # Packet count per connected master and slave (bytes) 1094system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651284 # Packet count per connected master and slave (bytes) 1095system.cpu.toL2Bus.pkt_count::total 5509594 # Packet count per connected master and slave (bytes) 1096system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59465280 # Cumulative packet size per connected master and slave (bytes) 1097system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142559956 # Cumulative packet size per connected master and slave (bytes) 1098system.cpu.toL2Bus.tot_pkt_size::total 202025236 # Cumulative packet size per connected master and slave (bytes) 1099system.cpu.toL2Bus.data_through_bus 202015188 # Total data (bytes) | 1127system.cpu.toL2Bus.trans_dist::ReadExReq 345775 # Transaction distribution 1128system.cpu.toL2Bus.trans_dist::ReadExResp 304224 # Transaction distribution 1129system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857072 # Packet count per connected master and slave (bytes) 1130system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649346 # Packet count per connected master and slave (bytes) 1131system.cpu.toL2Bus.pkt_count::total 5506418 # Packet count per connected master and slave (bytes) 1132system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59425664 # Cumulative packet size per connected master and slave (bytes) 1133system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142473420 # Cumulative packet size per connected master and slave (bytes) 1134system.cpu.toL2Bus.tot_pkt_size::total 201899084 # Cumulative packet size per connected master and slave (bytes) 1135system.cpu.toL2Bus.data_through_bus 201889036 # Total data (bytes) |
| 1100system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) | 1136system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) |
| 1101system.cpu.toL2Bus.reqLayer0.occupancy 2426388000 # Layer occupancy (ticks) | 1137system.cpu.toL2Bus.reqLayer0.occupancy 2424633500 # Layer occupancy (ticks) |
| 1102system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1103system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 1104system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1138system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1139system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 1140system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1105system.cpu.toL2Bus.respLayer0.occupancy 1396297259 # Layer occupancy (ticks) | 1141system.cpu.toL2Bus.respLayer0.occupancy 1395400760 # Layer occupancy (ticks) |
| 1106system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1142system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1107system.cpu.toL2Bus.respLayer1.occupancy 2187438394 # Layer occupancy (ticks) | 1143system.cpu.toL2Bus.respLayer1.occupancy 2186975140 # Layer occupancy (ticks) |
| 1108system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1109 1110---------- End Simulation Statistics ---------- | 1144system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1145 1146---------- End Simulation Statistics ---------- |