| stats.txt (10063:9595c7a1d837) | stats.txt (10148:4574d5882066) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.920428 # Number of seconds simulated 4sim_ticks 1920428041000 # Number of ticks simulated 5final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.920416 # Number of seconds simulated 4sim_ticks 1920416181000 # Number of ticks simulated 5final_tick 1920416181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1405906 # Simulator instruction rate (inst/s) 8host_op_rate 1405905 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 48056353161 # Simulator tick rate (ticks/s) 10host_mem_usage 307800 # Number of bytes of host memory used 11host_seconds 39.96 # Real time elapsed on the host 12sim_insts 56182750 # Number of instructions simulated 13sim_ops 56182750 # Number of ops (including micro ops) simulated | 7host_inst_rate 1752736 # Simulator instruction rate (inst/s) 8host_op_rate 1752735 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59896862792 # Simulator tick rate (ticks/s) 10host_mem_usage 308520 # Number of bytes of host memory used 11host_seconds 32.06 # Real time elapsed on the host 12sim_insts 56196255 # Number of instructions simulated 13sim_ops 56196255 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 28349952 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7389824 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7389824 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388233 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 28363328 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7405888 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7405888 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory | 26system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::total 442968 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115466 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115466 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 442968 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 12938216 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 1381125 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 14762309 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 442968 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 442968 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 3848009 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 3848009 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 3848009 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 442968 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 12938216 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 1381125 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 18610318 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 442968 # Number of read requests accepted 44system.physmem.writeReqs 115466 # Number of write requests accepted 45system.physmem.readBursts 442968 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 115466 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 28346688 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7389440 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 28349952 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7389824 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue | 27system.physmem.num_reads::total 443177 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115717 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115717 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 443004 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 12945227 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 1381134 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 14769365 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 443004 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 443004 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 3856397 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 3856397 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 3856397 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 443004 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 12945227 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 1381134 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 18625763 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 443177 # Number of read requests accepted 44system.physmem.writeReqs 115717 # Number of write requests accepted 45system.physmem.readBursts 443177 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 115717 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 28355584 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue 49system.physmem.bytesWritten 7404416 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 28363328 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 7405888 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue |
| 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write | 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write |
| 55system.physmem.perBankRdBursts::0 27966 # Per bank write bursts 56system.physmem.perBankRdBursts::1 28089 # Per bank write bursts 57system.physmem.perBankRdBursts::2 28297 # Per bank write bursts 58system.physmem.perBankRdBursts::3 28053 # Per bank write bursts 59system.physmem.perBankRdBursts::4 27407 # Per bank write bursts 60system.physmem.perBankRdBursts::5 27545 # Per bank write bursts 61system.physmem.perBankRdBursts::6 26911 # Per bank write bursts 62system.physmem.perBankRdBursts::7 26762 # Per bank write bursts 63system.physmem.perBankRdBursts::8 27807 # Per bank write bursts 64system.physmem.perBankRdBursts::9 27255 # Per bank write bursts 65system.physmem.perBankRdBursts::10 27714 # Per bank write bursts 66system.physmem.perBankRdBursts::11 27327 # Per bank write bursts 67system.physmem.perBankRdBursts::12 27431 # Per bank write bursts 68system.physmem.perBankRdBursts::13 28073 # Per bank write bursts 69system.physmem.perBankRdBursts::14 28024 # Per bank write bursts 70system.physmem.perBankRdBursts::15 28256 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7722 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7593 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7833 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7543 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7010 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6982 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6469 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6223 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7224 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6661 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7099 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6780 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7009 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7722 # Per bank write bursts 85system.physmem.perBankWrBursts::14 7773 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7817 # Per bank write bursts | 55system.physmem.perBankRdBursts::0 27851 # Per bank write bursts 56system.physmem.perBankRdBursts::1 28132 # Per bank write bursts 57system.physmem.perBankRdBursts::2 28319 # Per bank write bursts 58system.physmem.perBankRdBursts::3 28010 # Per bank write bursts 59system.physmem.perBankRdBursts::4 27531 # Per bank write bursts 60system.physmem.perBankRdBursts::5 27552 # Per bank write bursts 61system.physmem.perBankRdBursts::6 26732 # Per bank write bursts 62system.physmem.perBankRdBursts::7 26855 # Per bank write bursts 63system.physmem.perBankRdBursts::8 27890 # Per bank write bursts 64system.physmem.perBankRdBursts::9 27110 # Per bank write bursts 65system.physmem.perBankRdBursts::10 27744 # Per bank write bursts 66system.physmem.perBankRdBursts::11 27465 # Per bank write bursts 67system.physmem.perBankRdBursts::12 27482 # Per bank write bursts 68system.physmem.perBankRdBursts::13 28199 # Per bank write bursts 69system.physmem.perBankRdBursts::14 28116 # Per bank write bursts 70system.physmem.perBankRdBursts::15 28068 # Per bank write bursts 71system.physmem.perBankWrBursts::0 7630 # Per bank write bursts 72system.physmem.perBankWrBursts::1 7636 # Per bank write bursts 73system.physmem.perBankWrBursts::2 7854 # Per bank write bursts 74system.physmem.perBankWrBursts::3 7535 # Per bank write bursts 75system.physmem.perBankWrBursts::4 7127 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6994 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6317 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6319 # Per bank write bursts 79system.physmem.perBankWrBursts::8 7309 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6529 # Per bank write bursts 81system.physmem.perBankWrBursts::10 7110 # Per bank write bursts 82system.physmem.perBankWrBursts::11 6915 # Per bank write bursts 83system.physmem.perBankWrBursts::12 7060 # Per bank write bursts 84system.physmem.perBankWrBursts::13 7819 # Per bank write bursts 85system.physmem.perBankWrBursts::14 7860 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7680 # Per bank write bursts |
| 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 88system.physmem.numWrRetry 12 # Number of times write queue was full causing retry 89system.physmem.totGap 1920416169000 # Total gap between requests | 88system.physmem.numWrRetry 11 # Number of times write queue was full causing retry 89system.physmem.totGap 1920404309000 # Total gap between requests |
| 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) | 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 96system.physmem.readPktSize::6 442968 # Read request sizes (log2) | 96system.physmem.readPktSize::6 443177 # Read request sizes (log2) |
| 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) | 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 103system.physmem.writePktSize::6 115466 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 403787 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 10503 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 5396 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 2702 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 2330 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 2324 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 1381 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 1352 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1304 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 1247 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 967 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 958 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 953 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 963 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see | 103system.physmem.writePktSize::6 115717 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 402196 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 1714 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 1586 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 1056 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 1122 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 4268 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 3790 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 3793 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3969 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 2575 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 2119 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2033 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1897 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 1793 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 1556 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 1524 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 1560 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 1710 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 1268 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see |
| 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 136system.physmem.wrQLenPdf::0 4636 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 4672 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 5362 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 6093 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 5438 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 5429 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 5533 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 5593 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 4916 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 4913 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 4899 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 5734 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 5836 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 5819 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 5861 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 5900 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 4775 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 4734 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4698 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 4676 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 213 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 175 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 26 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see 168system.physmem.bytesPerActivate::samples 46254 # Bytes accessed per row activation 169system.physmem.bytesPerActivate::mean 772.575777 # Bytes accessed per row activation 170system.physmem.bytesPerActivate::gmean 229.901205 # Bytes accessed per row activation 171system.physmem.bytesPerActivate::stdev 1785.674907 # Bytes accessed per row activation 172system.physmem.bytesPerActivate::64-67 16351 35.35% 35.35% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::128-131 6669 14.42% 49.77% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::192-195 4598 9.94% 59.71% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::256-259 2705 5.85% 65.56% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::320-323 1760 3.81% 69.36% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::384-387 1480 3.20% 72.56% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::448-451 1070 2.31% 74.88% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::512-515 848 1.83% 76.71% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::576-579 733 1.58% 78.29% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::640-643 614 1.33% 79.62% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::704-707 629 1.36% 80.98% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::768-771 417 0.90% 81.88% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::832-835 327 0.71% 82.59% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::896-899 305 0.66% 83.25% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::960-963 281 0.61% 83.86% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1024-1027 335 0.72% 84.58% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1088-1091 208 0.45% 85.03% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1152-1155 173 0.37% 85.40% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1216-1219 157 0.34% 85.74% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1280-1283 138 0.30% 86.04% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1344-1347 163 0.35% 86.39% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1408-1411 903 1.95% 88.35% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1472-1475 167 0.36% 88.71% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1536-1539 98 0.21% 88.92% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1600-1603 103 0.22% 89.14% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1664-1667 86 0.19% 89.33% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1728-1731 86 0.19% 89.51% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1792-1795 55 0.12% 89.63% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1856-1859 76 0.16% 89.80% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1920-1923 70 0.15% 89.95% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1984-1987 69 0.15% 90.10% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2048-2051 49 0.11% 90.20% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2112-2115 76 0.16% 90.37% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2176-2179 62 0.13% 90.50% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2240-2243 63 0.14% 90.64% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2304-2307 35 0.08% 90.71% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2368-2371 62 0.13% 90.85% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2432-2435 58 0.13% 90.97% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2496-2499 65 0.14% 91.11% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2560-2563 35 0.08% 91.19% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2624-2627 74 0.16% 91.35% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2688-2691 59 0.13% 91.48% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2752-2755 59 0.13% 91.61% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2816-2819 26 0.06% 91.66% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2880-2883 59 0.13% 91.79% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2944-2947 60 0.13% 91.92% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3008-3011 63 0.14% 92.05% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3072-3075 34 0.07% 92.13% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3136-3139 64 0.14% 92.27% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3200-3203 58 0.13% 92.39% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3264-3267 54 0.12% 92.51% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3328-3331 33 0.07% 92.58% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3392-3395 54 0.12% 92.70% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3456-3459 58 0.13% 92.82% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3520-3523 64 0.14% 92.96% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3584-3587 34 0.07% 93.03% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3648-3651 65 0.14% 93.17% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3712-3715 57 0.12% 93.30% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3776-3779 56 0.12% 93.42% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3840-3843 28 0.06% 93.48% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3904-3907 54 0.12% 93.60% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3968-3971 53 0.11% 93.71% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4032-4035 65 0.14% 93.85% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.92% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4160-4163 67 0.14% 94.06% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4224-4227 53 0.11% 94.18% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4288-4291 55 0.12% 94.30% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4352-4355 27 0.06% 94.36% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4416-4419 54 0.12% 94.47% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4480-4483 56 0.12% 94.59% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4544-4547 66 0.14% 94.74% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4608-4611 372 0.80% 95.54% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4672-4675 49 0.11% 95.65% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4736-4739 28 0.06% 95.71% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4800-4803 48 0.10% 95.81% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4864-4867 28 0.06% 95.87% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4928-4931 51 0.11% 95.98% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4992-4995 28 0.06% 96.04% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5056-5059 52 0.11% 96.15% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5120-5123 28 0.06% 96.21% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5184-5187 51 0.11% 96.32% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5248-5251 40 0.09% 96.41% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5312-5315 53 0.11% 96.53% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5376-5379 25 0.05% 96.58% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5440-5443 51 0.11% 96.69% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5504-5507 26 0.06% 96.75% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5568-5571 51 0.11% 96.86% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5632-5635 24 0.05% 96.91% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5696-5699 50 0.11% 97.02% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5760-5763 28 0.06% 97.08% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5824-5827 50 0.11% 97.19% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5888-5891 26 0.06% 97.24% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5952-5955 50 0.11% 97.35% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6016-6019 27 0.06% 97.41% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6080-6083 51 0.11% 97.52% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6144-6147 28 0.06% 97.58% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6208-6211 50 0.11% 97.69% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6272-6275 26 0.06% 97.74% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6336-6339 49 0.11% 97.85% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6400-6403 26 0.06% 97.91% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6464-6467 52 0.11% 98.02% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6528-6531 25 0.05% 98.07% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6592-6595 52 0.11% 98.18% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6656-6659 25 0.05% 98.24% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6720-6723 52 0.11% 98.35% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6784-6787 425 0.92% 99.27% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.27% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7168-7171 13 0.03% 99.30% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.30% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.30% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.31% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7680-7683 4 0.01% 99.31% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.32% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.32% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.32% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.33% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.34% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.34% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.35% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.35% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.35% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.36% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.36% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.38% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.38% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.38% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.38% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.39% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.39% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.39% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.39% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.40% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.40% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.40% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.40% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.41% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::10880-10883 2 0.00% 99.41% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.42% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.43% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.43% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.44% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.44% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.44% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.45% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.45% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.46% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.46% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.46% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.46% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.46% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::13504-13507 3 0.01% 99.47% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.47% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.48% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.48% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.49% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.49% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.49% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.50% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::14336-14339 2 0.00% 99.50% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.50% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.51% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::14848-14851 2 0.00% 99.51% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.51% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.52% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.52% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.52% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::15360-15363 35 0.08% 99.60% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.60% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.60% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.60% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.61% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.61% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.61% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::16384-16387 180 0.39% 100.00% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::total 46254 # Bytes accessed per row activation 353system.physmem.totQLat 6257775000 # Total ticks spent queuing 354system.physmem.totMemAccLat 14505282500 # Total ticks spent from burst creation until serviced by the DRAM 355system.physmem.totBusLat 2214585000 # Total ticks spent in databus transfers 356system.physmem.totBankLat 6032922500 # Total ticks spent accessing banks 357system.physmem.avgQLat 14128.55 # Average queueing delay per DRAM burst 358system.physmem.avgBankLat 13620.89 # Average bank access latency per DRAM burst | 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1547 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1870 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 2302 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 4388 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 4414 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4425 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 4435 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4520 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4492 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4550 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 6087 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 4874 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 6417 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 5284 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 5514 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 5555 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 5389 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 1180 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 1138 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 1092 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 1057 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 1105 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 1067 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 1057 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 1183 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1517 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1561 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1644 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 1709 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 1772 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 1718 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 1911 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 1872 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 1806 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 1830 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 1705 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 1482 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 1269 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 917 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 667 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 286 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 25 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 46117 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 658.429646 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 435.074403 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 420.347464 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 7559 16.39% 16.39% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 6338 13.74% 30.13% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 2663 5.77% 35.91% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1600 3.47% 39.38% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1319 2.86% 42.24% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 861 1.87% 44.11% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 594 1.29% 45.39% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 461 1.00% 46.39% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 24722 53.61% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 46117 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 6598 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 67.149288 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 2598.278449 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-8191 6595 99.95% 99.95% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::total 6598 # Reads before turning the bus around for writes 222system.physmem.wrPerTurnAround::samples 6598 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::mean 17.534707 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::gmean 17.278859 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::stdev 3.820387 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::16 4179 63.34% 63.34% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::17 322 4.88% 68.22% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::18 428 6.49% 74.70% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::19 1303 19.75% 94.45% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::20 22 0.33% 94.79% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::21 17 0.26% 95.04% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::22 11 0.17% 95.21% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::23 27 0.41% 95.62% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24 43 0.65% 96.27% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::25 28 0.42% 96.70% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::26 21 0.32% 97.01% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::27 25 0.38% 97.39% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28 19 0.29% 97.68% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::29 43 0.65% 98.33% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::30 4 0.06% 98.39% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::31 12 0.18% 98.58% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::32 10 0.15% 98.73% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::33 1 0.02% 98.74% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::34 5 0.08% 98.82% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::35 4 0.06% 98.88% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::37 5 0.08% 99.01% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::38 2 0.03% 99.05% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::39 9 0.14% 99.18% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::40 4 0.06% 99.24% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::41 4 0.06% 99.30% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::42 1 0.02% 99.32% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::43 2 0.03% 99.35% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::44 3 0.05% 99.39% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::45 1 0.02% 99.41% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::46 1 0.02% 99.42% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::47 6 0.09% 99.52% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::48 8 0.12% 99.64% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::49 5 0.08% 99.71% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::50 6 0.09% 99.80% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::52 3 0.05% 99.85% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::53 1 0.02% 99.86% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::54 4 0.06% 99.92% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::55 2 0.03% 99.95% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::56 1 0.02% 99.97% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::57 1 0.02% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::58 1 0.02% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::total 6598 # Writes before turning the bus around for reads 269system.physmem.totQLat 7790286250 # Total ticks spent queuing 270system.physmem.totMemAccLat 16274878750 # Total ticks spent from burst creation until serviced by the DRAM 271system.physmem.totBusLat 2215280000 # Total ticks spent in databus transfers 272system.physmem.totBankLat 6269312500 # Total ticks spent accessing banks 273system.physmem.avgQLat 17583.07 # Average queueing delay per DRAM burst 274system.physmem.avgBankLat 14150.16 # Average bank access latency per DRAM burst |
| 359system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 360system.physmem.avgMemAccLat 32749.44 # Average memory access latency per DRAM burst 361system.physmem.avgRdBW 14.76 # Average DRAM read bandwidth in MiByte/s 362system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s 363system.physmem.avgRdBWSys 14.76 # Average system read bandwidth in MiByte/s 364system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s | 276system.physmem.avgMemAccLat 36733.23 # Average memory access latency per DRAM burst 277system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 14.77 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s |
| 365system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 366system.physmem.busUtil 0.15 # Data bus utilization in percentage 367system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 368system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 282system.physmem.busUtil 0.15 # Data bus utilization in percentage 283system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 369system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing 370system.physmem.avgWrQLen 14.25 # Average write queue length when enqueuing 371system.physmem.readRowHits 419360 # Number of row buffer hits during reads 372system.physmem.writeRowHits 92763 # Number of row buffer hits during writes 373system.physmem.readRowHitRate 94.68 # Row buffer hit rate for reads 374system.physmem.writeRowHitRate 80.34 # Row buffer hit rate for writes 375system.physmem.avgGap 3438931.31 # Average gap between requests 376system.physmem.pageHitRate 91.72 # Row buffer hit rate, read and write combined 377system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state 378system.membus.throughput 18651952 # Throughput (bytes/s) 379system.membus.trans_dist::ReadReq 292310 # Transaction distribution 380system.membus.trans_dist::ReadResp 292310 # Transaction distribution | 285system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 286system.physmem.avgWrQLen 24.59 # Average write queue length when enqueuing 287system.physmem.readRowHits 398457 # Number of row buffer hits during reads 288system.physmem.writeRowHits 94179 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 81.39 # Row buffer hit rate for writes 291system.physmem.avgGap 3436079.67 # Average gap between requests 292system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined 293system.physmem.prechargeAllPercent 0.57 # Percentage of time for which DRAM has all the banks in precharge state 294system.membus.throughput 18667397 # Throughput (bytes/s) 295system.membus.trans_dist::ReadReq 292363 # Transaction distribution 296system.membus.trans_dist::ReadResp 292363 # Transaction distribution |
| 381system.membus.trans_dist::WriteReq 9650 # Transaction distribution 382system.membus.trans_dist::WriteResp 9650 # Transaction distribution | 297system.membus.trans_dist::WriteReq 9650 # Transaction distribution 298system.membus.trans_dist::WriteResp 9650 # Transaction distribution |
| 383system.membus.trans_dist::Writeback 115466 # Transaction distribution | 299system.membus.trans_dist::Writeback 115717 # Transaction distribution |
| 384system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 385system.membus.trans_dist::UpgradeResp 132 # Transaction distribution | 300system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 301system.membus.trans_dist::UpgradeResp 132 # Transaction distribution |
| 386system.membus.trans_dist::ReadExReq 158141 # Transaction distribution 387system.membus.trans_dist::ReadExResp 158141 # Transaction distribution | 302system.membus.trans_dist::ReadExReq 158297 # Transaction distribution 303system.membus.trans_dist::ReadExResp 158297 # Transaction distribution |
| 388system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) | 304system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) |
| 389system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877537 # Packet count per connected master and slave (bytes) 390system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910697 # Packet count per connected master and slave (bytes) | 305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878206 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911366 # Packet count per connected master and slave (bytes) |
| 391system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) 392system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) | 307system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) 308system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) |
| 393system.membus.pkt_count::total 1035377 # Packet count per connected master and slave (bytes) | 309system.membus.pkt_count::total 1036046 # Packet count per connected master and slave (bytes) |
| 394system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) | 310system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) |
| 395system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30430656 # Cumulative packet size per connected master and slave (bytes) 396system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475220 # Cumulative packet size per connected master and slave (bytes) | 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30460096 # Cumulative packet size per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30504660 # Cumulative packet size per connected master and slave (bytes) |
| 397system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) 398system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) | 313system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) |
| 399system.membus.tot_pkt_size::total 35784340 # Cumulative packet size per connected master and slave (bytes) 400system.membus.data_through_bus 35784340 # Total data (bytes) | 315system.membus.tot_pkt_size::total 35813780 # Cumulative packet size per connected master and slave (bytes) 316system.membus.data_through_bus 35813780 # Total data (bytes) |
| 401system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) 402system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) 403system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 317system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) 318system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) 319system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 404system.membus.reqLayer1.occupancy 1489694250 # Layer occupancy (ticks) | 320system.membus.reqLayer1.occupancy 1492987250 # Layer occupancy (ticks) |
| 405system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 321system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 406system.membus.respLayer1.occupancy 3746415596 # Layer occupancy (ticks) | 322system.membus.respLayer1.occupancy 3752965347 # Layer occupancy (ticks) |
| 407system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 323system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 408system.membus.respLayer2.occupancy 376299750 # Layer occupancy (ticks) | 324system.membus.respLayer2.occupancy 376688000 # Layer occupancy (ticks) |
| 409system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 410system.iocache.tags.replacements 41685 # number of replacements | 325system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 326system.iocache.tags.replacements 41685 # number of replacements |
| 411system.iocache.tags.tagsinuse 1.352288 # Cycle average of tags in use | 327system.iocache.tags.tagsinuse 1.344147 # Cycle average of tags in use |
| 412system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 413system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 414system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 328system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 329system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 330system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 415system.iocache.tags.warmup_cycle 1753529489000 # Cycle when the warmup percentage was hit. 416system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor 417system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy 418system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy | 331system.iocache.tags.warmup_cycle 1754500427000 # Cycle when the warmup percentage was hit. 332system.iocache.tags.occ_blocks::tsunami.ide 1.344147 # Average occupied blocks per requestor 333system.iocache.tags.occ_percent::tsunami.ide 0.084009 # Average percentage of cache occupancy 334system.iocache.tags.occ_percent::total 0.084009 # Average percentage of cache occupancy |
| 419system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 420system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 421system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 422system.iocache.tags.tag_accesses 375525 # Number of tag accesses 423system.iocache.tags.data_accesses 375525 # Number of data accesses 424system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 425system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 426system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 427system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 428system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 429system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 430system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 431system.iocache.overall_misses::total 41725 # number of overall misses | 335system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 336system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 337system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 338system.iocache.tags.tag_accesses 375525 # Number of tag accesses 339system.iocache.tags.data_accesses 375525 # Number of data accesses 340system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 341system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 342system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 343system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 344system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 345system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 346system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 347system.iocache.overall_misses::total 41725 # number of overall misses |
| 432system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles 433system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles 434system.iocache.WriteReq_miss_latency::tsunami.ide 12989922573 # number of WriteReq miss cycles 435system.iocache.WriteReq_miss_latency::total 12989922573 # number of WriteReq miss cycles 436system.iocache.demand_miss_latency::tsunami.ide 13011056956 # number of demand (read+write) miss cycles 437system.iocache.demand_miss_latency::total 13011056956 # number of demand (read+write) miss cycles 438system.iocache.overall_miss_latency::tsunami.ide 13011056956 # number of overall miss cycles 439system.iocache.overall_miss_latency::total 13011056956 # number of overall miss cycles | 348system.iocache.ReadReq_miss_latency::tsunami.ide 21134633 # number of ReadReq miss cycles 349system.iocache.ReadReq_miss_latency::total 21134633 # number of ReadReq miss cycles 350system.iocache.WriteReq_miss_latency::tsunami.ide 13148459442 # number of WriteReq miss cycles 351system.iocache.WriteReq_miss_latency::total 13148459442 # number of WriteReq miss cycles 352system.iocache.demand_miss_latency::tsunami.ide 13169594075 # number of demand (read+write) miss cycles 353system.iocache.demand_miss_latency::total 13169594075 # number of demand (read+write) miss cycles 354system.iocache.overall_miss_latency::tsunami.ide 13169594075 # number of overall miss cycles 355system.iocache.overall_miss_latency::total 13169594075 # number of overall miss cycles |
| 440system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 441system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 442system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 443system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 444system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 445system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 446system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 447system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 448system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 449system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 450system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 451system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 452system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 453system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 454system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 455system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 356system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 357system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 358system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 359system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 360system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 361system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 362system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 363system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 364system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 365system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 366system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 367system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 368system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 369system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 370system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 371system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 456system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency 457system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency 458system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775 # average WriteReq miss latency 459system.iocache.WriteReq_avg_miss_latency::total 312618.467775 # average WriteReq miss latency 460system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency 461system.iocache.demand_avg_miss_latency::total 311828.806615 # average overall miss latency 462system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency 463system.iocache.overall_avg_miss_latency::total 311828.806615 # average overall miss latency 464system.iocache.blocked_cycles::no_mshrs 403484 # number of cycles access was blocked | 372system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122165.508671 # average ReadReq miss latency 373system.iocache.ReadReq_avg_miss_latency::total 122165.508671 # average ReadReq miss latency 374system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316433.852570 # average WriteReq miss latency 375system.iocache.WriteReq_avg_miss_latency::total 316433.852570 # average WriteReq miss latency 376system.iocache.demand_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency 377system.iocache.demand_avg_miss_latency::total 315628.378071 # average overall miss latency 378system.iocache.overall_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency 379system.iocache.overall_avg_miss_latency::total 315628.378071 # average overall miss latency 380system.iocache.blocked_cycles::no_mshrs 393896 # number of cycles access was blocked |
| 465system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 381system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 466system.iocache.blocked::no_mshrs 29141 # number of cycles access was blocked | 382system.iocache.blocked::no_mshrs 28296 # number of cycles access was blocked |
| 467system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 383system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 468system.iocache.avg_blocked_cycles::no_mshrs 13.845922 # average number of cycles each access was blocked | 384system.iocache.avg_blocked_cycles::no_mshrs 13.920554 # average number of cycles each access was blocked |
| 469system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 470system.iocache.fast_writes 0 # number of fast writes performed 471system.iocache.cache_copies 0 # number of cache copies performed 472system.iocache.writebacks::writebacks 41512 # number of writebacks 473system.iocache.writebacks::total 41512 # number of writebacks 474system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 475system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 476system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 477system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 478system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 479system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 480system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 481system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses | 385system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 386system.iocache.fast_writes 0 # number of fast writes performed 387system.iocache.cache_copies 0 # number of cache copies performed 388system.iocache.writebacks::writebacks 41512 # number of writebacks 389system.iocache.writebacks::total 41512 # number of writebacks 390system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 391system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 392system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 393system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 394system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 395system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 396system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 397system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses |
| 482system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles 483system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles 484system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10827670073 # number of WriteReq MSHR miss cycles 485system.iocache.WriteReq_mshr_miss_latency::total 10827670073 # number of WriteReq MSHR miss cycles 486system.iocache.demand_mshr_miss_latency::tsunami.ide 10839807456 # number of demand (read+write) MSHR miss cycles 487system.iocache.demand_mshr_miss_latency::total 10839807456 # number of demand (read+write) MSHR miss cycles 488system.iocache.overall_mshr_miss_latency::tsunami.ide 10839807456 # number of overall MSHR miss cycles 489system.iocache.overall_mshr_miss_latency::total 10839807456 # number of overall MSHR miss cycles | 398system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137633 # number of ReadReq MSHR miss cycles 399system.iocache.ReadReq_mshr_miss_latency::total 12137633 # number of ReadReq MSHR miss cycles 400system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10985430442 # number of WriteReq MSHR miss cycles 401system.iocache.WriteReq_mshr_miss_latency::total 10985430442 # number of WriteReq MSHR miss cycles 402system.iocache.demand_mshr_miss_latency::tsunami.ide 10997568075 # number of demand (read+write) MSHR miss cycles 403system.iocache.demand_mshr_miss_latency::total 10997568075 # number of demand (read+write) MSHR miss cycles 404system.iocache.overall_mshr_miss_latency::tsunami.ide 10997568075 # number of overall MSHR miss cycles 405system.iocache.overall_mshr_miss_latency::total 10997568075 # number of overall MSHR miss cycles |
| 490system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 491system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 492system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 493system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 494system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 495system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 496system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 497system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 406system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 407system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 408system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 409system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 410system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 411system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 412system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 413system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 498system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency 499system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency 500system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218 # average WriteReq mshr miss latency 501system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218 # average WriteReq mshr miss latency 502system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency 503system.iocache.demand_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency 504system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency 505system.iocache.overall_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency | 414system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70159.728324 # average ReadReq mshr miss latency 415system.iocache.ReadReq_avg_mshr_miss_latency::total 70159.728324 # average ReadReq mshr miss latency 416system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264377.898585 # average WriteReq mshr miss latency 417system.iocache.WriteReq_avg_mshr_miss_latency::total 264377.898585 # average WriteReq mshr miss latency 418system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency 419system.iocache.demand_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency 420system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency 421system.iocache.overall_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency |
| 506system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 507system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 508system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 509system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 510system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 511system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 512system.disk0.dma_write_txs 395 # Number of DMA write transactions. 513system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 514system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 515system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 516system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 517system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 518system.disk2.dma_write_txs 1 # Number of DMA write transactions. 519system.cpu_clk_domain.clock 500 # Clock period in ticks 520system.cpu.dtb.fetch_hits 0 # ITB hits 521system.cpu.dtb.fetch_misses 0 # ITB misses 522system.cpu.dtb.fetch_acv 0 # ITB acv 523system.cpu.dtb.fetch_accesses 0 # ITB accesses | 422system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 423system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 424system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 425system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 426system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 427system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 428system.disk0.dma_write_txs 395 # Number of DMA write transactions. 429system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 430system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 431system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 432system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 433system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 434system.disk2.dma_write_txs 1 # Number of DMA write transactions. 435system.cpu_clk_domain.clock 500 # Clock period in ticks 436system.cpu.dtb.fetch_hits 0 # ITB hits 437system.cpu.dtb.fetch_misses 0 # ITB misses 438system.cpu.dtb.fetch_acv 0 # ITB acv 439system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 524system.cpu.dtb.read_hits 9064966 # DTB read hits 525system.cpu.dtb.read_misses 10312 # DTB read misses | 440system.cpu.dtb.read_hits 9066711 # DTB read hits 441system.cpu.dtb.read_misses 10324 # DTB read misses |
| 526system.cpu.dtb.read_acv 210 # DTB read access violations | 442system.cpu.dtb.read_acv 210 # DTB read access violations |
| 527system.cpu.dtb.read_accesses 728817 # DTB read accesses 528system.cpu.dtb.write_hits 6356267 # DTB write hits 529system.cpu.dtb.write_misses 1140 # DTB write misses | 443system.cpu.dtb.read_accesses 728853 # DTB read accesses 444system.cpu.dtb.write_hits 6357503 # DTB write hits 445system.cpu.dtb.write_misses 1142 # DTB write misses |
| 530system.cpu.dtb.write_acv 157 # DTB write access violations | 446system.cpu.dtb.write_acv 157 # DTB write access violations |
| 531system.cpu.dtb.write_accesses 291929 # DTB write accesses 532system.cpu.dtb.data_hits 15421233 # DTB hits 533system.cpu.dtb.data_misses 11452 # DTB misses | 447system.cpu.dtb.write_accesses 291931 # DTB write accesses 448system.cpu.dtb.data_hits 15424214 # DTB hits 449system.cpu.dtb.data_misses 11466 # DTB misses |
| 534system.cpu.dtb.data_acv 367 # DTB access violations | 450system.cpu.dtb.data_acv 367 # DTB access violations |
| 535system.cpu.dtb.data_accesses 1020746 # DTB accesses 536system.cpu.itb.fetch_hits 4973920 # ITB hits 537system.cpu.itb.fetch_misses 4997 # ITB misses | 451system.cpu.dtb.data_accesses 1020784 # DTB accesses 452system.cpu.itb.fetch_hits 4974520 # ITB hits 453system.cpu.itb.fetch_misses 5010 # ITB misses |
| 538system.cpu.itb.fetch_acv 184 # ITB acv | 454system.cpu.itb.fetch_acv 184 # ITB acv |
| 539system.cpu.itb.fetch_accesses 4978917 # ITB accesses | 455system.cpu.itb.fetch_accesses 4979530 # ITB accesses |
| 540system.cpu.itb.read_hits 0 # DTB read hits 541system.cpu.itb.read_misses 0 # DTB read misses 542system.cpu.itb.read_acv 0 # DTB read access violations 543system.cpu.itb.read_accesses 0 # DTB read accesses 544system.cpu.itb.write_hits 0 # DTB write hits 545system.cpu.itb.write_misses 0 # DTB write misses 546system.cpu.itb.write_acv 0 # DTB write access violations 547system.cpu.itb.write_accesses 0 # DTB write accesses 548system.cpu.itb.data_hits 0 # DTB hits 549system.cpu.itb.data_misses 0 # DTB misses 550system.cpu.itb.data_acv 0 # DTB access violations 551system.cpu.itb.data_accesses 0 # DTB accesses | 456system.cpu.itb.read_hits 0 # DTB read hits 457system.cpu.itb.read_misses 0 # DTB read misses 458system.cpu.itb.read_acv 0 # DTB read access violations 459system.cpu.itb.read_accesses 0 # DTB read accesses 460system.cpu.itb.write_hits 0 # DTB write hits 461system.cpu.itb.write_misses 0 # DTB write misses 462system.cpu.itb.write_acv 0 # DTB write access violations 463system.cpu.itb.write_accesses 0 # DTB write accesses 464system.cpu.itb.data_hits 0 # DTB hits 465system.cpu.itb.data_misses 0 # DTB misses 466system.cpu.itb.data_acv 0 # DTB access violations 467system.cpu.itb.data_accesses 0 # DTB accesses |
| 552system.cpu.numCycles 3840856082 # number of cpu cycles simulated | 468system.cpu.numCycles 3840832362 # number of cpu cycles simulated |
| 553system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 554system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 469system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 470system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 555system.cpu.committedInsts 56182750 # Number of instructions committed 556system.cpu.committedOps 56182750 # Number of ops (including micro ops) committed 557system.cpu.num_int_alu_accesses 52054772 # Number of integer alu accesses 558system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses 559system.cpu.num_func_calls 1483342 # number of times a function call or return occured 560system.cpu.num_conditional_control_insts 6468084 # number of instructions that are conditional controls 561system.cpu.num_int_insts 52054772 # number of integer instructions 562system.cpu.num_fp_insts 324326 # number of float instructions 563system.cpu.num_int_register_reads 71321847 # number of times the integer registers were read 564system.cpu.num_int_register_writes 38521555 # number of times the integer registers were written 565system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read 566system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written 567system.cpu.num_mem_refs 15473812 # number of memory refs 568system.cpu.num_load_insts 9101789 # Number of load instructions 569system.cpu.num_store_insts 6372023 # Number of store instructions 570system.cpu.num_idle_cycles 3588896828.998131 # Number of idle cycles 571system.cpu.num_busy_cycles 251959253.001869 # Number of busy cycles 572system.cpu.not_idle_fraction 0.065600 # Percentage of non-idle cycles 573system.cpu.idle_fraction 0.934400 # Percentage of idle cycles 574system.cpu.Branches 8421946 # Number of branches fetched | 471system.cpu.committedInsts 56196255 # Number of instructions committed 472system.cpu.committedOps 56196255 # Number of ops (including micro ops) committed 473system.cpu.num_int_alu_accesses 52067788 # Number of integer alu accesses 474system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses 475system.cpu.num_func_calls 1483738 # number of times a function call or return occured 476system.cpu.num_conditional_control_insts 6469789 # number of instructions that are conditional controls 477system.cpu.num_int_insts 52067788 # number of integer instructions 478system.cpu.num_fp_insts 324393 # number of float instructions 479system.cpu.num_int_register_reads 71342399 # number of times the integer registers were read 480system.cpu.num_int_register_writes 38531411 # number of times the integer registers were written 481system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read 482system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written 483system.cpu.num_mem_refs 15476821 # number of memory refs 484system.cpu.num_load_insts 9103557 # Number of load instructions 485system.cpu.num_store_insts 6373264 # Number of store instructions 486system.cpu.num_idle_cycles 3589010980.998131 # Number of idle cycles 487system.cpu.num_busy_cycles 251821381.001869 # Number of busy cycles 488system.cpu.not_idle_fraction 0.065564 # Percentage of non-idle cycles 489system.cpu.idle_fraction 0.934436 # Percentage of idle cycles 490system.cpu.Branches 8424076 # Number of branches fetched |
| 575system.cpu.kern.inst.arm 0 # number of arm instructions executed | 491system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 576system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed 577system.cpu.kern.inst.hwrei 211963 # number of hwrei instructions executed 578system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl | 492system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed 493system.cpu.kern.inst.hwrei 212001 # number of hwrei instructions executed 494system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl |
| 579system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 580system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl | 495system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl 496system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl |
| 581system.cpu.kern.ipl_count::31 106216 57.99% 100.00% # number of times we switched to this ipl 582system.cpu.kern.ipl_count::total 183174 # number of times we switched to this ipl 583system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl | 497system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl 498system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl 499system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl |
| 584system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 585system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl | 500system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl 501system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl |
| 586system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl 587system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl 588system.cpu.kern.ipl_ticks::0 1858257404500 96.76% 96.76% # number of cycles we spent at this ipl 589system.cpu.kern.ipl_ticks::21 91623500 0.00% 96.77% # number of cycles we spent at this ipl 590system.cpu.kern.ipl_ticks::22 737068500 0.04% 96.81% # number of cycles we spent at this ipl 591system.cpu.kern.ipl_ticks::31 61341210500 3.19% 100.00% # number of cycles we spent at this ipl 592system.cpu.kern.ipl_ticks::total 1920427307000 # number of cycles we spent at this ipl 593system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl | 502system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl 503system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl 504system.cpu.kern.ipl_ticks::0 1858066400000 96.75% 96.75% # number of cycles we spent at this ipl 505system.cpu.kern.ipl_ticks::21 91407000 0.00% 96.76% # number of cycles we spent at this ipl 506system.cpu.kern.ipl_ticks::22 737349500 0.04% 96.80% # number of cycles we spent at this ipl 507system.cpu.kern.ipl_ticks::31 61520290500 3.20% 100.00% # number of cycles we spent at this ipl 508system.cpu.kern.ipl_ticks::total 1920415447000 # number of cycles we spent at this ipl 509system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl |
| 594system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 595system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 510system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 511system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 596system.cpu.kern.ipl_used::31 0.692250 # fraction of swpipl calls that actually changed the ipl 597system.cpu.kern.ipl_used::total 0.814084 # fraction of swpipl calls that actually changed the ipl | 512system.cpu.kern.ipl_used::31 0.692248 # fraction of swpipl calls that actually changed the ipl 513system.cpu.kern.ipl_used::total 0.814083 # fraction of swpipl calls that actually changed the ipl |
| 598system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 599system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 600system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 601system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 602system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 603system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 604system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 605system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 625system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 626system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 627system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 628system.cpu.kern.syscall::total 326 # number of syscalls executed 629system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 630system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 631system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 632system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed | 514system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 515system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 516system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 517system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 518system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 519system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 520system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 521system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 19 unchanged lines hidden (view full) --- 541system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 542system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 543system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 544system.cpu.kern.syscall::total 326 # number of syscalls executed 545system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 546system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 547system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 548system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed |
| 633system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed | 549system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed |
| 634system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 635system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed | 550system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed 551system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed |
| 636system.cpu.kern.callpal::swpipl 175953 91.22% 93.41% # number of callpals executed | 552system.cpu.kern.callpal::swpipl 175963 91.22% 93.41% # number of callpals executed |
| 637system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed 638system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 639system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 640system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed 641system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 642system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed 643system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 644system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 553system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed 554system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed 555system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed 556system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed 557system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed 558system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed 559system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 560system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 645system.cpu.kern.callpal::total 192898 # number of callpals executed 646system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches 647system.cpu.kern.mode_switch::user 1739 # number of protection mode switches | 561system.cpu.kern.callpal::total 192909 # number of callpals executed 562system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches 563system.cpu.kern.mode_switch::user 1741 # number of protection mode switches |
| 648system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches | 564system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches |
| 649system.cpu.kern.mode_good::kernel 1908 650system.cpu.kern.mode_good::user 1739 651system.cpu.kern.mode_good::idle 169 652system.cpu.kern.mode_switch_good::kernel 0.323225 # fraction of useful protection mode switches | 565system.cpu.kern.mode_good::kernel 1911 566system.cpu.kern.mode_good::user 1741 567system.cpu.kern.mode_good::idle 170 568system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches |
| 653system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 569system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 654system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches 655system.cpu.kern.mode_switch_good::total 0.391907 # fraction of useful protection mode switches 656system.cpu.kern.mode_ticks::kernel 46222890000 2.41% 2.41% # number of ticks spent at the given mode 657system.cpu.kern.mode_ticks::user 5212630500 0.27% 2.68% # number of ticks spent at the given mode 658system.cpu.kern.mode_ticks::idle 1868991784500 97.32% 100.00% # number of ticks spent at the given mode 659system.cpu.kern.swap_context 4176 # number of times the context was actually changed | 570system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches 571system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches 572system.cpu.kern.mode_ticks::kernel 46067941500 2.40% 2.40% # number of ticks spent at the given mode 573system.cpu.kern.mode_ticks::user 5182686000 0.27% 2.67% # number of ticks spent at the given mode 574system.cpu.kern.mode_ticks::idle 1869164817500 97.33% 100.00% # number of ticks spent at the given mode 575system.cpu.kern.swap_context 4177 # number of times the context was actually changed |
| 660system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 661system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 662system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 663system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 664system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 665system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 666system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 667system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 683system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 684system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 685system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 686system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 687system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 688system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 689system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 690system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 576system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 577system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 578system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 579system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 580system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 581system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 582system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 583system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 599system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 600system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 601system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 602system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 603system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 604system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 605system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 606system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 691system.iobus.throughput 1409150 # Throughput (bytes/s) | 607system.iobus.throughput 1409159 # Throughput (bytes/s) |
| 692system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 693system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 694system.iobus.trans_dist::WriteReq 51202 # Transaction distribution 695system.iobus.trans_dist::WriteResp 51202 # Transaction distribution 696system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) 697system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 698system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 699system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 43 unchanged lines hidden (view full) --- 743system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 744system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 745system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 746system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 747system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 748system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 749system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 750system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 608system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 609system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 610system.iobus.trans_dist::WriteReq 51202 # Transaction distribution 611system.iobus.trans_dist::WriteResp 51202 # Transaction distribution 612system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) 613system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 614system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 615system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 43 unchanged lines hidden (view full) --- 659system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 660system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 662system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 663system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 664system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 665system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 666system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 751system.iobus.reqLayer29.occupancy 377727206 # Layer occupancy (ticks) | 667system.iobus.reqLayer29.occupancy 380034075 # Layer occupancy (ticks) |
| 752system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 753system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 754system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 755system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) 756system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 668system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 669system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 670system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 671system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) 672system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 757system.iobus.respLayer1.occupancy 42674250 # Layer occupancy (ticks) | 673system.iobus.respLayer1.occupancy 43162000 # Layer occupancy (ticks) |
| 758system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 674system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 759system.cpu.icache.tags.replacements 928358 # number of replacements 760system.cpu.icache.tags.tagsinuse 508.321671 # Cycle average of tags in use 761system.cpu.icache.tags.total_refs 55265541 # Total number of references to valid blocks. 762system.cpu.icache.tags.sampled_refs 928869 # Sample count of references to valid blocks. 763system.cpu.icache.tags.avg_refs 59.497670 # Average number of references to valid blocks. 764system.cpu.icache.tags.warmup_cycle 39723654250 # Cycle when the warmup percentage was hit. 765system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor 766system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy 767system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy | 675system.cpu.icache.tags.replacements 928494 # number of replacements 676system.cpu.icache.tags.tagsinuse 508.301721 # Cycle average of tags in use 677system.cpu.icache.tags.total_refs 55278924 # Total number of references to valid blocks. 678system.cpu.icache.tags.sampled_refs 929005 # Sample count of references to valid blocks. 679system.cpu.icache.tags.avg_refs 59.503365 # Average number of references to valid blocks. 680system.cpu.icache.tags.warmup_cycle 39895254250 # Cycle when the warmup percentage was hit. 681system.cpu.icache.tags.occ_blocks::cpu.inst 508.301721 # Average occupied blocks per requestor 682system.cpu.icache.tags.occ_percent::cpu.inst 0.992777 # Average percentage of cache occupancy 683system.cpu.icache.tags.occ_percent::total 0.992777 # Average percentage of cache occupancy |
| 768system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 769system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id | 684system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 685system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id |
| 770system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 771system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id | 686system.cpu.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id |
| 772system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 773system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 688system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 689system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 774system.cpu.icache.tags.tag_accesses 57123599 # Number of tag accesses 775system.cpu.icache.tags.data_accesses 57123599 # Number of data accesses 776system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits 777system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits 778system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits 779system.cpu.icache.demand_hits::total 55265541 # number of demand (read+write) hits 780system.cpu.icache.overall_hits::cpu.inst 55265541 # number of overall hits 781system.cpu.icache.overall_hits::total 55265541 # number of overall hits 782system.cpu.icache.ReadReq_misses::cpu.inst 929029 # number of ReadReq misses 783system.cpu.icache.ReadReq_misses::total 929029 # number of ReadReq misses 784system.cpu.icache.demand_misses::cpu.inst 929029 # number of demand (read+write) misses 785system.cpu.icache.demand_misses::total 929029 # number of demand (read+write) misses 786system.cpu.icache.overall_misses::cpu.inst 929029 # number of overall misses 787system.cpu.icache.overall_misses::total 929029 # number of overall misses 788system.cpu.icache.ReadReq_miss_latency::cpu.inst 12961853258 # number of ReadReq miss cycles 789system.cpu.icache.ReadReq_miss_latency::total 12961853258 # number of ReadReq miss cycles 790system.cpu.icache.demand_miss_latency::cpu.inst 12961853258 # number of demand (read+write) miss cycles 791system.cpu.icache.demand_miss_latency::total 12961853258 # number of demand (read+write) miss cycles 792system.cpu.icache.overall_miss_latency::cpu.inst 12961853258 # number of overall miss cycles 793system.cpu.icache.overall_miss_latency::total 12961853258 # number of overall miss cycles 794system.cpu.icache.ReadReq_accesses::cpu.inst 56194570 # number of ReadReq accesses(hits+misses) 795system.cpu.icache.ReadReq_accesses::total 56194570 # number of ReadReq accesses(hits+misses) 796system.cpu.icache.demand_accesses::cpu.inst 56194570 # number of demand (read+write) accesses 797system.cpu.icache.demand_accesses::total 56194570 # number of demand (read+write) accesses 798system.cpu.icache.overall_accesses::cpu.inst 56194570 # number of overall (read+write) accesses 799system.cpu.icache.overall_accesses::total 56194570 # number of overall (read+write) accesses 800system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses 801system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses 802system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses 803system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses 804system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses 805system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses 806system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13952.043755 # average ReadReq miss latency 807system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755 # average ReadReq miss latency 808system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency 809system.cpu.icache.demand_avg_miss_latency::total 13952.043755 # average overall miss latency 810system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency 811system.cpu.icache.overall_avg_miss_latency::total 13952.043755 # average overall miss latency | 690system.cpu.icache.tags.tag_accesses 57137254 # Number of tag accesses 691system.cpu.icache.tags.data_accesses 57137254 # Number of data accesses 692system.cpu.icache.ReadReq_hits::cpu.inst 55278924 # number of ReadReq hits 693system.cpu.icache.ReadReq_hits::total 55278924 # number of ReadReq hits 694system.cpu.icache.demand_hits::cpu.inst 55278924 # number of demand (read+write) hits 695system.cpu.icache.demand_hits::total 55278924 # number of demand (read+write) hits 696system.cpu.icache.overall_hits::cpu.inst 55278924 # number of overall hits 697system.cpu.icache.overall_hits::total 55278924 # number of overall hits 698system.cpu.icache.ReadReq_misses::cpu.inst 929165 # number of ReadReq misses 699system.cpu.icache.ReadReq_misses::total 929165 # number of ReadReq misses 700system.cpu.icache.demand_misses::cpu.inst 929165 # number of demand (read+write) misses 701system.cpu.icache.demand_misses::total 929165 # number of demand (read+write) misses 702system.cpu.icache.overall_misses::cpu.inst 929165 # number of overall misses 703system.cpu.icache.overall_misses::total 929165 # number of overall misses 704system.cpu.icache.ReadReq_miss_latency::cpu.inst 12919006759 # number of ReadReq miss cycles 705system.cpu.icache.ReadReq_miss_latency::total 12919006759 # number of ReadReq miss cycles 706system.cpu.icache.demand_miss_latency::cpu.inst 12919006759 # number of demand (read+write) miss cycles 707system.cpu.icache.demand_miss_latency::total 12919006759 # number of demand (read+write) miss cycles 708system.cpu.icache.overall_miss_latency::cpu.inst 12919006759 # number of overall miss cycles 709system.cpu.icache.overall_miss_latency::total 12919006759 # number of overall miss cycles 710system.cpu.icache.ReadReq_accesses::cpu.inst 56208089 # number of ReadReq accesses(hits+misses) 711system.cpu.icache.ReadReq_accesses::total 56208089 # number of ReadReq accesses(hits+misses) 712system.cpu.icache.demand_accesses::cpu.inst 56208089 # number of demand (read+write) accesses 713system.cpu.icache.demand_accesses::total 56208089 # number of demand (read+write) accesses 714system.cpu.icache.overall_accesses::cpu.inst 56208089 # number of overall (read+write) accesses 715system.cpu.icache.overall_accesses::total 56208089 # number of overall (read+write) accesses 716system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016531 # miss rate for ReadReq accesses 717system.cpu.icache.ReadReq_miss_rate::total 0.016531 # miss rate for ReadReq accesses 718system.cpu.icache.demand_miss_rate::cpu.inst 0.016531 # miss rate for demand accesses 719system.cpu.icache.demand_miss_rate::total 0.016531 # miss rate for demand accesses 720system.cpu.icache.overall_miss_rate::cpu.inst 0.016531 # miss rate for overall accesses 721system.cpu.icache.overall_miss_rate::total 0.016531 # miss rate for overall accesses 722system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.888716 # average ReadReq miss latency 723system.cpu.icache.ReadReq_avg_miss_latency::total 13903.888716 # average ReadReq miss latency 724system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency 725system.cpu.icache.demand_avg_miss_latency::total 13903.888716 # average overall miss latency 726system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency 727system.cpu.icache.overall_avg_miss_latency::total 13903.888716 # average overall miss latency |
| 812system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 813system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 814system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 815system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 816system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 817system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 818system.cpu.icache.fast_writes 0 # number of fast writes performed 819system.cpu.icache.cache_copies 0 # number of cache copies performed | 728system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 729system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 730system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 731system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 732system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 733system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 734system.cpu.icache.fast_writes 0 # number of fast writes performed 735system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 820system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929029 # number of ReadReq MSHR misses 821system.cpu.icache.ReadReq_mshr_misses::total 929029 # number of ReadReq MSHR misses 822system.cpu.icache.demand_mshr_misses::cpu.inst 929029 # number of demand (read+write) MSHR misses 823system.cpu.icache.demand_mshr_misses::total 929029 # number of demand (read+write) MSHR misses 824system.cpu.icache.overall_mshr_misses::cpu.inst 929029 # number of overall MSHR misses 825system.cpu.icache.overall_mshr_misses::total 929029 # number of overall MSHR misses 826system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11098555742 # number of ReadReq MSHR miss cycles 827system.cpu.icache.ReadReq_mshr_miss_latency::total 11098555742 # number of ReadReq MSHR miss cycles 828system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11098555742 # number of demand (read+write) MSHR miss cycles 829system.cpu.icache.demand_mshr_miss_latency::total 11098555742 # number of demand (read+write) MSHR miss cycles 830system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11098555742 # number of overall MSHR miss cycles 831system.cpu.icache.overall_mshr_miss_latency::total 11098555742 # number of overall MSHR miss cycles 832system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses 833system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses 834system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses 835system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses 836system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses 837system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses 838system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11946.403979 # average ReadReq mshr miss latency 839system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11946.403979 # average ReadReq mshr miss latency 840system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency 841system.cpu.icache.demand_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency 842system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency 843system.cpu.icache.overall_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency | 736system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929165 # number of ReadReq MSHR misses 737system.cpu.icache.ReadReq_mshr_misses::total 929165 # number of ReadReq MSHR misses 738system.cpu.icache.demand_mshr_misses::cpu.inst 929165 # number of demand (read+write) MSHR misses 739system.cpu.icache.demand_mshr_misses::total 929165 # number of demand (read+write) MSHR misses 740system.cpu.icache.overall_mshr_misses::cpu.inst 929165 # number of overall MSHR misses 741system.cpu.icache.overall_mshr_misses::total 929165 # number of overall MSHR misses 742system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11055577241 # number of ReadReq MSHR miss cycles 743system.cpu.icache.ReadReq_mshr_miss_latency::total 11055577241 # number of ReadReq MSHR miss cycles 744system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11055577241 # number of demand (read+write) MSHR miss cycles 745system.cpu.icache.demand_mshr_miss_latency::total 11055577241 # number of demand (read+write) MSHR miss cycles 746system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11055577241 # number of overall MSHR miss cycles 747system.cpu.icache.overall_mshr_miss_latency::total 11055577241 # number of overall MSHR miss cycles 748system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for ReadReq accesses 749system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016531 # mshr miss rate for ReadReq accesses 750system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for demand accesses 751system.cpu.icache.demand_mshr_miss_rate::total 0.016531 # mshr miss rate for demand accesses 752system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for overall accesses 753system.cpu.icache.overall_mshr_miss_rate::total 0.016531 # mshr miss rate for overall accesses 754system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.400436 # average ReadReq mshr miss latency 755system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.400436 # average ReadReq mshr miss latency 756system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency 757system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency 758system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency 759system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency |
| 844system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 760system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 845system.cpu.l2cache.tags.replacements 336056 # number of replacements 846system.cpu.l2cache.tags.tagsinuse 65296.863719 # Cycle average of tags in use 847system.cpu.l2cache.tags.total_refs 2447536 # Total number of references to valid blocks. 848system.cpu.l2cache.tags.sampled_refs 401218 # Sample count of references to valid blocks. 849system.cpu.l2cache.tags.avg_refs 6.100265 # Average number of references to valid blocks. 850system.cpu.l2cache.tags.warmup_cycle 6747777750 # Cycle when the warmup percentage was hit. 851system.cpu.l2cache.tags.occ_blocks::writebacks 55582.845445 # Average occupied blocks per requestor 852system.cpu.l2cache.tags.occ_blocks::cpu.inst 4758.900638 # Average occupied blocks per requestor 853system.cpu.l2cache.tags.occ_blocks::cpu.data 4955.117636 # Average occupied blocks per requestor 854system.cpu.l2cache.tags.occ_percent::writebacks 0.848127 # Average percentage of cache occupancy 855system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072615 # Average percentage of cache occupancy 856system.cpu.l2cache.tags.occ_percent::cpu.data 0.075609 # Average percentage of cache occupancy 857system.cpu.l2cache.tags.occ_percent::total 0.996351 # Average percentage of cache occupancy | 761system.cpu.l2cache.tags.replacements 336265 # number of replacements 762system.cpu.l2cache.tags.tagsinuse 65295.577509 # Cycle average of tags in use 763system.cpu.l2cache.tags.total_refs 2447728 # Total number of references to valid blocks. 764system.cpu.l2cache.tags.sampled_refs 401427 # Sample count of references to valid blocks. 765system.cpu.l2cache.tags.avg_refs 6.097567 # Average number of references to valid blocks. 766system.cpu.l2cache.tags.warmup_cycle 6793166750 # Cycle when the warmup percentage was hit. 767system.cpu.l2cache.tags.occ_blocks::writebacks 55588.679267 # Average occupied blocks per requestor 768system.cpu.l2cache.tags.occ_blocks::cpu.inst 4757.001179 # Average occupied blocks per requestor 769system.cpu.l2cache.tags.occ_blocks::cpu.data 4949.897063 # Average occupied blocks per requestor 770system.cpu.l2cache.tags.occ_percent::writebacks 0.848216 # Average percentage of cache occupancy 771system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072586 # Average percentage of cache occupancy 772system.cpu.l2cache.tags.occ_percent::cpu.data 0.075529 # Average percentage of cache occupancy 773system.cpu.l2cache.tags.occ_percent::total 0.996331 # Average percentage of cache occupancy |
| 858system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 859system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id | 774system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id 775system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id |
| 860system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1050 # Occupied blocks per task id 861system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4896 # Occupied blocks per task id 862system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3257 # Occupied blocks per task id 863system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55781 # Occupied blocks per task id | 776system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id 777system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4882 # Occupied blocks per task id 778system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3251 # Occupied blocks per task id 779system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55777 # Occupied blocks per task id |
| 864system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id | 780system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id |
| 865system.cpu.l2cache.tags.tag_accesses 25947571 # Number of tag accesses 866system.cpu.l2cache.tags.data_accesses 25947571 # Number of data accesses 867system.cpu.l2cache.ReadReq_hits::cpu.inst 915717 # number of ReadReq hits 868system.cpu.l2cache.ReadReq_hits::cpu.data 814814 # number of ReadReq hits 869system.cpu.l2cache.ReadReq_hits::total 1730531 # number of ReadReq hits 870system.cpu.l2cache.Writeback_hits::writebacks 835114 # number of Writeback hits 871system.cpu.l2cache.Writeback_hits::total 835114 # number of Writeback hits | 781system.cpu.l2cache.tags.tag_accesses 25952661 # Number of tag accesses 782system.cpu.l2cache.tags.data_accesses 25952661 # Number of data accesses 783system.cpu.l2cache.ReadReq_hits::cpu.inst 915852 # number of ReadReq hits 784system.cpu.l2cache.ReadReq_hits::cpu.data 814775 # number of ReadReq hits 785system.cpu.l2cache.ReadReq_hits::total 1730627 # number of ReadReq hits 786system.cpu.l2cache.Writeback_hits::writebacks 835359 # number of Writeback hits 787system.cpu.l2cache.Writeback_hits::total 835359 # number of Writeback hits |
| 872system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 873system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 788system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 789system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 874system.cpu.l2cache.ReadExReq_hits::cpu.data 187645 # number of ReadExReq hits 875system.cpu.l2cache.ReadExReq_hits::total 187645 # number of ReadExReq hits 876system.cpu.l2cache.demand_hits::cpu.inst 915717 # number of demand (read+write) hits 877system.cpu.l2cache.demand_hits::cpu.data 1002459 # number of demand (read+write) hits 878system.cpu.l2cache.demand_hits::total 1918176 # number of demand (read+write) hits 879system.cpu.l2cache.overall_hits::cpu.inst 915717 # number of overall hits 880system.cpu.l2cache.overall_hits::cpu.data 1002459 # number of overall hits 881system.cpu.l2cache.overall_hits::total 1918176 # number of overall hits 882system.cpu.l2cache.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses 883system.cpu.l2cache.ReadReq_misses::cpu.data 271915 # number of ReadReq misses 884system.cpu.l2cache.ReadReq_misses::total 285207 # number of ReadReq misses | 790system.cpu.l2cache.ReadExReq_hits::cpu.data 187681 # number of ReadExReq hits 791system.cpu.l2cache.ReadExReq_hits::total 187681 # number of ReadExReq hits 792system.cpu.l2cache.demand_hits::cpu.inst 915852 # number of demand (read+write) hits 793system.cpu.l2cache.demand_hits::cpu.data 1002456 # number of demand (read+write) hits 794system.cpu.l2cache.demand_hits::total 1918308 # number of demand (read+write) hits 795system.cpu.l2cache.overall_hits::cpu.inst 915852 # number of overall hits 796system.cpu.l2cache.overall_hits::cpu.data 1002456 # number of overall hits 797system.cpu.l2cache.overall_hits::total 1918308 # number of overall hits 798system.cpu.l2cache.ReadReq_misses::cpu.inst 13293 # number of ReadReq misses 799system.cpu.l2cache.ReadReq_misses::cpu.data 271967 # number of ReadReq misses 800system.cpu.l2cache.ReadReq_misses::total 285260 # number of ReadReq misses |
| 885system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 886system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses | 801system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 802system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses |
| 887system.cpu.l2cache.ReadExReq_misses::cpu.data 116708 # number of ReadExReq misses 888system.cpu.l2cache.ReadExReq_misses::total 116708 # number of ReadExReq misses 889system.cpu.l2cache.demand_misses::cpu.inst 13292 # number of demand (read+write) misses 890system.cpu.l2cache.demand_misses::cpu.data 388623 # number of demand (read+write) misses 891system.cpu.l2cache.demand_misses::total 401915 # number of demand (read+write) misses 892system.cpu.l2cache.overall_misses::cpu.inst 13292 # number of overall misses 893system.cpu.l2cache.overall_misses::cpu.data 388623 # number of overall misses 894system.cpu.l2cache.overall_misses::total 401915 # number of overall misses 895system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1012336742 # number of ReadReq miss cycles 896system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17564329991 # number of ReadReq miss cycles 897system.cpu.l2cache.ReadReq_miss_latency::total 18576666733 # number of ReadReq miss cycles | 803system.cpu.l2cache.ReadExReq_misses::cpu.data 116864 # number of ReadExReq misses 804system.cpu.l2cache.ReadExReq_misses::total 116864 # number of ReadExReq misses 805system.cpu.l2cache.demand_misses::cpu.inst 13293 # number of demand (read+write) misses 806system.cpu.l2cache.demand_misses::cpu.data 388831 # number of demand (read+write) misses 807system.cpu.l2cache.demand_misses::total 402124 # number of demand (read+write) misses 808system.cpu.l2cache.overall_misses::cpu.inst 13293 # number of overall misses 809system.cpu.l2cache.overall_misses::cpu.data 388831 # number of overall misses 810system.cpu.l2cache.overall_misses::total 402124 # number of overall misses 811system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 967872241 # number of ReadReq miss cycles 812system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17714808491 # number of ReadReq miss cycles 813system.cpu.l2cache.ReadReq_miss_latency::total 18682680732 # number of ReadReq miss cycles |
| 898system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles 899system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles | 814system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles 815system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles |
| 900system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8190852374 # number of ReadExReq miss cycles 901system.cpu.l2cache.ReadExReq_miss_latency::total 8190852374 # number of ReadExReq miss cycles 902system.cpu.l2cache.demand_miss_latency::cpu.inst 1012336742 # number of demand (read+write) miss cycles 903system.cpu.l2cache.demand_miss_latency::cpu.data 25755182365 # number of demand (read+write) miss cycles 904system.cpu.l2cache.demand_miss_latency::total 26767519107 # number of demand (read+write) miss cycles 905system.cpu.l2cache.overall_miss_latency::cpu.inst 1012336742 # number of overall miss cycles 906system.cpu.l2cache.overall_miss_latency::cpu.data 25755182365 # number of overall miss cycles 907system.cpu.l2cache.overall_miss_latency::total 26767519107 # number of overall miss cycles 908system.cpu.l2cache.ReadReq_accesses::cpu.inst 929009 # number of ReadReq accesses(hits+misses) 909system.cpu.l2cache.ReadReq_accesses::cpu.data 1086729 # number of ReadReq accesses(hits+misses) 910system.cpu.l2cache.ReadReq_accesses::total 2015738 # number of ReadReq accesses(hits+misses) 911system.cpu.l2cache.Writeback_accesses::writebacks 835114 # number of Writeback accesses(hits+misses) 912system.cpu.l2cache.Writeback_accesses::total 835114 # number of Writeback accesses(hits+misses) | 816system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8011039626 # number of ReadExReq miss cycles 817system.cpu.l2cache.ReadExReq_miss_latency::total 8011039626 # number of ReadExReq miss cycles 818system.cpu.l2cache.demand_miss_latency::cpu.inst 967872241 # number of demand (read+write) miss cycles 819system.cpu.l2cache.demand_miss_latency::cpu.data 25725848117 # number of demand (read+write) miss cycles 820system.cpu.l2cache.demand_miss_latency::total 26693720358 # number of demand (read+write) miss cycles 821system.cpu.l2cache.overall_miss_latency::cpu.inst 967872241 # number of overall miss cycles 822system.cpu.l2cache.overall_miss_latency::cpu.data 25725848117 # number of overall miss cycles 823system.cpu.l2cache.overall_miss_latency::total 26693720358 # number of overall miss cycles 824system.cpu.l2cache.ReadReq_accesses::cpu.inst 929145 # number of ReadReq accesses(hits+misses) 825system.cpu.l2cache.ReadReq_accesses::cpu.data 1086742 # number of ReadReq accesses(hits+misses) 826system.cpu.l2cache.ReadReq_accesses::total 2015887 # number of ReadReq accesses(hits+misses) 827system.cpu.l2cache.Writeback_accesses::writebacks 835359 # number of Writeback accesses(hits+misses) 828system.cpu.l2cache.Writeback_accesses::total 835359 # number of Writeback accesses(hits+misses) |
| 913system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 914system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) | 829system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) 830system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) |
| 915system.cpu.l2cache.ReadExReq_accesses::cpu.data 304353 # number of ReadExReq accesses(hits+misses) 916system.cpu.l2cache.ReadExReq_accesses::total 304353 # number of ReadExReq accesses(hits+misses) 917system.cpu.l2cache.demand_accesses::cpu.inst 929009 # number of demand (read+write) accesses 918system.cpu.l2cache.demand_accesses::cpu.data 1391082 # number of demand (read+write) accesses 919system.cpu.l2cache.demand_accesses::total 2320091 # number of demand (read+write) accesses 920system.cpu.l2cache.overall_accesses::cpu.inst 929009 # number of overall (read+write) accesses 921system.cpu.l2cache.overall_accesses::cpu.data 1391082 # number of overall (read+write) accesses 922system.cpu.l2cache.overall_accesses::total 2320091 # number of overall (read+write) accesses 923system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014308 # miss rate for ReadReq accesses 924system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250214 # miss rate for ReadReq accesses 925system.cpu.l2cache.ReadReq_miss_rate::total 0.141490 # miss rate for ReadReq accesses | 831system.cpu.l2cache.ReadExReq_accesses::cpu.data 304545 # number of ReadExReq accesses(hits+misses) 832system.cpu.l2cache.ReadExReq_accesses::total 304545 # number of ReadExReq accesses(hits+misses) 833system.cpu.l2cache.demand_accesses::cpu.inst 929145 # number of demand (read+write) accesses 834system.cpu.l2cache.demand_accesses::cpu.data 1391287 # number of demand (read+write) accesses 835system.cpu.l2cache.demand_accesses::total 2320432 # number of demand (read+write) accesses 836system.cpu.l2cache.overall_accesses::cpu.inst 929145 # number of overall (read+write) accesses 837system.cpu.l2cache.overall_accesses::cpu.data 1391287 # number of overall (read+write) accesses 838system.cpu.l2cache.overall_accesses::total 2320432 # number of overall (read+write) accesses 839system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014307 # miss rate for ReadReq accesses 840system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250259 # miss rate for ReadReq accesses 841system.cpu.l2cache.ReadReq_miss_rate::total 0.141506 # miss rate for ReadReq accesses |
| 926system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 927system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses | 842system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses 843system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses |
| 928system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses 929system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses 930system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014308 # miss rate for demand accesses 931system.cpu.l2cache.demand_miss_rate::cpu.data 0.279367 # miss rate for demand accesses 932system.cpu.l2cache.demand_miss_rate::total 0.173232 # miss rate for demand accesses 933system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014308 # miss rate for overall accesses 934system.cpu.l2cache.overall_miss_rate::cpu.data 0.279367 # miss rate for overall accesses 935system.cpu.l2cache.overall_miss_rate::total 0.173232 # miss rate for overall accesses 936system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76161.355853 # average ReadReq miss latency 937system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64594.928529 # average ReadReq miss latency 938system.cpu.l2cache.ReadReq_avg_miss_latency::total 65133.978945 # average ReadReq miss latency | 844system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383733 # miss rate for ReadExReq accesses 845system.cpu.l2cache.ReadExReq_miss_rate::total 0.383733 # miss rate for ReadExReq accesses 846system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014307 # miss rate for demand accesses 847system.cpu.l2cache.demand_miss_rate::cpu.data 0.279476 # miss rate for demand accesses 848system.cpu.l2cache.demand_miss_rate::total 0.173297 # miss rate for demand accesses 849system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014307 # miss rate for overall accesses 850system.cpu.l2cache.overall_miss_rate::cpu.data 0.279476 # miss rate for overall accesses 851system.cpu.l2cache.overall_miss_rate::total 0.173297 # miss rate for overall accesses 852system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72810.670353 # average ReadReq miss latency 853system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65135.874908 # average ReadReq miss latency 854system.cpu.l2cache.ReadReq_avg_miss_latency::total 65493.517254 # average ReadReq miss latency |
| 939system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency 940system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency | 855system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency 856system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency |
| 941system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70182.441426 # average ReadExReq miss latency 942system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70182.441426 # average ReadExReq miss latency 943system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency 944system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency 945system.cpu.l2cache.demand_avg_miss_latency::total 66599.950504 # average overall miss latency 946system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency 947system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency 948system.cpu.l2cache.overall_avg_miss_latency::total 66599.950504 # average overall miss latency | 857system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68550.106329 # average ReadExReq miss latency 858system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68550.106329 # average ReadExReq miss latency 859system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72810.670353 # average overall miss latency 860system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66162.029563 # average overall miss latency 861system.cpu.l2cache.demand_avg_miss_latency::total 66381.813465 # average overall miss latency 862system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72810.670353 # average overall miss latency 863system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66162.029563 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::total 66381.813465 # average overall miss latency |
| 949system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 950system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 951system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 952system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 953system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 954system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 955system.cpu.l2cache.fast_writes 0 # number of fast writes performed 956system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 865system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 866system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 867system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 868system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 869system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 870system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 871system.cpu.l2cache.fast_writes 0 # number of fast writes performed 872system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 957system.cpu.l2cache.writebacks::writebacks 73954 # number of writebacks 958system.cpu.l2cache.writebacks::total 73954 # number of writebacks 959system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses 960system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses 961system.cpu.l2cache.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses | 873system.cpu.l2cache.writebacks::writebacks 74205 # number of writebacks 874system.cpu.l2cache.writebacks::total 74205 # number of writebacks 875system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13293 # number of ReadReq MSHR misses 876system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271967 # number of ReadReq MSHR misses 877system.cpu.l2cache.ReadReq_mshr_misses::total 285260 # number of ReadReq MSHR misses |
| 962system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 963system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses | 878system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 879system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses |
| 964system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116708 # number of ReadExReq MSHR misses 965system.cpu.l2cache.ReadExReq_mshr_misses::total 116708 # number of ReadExReq MSHR misses 966system.cpu.l2cache.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses 967system.cpu.l2cache.demand_mshr_misses::cpu.data 388623 # number of demand (read+write) MSHR misses 968system.cpu.l2cache.demand_mshr_misses::total 401915 # number of demand (read+write) MSHR misses 969system.cpu.l2cache.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses 970system.cpu.l2cache.overall_mshr_misses::cpu.data 388623 # number of overall MSHR misses 971system.cpu.l2cache.overall_mshr_misses::total 401915 # number of overall MSHR misses 972system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 845706258 # number of ReadReq MSHR miss cycles 973system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14164824509 # number of ReadReq MSHR miss cycles 974system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15010530767 # number of ReadReq MSHR miss cycles | 880system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116864 # number of ReadExReq MSHR misses 881system.cpu.l2cache.ReadExReq_mshr_misses::total 116864 # number of ReadExReq MSHR misses 882system.cpu.l2cache.demand_mshr_misses::cpu.inst 13293 # number of demand (read+write) MSHR misses 883system.cpu.l2cache.demand_mshr_misses::cpu.data 388831 # number of demand (read+write) MSHR misses 884system.cpu.l2cache.demand_mshr_misses::total 402124 # number of demand (read+write) MSHR misses 885system.cpu.l2cache.overall_mshr_misses::cpu.inst 13293 # number of overall MSHR misses 886system.cpu.l2cache.overall_mshr_misses::cpu.data 388831 # number of overall MSHR misses 887system.cpu.l2cache.overall_mshr_misses::total 402124 # number of overall MSHR misses 888system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 801329759 # number of ReadReq MSHR miss cycles 889system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14314442009 # number of ReadReq MSHR miss cycles 890system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15115771768 # number of ReadReq MSHR miss cycles |
| 975system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles 976system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles | 891system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles 892system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles |
| 977system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6731491626 # number of ReadExReq MSHR miss cycles 978system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6731491626 # number of ReadExReq MSHR miss cycles 979system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 845706258 # number of demand (read+write) MSHR miss cycles 980system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20896316135 # number of demand (read+write) MSHR miss cycles 981system.cpu.l2cache.demand_mshr_miss_latency::total 21742022393 # number of demand (read+write) MSHR miss cycles 982system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 845706258 # number of overall MSHR miss cycles 983system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20896316135 # number of overall MSHR miss cycles 984system.cpu.l2cache.overall_mshr_miss_latency::total 21742022393 # number of overall MSHR miss cycles 985system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles 986system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles 987system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895642000 # number of WriteReq MSHR uncacheable cycles 988system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895642000 # number of WriteReq MSHR uncacheable cycles | 893system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6549827374 # number of ReadExReq MSHR miss cycles 894system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6549827374 # number of ReadExReq MSHR miss cycles 895system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 801329759 # number of demand (read+write) MSHR miss cycles 896system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20864269383 # number of demand (read+write) MSHR miss cycles 897system.cpu.l2cache.demand_mshr_miss_latency::total 21665599142 # number of demand (read+write) MSHR miss cycles 898system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 801329759 # number of overall MSHR miss cycles 899system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20864269383 # number of overall MSHR miss cycles 900system.cpu.l2cache.overall_mshr_miss_latency::total 21665599142 # number of overall MSHR miss cycles 901system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles 902system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles 903system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895641500 # number of WriteReq MSHR uncacheable cycles 904system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895641500 # number of WriteReq MSHR uncacheable cycles |
| 989system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles 990system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles | 905system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles 906system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles |
| 991system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for ReadReq accesses 992system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250214 # mshr miss rate for ReadReq accesses 993system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141490 # mshr miss rate for ReadReq accesses | 907system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for ReadReq accesses 908system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses 909system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141506 # mshr miss rate for ReadReq accesses |
| 994system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 995system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses | 910system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses 911system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses |
| 996system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses 997system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses 998system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for demand accesses 999system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for demand accesses 1000system.cpu.l2cache.demand_mshr_miss_rate::total 0.173232 # mshr miss rate for demand accesses 1001system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for overall accesses 1002system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for overall accesses 1003system.cpu.l2cache.overall_mshr_miss_rate::total 0.173232 # mshr miss rate for overall accesses 1004system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63625.207493 # average ReadReq mshr miss latency 1005system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52092.839707 # average ReadReq mshr miss latency 1006system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52630.302787 # average ReadReq mshr miss latency | 912system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383733 # mshr miss rate for ReadExReq accesses 913system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383733 # mshr miss rate for ReadExReq accesses 914system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for demand accesses 915system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for demand accesses 916system.cpu.l2cache.demand_mshr_miss_rate::total 0.173297 # mshr miss rate for demand accesses 917system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for overall accesses 918system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for overall accesses 919system.cpu.l2cache.overall_mshr_miss_rate::total 0.173297 # mshr miss rate for overall accesses 920system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60282.085233 # average ReadReq mshr miss latency 921system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52633.010656 # average ReadReq mshr miss latency 922system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52989.454421 # average ReadReq mshr miss latency |
| 1007system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency 1008system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency | 923system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency 924system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency |
| 1009system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57678.065137 # average ReadExReq mshr miss latency 1010system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57678.065137 # average ReadExReq mshr miss latency 1011system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency 1012system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency 1013system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency 1014system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency 1015system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency 1016system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency | 925system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56046.578707 # average ReadExReq mshr miss latency 926system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56046.578707 # average ReadExReq mshr miss latency 927system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency 928system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency 929system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency 930system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency 931system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency 932system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency |
| 1017system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1018system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1019system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1020system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1021system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1022system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1023system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 933system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 934system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 935system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 936system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 937system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 938system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 939system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1024system.cpu.dcache.tags.replacements 1390568 # number of replacements 1025system.cpu.dcache.tags.tagsinuse 511.978915 # Cycle average of tags in use 1026system.cpu.dcache.tags.total_refs 14049173 # Total number of references to valid blocks. 1027system.cpu.dcache.tags.sampled_refs 1391080 # Sample count of references to valid blocks. 1028system.cpu.dcache.tags.avg_refs 10.099472 # Average number of references to valid blocks. 1029system.cpu.dcache.tags.warmup_cycle 107298250 # Cycle when the warmup percentage was hit. 1030system.cpu.dcache.tags.occ_blocks::cpu.data 511.978915 # Average occupied blocks per requestor | 940system.cpu.dcache.tags.replacements 1390774 # number of replacements 941system.cpu.dcache.tags.tagsinuse 511.978892 # Cycle average of tags in use 942system.cpu.dcache.tags.total_refs 14051964 # Total number of references to valid blocks. 943system.cpu.dcache.tags.sampled_refs 1391286 # Sample count of references to valid blocks. 944system.cpu.dcache.tags.avg_refs 10.099982 # Average number of references to valid blocks. 945system.cpu.dcache.tags.warmup_cycle 107796250 # Cycle when the warmup percentage was hit. 946system.cpu.dcache.tags.occ_blocks::cpu.data 511.978892 # Average occupied blocks per requestor |
| 1031system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy 1032system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy 1033system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1034system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 1035system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 1036system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 1037system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 947system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy 948system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy 949system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 950system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 951system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 952system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 953system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1038system.cpu.dcache.tags.tag_accesses 63152102 # Number of tag accesses 1039system.cpu.dcache.tags.data_accesses 63152102 # Number of data accesses 1040system.cpu.dcache.ReadReq_hits::cpu.data 7814622 # number of ReadReq hits 1041system.cpu.dcache.ReadReq_hits::total 7814622 # number of ReadReq hits 1042system.cpu.dcache.WriteReq_hits::cpu.data 5852326 # number of WriteReq hits 1043system.cpu.dcache.WriteReq_hits::total 5852326 # number of WriteReq hits 1044system.cpu.dcache.LoadLockedReq_hits::cpu.data 182986 # number of LoadLockedReq hits 1045system.cpu.dcache.LoadLockedReq_hits::total 182986 # number of LoadLockedReq hits 1046system.cpu.dcache.StoreCondReq_hits::cpu.data 199222 # number of StoreCondReq hits 1047system.cpu.dcache.StoreCondReq_hits::total 199222 # number of StoreCondReq hits 1048system.cpu.dcache.demand_hits::cpu.data 13666948 # number of demand (read+write) hits 1049system.cpu.dcache.demand_hits::total 13666948 # number of demand (read+write) hits 1050system.cpu.dcache.overall_hits::cpu.data 13666948 # number of overall hits 1051system.cpu.dcache.overall_hits::total 13666948 # number of overall hits 1052system.cpu.dcache.ReadReq_misses::cpu.data 1069470 # number of ReadReq misses 1053system.cpu.dcache.ReadReq_misses::total 1069470 # number of ReadReq misses 1054system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses 1055system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses 1056system.cpu.dcache.LoadLockedReq_misses::cpu.data 17259 # number of LoadLockedReq misses 1057system.cpu.dcache.LoadLockedReq_misses::total 17259 # number of LoadLockedReq misses 1058system.cpu.dcache.demand_misses::cpu.data 1373840 # number of demand (read+write) misses 1059system.cpu.dcache.demand_misses::total 1373840 # number of demand (read+write) misses 1060system.cpu.dcache.overall_misses::cpu.data 1373840 # number of overall misses 1061system.cpu.dcache.overall_misses::total 1373840 # number of overall misses 1062system.cpu.dcache.ReadReq_miss_latency::cpu.data 28875755759 # number of ReadReq miss cycles 1063system.cpu.dcache.ReadReq_miss_latency::total 28875755759 # number of ReadReq miss cycles 1064system.cpu.dcache.WriteReq_miss_latency::cpu.data 11035273137 # number of WriteReq miss cycles 1065system.cpu.dcache.WriteReq_miss_latency::total 11035273137 # number of WriteReq miss cycles 1066system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228925250 # number of LoadLockedReq miss cycles 1067system.cpu.dcache.LoadLockedReq_miss_latency::total 228925250 # number of LoadLockedReq miss cycles 1068system.cpu.dcache.demand_miss_latency::cpu.data 39911028896 # number of demand (read+write) miss cycles 1069system.cpu.dcache.demand_miss_latency::total 39911028896 # number of demand (read+write) miss cycles 1070system.cpu.dcache.overall_miss_latency::cpu.data 39911028896 # number of overall miss cycles 1071system.cpu.dcache.overall_miss_latency::total 39911028896 # number of overall miss cycles 1072system.cpu.dcache.ReadReq_accesses::cpu.data 8884092 # number of ReadReq accesses(hits+misses) 1073system.cpu.dcache.ReadReq_accesses::total 8884092 # number of ReadReq accesses(hits+misses) 1074system.cpu.dcache.WriteReq_accesses::cpu.data 6156696 # number of WriteReq accesses(hits+misses) 1075system.cpu.dcache.WriteReq_accesses::total 6156696 # number of WriteReq accesses(hits+misses) 1076system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses) 1077system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses) 1078system.cpu.dcache.StoreCondReq_accesses::cpu.data 199222 # number of StoreCondReq accesses(hits+misses) 1079system.cpu.dcache.StoreCondReq_accesses::total 199222 # number of StoreCondReq accesses(hits+misses) 1080system.cpu.dcache.demand_accesses::cpu.data 15040788 # number of demand (read+write) accesses 1081system.cpu.dcache.demand_accesses::total 15040788 # number of demand (read+write) accesses 1082system.cpu.dcache.overall_accesses::cpu.data 15040788 # number of overall (read+write) accesses 1083system.cpu.dcache.overall_accesses::total 15040788 # number of overall (read+write) accesses 1084system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120380 # miss rate for ReadReq accesses 1085system.cpu.dcache.ReadReq_miss_rate::total 0.120380 # miss rate for ReadReq accesses 1086system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049437 # miss rate for WriteReq accesses 1087system.cpu.dcache.WriteReq_miss_rate::total 0.049437 # miss rate for WriteReq accesses 1088system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086189 # miss rate for LoadLockedReq accesses 1089system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086189 # miss rate for LoadLockedReq accesses 1090system.cpu.dcache.demand_miss_rate::cpu.data 0.091341 # miss rate for demand accesses 1091system.cpu.dcache.demand_miss_rate::total 0.091341 # miss rate for demand accesses 1092system.cpu.dcache.overall_miss_rate::cpu.data 0.091341 # miss rate for overall accesses 1093system.cpu.dcache.overall_miss_rate::total 0.091341 # miss rate for overall accesses 1094system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27000.061487 # average ReadReq miss latency 1095system.cpu.dcache.ReadReq_avg_miss_latency::total 27000.061487 # average ReadReq miss latency 1096system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36256.113076 # average WriteReq miss latency 1097system.cpu.dcache.WriteReq_avg_miss_latency::total 36256.113076 # average WriteReq miss latency 1098system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13264.108581 # average LoadLockedReq miss latency 1099system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13264.108581 # average LoadLockedReq miss latency 1100system.cpu.dcache.demand_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency 1101system.cpu.dcache.demand_avg_miss_latency::total 29050.711070 # average overall miss latency 1102system.cpu.dcache.overall_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency 1103system.cpu.dcache.overall_avg_miss_latency::total 29050.711070 # average overall miss latency | 954system.cpu.dcache.tags.tag_accesses 63164291 # Number of tag accesses 955system.cpu.dcache.tags.data_accesses 63164291 # Number of data accesses 956system.cpu.dcache.ReadReq_hits::cpu.data 7816324 # number of ReadReq hits 957system.cpu.dcache.ReadReq_hits::total 7816324 # number of ReadReq hits 958system.cpu.dcache.WriteReq_hits::cpu.data 5853358 # number of WriteReq hits 959system.cpu.dcache.WriteReq_hits::total 5853358 # number of WriteReq hits 960system.cpu.dcache.LoadLockedReq_hits::cpu.data 183027 # number of LoadLockedReq hits 961system.cpu.dcache.LoadLockedReq_hits::total 183027 # number of LoadLockedReq hits 962system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits 963system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits 964system.cpu.dcache.demand_hits::cpu.data 13669682 # number of demand (read+write) hits 965system.cpu.dcache.demand_hits::total 13669682 # number of demand (read+write) hits 966system.cpu.dcache.overall_hits::cpu.data 13669682 # number of overall hits 967system.cpu.dcache.overall_hits::total 13669682 # number of overall hits 968system.cpu.dcache.ReadReq_misses::cpu.data 1069509 # number of ReadReq misses 969system.cpu.dcache.ReadReq_misses::total 1069509 # number of ReadReq misses 970system.cpu.dcache.WriteReq_misses::cpu.data 304562 # number of WriteReq misses 971system.cpu.dcache.WriteReq_misses::total 304562 # number of WriteReq misses 972system.cpu.dcache.LoadLockedReq_misses::cpu.data 17233 # number of LoadLockedReq misses 973system.cpu.dcache.LoadLockedReq_misses::total 17233 # number of LoadLockedReq misses 974system.cpu.dcache.demand_misses::cpu.data 1374071 # number of demand (read+write) misses 975system.cpu.dcache.demand_misses::total 1374071 # number of demand (read+write) misses 976system.cpu.dcache.overall_misses::cpu.data 1374071 # number of overall misses 977system.cpu.dcache.overall_misses::total 1374071 # number of overall misses 978system.cpu.dcache.ReadReq_miss_latency::cpu.data 29019471009 # number of ReadReq miss cycles 979system.cpu.dcache.ReadReq_miss_latency::total 29019471009 # number of ReadReq miss cycles 980system.cpu.dcache.WriteReq_miss_latency::cpu.data 10854033885 # number of WriteReq miss cycles 981system.cpu.dcache.WriteReq_miss_latency::total 10854033885 # number of WriteReq miss cycles 982system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228736500 # number of LoadLockedReq miss cycles 983system.cpu.dcache.LoadLockedReq_miss_latency::total 228736500 # number of LoadLockedReq miss cycles 984system.cpu.dcache.demand_miss_latency::cpu.data 39873504894 # number of demand (read+write) miss cycles 985system.cpu.dcache.demand_miss_latency::total 39873504894 # number of demand (read+write) miss cycles 986system.cpu.dcache.overall_miss_latency::cpu.data 39873504894 # number of overall miss cycles 987system.cpu.dcache.overall_miss_latency::total 39873504894 # number of overall miss cycles 988system.cpu.dcache.ReadReq_accesses::cpu.data 8885833 # number of ReadReq accesses(hits+misses) 989system.cpu.dcache.ReadReq_accesses::total 8885833 # number of ReadReq accesses(hits+misses) 990system.cpu.dcache.WriteReq_accesses::cpu.data 6157920 # number of WriteReq accesses(hits+misses) 991system.cpu.dcache.WriteReq_accesses::total 6157920 # number of WriteReq accesses(hits+misses) 992system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200260 # number of LoadLockedReq accesses(hits+misses) 993system.cpu.dcache.LoadLockedReq_accesses::total 200260 # number of LoadLockedReq accesses(hits+misses) 994system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses) 995system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses) 996system.cpu.dcache.demand_accesses::cpu.data 15043753 # number of demand (read+write) accesses 997system.cpu.dcache.demand_accesses::total 15043753 # number of demand (read+write) accesses 998system.cpu.dcache.overall_accesses::cpu.data 15043753 # number of overall (read+write) accesses 999system.cpu.dcache.overall_accesses::total 15043753 # number of overall (read+write) accesses 1000system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120361 # miss rate for ReadReq accesses 1001system.cpu.dcache.ReadReq_miss_rate::total 0.120361 # miss rate for ReadReq accesses 1002system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses 1003system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses 1004system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086053 # miss rate for LoadLockedReq accesses 1005system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086053 # miss rate for LoadLockedReq accesses 1006system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses 1007system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses 1008system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses 1009system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses 1010system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27133.451901 # average ReadReq miss latency 1011system.cpu.dcache.ReadReq_avg_miss_latency::total 27133.451901 # average ReadReq miss latency 1012system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35638.175101 # average WriteReq miss latency 1013system.cpu.dcache.WriteReq_avg_miss_latency::total 35638.175101 # average WriteReq miss latency 1014system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.167760 # average LoadLockedReq miss latency 1015system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.167760 # average LoadLockedReq miss latency 1016system.cpu.dcache.demand_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency 1017system.cpu.dcache.demand_avg_miss_latency::total 29018.518617 # average overall miss latency 1018system.cpu.dcache.overall_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency 1019system.cpu.dcache.overall_avg_miss_latency::total 29018.518617 # average overall miss latency |
| 1104system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1105system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1106system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1107system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1108system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1109system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1110system.cpu.dcache.fast_writes 0 # number of fast writes performed 1111system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1020system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1021system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1022system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1023system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1024system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1025system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1026system.cpu.dcache.fast_writes 0 # number of fast writes performed 1027system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1112system.cpu.dcache.writebacks::writebacks 835114 # number of writebacks 1113system.cpu.dcache.writebacks::total 835114 # number of writebacks 1114system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069470 # number of ReadReq MSHR misses 1115system.cpu.dcache.ReadReq_mshr_misses::total 1069470 # number of ReadReq MSHR misses 1116system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304370 # number of WriteReq MSHR misses 1117system.cpu.dcache.WriteReq_mshr_misses::total 304370 # number of WriteReq MSHR misses 1118system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17259 # number of LoadLockedReq MSHR misses 1119system.cpu.dcache.LoadLockedReq_mshr_misses::total 17259 # number of LoadLockedReq MSHR misses 1120system.cpu.dcache.demand_mshr_misses::cpu.data 1373840 # number of demand (read+write) MSHR misses 1121system.cpu.dcache.demand_mshr_misses::total 1373840 # number of demand (read+write) MSHR misses 1122system.cpu.dcache.overall_mshr_misses::cpu.data 1373840 # number of overall MSHR misses 1123system.cpu.dcache.overall_mshr_misses::total 1373840 # number of overall MSHR misses 1124system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26604805241 # number of ReadReq MSHR miss cycles 1125system.cpu.dcache.ReadReq_mshr_miss_latency::total 26604805241 # number of ReadReq MSHR miss cycles 1126system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10372104863 # number of WriteReq MSHR miss cycles 1127system.cpu.dcache.WriteReq_mshr_miss_latency::total 10372104863 # number of WriteReq MSHR miss cycles 1128system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194393750 # number of LoadLockedReq MSHR miss cycles 1129system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194393750 # number of LoadLockedReq MSHR miss cycles 1130system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36976910104 # number of demand (read+write) MSHR miss cycles 1131system.cpu.dcache.demand_mshr_miss_latency::total 36976910104 # number of demand (read+write) MSHR miss cycles 1132system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36976910104 # number of overall MSHR miss cycles 1133system.cpu.dcache.overall_mshr_miss_latency::total 36976910104 # number of overall MSHR miss cycles 1134system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles 1135system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles 1136system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011442000 # number of WriteReq MSHR uncacheable cycles 1137system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011442000 # number of WriteReq MSHR uncacheable cycles | 1028system.cpu.dcache.writebacks::writebacks 835359 # number of writebacks 1029system.cpu.dcache.writebacks::total 835359 # number of writebacks 1030system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069509 # number of ReadReq MSHR misses 1031system.cpu.dcache.ReadReq_mshr_misses::total 1069509 # number of ReadReq MSHR misses 1032system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304562 # number of WriteReq MSHR misses 1033system.cpu.dcache.WriteReq_mshr_misses::total 304562 # number of WriteReq MSHR misses 1034system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17233 # number of LoadLockedReq MSHR misses 1035system.cpu.dcache.LoadLockedReq_mshr_misses::total 17233 # number of LoadLockedReq MSHR misses 1036system.cpu.dcache.demand_mshr_misses::cpu.data 1374071 # number of demand (read+write) MSHR misses 1037system.cpu.dcache.demand_mshr_misses::total 1374071 # number of demand (read+write) MSHR misses 1038system.cpu.dcache.overall_mshr_misses::cpu.data 1374071 # number of overall MSHR misses 1039system.cpu.dcache.overall_mshr_misses::total 1374071 # number of overall MSHR misses 1040system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26755042991 # number of ReadReq MSHR miss cycles 1041system.cpu.dcache.ReadReq_mshr_miss_latency::total 26755042991 # number of ReadReq MSHR miss cycles 1042system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10192844115 # number of WriteReq MSHR miss cycles 1043system.cpu.dcache.WriteReq_mshr_miss_latency::total 10192844115 # number of WriteReq MSHR miss cycles 1044system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194257500 # number of LoadLockedReq MSHR miss cycles 1045system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194257500 # number of LoadLockedReq MSHR miss cycles 1046system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36947887106 # number of demand (read+write) MSHR miss cycles 1047system.cpu.dcache.demand_mshr_miss_latency::total 36947887106 # number of demand (read+write) MSHR miss cycles 1048system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36947887106 # number of overall MSHR miss cycles 1049system.cpu.dcache.overall_mshr_miss_latency::total 36947887106 # number of overall MSHR miss cycles 1050system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles 1051system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles 1052system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011441500 # number of WriteReq MSHR uncacheable cycles 1053system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011441500 # number of WriteReq MSHR uncacheable cycles |
| 1138system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles 1139system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles | 1054system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles 1055system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles |
| 1140system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120380 # mshr miss rate for ReadReq accesses 1141system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120380 # mshr miss rate for ReadReq accesses 1142system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049437 # mshr miss rate for WriteReq accesses 1143system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049437 # mshr miss rate for WriteReq accesses 1144system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086189 # mshr miss rate for LoadLockedReq accesses 1145system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086189 # mshr miss rate for LoadLockedReq accesses 1146system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for demand accesses 1147system.cpu.dcache.demand_mshr_miss_rate::total 0.091341 # mshr miss rate for demand accesses 1148system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for overall accesses 1149system.cpu.dcache.overall_mshr_miss_rate::total 0.091341 # mshr miss rate for overall accesses 1150system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031 # average ReadReq mshr miss latency 1151system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031 # average ReadReq mshr miss latency 1152system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347 # average WriteReq mshr miss latency 1153system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347 # average WriteReq mshr miss latency 1154system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380 # average LoadLockedReq mshr miss latency 1155system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380 # average LoadLockedReq mshr miss latency 1156system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency 1157system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency 1158system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency 1159system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency | 1056system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120361 # mshr miss rate for ReadReq accesses 1057system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120361 # mshr miss rate for ReadReq accesses 1058system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses 1059system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses 1060system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086053 # mshr miss rate for LoadLockedReq accesses 1061system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086053 # mshr miss rate for LoadLockedReq accesses 1062system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses 1063system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses 1064system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses 1065system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses 1066system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25016.192469 # average ReadReq mshr miss latency 1067system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25016.192469 # average ReadReq mshr miss latency 1068system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33467.222158 # average WriteReq mshr miss latency 1069system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33467.222158 # average WriteReq mshr miss latency 1070system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.413393 # average LoadLockedReq mshr miss latency 1071system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.413393 # average LoadLockedReq mshr miss latency 1072system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency 1073system.cpu.dcache.demand_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency 1074system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency 1075system.cpu.dcache.overall_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency |
| 1160system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1161system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1162system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1163system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1164system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1165system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1166system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1076system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1077system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1078system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1079system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1080system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1081system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1082system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1167system.cpu.toL2Bus.throughput 105179195 # Throughput (bytes/s) 1168system.cpu.toL2Bus.trans_dist::ReadReq 2022861 # Transaction distribution 1169system.cpu.toL2Bus.trans_dist::ReadResp 2022844 # Transaction distribution | 1083system.cpu.toL2Bus.throughput 105199341 # Throughput (bytes/s) 1084system.cpu.toL2Bus.trans_dist::ReadReq 2023010 # Transaction distribution 1085system.cpu.toL2Bus.trans_dist::ReadResp 2022993 # Transaction distribution |
| 1170system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution 1171system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution | 1086system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution 1087system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution |
| 1172system.cpu.toL2Bus.trans_dist::Writeback 835114 # Transaction distribution | 1088system.cpu.toL2Bus.trans_dist::Writeback 835359 # Transaction distribution |
| 1173system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution | 1089system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution 1090system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution |
| 1175system.cpu.toL2Bus.trans_dist::ReadExReq 345905 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::ReadExResp 304355 # Transaction distribution 1177system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858038 # Packet count per connected master and slave (bytes) 1178system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3650630 # Packet count per connected master and slave (bytes) 1179system.cpu.toL2Bus.pkt_count::total 5508668 # Packet count per connected master and slave (bytes) 1180system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59456576 # Cumulative packet size per connected master and slave (bytes) 1181system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142531220 # Cumulative packet size per connected master and slave (bytes) 1182system.cpu.toL2Bus.tot_pkt_size::total 201987796 # Cumulative packet size per connected master and slave (bytes) 1183system.cpu.toL2Bus.data_through_bus 201977684 # Total data (bytes) 1184system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) 1185system.cpu.toL2Bus.reqLayer0.occupancy 2425850000 # Layer occupancy (ticks) | 1091system.cpu.toL2Bus.trans_dist::ReadExReq 346097 # Transaction distribution 1092system.cpu.toL2Bus.trans_dist::ReadExResp 304546 # Transaction distribution 1093system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858310 # Packet count per connected master and slave (bytes) 1094system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651284 # Packet count per connected master and slave (bytes) 1095system.cpu.toL2Bus.pkt_count::total 5509594 # Packet count per connected master and slave (bytes) 1096system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59465280 # Cumulative packet size per connected master and slave (bytes) 1097system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142559956 # Cumulative packet size per connected master and slave (bytes) 1098system.cpu.toL2Bus.tot_pkt_size::total 202025236 # Cumulative packet size per connected master and slave (bytes) 1099system.cpu.toL2Bus.data_through_bus 202015188 # Total data (bytes) 1100system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) 1101system.cpu.toL2Bus.reqLayer0.occupancy 2426388000 # Layer occupancy (ticks) |
| 1186system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1102system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1187system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) | 1103system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) |
| 1188system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1104system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1189system.cpu.toL2Bus.respLayer0.occupancy 1396163258 # Layer occupancy (ticks) | 1105system.cpu.toL2Bus.respLayer0.occupancy 1396297259 # Layer occupancy (ticks) |
| 1190system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1106system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1191system.cpu.toL2Bus.respLayer1.occupancy 2191612646 # Layer occupancy (ticks) | 1107system.cpu.toL2Bus.respLayer1.occupancy 2187438394 # Layer occupancy (ticks) |
| 1192system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1193 1194---------- End Simulation Statistics ---------- | 1108system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1109 1110---------- End Simulation Statistics ---------- |