1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.941276 # Number of seconds simulated 4sim_ticks 1941275996000 # Number of ticks simulated 5final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 1512910 # Simulator instruction rate (inst/s) 8host_op_rate 1512909 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52275426747 # Simulator tick rate (ticks/s) 10host_mem_usage 372644 # Number of bytes of host memory used 11host_seconds 37.14 # Real time elapsed on the host |
12sim_insts 56182685 # Number of instructions simulated 13sim_ops 56182685 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
16system.physmem.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
17system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory 19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 20system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 844800 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 844800 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7410752 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7410752 # Number of bytes written to this memory --- 269 unchanged lines hidden (view full) --- 294system.physmem_1.preBackEnergy 1101055791000 # Energy for precharge background per rank (pJ) 295system.physmem_1.totalEnergy 1302809128905 # Total energy per rank (pJ) 296system.physmem_1.averagePower 671.109728 # Core power per rank (mW) 297system.physmem_1.memoryStateTime::IDLE 1831423384000 # Time in different power states 298system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states 299system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 300system.physmem_1.memoryStateTime::ACT 45029052250 # Time in different power states 301system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
302system.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 303system.bridge.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
304system.cpu_clk_domain.clock 500 # Clock period in ticks 305system.cpu.dtb.fetch_hits 0 # ITB hits 306system.cpu.dtb.fetch_misses 0 # ITB misses 307system.cpu.dtb.fetch_acv 0 # ITB acv 308system.cpu.dtb.fetch_accesses 0 # ITB accesses 309system.cpu.dtb.read_hits 9064642 # DTB read hits 310system.cpu.dtb.read_misses 10324 # DTB read misses 311system.cpu.dtb.read_acv 210 # DTB read access violations --- 17 unchanged lines hidden (view full) --- 329system.cpu.itb.write_hits 0 # DTB write hits 330system.cpu.itb.write_misses 0 # DTB write misses 331system.cpu.itb.write_acv 0 # DTB write access violations 332system.cpu.itb.write_accesses 0 # DTB write accesses 333system.cpu.itb.data_hits 0 # DTB hits 334system.cpu.itb.data_misses 0 # DTB misses 335system.cpu.itb.data_acv 0 # DTB access violations 336system.cpu.itb.data_accesses 0 # DTB accesses |
337system.cpu.numPwrStateTransitions 12750 # Number of power state transitions 338system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state 339system.cpu.pwrStateClkGateDist::mean 281084846.274667 # Distribution of time spent in the clock gated state 340system.cpu.pwrStateClkGateDist::stdev 439246514.470007 # Distribution of time spent in the clock gated state 341system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state 342system.cpu.pwrStateClkGateDist::1000-5e+10 6374 99.98% 100.00% # Distribution of time spent in the clock gated state 343system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 344system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 345system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state 346system.cpu.pwrStateResidencyTicks::ON 149360100999 # Cumulative time (in ticks) in various power states 347system.cpu.pwrStateResidencyTicks::CLK_GATED 1791915895001 # Cumulative time (in ticks) in various power states |
348system.cpu.numCycles 3882551992 # number of cpu cycles simulated 349system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 350system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 351system.cpu.kern.inst.arm 0 # number of arm instructions executed 352system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed 353system.cpu.kern.inst.hwrei 212050 # number of hwrei instructions executed 354system.cpu.kern.ipl_count::0 74912 40.88% 40.88% # number of times we switched to this ipl 355system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl --- 127 unchanged lines hidden (view full) --- 483system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction 484system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction 485system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction 486system.cpu.op_class::MemRead 9328618 16.60% 86.95% # Class of executed instruction 487system.cpu.op_class::MemWrite 6378045 11.35% 98.30% # Class of executed instruction 488system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction 489system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 490system.cpu.op_class::total 56194518 # Class of executed instruction |
491system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
492system.cpu.dcache.tags.replacements 1390402 # number of replacements 493system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use 494system.cpu.dcache.tags.total_refs 14048961 # Total number of references to valid blocks. 495system.cpu.dcache.tags.sampled_refs 1390914 # Sample count of references to valid blocks. 496system.cpu.dcache.tags.avg_refs 10.100525 # Average number of references to valid blocks. 497system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. 498system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor 499system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy 500system.cpu.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy 501system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 502system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 503system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 504system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 505system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 506system.cpu.dcache.tags.tag_accesses 63150419 # Number of tag accesses 507system.cpu.dcache.tags.data_accesses 63150419 # Number of data accesses |
508system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
509system.cpu.dcache.ReadReq_hits::cpu.data 7814383 # number of ReadReq hits 510system.cpu.dcache.ReadReq_hits::total 7814383 # number of ReadReq hits 511system.cpu.dcache.WriteReq_hits::cpu.data 5852265 # number of WriteReq hits 512system.cpu.dcache.WriteReq_hits::total 5852265 # number of WriteReq hits 513system.cpu.dcache.LoadLockedReq_hits::cpu.data 183036 # number of LoadLockedReq hits 514system.cpu.dcache.LoadLockedReq_hits::total 183036 # number of LoadLockedReq hits 515system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits 516system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits --- 110 unchanged lines hidden (view full) --- 627system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency 628system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency 629system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency 630system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency 631system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency 632system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency 633system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401 # average overall mshr uncacheable latency 634system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401 # average overall mshr uncacheable latency |
635system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
636system.cpu.icache.tags.replacements 928931 # number of replacements 637system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use 638system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks. 639system.cpu.icache.tags.sampled_refs 929442 # Sample count of references to valid blocks. 640system.cpu.icache.tags.avg_refs 59.460318 # Average number of references to valid blocks. 641system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. 642system.cpu.icache.tags.occ_blocks::cpu.inst 506.355616 # Average occupied blocks per requestor 643system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy 644system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy 645system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 646system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 647system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 648system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id 649system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 650system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 651system.cpu.icache.tags.tag_accesses 57124121 # Number of tag accesses 652system.cpu.icache.tags.data_accesses 57124121 # Number of data accesses |
653system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
654system.cpu.icache.ReadReq_hits::cpu.inst 55264917 # number of ReadReq hits 655system.cpu.icache.ReadReq_hits::total 55264917 # number of ReadReq hits 656system.cpu.icache.demand_hits::cpu.inst 55264917 # number of demand (read+write) hits 657system.cpu.icache.demand_hits::total 55264917 # number of demand (read+write) hits 658system.cpu.icache.overall_hits::cpu.inst 55264917 # number of overall hits 659system.cpu.icache.overall_hits::total 55264917 # number of overall hits 660system.cpu.icache.ReadReq_misses::cpu.inst 929602 # number of ReadReq misses 661system.cpu.icache.ReadReq_misses::total 929602 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 714system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses 715system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses 716system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459 # average ReadReq mshr miss latency 717system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459 # average ReadReq mshr miss latency 718system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency 719system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency 720system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency 721system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency |
722system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
723system.cpu.l2cache.tags.replacements 336393 # number of replacements 724system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use 725system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks. 726system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. 727system.cpu.l2cache.tags.avg_refs 9.787932 # Average number of references to valid blocks. 728system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. 729system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820493 # Average occupied blocks per requestor 730system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.121272 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 737system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id 738system.cpu.l2cache.tags.age_task_id_blocks_1024::1 722 # Occupied blocks per task id 739system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id 740system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id 741system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id 742system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 743system.cpu.l2cache.tags.tag_accesses 37812972 # Number of tag accesses 744system.cpu.l2cache.tags.data_accesses 37812972 # Number of data accesses |
745system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
746system.cpu.l2cache.WritebackDirty_hits::writebacks 834944 # number of WritebackDirty hits 747system.cpu.l2cache.WritebackDirty_hits::total 834944 # number of WritebackDirty hits 748system.cpu.l2cache.WritebackClean_hits::writebacks 928709 # number of WritebackClean hits 749system.cpu.l2cache.WritebackClean_hits::total 928709 # number of WritebackClean hits 750system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 751system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 752system.cpu.l2cache.ReadExReq_hits::cpu.data 187490 # number of ReadExReq hits 753system.cpu.l2cache.ReadExReq_hits::total 187490 # number of ReadExReq hits --- 160 unchanged lines hidden (view full) --- 914system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927 # average overall mshr uncacheable latency 915system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927 # average overall mshr uncacheable latency 916system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter. 917system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data. 918system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 919system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. 920system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 921system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
922system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
923system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution 924system.cpu.toL2Bus.trans_dist::ReadResp 2023294 # Transaction distribution 925system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution 926system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution 927system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution 928system.cpu.toL2Bus.trans_dist::WritebackClean 928931 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::CleanEvict 817743 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution --- 36 unchanged lines hidden (view full) --- 967system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 968system.disk0.dma_write_txs 395 # Number of DMA write transactions. 969system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 970system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 971system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 972system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 973system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 974system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
975system.iobus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
976system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 977system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 978system.iobus.trans_dist::WriteReq 51205 # Transaction distribution 979system.iobus.trans_dist::WriteResp 51205 # Transaction distribution 980system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) 981system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 982system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 983system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 38 unchanged lines hidden (view full) --- 1022system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) 1023system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1024system.iobus.reqLayer27.occupancy 215662167 # Layer occupancy (ticks) 1025system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1026system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) 1027system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1028system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) 1029system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
1030system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
1031system.iocache.tags.replacements 41685 # number of replacements 1032system.iocache.tags.tagsinuse 1.339384 # Cycle average of tags in use 1033system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1034system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 1035system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1036system.iocache.tags.warmup_cycle 1774106669000 # Cycle when the warmup percentage was hit. 1037system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor 1038system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy 1039system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy 1040system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1041system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1042system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1043system.iocache.tags.tag_accesses 375525 # Number of tag accesses 1044system.iocache.tags.data_accesses 375525 # Number of data accesses |
1045system.iocache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
1046system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 1047system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 1048system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1049system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1050system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 1051system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 1052system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 1053system.iocache.overall_misses::total 41725 # number of overall misses --- 64 unchanged lines hidden (view full) --- 1118system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency 1119system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency 1120system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency 1121system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency 1122system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency 1123system.iocache.demand_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency 1124system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency 1125system.iocache.overall_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency |
1126system.membus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
1127system.membus.trans_dist::ReadReq 6930 # Transaction distribution 1128system.membus.trans_dist::ReadResp 292274 # Transaction distribution 1129system.membus.trans_dist::WriteReq 9653 # Transaction distribution 1130system.membus.trans_dist::WriteResp 9653 # Transaction distribution 1131system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution 1132system.membus.trans_dist::CleanEvict 261560 # Transaction distribution 1133system.membus.trans_dist::UpgradeReq 150 # Transaction distribution 1134system.membus.trans_dist::UpgradeResp 2 # Transaction distribution --- 28 unchanged lines hidden (view full) --- 1163system.membus.reqLayer0.occupancy 30122500 # Layer occupancy (ticks) 1164system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1165system.membus.reqLayer1.occupancy 1287200967 # Layer occupancy (ticks) 1166system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1167system.membus.respLayer1.occupancy 2143013000 # Layer occupancy (ticks) 1168system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1169system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) 1170system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
1171system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1172system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1173system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1174system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1175system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
1176system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1177system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1178system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1179system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1180system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1181system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1182system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1183system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1199system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1200system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1201system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1202system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1203system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1204system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1205system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1206system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
1207system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1208system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1209system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1210system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1211system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1212system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1213system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1214system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1215system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1216system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1217system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1218system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1219system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1220system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1221system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1222system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1223system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1224system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1225system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1226system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1227system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1228system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states 1229system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states |
1230 1231---------- End Simulation Statistics ---------- |