3,5c3,5
< sim_seconds 1.918473 # Number of seconds simulated
< sim_ticks 1918473094000 # Number of ticks simulated
< final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.920428 # Number of seconds simulated
> sim_ticks 1920428041000 # Number of ticks simulated
> final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 948634 # Simulator instruction rate (inst/s)
< host_op_rate 948634 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 32389976926 # Simulator tick rate (ticks/s)
< host_mem_usage 304780 # Number of bytes of host memory used
< host_seconds 59.23 # Real time elapsed on the host
< sim_insts 56188014 # Number of instructions simulated
< sim_ops 56188014 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1218375 # Simulator instruction rate (inst/s)
> host_op_rate 1218374 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 41646226437 # Simulator tick rate (ticks/s)
> host_mem_usage 305884 # Number of bytes of host memory used
> host_seconds 46.11 # Real time elapsed on the host
> sim_insts 56182750 # Number of instructions simulated
> sim_ops 56182750 # Number of ops (including micro ops) simulated
15c15
< system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory
17c17
< system.physmem.bytes_read::total 28350528 # Number of bytes read from this memory
---
> system.physmem.bytes_read::total 28349952 # Number of bytes read from this memory
20,21c20,21
< system.physmem.bytes_written::writebacks 7389888 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7389888 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 7389824 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7389824 # Number of bytes written to this memory
23c23
< system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 388233 # Number of read requests responded to by this memory
25,120c25,122
< system.physmem.num_reads::total 442977 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 115467 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 115467 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 443419 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 12951700 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 1382533 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 14777652 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 443419 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 443419 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3851963 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3851963 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3851963 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 443419 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 442977 # Total number of read requests accepted by DRAM controller
< system.physmem.writeReqs 115467 # Total number of write requests accepted by DRAM controller
< system.physmem.readBursts 442977 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
< system.physmem.writeBursts 115467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
< system.physmem.bytesRead 28350528 # Total number of bytes read from memory
< system.physmem.bytesWritten 7389888 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q
< system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 28297 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 28045 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 27408 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 27547 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 26911 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 26768 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 27805 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 27257 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 27713 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 27329 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 27431 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 28072 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 28025 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 28266 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 7723 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 7594 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 7833 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 7543 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 7011 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 6984 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 6467 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 6223 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 7221 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 6661 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 7097 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 6780 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 7013 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 7721 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 7774 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 7822 # Track writes on a per bank basis
< system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
< system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
< system.physmem.totGap 1918461222000 # Total gap between requests
< system.physmem.readPktSize::0 0 # Categorize read packet sizes
< system.physmem.readPktSize::1 0 # Categorize read packet sizes
< system.physmem.readPktSize::2 0 # Categorize read packet sizes
< system.physmem.readPktSize::3 0 # Categorize read packet sizes
< system.physmem.readPktSize::4 0 # Categorize read packet sizes
< system.physmem.readPktSize::5 0 # Categorize read packet sizes
< system.physmem.readPktSize::6 442977 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # Categorize write packet sizes
< system.physmem.writePktSize::1 0 # Categorize write packet sizes
< system.physmem.writePktSize::2 0 # Categorize write packet sizes
< system.physmem.writePktSize::3 0 # Categorize write packet sizes
< system.physmem.writePktSize::4 0 # Categorize write packet sizes
< system.physmem.writePktSize::5 0 # Categorize write packet sizes
< system.physmem.writePktSize::6 115467 # Categorize write packet sizes
< system.physmem.rdQLenPdf::0 402244 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 7043 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 5311 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 3263 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3253 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 3011 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1562 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 1513 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1478 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1450 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1424 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1426 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1399 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 2029 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 2311 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 2193 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1221 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 460 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
---
> system.physmem.num_reads::total 442968 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 115466 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 115466 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 442968 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 12938216 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 1381125 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 14762309 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 442968 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 442968 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3848009 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3848009 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3848009 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 442968 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 12938216 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 1381125 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 18610318 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 442968 # Number of read requests accepted
> system.physmem.writeReqs 115466 # Number of write requests accepted
> system.physmem.readBursts 442968 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 115466 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 28346688 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7389440 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 28349952 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7389824 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 27966 # Per bank write bursts
> system.physmem.perBankRdBursts::1 28089 # Per bank write bursts
> system.physmem.perBankRdBursts::2 28297 # Per bank write bursts
> system.physmem.perBankRdBursts::3 28053 # Per bank write bursts
> system.physmem.perBankRdBursts::4 27407 # Per bank write bursts
> system.physmem.perBankRdBursts::5 27545 # Per bank write bursts
> system.physmem.perBankRdBursts::6 26911 # Per bank write bursts
> system.physmem.perBankRdBursts::7 26762 # Per bank write bursts
> system.physmem.perBankRdBursts::8 27807 # Per bank write bursts
> system.physmem.perBankRdBursts::9 27255 # Per bank write bursts
> system.physmem.perBankRdBursts::10 27714 # Per bank write bursts
> system.physmem.perBankRdBursts::11 27327 # Per bank write bursts
> system.physmem.perBankRdBursts::12 27431 # Per bank write bursts
> system.physmem.perBankRdBursts::13 28073 # Per bank write bursts
> system.physmem.perBankRdBursts::14 28024 # Per bank write bursts
> system.physmem.perBankRdBursts::15 28256 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7722 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7593 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7833 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7543 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7010 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6982 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6469 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6223 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7224 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6661 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7099 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6780 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7009 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7722 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7773 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7817 # Per bank write bursts
> system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
> system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
> system.physmem.totGap 1920416169000 # Total gap between requests
> system.physmem.readPktSize::0 0 # Read request sizes (log2)
> system.physmem.readPktSize::1 0 # Read request sizes (log2)
> system.physmem.readPktSize::2 0 # Read request sizes (log2)
> system.physmem.readPktSize::3 0 # Read request sizes (log2)
> system.physmem.readPktSize::4 0 # Read request sizes (log2)
> system.physmem.readPktSize::5 0 # Read request sizes (log2)
> system.physmem.readPktSize::6 442968 # Read request sizes (log2)
> system.physmem.writePktSize::0 0 # Write request sizes (log2)
> system.physmem.writePktSize::1 0 # Write request sizes (log2)
> system.physmem.writePktSize::2 0 # Write request sizes (log2)
> system.physmem.writePktSize::3 0 # Write request sizes (log2)
> system.physmem.writePktSize::4 0 # Write request sizes (log2)
> system.physmem.writePktSize::5 0 # Write request sizes (log2)
> system.physmem.writePktSize::6 115466 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 403787 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 10503 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 5396 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 2702 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 2330 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2324 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1381 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 1352 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1304 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1247 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 967 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 958 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 953 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 963 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
132,309c134,363
< system.physmem.wrQLenPdf::0 3591 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 3696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4739 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 5019 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 5021 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5020 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 1430 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 1325 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 282 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 37132 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 962.378541 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 229.718891 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 2449.750918 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64-67 13161 35.44% 35.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-131 5591 15.06% 50.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192-195 3357 9.04% 59.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-259 2263 6.09% 65.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320-323 1589 4.28% 69.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-387 1303 3.51% 73.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448-451 971 2.61% 76.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-515 731 1.97% 78.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576-579 647 1.74% 79.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-643 569 1.53% 81.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::704-707 543 1.46% 82.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-771 425 1.14% 83.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832-835 308 0.83% 84.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-899 237 0.64% 85.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960-963 163 0.44% 85.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1027 235 0.63% 86.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1088-1091 101 0.27% 86.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1152-1155 93 0.25% 86.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1216-1219 98 0.26% 87.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1280-1283 98 0.26% 87.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1344-1347 85 0.23% 87.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1408-1411 107 0.29% 88.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1472-1475 1046 2.82% 90.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1536-1539 157 0.42% 91.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1600-1603 87 0.23% 91.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664-1667 55 0.15% 91.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1728-1731 46 0.12% 91.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1792-1795 40 0.11% 91.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856-1859 31 0.08% 91.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1920-1923 18 0.05% 91.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1984-1987 16 0.04% 92.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2048-2051 26 0.07% 92.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176-2179 8 0.02% 92.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2240-2243 8 0.02% 92.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2304-2307 15 0.04% 92.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2368-2371 14 0.04% 92.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2560-2563 6 0.02% 92.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2688-2691 4 0.01% 92.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880-2883 2 0.01% 92.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2944-2947 4 0.01% 92.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3008-3011 2 0.01% 92.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3136-3139 3 0.01% 92.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3200-3203 4 0.01% 92.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3520-3523 4 0.01% 92.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4032-4035 1 0.00% 92.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4416-4419 3 0.01% 92.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4928-4931 4 0.01% 92.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5056-5059 2 0.01% 92.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5120-5123 1 0.00% 92.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5312-5315 2 0.01% 92.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5440-5443 2 0.01% 92.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5696-5699 1 0.00% 92.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5760-5763 1 0.00% 92.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6080-6083 1 0.00% 92.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6592-6595 1 0.00% 92.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7168-7171 3 0.01% 92.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7552-7555 1 0.00% 92.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7680-7683 1 0.00% 92.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7744-7747 1 0.00% 92.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7808-7811 1 0.00% 92.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7936-7939 3 0.01% 92.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8000-8003 3 0.01% 92.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8128-8131 4 0.01% 92.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8192-8195 2437 6.56% 99.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14656-14659 2 0.01% 99.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16384-16387 242 0.65% 99.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16448-16451 9 0.02% 99.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16512-16515 9 0.02% 99.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16576-16579 3 0.01% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16640-16643 3 0.01% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16704-16707 2 0.01% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16832-16835 4 0.01% 99.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17024-17027 3 0.01% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17344-17347 2 0.01% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 37132 # Bytes accessed per row activation
< system.physmem.totQLat 3659130000 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 11798708750 # Sum of mem lat for all requests
< system.physmem.totBusLat 2214635000 # Total cycles spent in databus access
< system.physmem.totBankLat 5924943750 # Total cycles spent in bank access
< system.physmem.avgQLat 8261.25 # Average queueing delay per request
< system.physmem.avgBankLat 13376.80 # Average bank access latency per request
< system.physmem.avgBusLat 5000.00 # Average bus latency per request
< system.physmem.avgMemAccLat 26638.04 # Average memory access latency
< system.physmem.avgRdBW 14.78 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 14.78 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 3.85 # Average consumed write bandwidth in MB/s
< system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
---
> system.physmem.wrQLenPdf::0 4636 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4672 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 5362 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 6093 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5438 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 5429 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 5533 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 5593 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 4916 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 4913 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 4899 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 5734 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 5836 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 5819 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 5861 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 5900 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4775 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4734 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4698 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4676 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 26 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 46254 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 772.575777 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 229.901205 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 1785.674907 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64-67 16351 35.35% 35.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-131 6669 14.42% 49.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192-195 4598 9.94% 59.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-259 2705 5.85% 65.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320-323 1760 3.81% 69.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-387 1480 3.20% 72.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448-451 1070 2.31% 74.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-515 848 1.83% 76.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576-579 733 1.58% 78.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-643 614 1.33% 79.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704-707 629 1.36% 80.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-771 417 0.90% 81.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832-835 327 0.71% 82.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-899 305 0.66% 83.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960-963 281 0.61% 83.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1027 335 0.72% 84.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088-1091 208 0.45% 85.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1152-1155 173 0.37% 85.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1216-1219 157 0.34% 85.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1280-1283 138 0.30% 86.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344-1347 163 0.35% 86.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1408-1411 903 1.95% 88.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472-1475 167 0.36% 88.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1536-1539 98 0.21% 88.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600-1603 103 0.22% 89.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1664-1667 86 0.19% 89.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1728-1731 86 0.19% 89.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792-1795 55 0.12% 89.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856-1859 76 0.16% 89.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920-1923 70 0.15% 89.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1984-1987 69 0.15% 90.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2048-2051 49 0.11% 90.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2112-2115 76 0.16% 90.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176-2179 62 0.13% 90.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2240-2243 63 0.14% 90.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304-2307 35 0.08% 90.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2368-2371 62 0.13% 90.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432-2435 58 0.13% 90.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2496-2499 65 0.14% 91.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2560-2563 35 0.08% 91.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2624-2627 74 0.16% 91.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2688-2691 59 0.13% 91.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2752-2755 59 0.13% 91.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2816-2819 26 0.06% 91.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2880-2883 59 0.13% 91.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2944-2947 60 0.13% 91.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3008-3011 63 0.14% 92.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3072-3075 34 0.07% 92.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3136-3139 64 0.14% 92.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3200-3203 58 0.13% 92.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3264-3267 54 0.12% 92.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3328-3331 33 0.07% 92.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3392-3395 54 0.12% 92.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3456-3459 58 0.13% 92.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3520-3523 64 0.14% 92.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3584-3587 34 0.07% 93.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3648-3651 65 0.14% 93.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3712-3715 57 0.12% 93.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3776-3779 56 0.12% 93.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3840-3843 28 0.06% 93.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3904-3907 54 0.12% 93.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3968-3971 53 0.11% 93.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4032-4035 65 0.14% 93.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4160-4163 67 0.14% 94.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4224-4227 53 0.11% 94.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4288-4291 55 0.12% 94.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4352-4355 27 0.06% 94.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4416-4419 54 0.12% 94.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4480-4483 56 0.12% 94.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4544-4547 66 0.14% 94.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4608-4611 372 0.80% 95.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4672-4675 49 0.11% 95.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4736-4739 28 0.06% 95.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4800-4803 48 0.10% 95.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4864-4867 28 0.06% 95.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4928-4931 51 0.11% 95.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4992-4995 28 0.06% 96.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5056-5059 52 0.11% 96.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5120-5123 28 0.06% 96.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5184-5187 51 0.11% 96.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5248-5251 40 0.09% 96.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5312-5315 53 0.11% 96.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5376-5379 25 0.05% 96.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5440-5443 51 0.11% 96.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5504-5507 26 0.06% 96.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5568-5571 51 0.11% 96.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5632-5635 24 0.05% 96.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5696-5699 50 0.11% 97.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5760-5763 28 0.06% 97.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5824-5827 50 0.11% 97.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5888-5891 26 0.06% 97.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5952-5955 50 0.11% 97.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6016-6019 27 0.06% 97.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6080-6083 51 0.11% 97.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6144-6147 28 0.06% 97.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6208-6211 50 0.11% 97.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6272-6275 26 0.06% 97.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6336-6339 49 0.11% 97.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6400-6403 26 0.06% 97.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6464-6467 52 0.11% 98.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6528-6531 25 0.05% 98.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6592-6595 52 0.11% 98.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6656-6659 25 0.05% 98.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6720-6723 52 0.11% 98.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6784-6787 425 0.92% 99.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7168-7171 13 0.03% 99.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7680-7683 4 0.01% 99.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.34% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10880-10883 2 0.00% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13504-13507 3 0.01% 99.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14336-14339 2 0.00% 99.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14848-14851 2 0.00% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15360-15363 35 0.08% 99.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16384-16387 180 0.39% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 46254 # Bytes accessed per row activation
> system.physmem.totQLat 6257775000 # Total ticks spent queuing
> system.physmem.totMemAccLat 14505282500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2214585000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 6032922500 # Total ticks spent accessing banks
> system.physmem.avgQLat 14128.55 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 13620.89 # Average bank access latency per DRAM burst
> system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
> system.physmem.avgMemAccLat 32749.44 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 14.76 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 14.76 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s
> system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
311,323c365,381
< system.physmem.avgRdQLen 0.01 # Average read queue length over time
< system.physmem.avgWrQLen 13.19 # Average write queue length over time
< system.physmem.readRowHits 427838 # Number of row buffer hits during reads
< system.physmem.writeRowHits 93417 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 96.59 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes
< system.physmem.avgGap 3435369.03 # Average gap between requests
< system.membus.throughput 18671288 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 292313 # Transaction distribution
< system.membus.trans_dist::ReadResp 292313 # Transaction distribution
< system.membus.trans_dist::WriteReq 9649 # Transaction distribution
< system.membus.trans_dist::WriteResp 9649 # Transaction distribution
< system.membus.trans_dist::Writeback 115467 # Transaction distribution
---
> system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 14.25 # Average write queue length when enqueuing
> system.physmem.readRowHits 419360 # Number of row buffer hits during reads
> system.physmem.writeRowHits 92763 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 94.68 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 80.34 # Row buffer hit rate for writes
> system.physmem.avgGap 3438931.31 # Average gap between requests
> system.physmem.pageHitRate 91.72 # Row buffer hit rate, read and write combined
> system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state
> system.membus.throughput 18651952 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 292310 # Transaction distribution
> system.membus.trans_dist::ReadResp 292310 # Transaction distribution
> system.membus.trans_dist::WriteReq 9650 # Transaction distribution
> system.membus.trans_dist::WriteResp 9650 # Transaction distribution
> system.membus.trans_dist::Writeback 115466 # Transaction distribution
326,330c384,388
< system.membus.trans_dist::ReadExReq 158147 # Transaction distribution
< system.membus.trans_dist::ReadExResp 158147 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877556 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadExReq 158141 # Transaction distribution
> system.membus.trans_dist::ReadExResp 158141 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877537 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910697 # Packet count per connected master and slave (bytes)
333,336c391,394
< system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1035377 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30430656 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475220 # Cumulative packet size per connected master and slave (bytes)
339,340c397,398
< system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 35784972 # Total data (bytes)
---
> system.membus.tot_pkt_size::total 35784340 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 35784340 # Total data (bytes)
342c400
< system.membus.reqLayer0.occupancy 32373000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks)
344c402
< system.membus.reqLayer1.occupancy 1487941500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1489694250 # Layer occupancy (ticks)
346c404
< system.membus.respLayer1.occupancy 3745756604 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 3746415596 # Layer occupancy (ticks)
348c406
< system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 376299750 # Layer occupancy (ticks)
351c409
< system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.352288 # Cycle average of tags in use
355,358c413,416
< system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1753529489000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy
367,374c425,432
< system.iocache.ReadReq_miss_latency::tsunami.ide 21343633 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21343633 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::tsunami.ide 10434225282 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 10434225282 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 10455568915 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 10455568915 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 10455568915 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 10455568915 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::tsunami.ide 12989922573 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 12989922573 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 13011056956 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 13011056956 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 13011056956 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 13011056956 # number of overall miss cycles
391,399c449,457
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123373.601156 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 123373.601156 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251112.468281 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 251112.468281 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 250582.837987 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 250582.837987 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 250582.837987 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 272640 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 312618.467775 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 311828.806615 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 311828.806615 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 403484 # number of cycles access was blocked
401c459
< system.iocache.blocked::no_mshrs 27184 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 29141 # number of cycles access was blocked
403c461
< system.iocache.avg_blocked_cycles::no_mshrs 10.029429 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 13.845922 # average number of cycles each access was blocked
417,424c475,482
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8272160782 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 8272160782 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 8284506915 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 8284506915 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 8284506915 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 8284506915 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10827670073 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 10827670073 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 10839807456 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 10839807456 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 10839807456 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 10839807456 # number of overall MSHR miss cycles
433,440c491,498
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199079.726174 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 199079.726174 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198550.195686 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 198550.195686 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency
458,459c516,517
< system.cpu.dtb.read_hits 9065600 # DTB read hits
< system.cpu.dtb.read_misses 10324 # DTB read misses
---
> system.cpu.dtb.read_hits 9064966 # DTB read hits
> system.cpu.dtb.read_misses 10312 # DTB read misses
461,463c519,521
< system.cpu.dtb.read_accesses 728853 # DTB read accesses
< system.cpu.dtb.write_hits 6356756 # DTB write hits
< system.cpu.dtb.write_misses 1142 # DTB write misses
---
> system.cpu.dtb.read_accesses 728817 # DTB read accesses
> system.cpu.dtb.write_hits 6356267 # DTB write hits
> system.cpu.dtb.write_misses 1140 # DTB write misses
465,467c523,525
< system.cpu.dtb.write_accesses 291931 # DTB write accesses
< system.cpu.dtb.data_hits 15422356 # DTB hits
< system.cpu.dtb.data_misses 11466 # DTB misses
---
> system.cpu.dtb.write_accesses 291929 # DTB write accesses
> system.cpu.dtb.data_hits 15421233 # DTB hits
> system.cpu.dtb.data_misses 11452 # DTB misses
469,471c527,529
< system.cpu.dtb.data_accesses 1020784 # DTB accesses
< system.cpu.itb.fetch_hits 4974352 # ITB hits
< system.cpu.itb.fetch_misses 5010 # ITB misses
---
> system.cpu.dtb.data_accesses 1020746 # DTB accesses
> system.cpu.itb.fetch_hits 4973920 # ITB hits
> system.cpu.itb.fetch_misses 4997 # ITB misses
473c531
< system.cpu.itb.fetch_accesses 4979362 # ITB accesses
---
> system.cpu.itb.fetch_accesses 4978917 # ITB accesses
486c544
< system.cpu.numCycles 3836946188 # number of cpu cycles simulated
---
> system.cpu.numCycles 3840856082 # number of cpu cycles simulated
489,507c547,565
< system.cpu.committedInsts 56188014 # Number of instructions committed
< system.cpu.committedOps 56188014 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 52059797 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses
< system.cpu.num_func_calls 1483456 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 6468822 # number of instructions that are conditional controls
< system.cpu.num_int_insts 52059797 # number of integer instructions
< system.cpu.num_fp_insts 324527 # number of float instructions
< system.cpu.num_int_register_reads 71330046 # number of times the integer registers were read
< system.cpu.num_int_register_writes 38525190 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read
< system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written
< system.cpu.num_mem_refs 15474978 # number of memory refs
< system.cpu.num_load_insts 9102456 # Number of load instructions
< system.cpu.num_store_insts 6372522 # Number of store instructions
< system.cpu.num_idle_cycles 3586988416.498130 # Number of idle cycles
< system.cpu.num_busy_cycles 249957771.501870 # Number of busy cycles
< system.cpu.not_idle_fraction 0.065145 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.934855 # Percentage of idle cycles
---
> system.cpu.committedInsts 56182750 # Number of instructions committed
> system.cpu.committedOps 56182750 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 52054772 # Number of integer alu accesses
> system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses
> system.cpu.num_func_calls 1483342 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 6468084 # number of instructions that are conditional controls
> system.cpu.num_int_insts 52054772 # number of integer instructions
> system.cpu.num_fp_insts 324326 # number of float instructions
> system.cpu.num_int_register_reads 71321847 # number of times the integer registers were read
> system.cpu.num_int_register_writes 38521555 # number of times the integer registers were written
> system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read
> system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written
> system.cpu.num_mem_refs 15473812 # number of memory refs
> system.cpu.num_load_insts 9101789 # Number of load instructions
> system.cpu.num_store_insts 6372023 # Number of store instructions
> system.cpu.num_idle_cycles 3588896828.998131 # Number of idle cycles
> system.cpu.num_busy_cycles 251959253.001869 # Number of busy cycles
> system.cpu.not_idle_fraction 0.065600 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.934400 # Percentage of idle cycles
509,511c567,569
< system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211982 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74893 40.89% 40.89% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 211963 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl
513,516c571,574
< system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 106209 57.99% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 183164 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73526 49.31% 49.31% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 106216 57.99% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 183174 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl
518,526c576,584
< system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73526 49.31% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 149114 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1857159489000 96.80% 96.80% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 91367000 0.00% 96.81% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 736929000 0.04% 96.85% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 60484575000 3.15% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1918472360000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1858257404500 96.76% 96.76% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 91623500 0.00% 96.77% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 737068500 0.04% 96.81% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 61341210500 3.19% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1920427307000 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl
529,530c587,588
< system.cpu.kern.ipl_used::31 0.692277 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814101 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.692250 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814084 # fraction of swpipl calls that actually changed the ipl
566,567c624,625
< system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed
< system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
---
> system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed
> system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
569,570c627,628
< system.cpu.kern.callpal::swpipl 175945 91.21% 93.41% # number of callpals executed
< system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175953 91.22% 93.41% # number of callpals executed
> system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed
573c631
< system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
---
> system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
575c633
< system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
---
> system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed
578c636
< system.cpu.kern.callpal::total 192891 # number of callpals executed
---
> system.cpu.kern.callpal::total 192898 # number of callpals executed
580,585c638,643
< system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
< system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
< system.cpu.kern.mode_good::kernel 1911
< system.cpu.kern.mode_good::user 1740
< system.cpu.kern.mode_good::idle 171
< system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
> system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
> system.cpu.kern.mode_good::kernel 1908
> system.cpu.kern.mode_good::user 1739
> system.cpu.kern.mode_good::idle 169
> system.cpu.kern.mode_switch_good::kernel 0.323225 # fraction of useful protection mode switches
587,592c645,650
< system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 46124802000 2.40% 2.40% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 5245072500 0.27% 2.68% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1867102483500 97.32% 100.00% # number of ticks spent at the given mode
< system.cpu.kern.swap_context 4179 # number of times the context was actually changed
---
> system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.391907 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 46222890000 2.41% 2.41% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 5212630500 0.27% 2.68% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1868991784500 97.32% 100.00% # number of ticks spent at the given mode
> system.cpu.kern.swap_context 4176 # number of times the context was actually changed
624c682
< system.iobus.throughput 1410582 # Throughput (bytes/s)
---
> system.iobus.throughput 1409150 # Throughput (bytes/s)
627,629c685,687
< system.iobus.trans_dist::WriteReq 51201 # Transaction distribution
< system.iobus.trans_dist::WriteResp 51201 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::WriteReq 51202 # Transaction distribution
> system.iobus.trans_dist::WriteResp 51202 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes)
641c699
< system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes)
644,645c702,703
< system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes)
657c715
< system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes)
660,662c718,720
< system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 2706164 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
---
> system.iobus.tot_pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 2706172 # Total data (bytes)
> system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks)
684c742
< system.iobus.reqLayer29.occupancy 378268915 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 377727206 # Layer occupancy (ticks)
688c746
< system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
690c748
< system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 42674250 # Layer occupancy (ticks)
692,736c750,794
< system.cpu.icache.tags.replacements 928665 # number of replacements
< system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 55270512 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 55270512 # number of overall hits
< system.cpu.icache.overall_hits::total 55270512 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 929336 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 929336 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 929336 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 929336 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 929336 # number of overall misses
< system.cpu.icache.overall_misses::total 929336 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 13015346257 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 13015346257 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 13015346257 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 13015346257 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 13015346257 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 13015346257 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 56199848 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 56199848 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 56199848 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 56199848 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 56199848 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 56199848 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016536 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.016536 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.016536 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.016536 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.016536 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.016536 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14004.995241 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14004.995241 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14004.995241 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14004.995241 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14004.995241 # average overall miss latency
---
> system.cpu.icache.tags.replacements 928358 # number of replacements
> system.cpu.icache.tags.tagsinuse 508.321671 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 55265541 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 928869 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 59.497670 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 39723654250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 55265541 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 55265541 # number of overall hits
> system.cpu.icache.overall_hits::total 55265541 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 929029 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 929029 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 929029 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 929029 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 929029 # number of overall misses
> system.cpu.icache.overall_misses::total 929029 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12961853258 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12961853258 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12961853258 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12961853258 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12961853258 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12961853258 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 56194570 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 56194570 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 56194570 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 56194570 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 56194570 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 56194570 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13952.043755 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13952.043755 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13952.043755 # average overall miss latency
745,768c803,826
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929336 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 929336 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 929336 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 929336 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 929336 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 929336 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11150220743 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 11150220743 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11150220743 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 11150220743 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11150220743 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 11150220743 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016536 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.016536 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016536 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.016536 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.051020 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.051020 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929029 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 929029 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 929029 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 929029 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 929029 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 929029 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11098555742 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 11098555742 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11098555742 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 11098555742 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11098555742 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 11098555742 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11946.403979 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11946.403979 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11946.403979 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11946.403979 # average overall mshr miss latency
770,787c828,845
< system.cpu.l2cache.tags.replacements 336065 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.848589 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072620 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.075203 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.inst 916024 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 814969 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1730993 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 835407 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 835407 # number of Writeback hits
---
> system.cpu.l2cache.tags.replacements 336056 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65296.863719 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2447536 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 401218 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.100265 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 6747777750 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 55582.845445 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 4758.900638 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 4955.117636 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.848127 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072615 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.075609 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996351 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 915717 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 814814 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1730531 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 835114 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 835114 # number of Writeback hits
790,797c848,855
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187779 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187779 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 916024 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1002748 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1918772 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 916024 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1002748 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1918772 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187645 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187645 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 915717 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1002459 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1918176 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 915717 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1002459 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1918176 # number of overall hits
799,800c857,858
< system.cpu.l2cache.ReadReq_misses::cpu.data 271918 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 285210 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.data 271915 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 285207 # number of ReadReq misses
803,804c861,862
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116714 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116714 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116708 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116708 # number of ReadExReq misses
806,807c864,865
< system.cpu.l2cache.demand_misses::cpu.data 388632 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 401924 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 388623 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 401915 # number of demand (read+write) misses
809,813c867,871
< system.cpu.l2cache.overall_misses::cpu.data 388632 # number of overall misses
< system.cpu.l2cache.overall_misses::total 401924 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1060624743 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16925556244 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 17986180987 # number of ReadReq miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.data 388623 # number of overall misses
> system.cpu.l2cache.overall_misses::total 401915 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1012336742 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17564329991 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 18576666733 # number of ReadReq miss cycles
816,828c874,886
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7757662128 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7757662128 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1060624743 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 24683218372 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 25743843115 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1060624743 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 24683218372 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 25743843115 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 929316 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1086887 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2016203 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 835407 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 835407 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8190852374 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8190852374 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1012336742 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 25755182365 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 26767519107 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1012336742 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 25755182365 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 26767519107 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 929009 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1086729 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2015738 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 835114 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 835114 # number of Writeback accesses(hits+misses)
831,841c889,899
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 304493 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304493 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 929316 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1391380 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2320696 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 929316 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1391380 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2320696 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014303 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250181 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.141459 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 304353 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304353 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 929009 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1391082 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2320091 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 929009 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1391082 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2320091 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014308 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250214 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.141490 # miss rate for ReadReq accesses
844,854c902,912
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383306 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383306 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014303 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.279314 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.173191 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014303 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.279314 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.173191 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79794.217800 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62245.074780 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 63062.939543 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014308 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.279367 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.173232 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014308 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.279367 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.173232 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76161.355853 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64594.928529 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 65133.978945 # average ReadReq miss latency
857,864c915,922
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66467.280086 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66467.280086 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 64051.519976 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79794.217800 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63513.087888 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 64051.519976 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70182.441426 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70182.441426 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 66599.950504 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76161.355853 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66272.923540 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 66599.950504 # average overall miss latency
873,874c931,932
< system.cpu.l2cache.writebacks::writebacks 73955 # number of writebacks
< system.cpu.l2cache.writebacks::total 73955 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 73954 # number of writebacks
> system.cpu.l2cache.writebacks::total 73954 # number of writebacks
876,877c934,935
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271918 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 285210 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses
880,881c938,939
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116714 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116714 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116708 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116708 # number of ReadExReq MSHR misses
883,884c941,942
< system.cpu.l2cache.demand_mshr_misses::cpu.data 388632 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 401924 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 388623 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 401915 # number of demand (read+write) MSHR misses
886,890c944,948
< system.cpu.l2cache.overall_mshr_misses::cpu.data 388632 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 401924 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 893093257 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13525299756 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14418393013 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 388623 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 401915 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 845706258 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14164824509 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15010530767 # number of ReadReq MSHR miss cycles
893,909c951,967
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6297401372 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6297401372 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 893093257 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19822701128 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 20715794385 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 893093257 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19822701128 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 20715794385 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334143500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334143500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895431500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895431500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229575000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229575000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250181 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141459 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6731491626 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6731491626 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 845706258 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20896316135 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 21742022393 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 845706258 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20896316135 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 21742022393 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895642000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895642000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250214 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141490 # mshr miss rate for ReadReq accesses
912,922c970,980
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383306 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383306 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.173191 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014303 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279314 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.173191 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67190.284156 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49740.362006 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50553.602654 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.173232 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279367 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.173232 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63625.207493 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52092.839707 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52630.302787 # average ReadReq mshr miss latency
925,932c983,990
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53955.835392 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53955.835392 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67190.284156 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51006.353383 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51541.571006 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57678.065137 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57678.065137 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63625.207493 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53770.147765 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54096.071042 # average overall mshr miss latency
940,946c998,1004
< system.cpu.dcache.tags.replacements 1390866 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.replacements 1390568 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.978915 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 14049173 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1391080 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 10.099472 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 107298250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.978915 # Average occupied blocks per requestor
949,1012c1007,1070
< system.cpu.dcache.ReadReq_hits::cpu.data 7815067 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7815067 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5852671 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5852671 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 183038 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 183038 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 199236 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 199236 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 13667738 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13667738 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13667738 # number of overall hits
< system.cpu.dcache.overall_hits::total 13667738 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1069668 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1069668 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 304510 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 304510 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 17219 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17219 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1374178 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1374178 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1374178 # number of overall misses
< system.cpu.dcache.overall_misses::total 1374178 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 28240934256 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 28240934256 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10606589383 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10606589383 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229410500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 229410500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 38847523639 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 38847523639 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 38847523639 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 38847523639 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 8884735 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 8884735 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6157181 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6157181 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200257 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200257 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 199236 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 199236 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15041916 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15041916 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15041916 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15041916 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120394 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.120394 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049456 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.049456 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085985 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085985 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.091357 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.091357 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.091357 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.091357 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26401.588396 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 26401.588396 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34831.661959 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34831.661959 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13323.102387 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13323.102387 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 28269.644572 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 28269.644572 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 28269.644572 # average overall miss latency
---
> system.cpu.dcache.ReadReq_hits::cpu.data 7814622 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7814622 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5852326 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5852326 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 182986 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 182986 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 199222 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 199222 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 13666948 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13666948 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13666948 # number of overall hits
> system.cpu.dcache.overall_hits::total 13666948 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1069470 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1069470 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 17259 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17259 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1373840 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1373840 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1373840 # number of overall misses
> system.cpu.dcache.overall_misses::total 1373840 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 28875755759 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 28875755759 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 11035273137 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 11035273137 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228925250 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 228925250 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 39911028896 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 39911028896 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 39911028896 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 39911028896 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 8884092 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 8884092 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6156696 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6156696 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 199222 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 199222 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15040788 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15040788 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15040788 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15040788 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120380 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.120380 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049437 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.049437 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086189 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086189 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.091341 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.091341 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.091341 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.091341 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27000.061487 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 27000.061487 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36256.113076 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 36256.113076 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13264.108581 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13264.108581 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29050.711070 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 29050.711070 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 29050.711070 # average overall miss latency
1021,1068c1079,1126
< system.cpu.dcache.writebacks::writebacks 835407 # number of writebacks
< system.cpu.dcache.writebacks::total 835407 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069668 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1069668 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304510 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304510 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1374178 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1374178 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1374178 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1374178 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25967193744 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 25967193744 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9940394617 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 9940394617 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194939500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194939500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35907588361 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 35907588361 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35907588361 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 35907588361 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424233500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424233500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435453000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435453000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120394 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120394 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049456 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049456 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085985 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085985 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.091357 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091357 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.091357 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24275.937715 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24275.937715 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32643.902062 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32643.902062 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.185899 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.185899 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26130.230844 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26130.230844 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 835114 # number of writebacks
> system.cpu.dcache.writebacks::total 835114 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069470 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1069470 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304370 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304370 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17259 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17259 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1373840 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1373840 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1373840 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1373840 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26604805241 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 26604805241 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10372104863 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10372104863 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194393750 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194393750 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36976910104 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 36976910104 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36976910104 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 36976910104 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011442000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011442000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120380 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120380 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049437 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049437 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086189 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086189 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.091341 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.091341 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency
1076,1081c1134,1139
< system.cpu.toL2Bus.throughput 105316327 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 2023326 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2023309 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 835407 # Transaction distribution
---
> system.cpu.toL2Bus.throughput 105179195 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 2022861 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2022844 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 835114 # Transaction distribution
1084,1092c1142,1150
< system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858652 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651517 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 5510169 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476224 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142569036 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 202045260 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 345905 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 304355 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858038 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3650630 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 5508668 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59456576 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142531220 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size::total 201987796 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 201977684 # Total data (bytes)
1094c1152
< system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.reqLayer0.occupancy 2425850000 # Layer occupancy (ticks)
1098c1156
< system.cpu.toL2Bus.respLayer0.occupancy 1397230757 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1396163258 # Layer occupancy (ticks)
1100c1158
< system.cpu.toL2Bus.respLayer1.occupancy 2194639139 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2191612646 # Layer occupancy (ticks)