3,5c3,5
< sim_seconds 1.910548 # Number of seconds simulated
< sim_ticks 1910547559000 # Number of ticks simulated
< final_tick 1910547559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.913475 # Number of seconds simulated
> sim_ticks 1913474690000 # Number of ticks simulated
> final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,48c7,48
< host_inst_rate 1284259 # Simulator instruction rate (inst/s)
< host_op_rate 1284258 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 43720523895 # Simulator tick rate (ticks/s)
< host_mem_usage 330356 # Number of bytes of host memory used
< host_seconds 43.70 # Real time elapsed on the host
< sim_insts 56120911 # Number of instructions simulated
< sim_ops 56120911 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24858368 # Number of bytes read from this memory
< system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
< system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388412 # Number of read requests responded to by this memory
< system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 445225 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 13011122 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 1388268 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 14844616 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 445225 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 445225 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3875513 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3875513 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3875513 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 445225 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 13011122 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1388268 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 18720129 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 443146 # Total number of read requests seen
< system.physmem.writeReqs 115693 # Total number of write requests seen
< system.physmem.cpureqs 561589 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 28361344 # Total number of bytes read from memory
< system.physmem.bytesWritten 7404352 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 28361344 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7404352 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 45 # Number of read reqs serviced by write Q
---
> host_inst_rate 1324010 # Simulator instruction rate (inst/s)
> host_op_rate 1324010 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 45134311907 # Simulator tick rate (ticks/s)
> host_mem_usage 328328 # Number of bytes of host memory used
> host_seconds 42.40 # Real time elapsed on the host
> sim_insts 56131527 # Number of instructions simulated
> sim_ops 56131527 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24859456 # Number of bytes read from this memory
> system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28362112 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7404992 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7404992 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388429 # Number of read requests responded to by this memory
> system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 443158 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 115703 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 115703 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 444511 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 12991787 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 1386010 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 14822308 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 444511 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 444511 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3869919 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3869919 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3869919 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 444511 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 12991787 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 1386010 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 443158 # Total number of read requests seen
> system.physmem.writeReqs 115703 # Total number of write requests seen
> system.physmem.cpureqs 560726 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 28362112 # Total number of bytes read from memory
> system.physmem.bytesWritten 7404992 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 28362112 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 7404992 # bytesWritten derated as per pkt->getSize()
> system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q
50,51c50,51
< system.physmem.perBankRdReqs::0 27901 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 27706 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::0 27906 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 27707 # Track reads on a per bank basis
53c53
< system.physmem.perBankRdReqs::3 27375 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::3 27383 # Track reads on a per bank basis
56,58c56,58
< system.physmem.perBankRdReqs::6 27827 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 27615 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 28008 # Track reads on a per bank basis
---
> system.physmem.perBankRdReqs::6 27828 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 27614 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 28005 # Track reads on a per bank basis
61,67c61,67
< system.physmem.perBankRdReqs::11 27562 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 27598 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 27733 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 27646 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 27564 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 7483 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 7263 # Track writes on a per bank basis
---
> system.physmem.perBankRdReqs::11 27558 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 27591 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 27731 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 27648 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 27560 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 7488 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 7264 # Track writes on a per bank basis
69,74c69,74
< system.physmem.perBankWrReqs::3 7032 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 7167 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 7214 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 7312 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 7182 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 7584 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::3 7040 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 7173 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::5 7213 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 7315 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 7581 # Track writes on a per bank basis
77,81c77,81
< system.physmem.perBankWrReqs::11 7067 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 7154 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 7184 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 7113 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 7079 # Track writes on a per bank basis
---
> system.physmem.perBankWrReqs::11 7063 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 7148 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 7186 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 7115 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 7077 # Track writes on a per bank basis
83,84c83,84
< system.physmem.numWrRetry 2065 # Number of times wr buffer was full causing retry
< system.physmem.totGap 1910535659000 # Total gap between requests
---
> system.physmem.numWrRetry 1735 # Number of times wr buffer was full causing retry
> system.physmem.totGap 1913462790000 # Total gap between requests
91,132c91,119
< system.physmem.readPktSize::6 443146 # Categorize read packet sizes
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 117758 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 130 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
< system.physmem.rdQLenPdf::0 402456 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 4645 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 3680 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3123 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2721 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2721 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 2666 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2589 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1544 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1454 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1412 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1360 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 1368 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1379 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 1491 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 926 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
---
> system.physmem.readPktSize::6 443158 # Categorize read packet sizes
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 115703 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 402452 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 4725 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 3681 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 2218 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2703 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 2585 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1528 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1423 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 1604 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 1473 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 916 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see
144,157c131,143
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
< system.physmem.wrQLenPdf::0 3510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 4153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 5001 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 5007 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 5012 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 5015 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 5030 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 5030 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 5030 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 5030 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 3531 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 3690 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4106 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 4152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 4652 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5003 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 5013 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 5015 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 5016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 5031 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 5031 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 5031 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 5031 # What write queue length does an incoming req see
168,175c154,161
< system.physmem.wrQLenPdf::23 1521 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 1348 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 930 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 877 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 377 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 29 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::23 1500 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 879 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 379 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
177,183c163,168
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 4718066660 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 13230246660 # Sum of mem lat for all requests
< system.physmem.totBusLat 2215505000 # Total cycles spent in databus access
< system.physmem.totBankLat 6296675000 # Total cycles spent in bank access
< system.physmem.avgQLat 10647.84 # Average queueing delay per request
< system.physmem.avgBankLat 14210.47 # Average bank access latency per request
---
> system.physmem.totQLat 4718928250 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 13231418250 # Sum of mem lat for all requests
> system.physmem.totBusLat 2215485000 # Total cycles spent in databus access
> system.physmem.totBankLat 6297005000 # Total cycles spent in bank access
> system.physmem.avgQLat 10649.88 # Average queueing delay per request
> system.physmem.avgBankLat 14211.35 # Average bank access latency per request
185,189c170,174
< system.physmem.avgMemAccLat 29858.31 # Average memory access latency
< system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 3.88 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 3.88 # Average consumed write bandwidth in MB/s
---
> system.physmem.avgMemAccLat 29861.22 # Average memory access latency
> system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s
> system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s
> system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s
> system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s
193,196c178,181
< system.physmem.avgWrQLen 11.47 # Average write queue length over time
< system.physmem.readRowHits 415807 # Number of row buffer hits during reads
< system.physmem.writeRowHits 89941 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads
---
> system.physmem.avgWrQLen 9.64 # Average write queue length over time
> system.physmem.readRowHits 415747 # Number of row buffer hits during reads
> system.physmem.writeRowHits 89943 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads
198c183
< system.physmem.avgGap 3418758.64 # Average gap between requests
---
> system.physmem.avgGap 3423861.73 # Average gap between requests
200c185
< system.iocache.tagsinuse 1.342284 # Cycle average of tags in use
---
> system.iocache.tagsinuse 1.364719 # Cycle average of tags in use
204,207c189,192
< system.iocache.warmup_cycle 1745701071000 # Cycle when the warmup percentage was hit.
< system.iocache.occ_blocks::tsunami.ide 1.342284 # Average occupied blocks per requestor
< system.iocache.occ_percent::tsunami.ide 0.083893 # Average percentage of cache occupancy
< system.iocache.occ_percent::total 0.083893 # Average percentage of cache occupancy
---
> system.iocache.warmup_cycle 1745699710000 # Cycle when the warmup percentage was hit.
> system.iocache.occ_blocks::tsunami.ide 1.364719 # Average occupied blocks per requestor
> system.iocache.occ_percent::tsunami.ide 0.085295 # Average percentage of cache occupancy
> system.iocache.occ_percent::total 0.085295 # Average percentage of cache occupancy
218,223c203,208
< system.iocache.WriteReq_miss_latency::tsunami.ide 10644331806 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 10644331806 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 10665259804 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 10665259804 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 10665259804 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 10665259804 # number of overall miss cycles
---
> system.iocache.WriteReq_miss_latency::tsunami.ide 10661973806 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 10661973806 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 10682901804 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 10682901804 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 10682901804 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 10682901804 # number of overall miss cycles
242,248c227,233
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256168.940268 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 256168.940268 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 255608.383559 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 255608.383559 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 285028 # number of cycles access was blocked
---
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256593.516702 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 256593.516702 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 256031.199617 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 256031.199617 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 285723 # number of cycles access was blocked
250c235
< system.iocache.blocked::no_mshrs 27152 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 27146 # number of cycles access was blocked
252c237
< system.iocache.avg_blocked_cycles::no_mshrs 10.497496 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 10.525418 # average number of cycles each access was blocked
266,273c251,258
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8482336109 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 8482336109 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 8494267359 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 8494267359 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 8494267359 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 8494267359 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8499962078 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 8499962078 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 8511893327 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 8511893327 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 8511893327 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 8511893327 # number of overall MSHR miss cycles
282,289c267,274
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204137.853990 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 204137.853990 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204562.044619 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 204562.044619 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency
307c292
< system.cpu.dtb.read_hits 9055197 # DTB read hits
---
> system.cpu.dtb.read_hits 9056964 # DTB read hits
311c296
< system.cpu.dtb.write_hits 6350929 # DTB write hits
---
> system.cpu.dtb.write_hits 6352252 # DTB write hits
315c300
< system.cpu.dtb.data_hits 15406126 # DTB hits
---
> system.cpu.dtb.data_hits 15409216 # DTB hits
319c304
< system.cpu.itb.fetch_hits 4974131 # ITB hits
---
> system.cpu.itb.fetch_hits 4974658 # ITB hits
322c307
< system.cpu.itb.fetch_accesses 4979137 # ITB accesses
---
> system.cpu.itb.fetch_accesses 4979664 # ITB accesses
335c320
< system.cpu.numCycles 3821095118 # number of cpu cycles simulated
---
> system.cpu.numCycles 3826949380 # number of cpu cycles simulated
338,340c323,325
< system.cpu.committedInsts 56120911 # Number of instructions committed
< system.cpu.committedOps 56120911 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 51995405 # Number of integer alu accesses
---
> system.cpu.committedInsts 56131527 # Number of instructions committed
> system.cpu.committedOps 56131527 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 52005592 # Number of integer alu accesses
342,344c327,329
< system.cpu.num_func_calls 1481756 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 6462892 # number of instructions that are conditional controls
< system.cpu.num_int_insts 51995405 # number of integer instructions
---
> system.cpu.num_func_calls 1482234 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 6464100 # number of instructions that are conditional controls
> system.cpu.num_int_insts 52005592 # number of integer instructions
346,347c331,332
< system.cpu.num_int_register_reads 71234690 # number of times the integer registers were read
< system.cpu.num_int_register_writes 38473511 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 71250465 # number of times the integer registers were read
> system.cpu.num_int_register_writes 38480970 # number of times the integer registers were written
350,356c335,341
< system.cpu.num_mem_refs 15458726 # number of memory refs
< system.cpu.num_load_insts 9092044 # Number of load instructions
< system.cpu.num_store_insts 6366682 # Number of store instructions
< system.cpu.num_idle_cycles 3587142255.998123 # Number of idle cycles
< system.cpu.num_busy_cycles 233952862.001878 # Number of busy cycles
< system.cpu.not_idle_fraction 0.061227 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.938773 # Percentage of idle cycles
---
> system.cpu.num_mem_refs 15461819 # number of memory refs
> system.cpu.num_load_insts 9093811 # Number of load instructions
> system.cpu.num_store_insts 6368008 # Number of store instructions
> system.cpu.num_idle_cycles 3593003741.998122 # Number of idle cycles
> system.cpu.num_busy_cycles 233945638.001878 # Number of busy cycles
> system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.938869 # Percentage of idle cycles
358,360c343,345
< system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211970 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74891 40.89% 40.89% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 212010 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl
362,365c347,350
< system.cpu.kern.ipl_count::22 1930 1.05% 42.01% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 106204 57.99% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 183156 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73524 49.31% 49.31% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::22 1933 1.06% 42.01% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 106230 57.99% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 183193 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl
367,375c352,360
< system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73524 49.31% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 149109 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1855675111500 97.13% 97.13% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 91586500 0.00% 97.13% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 735892500 0.04% 97.17% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 54044234500 2.83% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1910546825000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1858610780000 97.13% 97.13% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 54034599000 2.82% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
378,379c363,364
< system.cpu.kern.ipl_used::31 0.692290 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814109 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.692196 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814049 # fraction of swpipl calls that actually changed the ipl
418,419c403,404
< system.cpu.kern.callpal::swpipl 175939 91.22% 93.42% # number of callpals executed
< system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175970 91.22% 93.41% # number of callpals executed
> system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed
422c407
< system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
---
> system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
424c409
< system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed
---
> system.cpu.kern.callpal::rti 5158 2.67% 99.64% # number of callpals executed
427c412
< system.cpu.kern.callpal::total 192879 # number of callpals executed
---
> system.cpu.kern.callpal::total 192916 # number of callpals executed
429,432c414,417
< system.cpu.kern.mode_switch::user 1744 # number of protection mode switches
< system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
< system.cpu.kern.mode_good::kernel 1913
< system.cpu.kern.mode_good::user 1744
---
> system.cpu.kern.mode_switch::user 1742 # number of protection mode switches
> system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
> system.cpu.kern.mode_good::kernel 1911
> system.cpu.kern.mode_good::user 1742
434c419
< system.cpu.kern.mode_switch_good::kernel 0.324237 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch_good::kernel 0.323898 # fraction of useful protection mode switches
436,440c421,425
< system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.392853 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 45393996500 2.38% 2.38% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 5132973000 0.27% 2.64% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1860019853500 97.36% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 45394142000 2.37% 2.37% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 5131394000 0.27% 2.64% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1862948418000 97.36% 100.00% # number of ticks spent at the given mode
473,517c458,502
< system.cpu.icache.replacements 927816 # number of replacements
< system.cpu.icache.tagsinuse 509.100001 # Cycle average of tags in use
< system.cpu.icache.total_refs 55204264 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 928327 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 59.466399 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 32331359000 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 509.100001 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.994336 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.994336 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 55204264 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 55204264 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 55204264 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 55204264 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 55204264 # number of overall hits
< system.cpu.icache.overall_hits::total 55204264 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 928486 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 928486 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 928486 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 928486 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 928486 # number of overall misses
< system.cpu.icache.overall_misses::total 928486 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12769098000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12769098000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12769098000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12769098000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12769098000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12769098000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 56132750 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 56132750 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 56132750 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 56132750 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 56132750 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 56132750 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016541 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.016541 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.016541 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.016541 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.016541 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.016541 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13752.601547 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13752.601547 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13752.601547 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13752.601547 # average overall miss latency
---
> system.cpu.icache.replacements 927958 # number of replacements
> system.cpu.icache.tagsinuse 509.106403 # Cycle average of tags in use
> system.cpu.icache.total_refs 55214738 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 928469 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 59.468585 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 32313596000 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 509.106403 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.994348 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.994348 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 55214738 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 55214738 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 55214738 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 55214738 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 55214738 # number of overall hits
> system.cpu.icache.overall_hits::total 55214738 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 928628 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 928628 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 928628 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 928628 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 928628 # number of overall misses
> system.cpu.icache.overall_misses::total 928628 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770278000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12770278000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12770278000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12770278000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12770278000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12770278000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 56143366 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 56143366 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 56143366 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 56143366 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 56143366 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 56143366 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.016540 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.769277 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13751.769277 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13751.769277 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13751.769277 # average overall miss latency
526,549c511,534
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928486 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 928486 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 928486 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 928486 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 928486 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 928486 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10912126000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 10912126000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10912126000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 10912126000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10912126000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 10912126000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016541 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.016541 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016541 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.016541 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11752.601547 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11752.601547 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11752.601547 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11752.601547 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11752.601547 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11752.601547 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928628 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 928628 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 928628 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 928628 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 928628 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 928628 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10913022000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 10913022000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10913022000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 10913022000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10913022000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 10913022000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11751.769277 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11751.769277 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency
551,568c536,553
< system.cpu.l2cache.replacements 336232 # number of replacements
< system.cpu.l2cache.tagsinuse 65320.349460 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 2445455 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 401395 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 6.092390 # Average number of references to valid blocks.
< system.cpu.l2cache.warmup_cycle 5253905752 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 55746.369541 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 4781.447334 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 4792.532585 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.850622 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.inst 0.072959 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.073128 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.996709 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.inst 915175 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 814009 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1729184 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 834499 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 834499 # number of Writeback hits
---
> system.cpu.l2cache.replacements 336244 # number of replacements
> system.cpu.l2cache.tagsinuse 65321.744295 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 2445552 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 401406 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 6.092465 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 5250002751 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 55750.890928 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 4786.700552 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 4784.152815 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.850691 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.073039 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.073000 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.996731 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 915318 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 813981 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1729299 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 834498 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 834498 # number of Writeback hits
571,581c556,566
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187516 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187516 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 915175 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1001525 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1916700 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 915175 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1001525 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1916700 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 271961 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 285252 # number of ReadReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187514 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187514 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 915318 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1001495 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1916813 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 915318 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1001495 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1916813 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 271963 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 285253 # number of ReadReq misses
584,594c569,579
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116841 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116841 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 13291 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 388802 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 402093 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 13291 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 388802 # number of overall misses
< system.cpu.l2cache.overall_misses::total 402093 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 831870000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11715487000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 12547357000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116856 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116856 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 388819 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 402109 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 388819 # number of overall misses
> system.cpu.l2cache.overall_misses::total 402109 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 831194000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11699138000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 12530332000 # number of ReadReq miss cycles
597,609c582,594
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5599308500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5599308500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 831870000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 17314795500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 18146665500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 831870000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 17314795500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 18146665500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 928466 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1085970 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2014436 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 834499 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 834499 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5596958000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5596958000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 831194000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 17296096000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 18127290000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 831194000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 17296096000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 18127290000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 928608 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1085944 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2014552 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 834498 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 834498 # number of Writeback accesses(hits+misses)
612,622c597,607
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 304357 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304357 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 928466 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1390327 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2318793 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 928466 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1390327 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2318793 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014315 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250431 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.141604 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 304370 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304370 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 928608 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1390314 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2318922 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 928608 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1390314 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2318922 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014312 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250439 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.141596 # miss rate for ReadReq accesses
625,635c610,620
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383895 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383895 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014315 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.279648 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.173406 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014315 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.279648 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.173406 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62588.969980 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43077.819982 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 43986.920337 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383927 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383927 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014312 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.279663 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.173403 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014312 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.279663 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.173403 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62542.814146 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43017.388395 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 43927.082274 # average ReadReq miss latency
638,645c623,630
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47922.463005 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47922.463005 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62588.969980 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44533.709960 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 45130.518313 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62588.969980 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44533.709960 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 45130.518313 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47896.197029 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47896.197029 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 45080.537864 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 45080.537864 # average overall miss latency
654,658c639,643
< system.cpu.l2cache.writebacks::writebacks 74181 # number of writebacks
< system.cpu.l2cache.writebacks::total 74181 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271961 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 285252 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 74191 # number of writebacks
> system.cpu.l2cache.writebacks::total 74191 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271963 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 285253 # number of ReadReq MSHR misses
661,671c646,656
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116841 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116841 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 388802 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 402093 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 388802 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 402093 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 666952085 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8376868075 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9043820160 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116856 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116856 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 388819 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 402109 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 388819 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 402109 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 666266030 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8360156960 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9026422990 # number of ReadReq MSHR miss cycles
674,690c659,675
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4162858124 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4162858124 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666952085 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12539726199 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 13206678284 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666952085 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12539726199 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 13206678284 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895221000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895221000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229366500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229366500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250431 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141604 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4160193080 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4160193080 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666266030 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12520350040 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 13186616070 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666266030 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12520350040 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 13186616070 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895853000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895853000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229999000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229999000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250439 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141596 # mshr miss rate for ReadReq accesses
693,703c678,688
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383895 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383895 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279648 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.173406 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279648 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.173406 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50180.730193 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30801.725523 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31704.668714 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383927 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383927 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.173403 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.173403 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50132.884123 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30740.052728 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31643.569007 # average ReadReq mshr miss latency
706,713c691,698
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35628.402051 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35628.402051 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50180.730193 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32252.216293 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32844.835110 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50180.730193 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32252.216293 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32844.835110 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35601.022455 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35601.022455 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency
721,725c706,710
< system.cpu.dcache.replacements 1389814 # number of replacements
< system.cpu.dcache.tagsinuse 511.980842 # Cycle average of tags in use
< system.cpu.dcache.total_refs 14034828 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1390326 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 10.094631 # Average number of references to valid blocks.
---
> system.cpu.dcache.replacements 1389801 # number of replacements
> system.cpu.dcache.tagsinuse 511.980871 # Cycle average of tags in use
> system.cpu.dcache.total_refs 14037928 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1390313 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 10.096955 # Average number of references to valid blocks.
727c712
< system.cpu.dcache.occ_blocks::cpu.data 511.980842 # Average occupied blocks per requestor
---
> system.cpu.dcache.occ_blocks::cpu.data 511.980871 # Average occupied blocks per requestor
730,793c715,778
< system.cpu.dcache.ReadReq_hits::cpu.data 7805620 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7805620 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5846988 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5846988 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 182985 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 182985 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 199218 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 199218 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 13652608 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13652608 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13652608 # number of overall hits
< system.cpu.dcache.overall_hits::total 13652608 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1068716 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1068716 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 304374 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 304374 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 17254 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17254 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1373090 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1373090 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1373090 # number of overall misses
< system.cpu.dcache.overall_misses::total 1373090 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 22883646000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 22883646000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8388017500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8388017500 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229841000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 229841000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 31271663500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 31271663500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 31271663500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 31271663500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 8874336 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 8874336 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6151362 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6151362 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200239 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200239 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 199218 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 199218 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15025698 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15025698 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15025698 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15025698 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120428 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.120428 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049481 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.049481 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086167 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086167 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.091383 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.091383 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21412.279782 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 21412.279782 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27558.258918 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 27558.258918 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13321.027008 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13321.027008 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 22774.664079 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 22774.664079 # average overall miss latency
---
> system.cpu.dcache.ReadReq_hits::cpu.data 7807394 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7807394 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5848285 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5848285 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 199228 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 199228 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 13655679 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13655679 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13655679 # number of overall hits
> system.cpu.dcache.overall_hits::total 13655679 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1068700 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1068700 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 304387 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 304387 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1373087 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1373087 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1373087 # number of overall misses
> system.cpu.dcache.overall_misses::total 1373087 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 22867911000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 22867911000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385686000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8385686000 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228869000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 228869000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 31253597000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 31253597000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 31253597000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 31253597000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 8876094 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 8876094 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6152672 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6152672 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 199228 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 199228 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15028766 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15028766 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15028766 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15028766 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120402 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.120402 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049472 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.049472 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.091364 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.091364 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.091364 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.091364 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21397.876860 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 21397.876860 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.422282 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.422282 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13272.384598 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13272.384598 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 22761.556260 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 22761.556260 # average overall miss latency
802,849c787,834
< system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks
< system.cpu.dcache.writebacks::total 834499 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068716 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1068716 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304374 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304374 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17254 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17254 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1373090 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1373090 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1373090 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1373090 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20746214000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 20746214000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7779269500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 7779269500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195333000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195333000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28525483500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 28525483500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28525483500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 28525483500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435232500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435232500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120428 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120428 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049481 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049481 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086167 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086167 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.279782 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.279782 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25558.258918 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25558.258918 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.027008 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.027008 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 834498 # number of writebacks
> system.cpu.dcache.writebacks::total 834498 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068700 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1068700 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304387 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304387 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1373087 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1373087 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1373087 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1373087 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730511000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730511000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776912000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776912000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194381000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194381000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507423000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 28507423000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507423000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 28507423000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011665000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011665000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435901000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120402 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120402 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19397.876860 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19397.876860 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.422282 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.422282 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency