3,5c3,5
< sim_seconds 1.926421 # Number of seconds simulated
< sim_ticks 1926421414000 # Number of ticks simulated
< final_tick 1926421414000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.926422 # Number of seconds simulated
> sim_ticks 1926421638000 # Number of ticks simulated
> final_tick 1926421638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 834051 # Simulator instruction rate (inst/s)
< host_op_rate 834051 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 28592100047 # Simulator tick rate (ticks/s)
< host_mem_usage 333408 # Number of bytes of host memory used
< host_seconds 67.38 # Real time elapsed on the host
---
> host_inst_rate 1739419 # Simulator instruction rate (inst/s)
> host_op_rate 1739418 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 59628989604 # Simulator tick rate (ticks/s)
> host_mem_usage 334072 # Number of bytes of host memory used
> host_seconds 32.31 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
32c32
< system.physmem.bw_read::cpu.data 12903146 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 12903144 # Total read bandwidth from this memory (bytes/s)
34c34
< system.physmem.bw_read::total 13342111 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 13342109 # Total read bandwidth from this memory (bytes/s)
37,39c37,39
< system.physmem.bw_write::writebacks 3845971 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3845971 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3845971 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 3845970 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3845970 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3845970 # Total bandwidth to/from this memory (bytes/s)
41c41
< system.physmem.bw_total::cpu.data 12903146 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 12903144 # Total bandwidth to/from this memory (bytes/s)
43c43
< system.physmem.bw_total::total 17188081 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::total 17188079 # Total bandwidth to/from this memory (bytes/s)
90c90
< system.physmem.totGap 1926409540500 # Total gap between requests
---
> system.physmem.totGap 1926409764500 # Total gap between requests
153,169c153,169
< system.physmem.wrQLenPdf::16 2761 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5433 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5447 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5972 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6087 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6885 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7936 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 6558 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 6936 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 7510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 7184 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6518 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6660 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5973 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5660 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::16 2767 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5442 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5449 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5980 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6090 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6888 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7955 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6560 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6959 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6506 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6626 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5946 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5824 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5647 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5581 # What write queue length does an incoming req see
171,178c171,178
< system.physmem.wrQLenPdf::34 477 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 374 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 327 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 340 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 292 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 286 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 316 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::34 478 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 398 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 372 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 319 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 296 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 302 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 330 # What write queue length does an incoming req see
180,193c180,193
< system.physmem.wrQLenPdf::43 363 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 345 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 332 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 309 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 304 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 296 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 281 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 202 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 216 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 365 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 335 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 288 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 356 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 311 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 303 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 303 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 209 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 205 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 339 # What write queue length does an incoming req see
196,199c196,199
< system.physmem.wrQLenPdf::59 335 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 300 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::59 333 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 299 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see
201,214c201,214
< system.physmem.bytesPerActivate::samples 63474 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 521.529319 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 315.079750 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 415.298836 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14953 23.56% 23.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11433 18.01% 41.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4319 6.80% 48.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3083 4.86% 53.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3219 5.07% 58.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1509 2.38% 60.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1583 2.49% 63.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 998 1.57% 64.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 22377 35.25% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63474 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 63476 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 521.512887 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 315.060266 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 415.295929 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14957 23.56% 23.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11430 18.01% 41.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4320 6.81% 48.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3081 4.85% 53.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3222 5.08% 58.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1508 2.38% 60.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1584 2.50% 63.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 999 1.57% 64.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 22375 35.25% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63476 # Bytes accessed per row activation
225,229c225,229
< system.physmem.wrPerTurnAround::gmean 18.952060 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 24.989890 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 4540 89.92% 89.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 33 0.65% 90.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 164 3.25% 93.82% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::gmean 18.953728 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 24.991500 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-23 4538 89.88% 89.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-31 34 0.67% 90.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-39 165 3.27% 93.82% # Writes before turning the bus around for reads
233,235c233,235
< system.physmem.wrPerTurnAround::64-71 7 0.14% 94.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 4 0.08% 94.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 36 0.71% 95.19% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::64-71 8 0.16% 94.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-79 5 0.10% 94.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-87 34 0.67% 95.19% # Writes before turning the bus around for reads
237,238c237,238
< system.physmem.wrPerTurnAround::96-103 139 2.75% 97.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 18 0.36% 98.34% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::96-103 141 2.79% 98.02% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-111 16 0.32% 98.34% # Writes before turning the bus around for reads
245,247c245,247
< system.physmem.wrPerTurnAround::168-175 13 0.26% 99.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 4 0.08% 99.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-191 12 0.24% 99.56% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::168-175 12 0.24% 99.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-183 4 0.08% 99.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-191 13 0.26% 99.56% # Writes before turning the bus around for reads
255,256c255,256
< system.physmem.totQLat 6110965000 # Total ticks spent queuing
< system.physmem.totMemAccLat 13638958750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 6110922250 # Total ticks spent queuing
> system.physmem.totMemAccLat 13638916000 # Total ticks spent from burst creation until serviced by the DRAM
258c258
< system.physmem.avgQLat 15220.60 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 15220.50 # Average queueing delay per DRAM burst
260c260
< system.physmem.avgMemAccLat 33970.60 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 33970.50 # Average memory access latency per DRAM burst
271c271
< system.physmem.readRowHits 360227 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 360225 # Number of row buffer hits during reads
275c275
< system.physmem.avgGap 3723487.47 # Average gap between requests
---
> system.physmem.avgGap 3723487.90 # Average gap between requests
282,290c282,290
< system.physmem_0.actBackEnergy 5038358250 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 366301440 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 13030830420 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 6357713760 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 449603447400 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 481990669050 # Total energy per rank (pJ)
< system.physmem_0.averagePower 250.200016 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 1914256960750 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 613825000 # Time in different power states
---
> system.physmem_0.actBackEnergy 5038088640 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 365587680 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 13029981120 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 6359365440 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 449603503800 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 481990544460 # Total energy per rank (pJ)
> system.physmem_0.averagePower 250.199922 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 1914259413500 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 611958500 # Time in different power states
292,297c292,297
< system.physmem_0.memoryStateTime::SREF 1869275563500 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 16556600250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 9050884750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 28576648500 # Time in different power states
< system.physmem_1.actEnergy 232364160 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 123504480 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.memoryStateTime::SREF 1869275787500 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 16560859500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 9050522500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 28574618000 # Time in different power states
> system.physmem_1.actEnergy 232378440 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 123512070 # Energy for precharge commands per rank (pJ)
301,309c301,309
< system.physmem_1.actBackEnergy 5157840510 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 361297920 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 13647845730 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 6595007040 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 449082638955 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 482651277075 # Total energy per rank (pJ)
< system.physmem_1.averagePower 250.542936 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 1914153639500 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 598128250 # Time in different power states
---
> system.physmem_1.actBackEnergy 5156813940 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 361085280 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 13650484260 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 6593796000 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 449082763260 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 482651694330 # Total energy per rank (pJ)
> system.physmem_1.averagePower 250.543123 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 1914156494000 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 598122250 # Time in different power states
311,316c311,316
< system.physmem_1.memoryStateTime::SREF 1867054823500 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 17174624250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 9236704750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 29929623250 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
---
> system.physmem_1.memoryStateTime::SREF 1867055047500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 17171481750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 9234080250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 29935396250 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
352,353c352,353
< system.cpu.pwrStateClkGateDist::mean 281128919.188117 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 439406492.836173 # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::mean 281128919.971939 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 439406494.656653 # Distribution of time spent in the clock gated state
359,361c359,361
< system.cpu.pwrStateResidencyTicks::ON 133100038499 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321375501 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 3852842828 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 133100257499 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321380501 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 3852843276 # number of cpu cycles simulated
377c377
< system.cpu.kern.ipl_ticks::0 1859428695000 96.52% 96.52% # number of cycles we spent at this ipl
---
> system.cpu.kern.ipl_ticks::0 1859428733000 96.52% 96.52% # number of cycles we spent at this ipl
379,381c379,381
< system.cpu.kern.ipl_ticks::22 772442000 0.04% 96.57% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 66125040000 3.43% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1926420680000 # number of cycles we spent at this ipl
---
> system.cpu.kern.ipl_ticks::22 772464500 0.04% 96.57% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 66125203500 3.43% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1926420904000 # number of cycles we spent at this ipl
414,416c414,416
< system.cpu.kern.mode_ticks::kernel 47043056000 2.44% 2.44% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 5370301500 0.28% 2.72% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1874007320500 97.28% 100.00% # number of ticks spent at the given mode
---
> system.cpu.kern.mode_ticks::kernel 47043334000 2.44% 2.44% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 5370278500 0.28% 2.72% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1874007289500 97.28% 100.00% # number of ticks spent at the given mode
433,434c433,434
< system.cpu.num_idle_cycles 3586642751.000138 # Number of idle cycles
< system.cpu.num_busy_cycles 266200076.999862 # Number of busy cycles
---
> system.cpu.num_idle_cycles 3586642761.000138 # Number of idle cycles
> system.cpu.num_busy_cycles 266200514.999862 # Number of busy cycles
477,478c477,478
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 1390811 # number of replacements
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 1390804 # number of replacements
480,482c480,482
< system.cpu.dcache.tags.total_refs 14051752 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1391323 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 10.099561 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 14051759 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1391316 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 10.099617 # Average number of references to valid blocks.
492,500c492,500
< system.cpu.dcache.tags.tag_accesses 63163628 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63163628 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 7815905 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7815905 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5853570 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5853570 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 183002 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 183002 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.tag_accesses 63163621 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63163621 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 7815914 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7815914 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5853567 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5853567 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 183003 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 183003 # number of LoadLockedReq hits
503,526c503,526
< system.cpu.dcache.demand_hits::cpu.data 13669475 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13669475 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13669475 # number of overall hits
< system.cpu.dcache.overall_hits::total 13669475 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1069743 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1069743 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 304319 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 304319 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 17279 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17279 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1374062 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1374062 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1374062 # number of overall misses
< system.cpu.dcache.overall_misses::total 1374062 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050586500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 33050586500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442150000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 13442150000 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232520000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 232520000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 46492736500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 46492736500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 46492736500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 46492736500 # number of overall miss cycles
---
> system.cpu.dcache.demand_hits::cpu.data 13669481 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13669481 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13669481 # number of overall hits
> system.cpu.dcache.overall_hits::total 13669481 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1069734 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1069734 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 304322 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 304322 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 17278 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17278 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1374056 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1374056 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1374056 # number of overall misses
> system.cpu.dcache.overall_misses::total 1374056 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050329500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 33050329500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442227500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 13442227500 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 46492557000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 46492557000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 46492557000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 46492557000 # number of overall miss cycles
539,544c539,544
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120390 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.120390 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049419 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.049419 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086274 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086274 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120389 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.120389 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049420 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.049420 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086269 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086269 # miss rate for LoadLockedReq accesses
549,558c549,558
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.819370 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.819370 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.247934 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.247934 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.797268 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.797268 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 33835.981564 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 33835.981564 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.839059 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.839059 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.067159 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.067159 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.823706 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.823706 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 33835.998678 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.998678 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 33835.998678 # average overall miss latency
565,576c565,576
< system.cpu.dcache.writebacks::writebacks 835205 # number of writebacks
< system.cpu.dcache.writebacks::total 835205 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069743 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1069743 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304319 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304319 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17279 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17279 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1374062 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1374062 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1374062 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1374062 # number of overall MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 835203 # number of writebacks
> system.cpu.dcache.writebacks::total 835203 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069734 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1069734 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304322 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304322 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17278 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17278 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1374056 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1374056 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1374056 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1374056 # number of overall MSHR misses
583,592c583,592
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980843500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980843500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137831000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137831000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215241000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215241000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118674500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 45118674500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118674500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 45118674500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980595500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980595500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137905500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137905500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215229000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215229000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118501000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 45118501000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118501000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 45118501000 # number of overall MSHR miss cycles
597,602c597,602
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120390 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120390 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049419 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049419 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086274 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086274 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120389 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120389 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049420 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049420 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086269 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086269 # mshr miss rate for LoadLockedReq accesses
607,616c607,616
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.819370 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.819370 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.247934 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.247934 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.797268 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.797268 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.839059 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.839059 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.067159 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.067159 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.823706 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.823706 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.998678 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.998678 # average overall mshr miss latency
621,626c621,626
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 928683 # number of replacements
< system.cpu.icache.tags.tagsinuse 507.830404 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 55277502 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 929194 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 59.489732 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 928685 # number of replacements
> system.cpu.icache.tags.tagsinuse 507.830405 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 55277500 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 929196 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 59.489602 # Average number of references to valid blocks.
628c628
< system.cpu.icache.tags.occ_blocks::cpu.inst 507.830404 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 507.830405 # Average occupied blocks per requestor
637,657c637,657
< system.cpu.icache.tags.tag_accesses 57136210 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 57136210 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 55277502 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 55277502 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 55277502 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 55277502 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 55277502 # number of overall hits
< system.cpu.icache.overall_hits::total 55277502 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 929354 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 929354 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 929354 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 929354 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 929354 # number of overall misses
< system.cpu.icache.overall_misses::total 929354 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 13309679000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 13309679000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 13309679000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 13309679000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 13309679000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 13309679000 # number of overall miss cycles
---
> system.cpu.icache.tags.tag_accesses 57136212 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 57136212 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 55277500 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 55277500 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 55277500 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 55277500 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 55277500 # number of overall hits
> system.cpu.icache.overall_hits::total 55277500 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 929356 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 929356 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 929356 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 929356 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 929356 # number of overall misses
> system.cpu.icache.overall_misses::total 929356 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 13310087000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 13310087000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 13310087000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 13310087000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 13310087000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 13310087000 # number of overall miss cycles
670,675c670,675
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.430800 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14321.430800 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14321.430800 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14321.430800 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.838994 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14321.838994 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.838994 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14321.838994 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.838994 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14321.838994 # average overall miss latency
682,695c682,695
< system.cpu.icache.writebacks::writebacks 928683 # number of writebacks
< system.cpu.icache.writebacks::total 928683 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929354 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 929354 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 929354 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 929354 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 929354 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 929354 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380325000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12380325000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12380325000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12380325000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12380325000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12380325000 # number of overall MSHR miss cycles
---
> system.cpu.icache.writebacks::writebacks 928685 # number of writebacks
> system.cpu.icache.writebacks::total 928685 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929356 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 929356 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 929356 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 929356 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 929356 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 929356 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380731000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12380731000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12380731000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12380731000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12380731000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12380731000 # number of overall MSHR miss cycles
702,708c702,708
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.430800 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.430800 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.430800 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.430800 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.430800 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.430800 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.838994 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.838994 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.838994 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.838994 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
710,711c710,711
< system.cpu.l2cache.tags.tagsinuse 65387.710851 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4236321 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 65387.710870 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4236311 # Total number of references to valid blocks.
713c713
< system.cpu.l2cache.tags.avg_refs 10.540236 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 10.540211 # Average number of references to valid blocks.
715,717c715,717
< system.cpu.l2cache.tags.occ_blocks::writebacks 234.658578 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 4730.574413 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477860 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 234.658565 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 4730.574877 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477428 # Average occupied blocks per requestor
728,734c728,734
< system.cpu.l2cache.tags.tag_accesses 37511490 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 37511490 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 835205 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 835205 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 928450 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 928450 # number of WritebackClean hits
---
> system.cpu.l2cache.tags.tag_accesses 37511410 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 37511410 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 835203 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 835203 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 928452 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 928452 # number of WritebackClean hits
737,748c737,748
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187485 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187485 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916136 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 916136 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815048 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 815048 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 916136 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1002533 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1918669 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 916136 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1002533 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1918669 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187488 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187488 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916138 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 916138 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815038 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 815038 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 916138 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1002526 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1918664 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 916138 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1002526 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1918664 # number of overall hits
765,780c765,780
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10709040500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 10709040500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1353538000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 1353538000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21993492000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 21993492000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1353538000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 32702532500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34056070500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1353538000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 32702532500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34056070500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 835205 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 835205 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 928450 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 928450 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10708900500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10708900500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1353922000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 1353922000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21993208500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 21993208500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1353922000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 32702109000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 34056031000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1353922000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 32702109000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 34056031000 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 835203 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 835203 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 928452 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 928452 # number of WritebackClean accesses(hits+misses)
783,794c783,794
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 304302 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304302 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929334 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 929334 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087022 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1087022 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 929334 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1391324 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2320658 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 929334 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1391324 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2320658 # number of overall (read+write) accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 304305 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304305 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929336 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 929336 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087012 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1087012 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 929336 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1391317 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2320653 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 929336 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1391317 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2320653 # number of overall (read+write) accesses
797,798c797,798
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383885 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383885 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383881 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383881 # miss rate for ReadExReq accesses
801,802c801,802
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250201 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250201 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250203 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250203 # miss rate for ReadSharedReq accesses
804c804
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.279440 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.279441 # miss rate for demand accesses
807c807
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.279440 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.279441 # miss rate for overall accesses
811,822c811,822
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91673.647671 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91673.647671 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102556.296409 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102556.296409 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80866.156324 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80866.156324 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102556.296409 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84113.398973 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 84718.911463 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102556.296409 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84113.398973 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 84718.911463 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91672.449215 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91672.449215 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102585.391726 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102585.391726 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80865.113945 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80865.113945 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102585.391726 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84112.309699 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 84718.813201 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102585.391726 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84112.309699 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 84718.813201 # average overall miss latency
853,864c853,864
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540870500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540870500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221558000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221558000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273752000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273752000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221558000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814622500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 30036180500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221558000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814622500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 30036180500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540730500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540730500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221942000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221942000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273468500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273468500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221942000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814199000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 30036141000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221942000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814199000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 30036141000 # number of overall MSHR miss cycles
871,872c871,872
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383881 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383881 # mshr miss rate for ReadExReq accesses
875,876c875,876
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250201 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250201 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250203 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250203 # mshr miss rate for ReadSharedReq accesses
878c878
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for demand accesses
881c881
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279441 # mshr miss rate for overall accesses
885,896c885,896
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81673.647671 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81673.647671 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92556.296409 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92556.296409 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70866.156324 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70866.156324 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81672.449215 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81672.449215 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92585.391726 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92585.391726 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70865.113945 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70865.113945 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92585.391726 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74112.309699 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.813201 # average overall mshr miss latency
901,903c901,903
< system.cpu.toL2Bus.snoop_filter.tot_requests 4640189 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319660 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1516 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 4640179 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319543 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
907c907
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
909c909
< system.cpu.toL2Bus.trans_dist::ReadResp 2023463 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2023455 # Transaction distribution
912,914c912,914
< system.cpu.toL2Bus.trans_dist::WritebackDirty 909458 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 928683 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 817750 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 909456 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 928685 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 817745 # Transaction distribution
917,920c917,920
< system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 929354 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087182 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 304305 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 304305 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 929356 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087173 # Transaction distribution
922,928c922,929
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787371 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206814 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 6994185 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913088 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142552484 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 261465572 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 336953 # Total snoops (count)
---
> system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787377 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206794 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 6994171 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913344 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142551908 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 261465252 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 336955 # Total snoops (count)
930,932c931,933
< system.cpu.toL2Bus.snoop_fanout::samples 2674053 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.030932 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 2674049 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.001078 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.032812 # Request fanout histogram
934,935c935,936
< system.cpu.toL2Bus.snoop_fanout::0 2671492 99.90% 99.90% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 2561 0.10% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2671167 99.89% 99.89% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 2882 0.11% 100.00% # Request fanout histogram
940,941c941,942
< system.cpu.toL2Bus.snoop_fanout::total 2674053 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4097099500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 2674049 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4097094500 # Layer occupancy (ticks)
943c944
< system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 293883 # Layer occupancy (ticks)
945c946
< system.cpu.toL2Bus.respLayer0.occupancy 1394031000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1394034000 # Layer occupancy (ticks)
947c948
< system.cpu.toL2Bus.respLayer1.occupancy 2098750500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2098740000 # Layer occupancy (ticks)
961c962
< system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
992c993
< system.iobus.reqLayer0.occupancy 5344500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer0.occupancy 5344000 # Layer occupancy (ticks)
1010c1011
< system.iobus.reqLayer27.occupancy 216215769 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 216206774 # Layer occupancy (ticks)
1016c1017
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1018c1019
< system.iocache.tags.tagsinuse 1.340614 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.342515 # Cycle average of tags in use
1023,1025c1024,1026
< system.iocache.tags.occ_blocks::tsunami.ide 1.340614 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.083788 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.083788 # Average percentage of cache occupancy
---
> system.iocache.tags.occ_blocks::tsunami.ide 1.342515 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.083907 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.083907 # Average percentage of cache occupancy
1031c1032
< system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1042,1047c1043,1048
< system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937126886 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4937126886 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 4958975769 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4958975769 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 4958975769 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4958975769 # number of overall miss cycles
---
> system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937049891 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4937049891 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 4958898774 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4958898774 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 4958898774 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4958898774 # number of overall miss cycles
1066,1071c1067,1072
< system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118818.032489 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118818.032489 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 118849.029814 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 118849.029814 # average overall miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118816.179510 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 118816.179510 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 118847.184518 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 118847.184518 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 118847.184518 # average overall miss latency
1090,1095c1091,1096
< system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857073994 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2857073994 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 2870272877 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2870272877 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 2870272877 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2870272877 # number of overall MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857005811 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2857005811 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 2870204694 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2870204694 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 2870204694 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2870204694 # number of overall MSHR miss cycles
1106,1111c1107,1112
< system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68759.000626 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68759.000626 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68757.359718 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68757.359718 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68788.608604 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 68788.608604 # average overall mshr miss latency
1113,1114c1114,1115
< system.membus.snoop_filter.hit_single_requests 378246 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.membus.snoop_filter.hit_single_requests 378172 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1118c1119
< system.membus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1130a1132
> system.membus.trans_dist::InvalidateResp 124 # Transaction distribution
1143c1145
< system.membus.snoops 431 # Total snoops (count)
---
> system.membus.snoops 555 # Total snoops (count)
1146,1147c1148,1149
< system.membus.snoop_fanout::mean 0.001416 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.037609 # Request fanout histogram
---
> system.membus.snoop_fanout::mean 0.001419 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.037638 # Request fanout histogram
1149,1150c1151,1152
< system.membus.snoop_fanout::0 459649 99.86% 99.86% # Request fanout histogram
< system.membus.snoop_fanout::1 652 0.14% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 459648 99.86% 99.86% # Request fanout histogram
> system.membus.snoop_fanout::1 653 0.14% 100.00% # Request fanout histogram
1156c1158
< system.membus.reqLayer0.occupancy 30124000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 30123500 # Layer occupancy (ticks)
1158c1160
< system.membus.reqLayer1.occupancy 1287045337 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1287046834 # Layer occupancy (ticks)
1160c1162
< system.membus.respLayer1.occupancy 2142987750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2142988500 # Layer occupancy (ticks)
1162c1164
< system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1022522 # Layer occupancy (ticks)
1164,1168c1166,1170
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
1200,1222c1202,1224
< system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
< system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
---
> system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states
> system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421638000 # Cumulative time (in ticks) in various power states