3,5c3,5
< sim_seconds 1.922415 # Number of seconds simulated
< sim_ticks 1922415409000 # Number of ticks simulated
< final_tick 1922415409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.926421 # Number of seconds simulated
> sim_ticks 1926421414000 # Number of ticks simulated
> final_tick 1926421414000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 933149 # Simulator instruction rate (inst/s)
< host_op_rate 933149 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 31931169584 # Simulator tick rate (ticks/s)
< host_mem_usage 334404 # Number of bytes of host memory used
< host_seconds 60.21 # Real time elapsed on the host
< sim_insts 56180200 # Number of instructions simulated
< sim_ops 56180200 # Number of ops (including micro ops) simulated
---
> host_inst_rate 779030 # Simulator instruction rate (inst/s)
> host_op_rate 779030 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 26705916367 # Simulator tick rate (ticks/s)
> host_mem_usage 331544 # Number of bytes of host memory used
> host_seconds 72.13 # Real time elapsed on the host
> sim_insts 56195014 # Number of instructions simulated
> sim_ops 56195014 # Number of ops (including micro ops) simulated
16,18c16,18
< system.physmem.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 844608 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24856576 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 844672 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24856896 # Number of bytes read from this memory
20,26c20,26
< system.physmem.bytes_read::total 25702144 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 844608 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 844608 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7408512 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7408512 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 13197 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388384 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25702528 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 844672 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 844672 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7408960 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7408960 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 13198 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388389 # Number of read requests responded to by this memory
28,53c28,53
< system.physmem.num_reads::total 401596 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 115758 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 115758 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 439347 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 12929867 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 13369714 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 439347 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 439347 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3853752 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3853752 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3853752 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 439347 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 12929867 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 17223466 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 401596 # Number of read requests accepted
< system.physmem.writeReqs 115758 # Number of write requests accepted
< system.physmem.readBursts 401596 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 115758 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25695616 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7407424 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25702144 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7408512 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_reads::total 401602 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 115765 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 115765 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 438467 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 12903146 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 13342111 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 438467 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 438467 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3845971 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3845971 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3845971 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 438467 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 12903146 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 17188081 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 401602 # Number of read requests accepted
> system.physmem.writeReqs 115765 # Number of write requests accepted
> system.physmem.readBursts 401602 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 115765 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25695552 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7408000 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25702528 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7408960 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue
56,62c56,62
< system.physmem.perBankRdBursts::0 25227 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25633 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25570 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25510 # Per bank write bursts
< system.physmem.perBankRdBursts::4 24963 # Per bank write bursts
< system.physmem.perBankRdBursts::5 24975 # Per bank write bursts
< system.physmem.perBankRdBursts::6 24200 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 25229 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25631 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25563 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25503 # Per bank write bursts
> system.physmem.perBankRdBursts::4 24978 # Per bank write bursts
> system.physmem.perBankRdBursts::5 24964 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24209 # Per bank write bursts
64,69c64,69
< system.physmem.perBankRdBursts::8 25179 # Per bank write bursts
< system.physmem.perBankRdBursts::9 24767 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25265 # Per bank write bursts
< system.physmem.perBankRdBursts::11 24877 # Per bank write bursts
< system.physmem.perBankRdBursts::12 24504 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25368 # Per bank write bursts
---
> system.physmem.perBankRdBursts::8 25180 # Per bank write bursts
> system.physmem.perBankRdBursts::9 24757 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25269 # Per bank write bursts
> system.physmem.perBankRdBursts::11 24873 # Per bank write bursts
> system.physmem.perBankRdBursts::12 24512 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25367 # Per bank write bursts
71,84c71,84
< system.physmem.perBankRdBursts::15 25347 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7623 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7643 # Per bank write bursts
< system.physmem.perBankWrBursts::2 7871 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7543 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7113 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6990 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6317 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6320 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7316 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6519 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7114 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6905 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7090 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 25349 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7626 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7640 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7866 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7539 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7128 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6982 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6324 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6321 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7317 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6511 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7117 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6900 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7101 # Per bank write bursts
87c87
< system.physmem.perBankWrBursts::15 7686 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 7687 # Per bank write bursts
89,90c89,90
< system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
< system.physmem.totGap 1922403535500 # Total gap between requests
---
> system.physmem.numWrRetry 65 # Number of times write queue was full causing retry
> system.physmem.totGap 1926409540500 # Total gap between requests
97c97
< system.physmem.readPktSize::6 401596 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 401602 # Read request sizes (log2)
104,105c104,105
< system.physmem.writePktSize::6 115758 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 401480 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 115765 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 401479 # What read queue length does an incoming req see
152,218c152,218
< system.physmem.wrQLenPdf::15 1798 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3043 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5632 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5708 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6464 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6441 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7460 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8593 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 6948 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 7656 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8317 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 7511 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6845 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6921 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6031 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5597 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5475 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5364 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 235 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 149 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 193 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 100 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 131 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 63 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 71 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 44 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 63567 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 520.758255 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 315.623593 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 415.134860 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14658 23.06% 23.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11541 18.16% 41.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4861 7.65% 48.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3298 5.19% 54.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2285 3.59% 57.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1919 3.02% 60.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1565 2.46% 63.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1066 1.68% 64.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 22374 35.20% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63567 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5112 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 78.539124 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2951.473216 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5109 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1555 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2761 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5433 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5447 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5972 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6087 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6885 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7936 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6558 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6936 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 7510 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 7184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6518 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6660 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5973 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5660 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 477 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 374 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 327 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 340 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 292 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 286 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 316 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 363 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 345 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 332 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 309 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 304 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 296 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 281 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 202 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 216 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 238 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 176 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 335 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 300 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 63474 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 521.529319 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 315.079750 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 415.298836 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14953 23.56% 23.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11433 18.01% 41.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4319 6.80% 48.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3083 4.86% 53.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3219 5.07% 58.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1509 2.38% 60.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1583 2.49% 63.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 998 1.57% 64.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 22377 35.25% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63474 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5049 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 79.519311 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2969.676150 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5046 99.94% 99.94% # Reads before turning the bus around for writes
222,273c222,258
< system.physmem.rdPerTurnAround::total 5112 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5112 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.641041 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.167929 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 21.759533 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 4475 87.54% 87.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 34 0.67% 88.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 11 0.22% 88.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 14 0.27% 88.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 223 4.36% 93.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 16 0.31% 93.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 14 0.27% 93.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 12 0.23% 93.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 3 0.06% 93.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 7 0.14% 94.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 5 0.10% 94.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 2 0.04% 94.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 12 0.23% 94.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 2 0.04% 94.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 3 0.06% 94.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 1 0.02% 94.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 33 0.65% 95.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 3 0.06% 95.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 18 0.35% 95.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 1 0.02% 95.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 174 3.40% 99.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 4 0.08% 99.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.02% 99.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 4 0.08% 99.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 2 0.04% 99.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 2 0.04% 99.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.02% 99.35% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 1 0.02% 99.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.02% 99.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 1 0.02% 99.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 4 0.08% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.02% 99.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 9 0.18% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 2 0.04% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 2 0.04% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::188-191 3 0.06% 99.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::196-199 1 0.02% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-211 1 0.02% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-227 5 0.10% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5112 # Writes before turning the bus around for reads
< system.physmem.totQLat 2082530750 # Total ticks spent queuing
< system.physmem.totMemAccLat 9610543250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2007470000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 5186.95 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5049 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5049 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.925332 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.952060 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 24.989890 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-23 4540 89.92% 89.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-31 33 0.65% 90.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-39 164 3.25% 93.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-47 7 0.14% 93.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-55 1 0.02% 93.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-63 14 0.28% 94.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-71 7 0.14% 94.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-79 4 0.08% 94.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-87 36 0.71% 95.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-95 2 0.04% 95.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-103 139 2.75% 97.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-111 18 0.36% 98.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-119 13 0.26% 98.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-127 3 0.06% 98.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-135 6 0.12% 98.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-143 6 0.12% 98.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-159 3 0.06% 98.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-167 2 0.04% 98.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-175 13 0.26% 99.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-183 4 0.08% 99.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-191 12 0.24% 99.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-199 10 0.20% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-215 1 0.02% 99.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::216-223 6 0.12% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5049 # Writes before turning the bus around for reads
> system.physmem.totQLat 6110965000 # Total ticks spent queuing
> system.physmem.totMemAccLat 13638958750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2007465000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 15220.60 # Average queueing delay per DRAM burst
275,276c260,261
< system.physmem.avgMemAccLat 23936.95 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 33970.60 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.34 # Average DRAM read bandwidth in MiByte/s
278c263
< system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 13.34 # Average system read bandwidth in MiByte/s
285,321c270,316
< system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing
< system.physmem.readRowHits 359878 # Number of row buffer hits during reads
< system.physmem.writeRowHits 93790 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes
< system.physmem.avgGap 3715837.77 # Average gap between requests
< system.physmem.pageHitRate 87.71 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 235297440 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 128386500 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1564461600 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 372081600 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 64706229855 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1096686028500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1289254932375 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.645215 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1824198256500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 34018076000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 245269080 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 133827375 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1567191600 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 377920080 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 65408106195 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1096070355750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1289365116960 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.702526 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1823171088500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 35045257750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing
> system.physmem.readRowHits 360227 # Number of row buffer hits during reads
> system.physmem.writeRowHits 93542 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.72 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes
> system.physmem.avgGap 3723487.47 # Average gap between requests
> system.physmem.pageHitRate 87.73 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 220840200 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 117379350 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1432076940 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 299763720 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 5519467200.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 5038358250 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 366301440 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 13030830420 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 6357713760 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 449603447400 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 481990669050 # Total energy per rank (pJ)
> system.physmem_0.averagePower 250.200016 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 1914256960750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 613825000 # Time in different power states
> system.physmem_0.memoryStateTime::REF 2347892000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 1869275563500 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 16556600250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 9050884750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 28576648500 # Time in different power states
> system.physmem_1.actEnergy 232364160 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 123504480 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1434583080 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 304451280 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 5706932400.000001 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 5157840510 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 361297920 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 13647845730 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 6595007040 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 449082638955 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 482651277075 # Total energy per rank (pJ)
> system.physmem_1.averagePower 250.542936 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 1914153639500 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 598128250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 2427510000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 1867054823500 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 17174624250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 9236704750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 29929623250 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
327,328c322,323
< system.cpu.dtb.read_hits 9064160 # DTB read hits
< system.cpu.dtb.read_misses 10312 # DTB read misses
---
> system.cpu.dtb.read_hits 9066536 # DTB read hits
> system.cpu.dtb.read_misses 10331 # DTB read misses
330,332c325,327
< system.cpu.dtb.read_accesses 728817 # DTB read accesses
< system.cpu.dtb.write_hits 6356116 # DTB write hits
< system.cpu.dtb.write_misses 1140 # DTB write misses
---
> system.cpu.dtb.read_accesses 728865 # DTB read accesses
> system.cpu.dtb.write_hits 6357492 # DTB write hits
> system.cpu.dtb.write_misses 1143 # DTB write misses
334,336c329,331
< system.cpu.dtb.write_accesses 291929 # DTB write accesses
< system.cpu.dtb.data_hits 15420276 # DTB hits
< system.cpu.dtb.data_misses 11452 # DTB misses
---
> system.cpu.dtb.write_accesses 291932 # DTB write accesses
> system.cpu.dtb.data_hits 15424028 # DTB hits
> system.cpu.dtb.data_misses 11474 # DTB misses
338,340c333,335
< system.cpu.dtb.data_accesses 1020746 # DTB accesses
< system.cpu.itb.fetch_hits 4973965 # ITB hits
< system.cpu.itb.fetch_misses 4997 # ITB misses
---
> system.cpu.dtb.data_accesses 1020797 # DTB accesses
> system.cpu.itb.fetch_hits 4975201 # ITB hits
> system.cpu.itb.fetch_misses 5010 # ITB misses
342c337
< system.cpu.itb.fetch_accesses 4978962 # ITB accesses
---
> system.cpu.itb.fetch_accesses 4980211 # ITB accesses
355,358c350,353
< system.cpu.numPwrStateTransitions 12754 # Number of power state transitions
< system.cpu.pwrStateClkGateDist::samples 6377 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::mean 281224726.046887 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 439034613.415905 # Distribution of time spent in the clock gated state
---
> system.cpu.numPwrStateTransitions 12758 # Number of power state transitions
> system.cpu.pwrStateClkGateDist::samples 6379 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::mean 281128919.188117 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 439406492.836173 # Distribution of time spent in the clock gated state
360c355
< system.cpu.pwrStateClkGateDist::1000-5e+10 6376 99.98% 100.00% # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::1000-5e+10 6378 99.98% 100.00% # Distribution of time spent in the clock gated state
363,366c358,361
< system.cpu.pwrStateClkGateDist::total 6377 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateResidencyTicks::ON 129045330999 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 1793370078001 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 3844830818 # number of cpu cycles simulated
---
> system.cpu.pwrStateClkGateDist::total 6379 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateResidencyTicks::ON 133100038499 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321375501 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 3852842828 # number of cpu cycles simulated
370,372c365,367
< system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211971 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 212049 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74911 40.89% 40.89% # number of times we switched to this ipl
374,377c369,372
< system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 106221 57.99% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::22 1934 1.06% 42.01% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 106246 57.99% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 183222 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73544 49.31% 49.31% # number of times we switched to this ipl from a different ipl
379,387c374,382
< system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1857710123500 96.63% 96.63% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 93945500 0.00% 96.64% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 769790000 0.04% 96.68% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 63840816000 3.32% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1922414675000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73544 49.31% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 149153 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1859428695000 96.52% 96.52% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 94503000 0.00% 96.53% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 772442000 0.04% 96.57% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 66125040000 3.43% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1926420680000 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl
390,391c385,386
< system.cpu.kern.ipl_used::31 0.692255 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814088 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.692205 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814056 # fraction of swpipl calls that actually changed the ipl
427c422
< system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed
---
> system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed
430,431c425,426
< system.cpu.kern.callpal::swpipl 175962 91.22% 93.41% # number of callpals executed
< system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175997 91.22% 93.41% # number of callpals executed
> system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed
436c431
< system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed
---
> system.cpu.kern.callpal::rti 5159 2.67% 99.64% # number of callpals executed
439,441c434,436
< system.cpu.kern.callpal::total 192906 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches
< system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
---
> system.cpu.kern.callpal::total 192947 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches
> system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
443,446c438,441
< system.cpu.kern.mode_good::kernel 1910
< system.cpu.kern.mode_good::user 1741
< system.cpu.kern.mode_good::idle 169
< system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_good::kernel 1908
> system.cpu.kern.mode_good::user 1738
> system.cpu.kern.mode_good::idle 170
> system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches
448,476c443,471
< system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 46528757000 2.42% 2.42% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 5244548000 0.27% 2.69% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1870641368000 97.31% 100.00% # number of ticks spent at the given mode
< system.cpu.kern.swap_context 4175 # number of times the context was actually changed
< system.cpu.committedInsts 56180200 # Number of instructions committed
< system.cpu.committedOps 56180200 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 52052716 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses
< system.cpu.num_func_calls 1483318 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 6468478 # number of instructions that are conditional controls
< system.cpu.num_int_insts 52052716 # number of integer instructions
< system.cpu.num_fp_insts 324259 # number of float instructions
< system.cpu.num_int_register_reads 71320481 # number of times the integer registers were read
< system.cpu.num_int_register_writes 38519316 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read
< system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written
< system.cpu.num_mem_refs 15472847 # number of memory refs
< system.cpu.num_load_insts 9100978 # Number of load instructions
< system.cpu.num_store_insts 6371869 # Number of store instructions
< system.cpu.num_idle_cycles 3586740156.000134 # Number of idle cycles
< system.cpu.num_busy_cycles 258090661.999866 # Number of busy cycles
< system.cpu.not_idle_fraction 0.067127 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.932873 # Percentage of idle cycles
< system.cpu.Branches 8422318 # Number of branches fetched
< system.cpu.op_class::No_OpClass 3200272 5.70% 5.70% # Class of executed instruction
< system.cpu.op_class::IntAlu 36230015 64.48% 70.17% # Class of executed instruction
< system.cpu.op_class::IntMult 60990 0.11% 70.28% # Class of executed instruction
---
> system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.391786 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 47043056000 2.44% 2.44% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 5370301500 0.28% 2.72% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1874007320500 97.28% 100.00% # number of ticks spent at the given mode
> system.cpu.kern.swap_context 4178 # number of times the context was actually changed
> system.cpu.committedInsts 56195014 # Number of instructions committed
> system.cpu.committedOps 56195014 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 52066552 # Number of integer alu accesses
> system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
> system.cpu.num_func_calls 1483758 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 6469897 # number of instructions that are conditional controls
> system.cpu.num_int_insts 52066552 # number of integer instructions
> system.cpu.num_fp_insts 324460 # number of float instructions
> system.cpu.num_int_register_reads 71340789 # number of times the integer registers were read
> system.cpu.num_int_register_writes 38530081 # number of times the integer registers were written
> system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
> system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
> system.cpu.num_mem_refs 15476659 # number of memory refs
> system.cpu.num_load_insts 9103400 # Number of load instructions
> system.cpu.num_store_insts 6373259 # Number of store instructions
> system.cpu.num_idle_cycles 3586642751.000138 # Number of idle cycles
> system.cpu.num_busy_cycles 266200076.999862 # Number of busy cycles
> system.cpu.not_idle_fraction 0.069092 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.930908 # Percentage of idle cycles
> system.cpu.Branches 8424278 # Number of branches fetched
> system.cpu.op_class::No_OpClass 3201027 5.70% 5.70% # Class of executed instruction
> system.cpu.op_class::IntAlu 36239709 64.48% 70.17% # Class of executed instruction
> system.cpu.op_class::IntMult 61024 0.11% 70.28% # Class of executed instruction
478c473
< system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction
---
> system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction
504,506c499,501
< system.cpu.op_class::MemRead 9328048 16.60% 86.95% # Class of executed instruction
< system.cpu.op_class::MemWrite 6377943 11.35% 98.30% # Class of executed instruction
< system.cpu.op_class::IprAccess 953034 1.70% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 9330523 16.60% 86.95% # Class of executed instruction
> system.cpu.op_class::MemWrite 6379338 11.35% 98.30% # Class of executed instruction
> system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction
508,518c503,513
< system.cpu.op_class::total 56192019 # Class of executed instruction
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 1390892 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.977567 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 14047886 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1391404 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 10.096195 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.977567 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999956 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999956 # Average percentage of cache occupancy
---
> system.cpu.op_class::total 56206855 # Class of executed instruction
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 1390811 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.976541 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 14051752 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1391323 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 10.099561 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 121311500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.976541 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999954 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999954 # Average percentage of cache occupancy
521,522c516,517
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
524,540c519,535
< system.cpu.dcache.tags.tag_accesses 63148569 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63148569 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 7813455 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7813455 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5852226 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5852226 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 182968 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 182968 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 199220 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 199220 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 13665681 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13665681 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13665681 # number of overall hits
< system.cpu.dcache.overall_hits::total 13665681 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1069828 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1069828 # number of ReadReq misses
---
> system.cpu.dcache.tags.tag_accesses 63163628 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63163628 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 7815905 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7815905 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5853570 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5853570 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 183002 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 183002 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 199258 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 199258 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 13669475 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13669475 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13669475 # number of overall hits
> system.cpu.dcache.overall_hits::total 13669475 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1069743 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1069743 # number of ReadReq misses
543,590c538,585
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 17275 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17275 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1374147 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1374147 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1374147 # number of overall misses
< system.cpu.dcache.overall_misses::total 1374147 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 30980928500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 30980928500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 11763694500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 11763694500 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230325000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 230325000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 42744623000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 42744623000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 42744623000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 42744623000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 8883283 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 8883283 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6156545 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6156545 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 199220 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 199220 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15039828 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15039828 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15039828 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15039828 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120432 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.120432 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049430 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.049430 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086270 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086270 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.091367 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.091367 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.091367 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.091367 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.793843 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.793843 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38655.800328 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38655.800328 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13332.850941 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13332.850941 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 31106.295760 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 31106.295760 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 31106.295760 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 31106.295760 # average overall miss latency
---
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 17279 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17279 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1374062 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1374062 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1374062 # number of overall misses
> system.cpu.dcache.overall_misses::total 1374062 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050586500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 33050586500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442150000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 13442150000 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232520000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 232520000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 46492736500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 46492736500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 46492736500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 46492736500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 8885648 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 8885648 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6157889 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6157889 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200281 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200281 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 199258 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 199258 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15043537 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15043537 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15043537 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15043537 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120390 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.120390 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049419 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.049419 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086274 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086274 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.091339 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.091339 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.091339 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.091339 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.819370 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.819370 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.247934 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.247934 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.797268 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.797268 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 33835.981564 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 33835.981564 # average overall miss latency
597,600c592,595
< system.cpu.dcache.writebacks::writebacks 835265 # number of writebacks
< system.cpu.dcache.writebacks::total 835265 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069828 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1069828 # number of ReadReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 835205 # number of writebacks
> system.cpu.dcache.writebacks::total 835205 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069743 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1069743 # number of ReadReq MSHR misses
603,608c598,603
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17275 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17275 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1374147 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1374147 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1374147 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1374147 # number of overall MSHR misses
---
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17279 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17279 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1374062 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1374062 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1374062 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1374062 # number of overall MSHR misses
611,662c606,657
< system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses
< system.cpu.dcache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29911100500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 29911100500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11459375500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11459375500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 213050000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 213050000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41370476000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 41370476000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41370476000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 41370476000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533911000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533911000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533911000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533911000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120432 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120432 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049430 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049430 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086270 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086270 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091367 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.091367 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091367 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.091367 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27958.793843 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27958.793843 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37655.800328 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37655.800328 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12332.850941 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12332.850941 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.295760 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.295760 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.295760 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.295760 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.578644 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.578644 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92515.741858 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92515.741858 # average overall mshr uncacheable latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 928034 # number of replacements
< system.cpu.icache.tags.tagsinuse 508.064469 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 55263315 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 928545 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 59.516033 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 42160205500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 508.064469 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.992313 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.992313 # Average percentage of cache occupancy
---
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980843500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980843500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137831000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137831000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215241000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215241000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118674500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 45118674500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118674500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 45118674500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533908500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533908500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533908500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533908500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120390 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120390 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049419 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049419 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086274 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086274 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.091339 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091339 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.091339 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29895.819370 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29895.819370 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.247934 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.247934 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.797268 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.797268 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.217893 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.217893 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92504.432517 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92504.432517 # average overall mshr uncacheable latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 928683 # number of replacements
> system.cpu.icache.tags.tagsinuse 507.830404 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 55277502 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 929194 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 59.489732 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 44439092500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 507.830404 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.991856 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.991856 # Average percentage of cache occupancy
669,707c664,702
< system.cpu.icache.tags.tag_accesses 57120725 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 57120725 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 55263315 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 55263315 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 55263315 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 55263315 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 55263315 # number of overall hits
< system.cpu.icache.overall_hits::total 55263315 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 928705 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 928705 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 928705 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 928705 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 928705 # number of overall misses
< system.cpu.icache.overall_misses::total 928705 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 13023819500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 13023819500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 13023819500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 13023819500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 13023819500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 13023819500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 56192020 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 56192020 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 56192020 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 56192020 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 56192020 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 56192020 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016527 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.016527 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.016527 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.016527 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.016527 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.016527 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14023.634523 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14023.634523 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14023.634523 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14023.634523 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14023.634523 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14023.634523 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 57136210 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 57136210 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 55277502 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 55277502 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 55277502 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 55277502 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 55277502 # number of overall hits
> system.cpu.icache.overall_hits::total 55277502 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 929354 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 929354 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 929354 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 929354 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 929354 # number of overall misses
> system.cpu.icache.overall_misses::total 929354 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 13309679000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 13309679000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 13309679000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 13309679000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 13309679000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 13309679000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 56206856 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 56206856 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 56206856 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 56206856 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 56206856 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 56206856 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016535 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.016535 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.016535 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.016535 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.016535 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.016535 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14321.430800 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14321.430800 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14321.430800 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14321.430800 # average overall miss latency
714,753c709,748
< system.cpu.icache.writebacks::writebacks 928034 # number of writebacks
< system.cpu.icache.writebacks::total 928034 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928705 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 928705 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 928705 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 928705 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 928705 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 928705 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12095114500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12095114500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12095114500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12095114500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12095114500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12095114500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016527 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.016527 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.016527 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13023.634523 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13023.634523 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13023.634523 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13023.634523 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13023.634523 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13023.634523 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 336391 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65395.484463 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4235202 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 401913 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 10.537609 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 7260348000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 235.775942 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 4738.507265 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 60421.201256 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.003598 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072304 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.921954 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.997856 # Average percentage of cache occupancy
---
> system.cpu.icache.writebacks::writebacks 928683 # number of writebacks
> system.cpu.icache.writebacks::total 928683 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929354 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 929354 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 929354 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 929354 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 929354 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 929354 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380325000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12380325000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12380325000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12380325000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12380325000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12380325000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016535 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.016535 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.016535 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.430800 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.430800 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.430800 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.430800 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.430800 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.430800 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 336397 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65387.710851 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4236321 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 401919 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 10.540236 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 7724199000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 234.658578 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 4730.574413 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 60422.477860 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.003581 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072183 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.921974 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.997737 # Average percentage of cache occupancy
757,758c752,753
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4753 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59867 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4685 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59935 # Occupied blocks per task id
760,766c755,761
< system.cpu.l2cache.tags.tag_accesses 37502484 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 37502484 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 835265 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 835265 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 927811 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 927811 # number of WritebackClean hits
---
> system.cpu.l2cache.tags.tag_accesses 37511490 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 37511490 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 835205 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 835205 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 928450 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 928450 # number of WritebackClean hits
769,780c764,775
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187491 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187491 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 915488 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 915488 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815128 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 815128 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 915488 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1002619 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1918107 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 915488 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1002619 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1918107 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187485 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187485 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916136 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 916136 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815048 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 815048 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 916136 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1002533 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1918669 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 916136 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1002533 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1918669 # number of overall hits
783,794c778,789
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116811 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116811 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13197 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 13197 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271975 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 271975 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 13197 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 388786 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 401983 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 13197 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 388786 # number of overall misses
< system.cpu.l2cache.overall_misses::total 401983 # number of overall misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116817 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116817 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13198 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 13198 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271974 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 271974 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 13198 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 388791 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 401989 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 13198 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses
> system.cpu.l2cache.overall_misses::total 401989 # number of overall misses
797,812c792,807
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9030572500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9030572500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1076146500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 1076146500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19920583000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 19920583000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1076146500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 28951155500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 30027302000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1076146500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 28951155500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 30027302000 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 835265 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 835265 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 927811 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 927811 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10709040500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10709040500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1353538000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 1353538000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21993492000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 21993492000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1353538000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 32702532500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 34056070500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1353538000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 32702532500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 34056070500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 835205 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 835205 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 928450 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 928450 # number of WritebackClean accesses(hits+misses)
817,826c812,821
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 928685 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 928685 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087103 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 1087103 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 928685 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1391405 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2320090 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 928685 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1391405 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2320090 # number of overall (read+write) accesses
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929334 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 929334 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087022 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 1087022 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 929334 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1391324 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2320658 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 929334 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1391324 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2320658 # number of overall (read+write) accesses
829,840c824,835
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383865 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383865 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014210 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014210 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250183 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250183 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014210 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.279420 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.173262 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014210 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.279420 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.173262 # miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383885 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383885 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014202 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014202 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250201 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250201 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014202 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.279440 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.173222 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014202 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.279440 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.173222 # miss rate for overall accesses
843,854c838,849
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77309.264538 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77309.264538 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81544.782905 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81544.782905 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73244.169501 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73244.169501 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81544.782905 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74465.529880 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74697.939963 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81544.782905 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74465.529880 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74697.939963 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91673.647671 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91673.647671 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102556.296409 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102556.296409 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80866.156324 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80866.156324 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102556.296409 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84113.398973 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 84718.911463 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102556.296409 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84113.398973 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 84718.911463 # average overall miss latency
861,862c856,857
< system.cpu.l2cache.writebacks::writebacks 74246 # number of writebacks
< system.cpu.l2cache.writebacks::total 74246 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 74253 # number of writebacks
> system.cpu.l2cache.writebacks::total 74253 # number of writebacks
865,876c860,871
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116811 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116811 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13197 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13197 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271975 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271975 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 13197 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 388786 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 401983 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 13197 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 388786 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 401983 # number of overall MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116817 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116817 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13198 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13198 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271974 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271974 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 13198 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 388791 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 401989 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 13198 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 388791 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 401989 # number of overall MSHR misses
879,882c874,877
< system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses
---
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses
885,900c880,895
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7862462500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7862462500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 944176500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 944176500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17200833000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17200833000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 944176500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25063295500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26007472000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 944176500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25063295500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26007472000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447255500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447255500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447255500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447255500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540870500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540870500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221558000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221558000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273752000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273752000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221558000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814622500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 30036180500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221558000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814622500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 30036180500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447252500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447252500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447252500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447252500 # number of overall MSHR uncacheable cycles
903,914c898,909
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383865 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383865 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014210 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250183 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250183 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279420 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.173262 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279420 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.173262 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014202 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250201 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250201 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.173222 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.173222 # mshr miss rate for overall accesses
917,935c912,930
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67309.264538 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67309.264538 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71544.782905 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71544.782905 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63244.169501 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63244.169501 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71544.782905 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64465.529880 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64697.939963 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71544.782905 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64465.529880 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64697.939963 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208839.177489 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208839.177489 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87289.234017 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87289.234017 # average overall mshr uncacheable latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 4639053 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319092 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81673.647671 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81673.647671 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92556.296409 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92556.296409 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70866.156324 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70866.156324 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907 # average overall mshr uncacheable latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 4640189 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319660 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1516 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
939c934
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
941,946c936,941
< system.cpu.toL2Bus.trans_dist::ReadResp 2022895 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 909511 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 928034 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 817772 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2023463 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 9652 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 9652 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 909458 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 928683 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 817750 # Transaction distribution
951,952c946,947
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 928705 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087263 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 929354 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087182 # Transaction distribution
954,964c949,959
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2785424 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4207053 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 6992477 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118830016 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142561492 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 261391508 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 336947 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 4763072 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 2673477 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.000954 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.030869 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787371 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206814 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 6994185 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913088 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142552484 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 261465572 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 336953 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 4763520 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 2674053 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.030932 # Request fanout histogram
966,967c961,962
< system.cpu.toL2Bus.snoop_fanout::0 2670927 99.90% 99.90% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 2550 0.10% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2671492 99.90% 99.90% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 2561 0.10% 100.00% # Request fanout histogram
972,973c967,968
< system.cpu.toL2Bus.snoop_fanout::total 2673477 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 4095940500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 2674053 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 4097099500 # Layer occupancy (ticks)
977c972
< system.cpu.toL2Bus.respLayer0.occupancy 1393057500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1394031000 # Layer occupancy (ticks)
979c974
< system.cpu.toL2Bus.respLayer1.occupancy 2098871000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2098750500 # Layer occupancy (ticks)
993c988
< system.iobus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
996,998c991,993
< system.iobus.trans_dist::WriteReq 51202 # Transaction distribution
< system.iobus.trans_dist::WriteResp 51202 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::WriteReq 51204 # Transaction distribution
> system.iobus.trans_dist::WriteResp 51204 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5160 # Packet count per connected master and slave (bytes)
1007c1002
< system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 33164 # Packet count per connected master and slave (bytes)
1010,1011c1005,1006
< system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 116614 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20640 # Cumulative packet size per connected master and slave (bytes)
1020c1015
< system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 44580 # Cumulative packet size per connected master and slave (bytes)
1023,1024c1018,1019
< system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 5337500 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 2706188 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 5344500 # Layer occupancy (ticks)
1026c1021
< system.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 757500 # Layer occupancy (ticks)
1034c1029
< system.iobus.reqLayer23.occupancy 15814000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 15813000 # Layer occupancy (ticks)
1040c1035
< system.iobus.reqLayer26.occupancy 82000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks)
1042c1037
< system.iobus.reqLayer27.occupancy 216133054 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 216215769 # Layer occupancy (ticks)
1044c1039
< system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 23512000 # Layer occupancy (ticks)
1048c1043
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
1050c1045
< system.iocache.tags.tagsinuse 1.342865 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.340614 # Cycle average of tags in use
1054,1057c1049,1052
< system.iocache.tags.warmup_cycle 1756469369000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.342865 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.083929 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.083929 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1760392723000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.340614 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.083788 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.083788 # Average percentage of cache occupancy
1063c1058
< system.iocache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
1072,1079c1067,1074
< system.iocache.ReadReq_miss_latency::tsunami.ide 21758883 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21758883 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::tsunami.ide 4857806171 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4857806171 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 4879565054 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 4879565054 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 4879565054 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 4879565054 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21848883 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21848883 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937126886 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4937126886 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 4958975769 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 4958975769 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 4958975769 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 4958975769 # number of overall miss cycles
1096,1104c1091,1099
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125773.890173 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 125773.890173 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116909.081897 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 116909.081897 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 116945.837124 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 116945.837124 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 116945.837124 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 116945.837124 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 126294.121387 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118818.032489 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 118818.032489 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 118849.029814 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 118849.029814 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked
1106c1101
< system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
1108c1103
< system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 175 # average number of cycles each access was blocked
1120,1127c1115,1122
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13108883 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 13108883 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2777800981 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2777800981 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 2790909864 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 2790909864 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 2790909864 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 2790909864 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13198883 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 13198883 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857073994 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2857073994 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 2870272877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 2870272877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 2870272877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 2870272877 # number of overall MSHR miss cycles
1136,1145c1131,1140
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75773.890173 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 75773.890173 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66851.198041 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66851.198041 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66888.193265 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 66888.193265 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66888.193265 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 66888.193265 # average overall mshr miss latency
< system.membus.snoop_filter.tot_requests 821076 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 378187 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68759.000626 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68759.000626 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency
> system.membus.snoop_filter.tot_requests 821141 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 378246 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1150c1145
< system.membus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
1153,1156c1148,1151
< system.membus.trans_dist::WriteReq 9650 # Transaction distribution
< system.membus.trans_dist::WriteResp 9650 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 115758 # Transaction distribution
< system.membus.trans_dist::CleanEvict 261593 # Transaction distribution
---
> system.membus.trans_dist::WriteReq 9652 # Transaction distribution
> system.membus.trans_dist::WriteResp 9652 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 115765 # Transaction distribution
> system.membus.trans_dist::CleanEvict 261592 # Transaction distribution
1159,1160c1154,1155
< system.membus.trans_dist::ReadExReq 116680 # Transaction distribution
< system.membus.trans_dist::ReadExResp 116680 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 116686 # Transaction distribution
> system.membus.trans_dist::ReadExResp 116686 # Transaction distribution
1163,1165c1158,1160
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139235 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172395 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33164 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139253 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172417 # Packet count per connected master and slave (bytes)
1168,1171c1163,1166
< system.membus.pkt_count::total 1255820 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30452928 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30497492 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1255842 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44580 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30453760 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30498340 # Cumulative packet size per connected master and slave (bytes)
1174c1169
< system.membus.pkt_size::total 33155220 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 33156068 # Cumulative packet size per connected master and slave (bytes)
1177c1172
< system.membus.snoop_fanout::samples 460293 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 460301 # Request fanout histogram
1179c1174
< system.membus.snoop_fanout::stdev 0.037610 # Request fanout histogram
---
> system.membus.snoop_fanout::stdev 0.037609 # Request fanout histogram
1181c1176
< system.membus.snoop_fanout::0 459641 99.86% 99.86% # Request fanout histogram
---
> system.membus.snoop_fanout::0 459649 99.86% 99.86% # Request fanout histogram
1187,1188c1182,1183
< system.membus.snoop_fanout::total 460293 # Request fanout histogram
< system.membus.reqLayer0.occupancy 30118500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 460301 # Request fanout histogram
> system.membus.reqLayer0.occupancy 30124000 # Layer occupancy (ticks)
1190c1185
< system.membus.reqLayer1.occupancy 1286935040 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1287045337 # Layer occupancy (ticks)
1192c1187
< system.membus.respLayer1.occupancy 2142767250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2142987750 # Layer occupancy (ticks)
1196,1200c1191,1195
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
1232,1254c1227,1249
< system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
< system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states
---
> system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states
> system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states