7,11c7,11
< host_inst_rate 1255554 # Simulator instruction rate (inst/s)
< host_op_rate 1255553 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 43383023327 # Simulator tick rate (ticks/s)
< host_mem_usage 332188 # Number of bytes of host memory used
< host_seconds 44.75 # Real time elapsed on the host
---
> host_inst_rate 1048317 # Simulator instruction rate (inst/s)
> host_op_rate 1048317 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 36222399744 # Simulator tick rate (ticks/s)
> host_mem_usage 330588 # Number of bytes of host memory used
> host_seconds 53.59 # Real time elapsed on the host
563,564d562
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
595,598c593,594
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172486500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172486500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699465000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699465000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1526978500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 1526978500 # number of overall MSHR uncacheable cycles
621,625c617,618
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225058.168445 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225058.168445 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223087.800760 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223087.800760 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401 # average overall mshr uncacheable latency
685,686d677
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
713d703
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
834,835d823
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
874,877c862,863
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061396500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061396500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501719000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501719000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1440322500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1440322500 # number of overall MSHR uncacheable cycles
908,912c894,895
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213549.829069 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213549.829069 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211163.179159 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211163.179159 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927 # average overall mshr uncacheable latency
1043,1046c1026,1029
< system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
< system.iocache.demand_misses::total 173 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
< system.iocache.overall_misses::total 173 # number of overall misses
---
> system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
> system.iocache.overall_misses::total 41725 # number of overall misses
1051,1054c1034,1037
< system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21742883 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::tsunami.ide 5266456167 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 5266456167 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 5266456167 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 5266456167 # number of overall miss cycles
1059,1062c1042,1045
< system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
1075,1078c1058,1061
< system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126218.242469 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126218.242469 # average overall miss latency
1085,1086d1067
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1093,1096c1074,1077
< system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
1101,1104c1082,1085
< system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 13092883 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::tsunami.ide 3178407867 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3178407867 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 3178407867 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3178407867 # number of overall MSHR miss cycles
1117,1121c1098,1101
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency
< host_inst_rate 1255554 # Simulator instruction rate (inst/s)
< host_op_rate 1255553 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 43383023327 # Simulator tick rate (ticks/s)
< host_mem_usage 332188 # Number of bytes of host memory used
< host_seconds 44.75 # Real time elapsed on the host
---
> host_inst_rate 1048317 # Simulator instruction rate (inst/s)
> host_op_rate 1048317 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 36222399744 # Simulator tick rate (ticks/s)
> host_mem_usage 330588 # Number of bytes of host memory used
> host_seconds 53.59 # Real time elapsed on the host
563,564d562
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
595,598c593,594
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172486500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172486500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699465000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699465000 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1526978500 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 1526978500 # number of overall MSHR uncacheable cycles
621,625c617,618
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225058.168445 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225058.168445 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223087.800760 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223087.800760 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401 # average overall mshr uncacheable latency
685,686d677
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
713d703
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
834,835d823
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
874,877c862,863
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061396500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061396500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501719000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501719000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1440322500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1440322500 # number of overall MSHR uncacheable cycles
908,912c894,895
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213549.829069 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213549.829069 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211163.179159 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211163.179159 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927 # average overall mshr uncacheable latency
1043,1046c1026,1029
< system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
< system.iocache.demand_misses::total 173 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
< system.iocache.overall_misses::total 173 # number of overall misses
---
> system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
> system.iocache.overall_misses::total 41725 # number of overall misses
1051,1054c1034,1037
< system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21742883 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::tsunami.ide 5266456167 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 5266456167 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 5266456167 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 5266456167 # number of overall miss cycles
1059,1062c1042,1045
< system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
1075,1078c1058,1061
< system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126218.242469 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126218.242469 # average overall miss latency
1085,1086d1067
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1093,1096c1074,1077
< system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
1101,1104c1082,1085
< system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 13092883 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::tsunami.ide 3178407867 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3178407867 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 3178407867 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3178407867 # number of overall MSHR miss cycles
1117,1121c1098,1101
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency