3,5c3,5
< sim_seconds 1.920419 # Number of seconds simulated
< sim_ticks 1920418772000 # Number of ticks simulated
< final_tick 1920418772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.922414 # Number of seconds simulated
> sim_ticks 1922413663500 # Number of ticks simulated
> final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1235696 # Simulator instruction rate (inst/s)
< host_op_rate 1235696 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 42298287542 # Simulator tick rate (ticks/s)
< host_mem_usage 370580 # Number of bytes of host memory used
< host_seconds 45.40 # Real time elapsed on the host
< sim_insts 56102800 # Number of instructions simulated
< sim_ops 56102800 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1122927 # Simulator instruction rate (inst/s)
> host_op_rate 1122927 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 38428929684 # Simulator tick rate (ticks/s)
> host_mem_usage 370248 # Number of bytes of host memory used
> host_seconds 50.03 # Real time elapsed on the host
> sim_insts 56174594 # Number of instructions simulated
> sim_ops 56174594 # Number of ops (including micro ops) simulated
16,17c16,17
< system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory
19,25c19,25
< system.physmem.bytes_read::total 25709504 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7403648 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7403648 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388431 # Number of read requests responded to by this memory
27,53c27,53
< system.physmem.num_reads::total 401711 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 115682 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 115682 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 442903 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 12944043 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 13387447 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 442903 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 442903 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3855226 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3855226 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3855226 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 442903 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 12944043 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 17242673 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 401711 # Number of read requests accepted
< system.physmem.writeReqs 157234 # Number of write requests accepted
< system.physmem.readBursts 401711 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 157234 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25703040 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 6464 # Total number of bytes read from write queue
< system.physmem.bytesWritten 9922432 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25709504 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 10062976 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2169 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.num_reads::total 401737 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 442477 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 12931444 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 13374420 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 442477 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 442477 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3851591 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3851591 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3851591 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 442477 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 12931444 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 17226012 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 401737 # Number of read requests accepted
> system.physmem.writeReqs 157245 # Number of write requests accepted
> system.physmem.readBursts 401737 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 157245 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25705152 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8387264 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25711168 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 10063680 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 26167 # Number of DRAM write bursts merged with an existing one
55,57c55,57
< system.physmem.perBankRdBursts::0 25160 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25539 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25602 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 25230 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25660 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25603 # Per bank write bursts
59,86c59,86
< system.physmem.perBankRdBursts::4 24974 # Per bank write bursts
< system.physmem.perBankRdBursts::5 24969 # Per bank write bursts
< system.physmem.perBankRdBursts::6 24210 # Per bank write bursts
< system.physmem.perBankRdBursts::7 24487 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25140 # Per bank write bursts
< system.physmem.perBankRdBursts::9 24800 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25360 # Per bank write bursts
< system.physmem.perBankRdBursts::11 24834 # Per bank write bursts
< system.physmem.perBankRdBursts::12 24395 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25368 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25772 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25477 # Per bank write bursts
< system.physmem.perBankWrBursts::0 10048 # Per bank write bursts
< system.physmem.perBankWrBursts::1 9910 # Per bank write bursts
< system.physmem.perBankWrBursts::2 10442 # Per bank write bursts
< system.physmem.perBankWrBursts::3 9959 # Per bank write bursts
< system.physmem.perBankWrBursts::4 9552 # Per bank write bursts
< system.physmem.perBankWrBursts::5 9342 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8789 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8561 # Per bank write bursts
< system.physmem.perBankWrBursts::8 9905 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8742 # Per bank write bursts
< system.physmem.perBankWrBursts::10 9526 # Per bank write bursts
< system.physmem.perBankWrBursts::11 9262 # Per bank write bursts
< system.physmem.perBankWrBursts::12 9811 # Per bank write bursts
< system.physmem.perBankWrBursts::13 10568 # Per bank write bursts
< system.physmem.perBankWrBursts::14 10305 # Per bank write bursts
< system.physmem.perBankWrBursts::15 10316 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 24970 # Per bank write bursts
> system.physmem.perBankRdBursts::5 24976 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24206 # Per bank write bursts
> system.physmem.perBankRdBursts::7 24492 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25173 # Per bank write bursts
> system.physmem.perBankRdBursts::9 24777 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25267 # Per bank write bursts
> system.physmem.perBankRdBursts::11 24875 # Per bank write bursts
> system.physmem.perBankRdBursts::12 24505 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25378 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25651 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25357 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8677 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8490 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8972 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8549 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8030 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7962 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7256 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7133 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8241 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7447 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7887 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7738 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8187 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8962 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8876 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8644 # Per bank write bursts
88,89c88,89
< system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
< system.physmem.totGap 1920406851000 # Total gap between requests
---
> system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
> system.physmem.totGap 1922401791500 # Total gap between requests
96c96
< system.physmem.readPktSize::6 401711 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 401737 # Read request sizes (log2)
103,104c103,104
< system.physmem.writePktSize::6 157234 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 401596 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 157245 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 401629 # What read queue length does an incoming req see
151,217c151,217
< system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 4336 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 7978 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 9053 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 9729 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 10585 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 11129 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 12018 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 11559 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 11623 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 10445 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9597 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 8159 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7669 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6479 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6050 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5940 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5895 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 361 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 365 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 246 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 254 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 229 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 216 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 135 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 66451 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 536.116417 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 326.833533 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 417.088244 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 15015 22.60% 22.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11499 17.30% 39.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4712 7.09% 46.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3144 4.73% 51.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3072 4.62% 56.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1860 2.80% 59.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1297 1.95% 61.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1463 2.20% 63.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 24389 36.70% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 66451 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5539 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 72.502618 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2835.834060 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5536 99.95% 99.95% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1447 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2050 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5797 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5431 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5499 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5256 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5198 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 5228 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 5522 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5548 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 6794 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5788 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6388 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7612 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6420 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5573 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1278 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 786 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1151 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 1489 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 1383 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 874 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1604 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 2104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1549 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1761 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1892 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1974 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1877 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 2468 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 2834 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 2127 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 1812 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 1264 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 1177 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 712 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 482 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 281 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 93 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 50 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 64754 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 526.491275 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 319.634857 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 416.364161 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14682 22.67% 22.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11626 17.95% 40.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5040 7.78% 48.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3263 5.04% 53.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2595 4.01% 57.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1540 2.38% 59.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1251 1.93% 61.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1707 2.64% 64.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 23050 35.60% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 64754 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 4707 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 85.326110 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 3076.141166 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 4704 99.94% 99.94% # Reads before turning the bus around for writes
221,261c221,266
< system.physmem.rdPerTurnAround::total 5539 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5539 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 27.990251 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 21.086567 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 34.704660 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-23 4497 81.19% 81.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-31 178 3.21% 84.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-39 301 5.43% 89.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-47 51 0.92% 90.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-55 99 1.79% 92.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-63 47 0.85% 93.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-71 17 0.31% 93.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-79 11 0.20% 93.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-87 12 0.22% 94.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-95 4 0.07% 94.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-103 17 0.31% 94.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-111 7 0.13% 94.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-119 14 0.25% 94.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-127 6 0.11% 94.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-135 9 0.16% 95.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-143 38 0.69% 95.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-151 16 0.29% 96.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-159 19 0.34% 96.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-167 88 1.59% 98.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-175 43 0.78% 98.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-183 11 0.20% 99.03% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-191 20 0.36% 99.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-199 10 0.18% 99.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-207 3 0.05% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-215 3 0.05% 99.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::216-223 4 0.07% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-231 4 0.07% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::232-239 5 0.09% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::240-247 3 0.05% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5539 # Writes before turning the bus around for reads
< system.physmem.totQLat 2115529750 # Total ticks spent queuing
< system.physmem.totMemAccLat 9645717250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2008050000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 5267.62 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 4707 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 4707 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 27.841725 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.684188 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 62.214453 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 4459 94.73% 94.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 47 1.00% 95.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 10 0.21% 95.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 2 0.04% 95.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 12 0.25% 96.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 3 0.06% 96.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 7 0.15% 96.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 17 0.36% 96.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 21 0.45% 97.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 12 0.25% 97.51% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 17 0.36% 97.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-223 2 0.04% 97.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-239 5 0.11% 98.02% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-255 3 0.06% 98.09% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-287 1 0.02% 98.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-303 2 0.04% 98.15% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::304-319 4 0.08% 98.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-335 11 0.23% 98.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 21 0.45% 98.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 6 0.13% 99.04% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::368-383 6 0.13% 99.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-399 6 0.13% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::448-463 1 0.02% 99.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::464-479 8 0.17% 99.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-495 2 0.04% 99.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::496-511 2 0.04% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-527 5 0.11% 99.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 2 0.04% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::544-559 3 0.06% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::560-575 1 0.02% 99.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::640-655 1 0.02% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::672-687 3 0.06% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::688-703 1 0.02% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::720-735 2 0.04% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::800-815 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::832-847 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 4707 # Writes before turning the bus around for reads
> system.physmem.totQLat 2057087750 # Total ticks spent queuing
> system.physmem.totMemAccLat 9587894000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2008215000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 5121.68 # Average queueing delay per DRAM burst
263,267c268,272
< system.physmem.avgMemAccLat 24017.62 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 23871.68 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 4.36 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 5.23 # Average system write bandwidth in MiByte/s
271c276
< system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
---
> system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
273,290c278,295
< system.physmem.avgWrQLen 25.84 # Average write queue length when enqueuing
< system.physmem.readRowHits 359951 # Number of row buffer hits during reads
< system.physmem.writeRowHits 130246 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 83.99 # Row buffer hit rate for writes
< system.physmem.avgGap 3435770.69 # Average gap between requests
< system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 245601720 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 134008875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 1563619200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 496387440 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 64124070615 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1096000726500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1287996669870 # Total energy per rank (pJ)
< system.physmem_0.averagePower 670.686102 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1823056528000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 64126920000 # Time in different power states
---
> system.physmem.avgWrQLen 25.61 # Average write queue length when enqueuing
> system.physmem.readRowHits 360176 # Number of row buffer hits during reads
> system.physmem.writeRowHits 107764 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 82.21 # Row buffer hit rate for writes
> system.physmem.avgGap 3439112.16 # Average gap between requests
> system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 240309720 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 131121375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1565148000 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 421647120 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 64744742475 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1096652245500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1289317661070 # Total energy per rank (pJ)
> system.physmem_0.averagePower 670.677845 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1824141880650 # Time in different power states
> system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states
292c297
< system.physmem_0.memoryStateTime::ACT 33233084500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 34074451850 # Time in different power states
294,304c299,309
< system.physmem_1.actEnergy 256767840 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 140101500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 1568938800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 508258800 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 64541926215 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1095634186500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1288082435175 # Total energy per rank (pJ)
< system.physmem_1.averagePower 670.730762 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1822448681750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 64126920000 # Time in different power states
---
> system.physmem_1.actEnergy 249230520 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 135988875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 1567667400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 427563360 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 65411599725 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1096067283000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1289421779760 # Total energy per rank (pJ)
> system.physmem_1.averagePower 670.732006 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1823167298902 # Time in different power states
> system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states
306c311
< system.physmem_1.memoryStateTime::ACT 33840930750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 35049033598 # Time in different power states
313,314c318,319
< system.cpu.dtb.read_hits 9052701 # DTB read hits
< system.cpu.dtb.read_misses 10312 # DTB read misses
---
> system.cpu.dtb.read_hits 9063642 # DTB read hits
> system.cpu.dtb.read_misses 10324 # DTB read misses
316,318c321,323
< system.cpu.dtb.read_accesses 728817 # DTB read accesses
< system.cpu.dtb.write_hits 6349364 # DTB write hits
< system.cpu.dtb.write_misses 1140 # DTB write misses
---
> system.cpu.dtb.read_accesses 728853 # DTB read accesses
> system.cpu.dtb.write_hits 6355525 # DTB write hits
> system.cpu.dtb.write_misses 1142 # DTB write misses
320,322c325,327
< system.cpu.dtb.write_accesses 291929 # DTB write accesses
< system.cpu.dtb.data_hits 15402065 # DTB hits
< system.cpu.dtb.data_misses 11452 # DTB misses
---
> system.cpu.dtb.write_accesses 291931 # DTB write accesses
> system.cpu.dtb.data_hits 15419167 # DTB hits
> system.cpu.dtb.data_misses 11466 # DTB misses
324,326c329,331
< system.cpu.dtb.data_accesses 1020746 # DTB accesses
< system.cpu.itb.fetch_hits 4973977 # ITB hits
< system.cpu.itb.fetch_misses 4997 # ITB misses
---
> system.cpu.dtb.data_accesses 1020784 # DTB accesses
> system.cpu.itb.fetch_hits 4974414 # ITB hits
> system.cpu.itb.fetch_misses 5010 # ITB misses
328c333
< system.cpu.itb.fetch_accesses 4978974 # ITB accesses
---
> system.cpu.itb.fetch_accesses 4979424 # ITB accesses
341c346
< system.cpu.numCycles 3840837544 # number of cpu cycles simulated
---
> system.cpu.numCycles 3844827327 # number of cpu cycles simulated
344,396c349,401
< system.cpu.committedInsts 56102800 # Number of instructions committed
< system.cpu.committedOps 56102800 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 51978055 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses
< system.cpu.num_func_calls 1481300 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 6461124 # number of instructions that are conditional controls
< system.cpu.num_int_insts 51978055 # number of integer instructions
< system.cpu.num_fp_insts 324393 # number of float instructions
< system.cpu.num_int_register_reads 71208426 # number of times the integer registers were read
< system.cpu.num_int_register_writes 38459690 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read
< system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written
< system.cpu.num_mem_refs 15454652 # number of memory refs
< system.cpu.num_load_insts 9089529 # Number of load instructions
< system.cpu.num_store_insts 6365123 # Number of store instructions
< system.cpu.num_idle_cycles 3589204507.998131 # Number of idle cycles
< system.cpu.num_busy_cycles 251633036.001869 # Number of busy cycles
< system.cpu.not_idle_fraction 0.065515 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.934485 # Percentage of idle cycles
< system.cpu.Branches 8412940 # Number of branches fetched
< system.cpu.op_class::No_OpClass 3197536 5.70% 5.70% # Class of executed instruction
< system.cpu.op_class::IntAlu 36173540 64.46% 70.16% # Class of executed instruction
< system.cpu.op_class::IntMult 60992 0.11% 70.27% # Class of executed instruction
< system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction
< system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction
< system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction
< system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction
< system.cpu.op_class::MemRead 9316603 16.60% 86.95% # Class of executed instruction
< system.cpu.op_class::MemWrite 6371197 11.35% 98.30% # Class of executed instruction
< system.cpu.op_class::IprAccess 953030 1.70% 100.00% # Class of executed instruction
---
> system.cpu.committedInsts 56174594 # Number of instructions committed
> system.cpu.committedOps 56174594 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 52047018 # Number of integer alu accesses
> system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
> system.cpu.num_func_calls 1483106 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 6467546 # number of instructions that are conditional controls
> system.cpu.num_int_insts 52047018 # number of integer instructions
> system.cpu.num_fp_insts 324460 # number of float instructions
> system.cpu.num_int_register_reads 71310653 # number of times the integer registers were read
> system.cpu.num_int_register_writes 38515122 # number of times the integer registers were written
> system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
> system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
> system.cpu.num_mem_refs 15471782 # number of memory refs
> system.cpu.num_load_insts 9100493 # Number of load instructions
> system.cpu.num_store_insts 6371289 # Number of store instructions
> system.cpu.num_idle_cycles 3587399919.998134 # Number of idle cycles
> system.cpu.num_busy_cycles 257427407.001866 # Number of busy cycles
> system.cpu.not_idle_fraction 0.066954 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.933046 # Percentage of idle cycles
> system.cpu.Branches 8421188 # Number of branches fetched
> system.cpu.op_class::No_OpClass 3200330 5.70% 5.70% # Class of executed instruction
> system.cpu.op_class::IntAlu 36225212 64.47% 70.17% # Class of executed instruction
> system.cpu.op_class::IntMult 61016 0.11% 70.28% # Class of executed instruction
> system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction
> system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction
> system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction
> system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction
> system.cpu.op_class::MemRead 9327578 16.60% 86.95% # Class of executed instruction
> system.cpu.op_class::MemWrite 6377363 11.35% 98.30% # Class of executed instruction
> system.cpu.op_class::IprAccess 953205 1.70% 100.00% # Class of executed instruction
398c403
< system.cpu.op_class::total 56114619 # Class of executed instruction
---
> system.cpu.op_class::total 56186427 # Class of executed instruction
400,402c405,407
< system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 211965 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 211986 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl
405,407c410,412
< system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 183175 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::31 106213 57.99% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl
410,417c415,422
< system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1858230927500 96.76% 96.76% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 91348000 0.00% 96.77% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 737130000 0.04% 96.80% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 61358632500 3.20% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1920418038000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 149113 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1857939859000 96.65% 96.65% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 91692000 0.00% 96.65% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 740049500 0.04% 96.69% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 63641329000 3.31% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1922412929500 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl
420,421c425,426
< system.cpu.kern.ipl_used::31 0.692243 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814079 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.692241 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814078 # fraction of swpipl calls that actually changed the ipl
457,458c462,463
< system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed
< system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
---
> system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
> system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
460c465
< system.cpu.kern.callpal::swpipl 175954 91.22% 93.41% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175947 91.21% 93.41% # number of callpals executed
469,474c474,479
< system.cpu.kern.callpal::total 192900 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches
< system.cpu.kern.mode_switch::user 1743 # number of protection mode switches
< system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
< system.cpu.kern.mode_good::kernel 1913
< system.cpu.kern.mode_good::user 1743
---
> system.cpu.kern.callpal::total 192894 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches
> system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
> system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
> system.cpu.kern.mode_good::kernel 1910
> system.cpu.kern.mode_good::user 1740
476c481
< system.cpu.kern.mode_switch_good::kernel 0.324182 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_switch_good::kernel 0.323455 # fraction of useful protection mode switches
478,492c483,497
< system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.392732 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 46109911500 2.40% 2.40% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 5189208000 0.27% 2.67% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1869118916500 97.33% 100.00% # number of ticks spent at the given mode
< system.cpu.kern.swap_context 4177 # number of times the context was actually changed
< system.cpu.dcache.tags.replacements 1389979 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 14030604 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1390491 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 10.090395 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
---
> system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.392197 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 46428613000 2.42% 2.42% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 5237727500 0.27% 2.69% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1870746587000 97.31% 100.00% # number of ticks spent at the given mode
> system.cpu.kern.swap_context 4178 # number of times the context was actually changed
> system.cpu.dcache.tags.replacements 1391374 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.978196 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 14046325 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1391886 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 10.091577 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.978196 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy
498,563c503,568
< system.cpu.dcache.tags.tag_accesses 63074876 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63074876 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 7802731 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7802731 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5845607 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5845607 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 183026 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 183026 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 13648338 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13648338 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13648338 # number of overall hits
< system.cpu.dcache.overall_hits::total 13648338 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1069103 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1069103 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 304189 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 304189 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 17217 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17217 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1373292 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1373292 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1373292 # number of overall misses
< system.cpu.dcache.overall_misses::total 1373292 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 29000817500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 29000817500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906930630 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10906930630 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228178000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 228178000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 39907748130 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 39907748130 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 39907748130 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 39907748130 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 8871834 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 8871834 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6149796 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6149796 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15021630 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15021630 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15021630 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15021630 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120505 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.120505 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049463 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.049463 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085981 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085981 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.091421 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.091421 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.091421 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.091421 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27126.308223 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 27126.308223 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.769374 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.769374 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13253.063832 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13253.063832 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29059.914519 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 29059.914519 # average overall miss latency
---
> system.cpu.dcache.tags.tag_accesses 63144735 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63144735 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 7812525 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7812525 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5851580 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5851580 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 182969 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 182969 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 199234 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 199234 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 13664105 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13664105 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13664105 # number of overall hits
> system.cpu.dcache.overall_hits::total 13664105 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1070248 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1070248 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 304369 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 304369 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 17287 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17287 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1374617 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1374617 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1374617 # number of overall misses
> system.cpu.dcache.overall_misses::total 1374617 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 30897353500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 30897353500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 11699394130 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 11699394130 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229714500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 229714500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 42596747630 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 42596747630 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 42596747630 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 42596747630 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 8882773 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 8882773 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6155949 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6155949 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200256 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200256 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 199234 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 199234 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15038722 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15038722 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15038722 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15038722 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120486 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.120486 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049443 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.049443 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086325 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086325 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.091405 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.091405 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.091405 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.091405 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28869.340097 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 28869.340097 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38438.192227 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 38438.192227 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13288.280211 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13288.280211 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 30988.084412 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 30988.084412 # average overall miss latency
572,619c577,624
< system.cpu.dcache.writebacks::writebacks 834368 # number of writebacks
< system.cpu.dcache.writebacks::total 834368 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069103 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1069103 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304189 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304189 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17217 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17217 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1373292 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1373292 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1373292 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1373292 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26736955500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 26736955500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245884370 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245884370 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36982839870 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 36982839870 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36982839870 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 36982839870 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424272500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424272500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009399000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009399000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433671500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433671500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120505 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120505 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049463 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049463 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085981 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085981 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091421 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.091421 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091421 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.091421 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25008.774178 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25008.774178 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33682.626163 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33682.626163 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11252.366847 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11252.366847 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 835634 # number of writebacks
> system.cpu.dcache.writebacks::total 835634 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1070248 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1070248 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304369 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304369 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17287 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17287 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1374617 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11190140370 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 203771000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 203771000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40356234870 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 40356234870 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40356234870 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 40356234870 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1432759000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1432759000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2025445000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2025445000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3458204000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3458204000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120486 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120486 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086325 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086325 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.091405 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.091405 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27251.715957 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27251.715957 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36765.046276 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36765.046276 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11787.528200 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11787.528200 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
627,635c632,640
< system.cpu.icache.tags.replacements 927664 # number of replacements
< system.cpu.icache.tags.tagsinuse 508.305908 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 55186285 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 928175 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 59.456767 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 508.305908 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.992785 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.992785 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 928205 # number of replacements
> system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 55257552 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 928716 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 59.498869 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 42087191250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 508.070911 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.992326 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.992326 # Average percentage of cache occupancy
642,679c647,684
< system.cpu.icache.tags.tag_accesses 57042955 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 57042955 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 55186285 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 55186285 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 55186285 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 55186285 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 55186285 # number of overall hits
< system.cpu.icache.overall_hits::total 55186285 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 928335 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 928335 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 928335 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 928335 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 928335 # number of overall misses
< system.cpu.icache.overall_misses::total 928335 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12909899750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12909899750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12909899750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12909899750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12909899750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12909899750 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 56114620 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 56114620 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 56114620 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 56114620 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 56114620 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 56114620 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016544 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.016544 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.016544 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.016544 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.016544 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.016544 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13906.509773 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13906.509773 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13906.509773 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13906.509773 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 57115304 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 57115304 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 55257552 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 55257552 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 55257552 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 55257552 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 55257552 # number of overall hits
> system.cpu.icache.overall_hits::total 55257552 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 928876 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 928876 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 928876 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 928876 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 928876 # number of overall misses
> system.cpu.icache.overall_misses::total 928876 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 13004894000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 13004894000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 13004894000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 13004894000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 13004894000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 13004894000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 56186428 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 56186428 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 56186428 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 56186428 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 56186428 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 56186428 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14000.678239 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14000.678239 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14000.678239 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14000.678239 # average overall miss latency
688,711c693,716
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928335 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 928335 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 928335 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 928335 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 928335 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 928335 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048066250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 11048066250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048066250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 11048066250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11048066250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 11048066250 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016544 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.016544 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.016544 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11900.947664 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11900.947664 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11900.947664 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11900.947664 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11900.947664 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11900.947664 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928876 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 928876 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 928876 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 928876 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 928876 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 928876 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11606411000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 11606411000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11606411000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 11606411000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11606411000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 11606411000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12495.113449 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12495.113449 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency
713,725c718,730
< system.cpu.l2cache.tags.replacements 336225 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65295.018505 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2445535 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 401387 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.092711 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 55550.770505 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 4768.438466 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.809535 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.847637 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072761 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.075925 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996323 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.replacements 336253 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65287.674931 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2448546 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 401415 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.099787 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 7245222750 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 55515.781465 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 4753.205077 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5018.688389 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.847104 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072528 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.076579 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996211 # Average percentage of cache occupancy
727,731c732,736
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4873 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3256 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55781 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4937 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3234 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55805 # Occupied blocks per task id
733,739c738,744
< system.cpu.l2cache.tags.tag_accesses 25931322 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 25931322 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 915025 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 814362 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1729387 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 834368 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 834368 # number of Writeback hits
---
> system.cpu.l2cache.tags.tag_accesses 25957144 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 25957144 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 915565 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 815571 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1731136 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 835634 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 835634 # number of Writeback hits
742,752c747,757
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187334 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187334 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 915025 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1001696 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1916721 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 915025 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1001696 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1916721 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 271958 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 285248 # number of ReadReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187495 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187495 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 915565 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1003066 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1918631 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 915565 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1003066 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1918631 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 271964 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 285255 # number of ReadReq misses
755,780c760,785
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116838 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116838 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 388796 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 402086 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 388796 # number of overall misses
< system.cpu.l2cache.overall_misses::total 402086 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 969461250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17700747500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 18670208750 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8067922881 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8067922881 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 969461250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 25768670381 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 26738131631 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 969461250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 25768670381 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 26738131631 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 928315 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1086320 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2014635 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 834368 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 834368 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116857 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116857 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 13291 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 388821 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 402112 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 13291 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 388821 # number of overall misses
> system.cpu.l2cache.overall_misses::total 402112 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1064072500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19718835000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 20782907500 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 220998 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 220998 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8916531881 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8916531881 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1064072500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 28635366881 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 29699439381 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1064072500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 28635366881 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 29699439381 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 928856 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1087535 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2016391 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 835634 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 835634 # number of Writeback accesses(hits+misses)
783,793c788,798
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 928315 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1390492 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2318807 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 928315 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1390492 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2318807 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014316 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250348 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.141588 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 304352 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304352 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 928856 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1391887 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2320743 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 928856 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1391887 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2320743 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014309 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250074 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.141468 # miss rate for ReadReq accesses
796,816c801,821
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384118 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.384118 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014316 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.279610 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.173402 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014316 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.279610 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.173402 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72946.670429 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65086.327668 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 65452.549185 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69052.216582 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69052.216582 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72946.670429 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66278.126269 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 66498.539196 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72946.670429 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66278.126269 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 66498.539196 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383953 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.383953 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014309 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.279348 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.173269 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014309 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.279348 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.173269 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80059.626815 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72505.313203 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72857.294351 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16999.846154 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16999.846154 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76302.933337 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76302.933337 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80059.626815 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73646.657153 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73858.624913 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80059.626815 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73646.657153 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73858.624913 # average overall miss latency
825,829c830,834
< system.cpu.l2cache.writebacks::writebacks 74170 # number of writebacks
< system.cpu.l2cache.writebacks::total 74170 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271958 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 285248 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 74181 # number of writebacks
> system.cpu.l2cache.writebacks::total 74181 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271964 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses
832,861c837,866
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116838 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116838 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 388796 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 402086 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 388796 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 402086 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 802917750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14300848500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15103766250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607051619 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607051619 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802917750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20907900119 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 21710817869 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802917750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20907900119 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 21710817869 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334182500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334182500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893599000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893599000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227781500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227781500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250348 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141588 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116857 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116857 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 388821 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 402112 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23773879119 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 24671360619 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 897481500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23773879119 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 24671360619 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1335739000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1335739000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1899995000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1899995000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3235734000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3235734000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250074 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141468 # mshr miss rate for ReadReq accesses
864,884c869,889
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384118 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384118 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.173402 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.173402 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60415.180587 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52584.768604 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52949.595615 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56548.825031 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56548.825031 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383953 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383953 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.173269 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.173269 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency
892,893c897,898
< system.cpu.toL2Bus.trans_dist::ReadReq 2021758 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2021741 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution
896,897c901,902
< system.cpu.toL2Bus.trans_dist::Writeback 834368 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution
900,911c905,916
< system.cpu.toL2Bus.trans_dist::ReadExReq 304172 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 304172 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856650 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648702 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 5505352 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59412160 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142445588 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 201857748 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 41901 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3194937 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.013060 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.113530 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 41937 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3198175 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.013058 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.113522 # Request fanout histogram
914,915c919,920
< system.cpu.toL2Bus.snoop_fanout::1 3153212 98.69% 98.69% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 3156414 98.69% 98.69% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 41761 1.31% 100.00% # Request fanout histogram
919,920c924,925
< system.cpu.toL2Bus.snoop_fanout::total 3194937 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2424089000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 3198175 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks)
924c929
< system.cpu.toL2Bus.respLayer0.occupancy 1395084250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks)
926c931
< system.cpu.toL2Bus.respLayer1.occupancy 2186669630 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks)
999c1004
< system.iobus.reqLayer29.occupancy 406198788 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 242042219 # Layer occupancy (ticks)
1005c1010
< system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks)
1008c1013
< system.iocache.tags.tagsinuse 1.352284 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.342966 # Cycle average of tags in use
1012,1015c1017,1020
< system.iocache.tags.warmup_cycle 1753525494000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.352284 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1756462668000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.342966 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.083935 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.083935 # Average percentage of cache occupancy
1029,1036c1034,1041
< system.iocache.ReadReq_miss_latency::tsunami.ide 23338383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 23338383 # number of ReadReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635239905 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 13635239905 # number of WriteInvalidateReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 23338383 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 23338383 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 23338383 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 23338383 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8755465836 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 8755465836 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles
1053,1061c1058,1066
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 134903.947977 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 134903.947977 # average ReadReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328148.823282 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 328148.823282 # average WriteInvalidateReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 134903.947977 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 134903.947977 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 206255 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 72960 # number of cycles access was blocked
1063c1068
< system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 9989 # number of cycles access was blocked
1065c1070
< system.iocache.avg_blocked_cycles::no_mshrs 8.754085 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 7.304034 # average number of cycles each access was blocked
1079,1086c1084,1091
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14341383 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 14341383 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474535905 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474535905 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 14341383 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 14341383 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 14341383 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 14341383 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6594761836 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6594761836 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles
1095,1102c1100,1107
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 82898.167630 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276148.823282 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276148.823282 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
1104,1105c1109,1110
< system.membus.trans_dist::ReadReq 292351 # Transaction distribution
< system.membus.trans_dist::ReadResp 292351 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 292358 # Transaction distribution
> system.membus.trans_dist::ReadResp 292358 # Transaction distribution
1108c1113
< system.membus.trans_dist::Writeback 115682 # Transaction distribution
---
> system.membus.trans_dist::Writeback 115693 # Transaction distribution
1113,1114c1118,1119
< system.membus.trans_dist::ReadExReq 116719 # Transaction distribution
< system.membus.trans_dist::ReadExResp 116719 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 116738 # Transaction distribution
> system.membus.trans_dist::ReadExResp 116738 # Transaction distribution
1116,1117c1121,1122
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878095 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911255 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878158 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911318 # Packet count per connected master and slave (bytes)
1120c1125
< system.membus.pkt_count::total 1036059 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes)
1122,1123c1127,1128
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455424 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499988 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes)
1126c1131
< system.membus.pkt_size::total 35817044 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes)
1128c1133
< system.membus.snoop_fanout::samples 559506 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 559589 # Request fanout histogram
1133c1138
< system.membus.snoop_fanout::1 559506 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 559589 100.00% 100.00% # Request fanout histogram
1138,1139c1143,1144
< system.membus.snoop_fanout::total 559506 # Request fanout histogram
< system.membus.reqLayer0.occupancy 30371500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 559589 # Request fanout histogram
> system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks)
1141c1146
< system.membus.reqLayer1.occupancy 1824515500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks)
1143,1145c1148,1150
< system.membus.respLayer1.occupancy 3751827620 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
< system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2144408870 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
> system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks)