3,5c3,5
< sim_seconds 1.919439 # Number of seconds simulated
< sim_ticks 1919439025000 # Number of ticks simulated
< final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.920428 # Number of seconds simulated
> sim_ticks 1920427877000 # Number of ticks simulated
> final_tick 1920427877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1406989 # Simulator instruction rate (inst/s)
< host_op_rate 1406988 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 48137648137 # Simulator tick rate (ticks/s)
< host_mem_usage 309300 # Number of bytes of host memory used
< host_seconds 39.87 # Real time elapsed on the host
< sim_insts 56102180 # Number of instructions simulated
< sim_ops 56102180 # Number of ops (including micro ops) simulated
---
> host_inst_rate 694902 # Simulator instruction rate (inst/s)
> host_op_rate 694902 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 23785763794 # Simulator tick rate (ticks/s)
> host_mem_usage 317148 # Number of bytes of host memory used
> host_seconds 80.74 # Real time elapsed on the host
> sim_insts 56105324 # Number of instructions simulated
> sim_ops 56105324 # Number of ops (including micro ops) simulated
16,17c16,17
< system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 24858304 # Number of bytes read from this memory
19,26c19,25
< system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 4747520 # Number of bytes written to this memory
< system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7406848 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 388686 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 25710016 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7404096 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7404096 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 388411 # Number of read requests responded to by this memory
28,33c27,31
< system.physmem.num_reads::total 401995 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 74180 # Number of write requests responded to by this memory
< system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 115732 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 12959987 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::total 401719 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 115689 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 115689 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 443001 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 12944149 # Total read bandwidth from this memory (bytes/s)
35,58c33,55
< system.physmem.bw_read::total 13403750 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2473389 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::tsunami.ide 1385471 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3858861 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2473389 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 12959987 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 17262610 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 401995 # Number of read requests accepted
< system.physmem.writeReqs 115732 # Number of write requests accepted
< system.physmem.readBursts 401995 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 115732 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25715968 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7405120 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25727680 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7406848 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 25161 # Per bank write bursts
---
> system.physmem.bw_read::total 13387650 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 443001 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 443001 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3855441 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3855441 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3855441 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 443001 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 12944149 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 17243091 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 401719 # Number of read requests accepted
> system.physmem.writeReqs 157241 # Number of write requests accepted
> system.physmem.readBursts 401719 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 157241 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25703424 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9932992 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25710016 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 10063424 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2011 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 25160 # Per bank write bursts
60,89c57,86
< system.physmem.perBankRdBursts::2 25618 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25536 # Per bank write bursts
< system.physmem.perBankRdBursts::4 24982 # Per bank write bursts
< system.physmem.perBankRdBursts::5 24977 # Per bank write bursts
< system.physmem.perBankRdBursts::6 24228 # Per bank write bursts
< system.physmem.perBankRdBursts::7 24506 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25158 # Per bank write bursts
< system.physmem.perBankRdBursts::9 24823 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25363 # Per bank write bursts
< system.physmem.perBankRdBursts::11 24839 # Per bank write bursts
< system.physmem.perBankRdBursts::12 24418 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25388 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25795 # Per bank write bursts
< system.physmem.perBankRdBursts::15 25481 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7550 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7529 # Per bank write bursts
< system.physmem.perBankWrBursts::2 7880 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7553 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7115 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6983 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6321 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6315 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7293 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6555 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7205 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6861 # Per bank write bursts
< system.physmem.perBankWrBursts::12 6964 # Per bank write bursts
< system.physmem.perBankWrBursts::13 7821 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7980 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7780 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 25602 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25522 # Per bank write bursts
> system.physmem.perBankRdBursts::4 24974 # Per bank write bursts
> system.physmem.perBankRdBursts::5 24970 # Per bank write bursts
> system.physmem.perBankRdBursts::6 24210 # Per bank write bursts
> system.physmem.perBankRdBursts::7 24489 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25140 # Per bank write bursts
> system.physmem.perBankRdBursts::9 24800 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25361 # Per bank write bursts
> system.physmem.perBankRdBursts::11 24836 # Per bank write bursts
> system.physmem.perBankRdBursts::12 24395 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25368 # Per bank write bursts
> system.physmem.perBankRdBursts::14 25772 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25478 # Per bank write bursts
> system.physmem.perBankWrBursts::0 10040 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9905 # Per bank write bursts
> system.physmem.perBankWrBursts::2 10447 # Per bank write bursts
> system.physmem.perBankWrBursts::3 9982 # Per bank write bursts
> system.physmem.perBankWrBursts::4 9551 # Per bank write bursts
> system.physmem.perBankWrBursts::5 9392 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8805 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8555 # Per bank write bursts
> system.physmem.perBankWrBursts::8 9942 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8777 # Per bank write bursts
> system.physmem.perBankWrBursts::10 9524 # Per bank write bursts
> system.physmem.perBankWrBursts::11 9288 # Per bank write bursts
> system.physmem.perBankWrBursts::12 9847 # Per bank write bursts
> system.physmem.perBankWrBursts::13 10608 # Per bank write bursts
> system.physmem.perBankWrBursts::14 10278 # Per bank write bursts
> system.physmem.perBankWrBursts::15 10262 # Per bank write bursts
91,92c88,89
< system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
< system.physmem.totGap 1919427104000 # Total gap between requests
---
> system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
> system.physmem.totGap 1920415956000 # Total gap between requests
99c96
< system.physmem.readPktSize::6 401995 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 401719 # Read request sizes (log2)
106,107c103,104
< system.physmem.writePktSize::6 115732 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 401798 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 157241 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 401602 # What read queue length does an incoming req see
154,220c151,217
< system.physmem.wrQLenPdf::15 1803 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2465 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5623 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5839 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6566 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6884 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8073 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8473 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8504 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8199 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6888 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6495 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5617 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5359 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5332 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5312 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 177 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 216 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 208 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 201 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 197 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 132 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 112 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 63991 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 517.589786 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 312.394273 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 414.375602 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 15074 23.56% 23.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11584 18.10% 41.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4587 7.17% 48.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3091 4.83% 53.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3045 4.76% 58.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1807 2.82% 61.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1323 2.07% 63.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1474 2.30% 65.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 22006 34.39% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63991 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5109 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 78.644353 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2952.702952 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5106 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 4297 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 7960 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 9080 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 9749 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 10574 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 11119 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 12096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 11614 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 11639 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 10464 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9678 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 8171 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7710 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6526 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5950 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5885 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 334 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 315 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 274 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 210 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 95 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 24 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 536.458715 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 326.725513 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 417.454187 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 15065 22.68% 22.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11458 17.25% 39.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4677 7.04% 46.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3146 4.74% 51.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3014 4.54% 56.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1853 2.79% 59.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1319 1.99% 61.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1472 2.22% 63.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 24425 36.77% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5535 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 72.556098 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2836.858046 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5532 99.95% 99.95% # Reads before turning the bus around for writes
224,268c221,262
< system.physmem.rdPerTurnAround::total 5109 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5109 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.647289 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.199358 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 21.195525 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 4460 87.30% 87.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 21 0.41% 87.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 12 0.23% 87.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 224 4.38% 92.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 41 0.80% 93.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 20 0.39% 93.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 7 0.14% 93.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 6 0.12% 93.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 14 0.27% 94.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 4 0.08% 94.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 3 0.06% 94.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 1 0.02% 94.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 9 0.18% 94.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 5 0.10% 94.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 4 0.08% 94.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 25 0.49% 95.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 9 0.18% 95.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 15 0.29% 95.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 168 3.29% 98.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.04% 98.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.02% 98.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.04% 98.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.02% 98.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 2 0.04% 98.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 8 0.16% 99.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 5 0.10% 99.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 5 0.10% 99.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 9 0.18% 99.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 13 0.25% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.02% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.02% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 2 0.04% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 5 0.10% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 1 0.02% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5109 # Writes before turning the bus around for reads
< system.physmem.totQLat 2129492750 # Total ticks spent queuing
< system.physmem.totMemAccLat 9663467750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2009060000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 5299.72 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5535 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5535 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 28.040289 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 21.079799 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 34.913440 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-23 4499 81.28% 81.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-31 176 3.18% 84.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-39 297 5.37% 89.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-47 50 0.90% 90.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-55 97 1.75% 92.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-63 48 0.87% 93.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-71 11 0.20% 93.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-79 7 0.13% 93.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-87 21 0.38% 94.06% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-95 7 0.13% 94.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-103 14 0.25% 94.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-111 6 0.11% 94.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-119 14 0.25% 94.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-127 3 0.05% 94.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-135 11 0.20% 95.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-143 48 0.87% 95.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-151 16 0.29% 96.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-159 19 0.34% 96.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-167 91 1.64% 98.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-175 36 0.65% 98.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-183 6 0.11% 98.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-191 14 0.25% 99.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-199 14 0.25% 99.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::200-207 5 0.09% 99.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-215 9 0.16% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::216-223 3 0.05% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-231 5 0.09% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::232-239 1 0.02% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-247 3 0.05% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::248-255 2 0.04% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5535 # Writes before turning the bus around for reads
> system.physmem.totQLat 2119831750 # Total ticks spent queuing
> system.physmem.totMemAccLat 9650131750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2008080000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 5278.26 # Average queueing delay per DRAM burst
270,274c264,268
< system.physmem.avgMemAccLat 24049.72 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24028.26 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s
276c270
< system.physmem.busUtil 0.13 # Data bus utilization in percentage
---
> system.physmem.busUtil 0.14 # Data bus utilization in percentage
278c272
< system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
---
> system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
280,288c274,282
< system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing
< system.physmem.readRowHits 359991 # Number of row buffer hits during reads
< system.physmem.writeRowHits 93535 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes
< system.physmem.avgGap 3707411.64 # Average gap between requests
< system.physmem.pageHitRate 87.63 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 1800186005000 # Time in different power states
< system.physmem.memoryStateTime::REF 64094160000 # Time in different power states
---
> system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing
> system.physmem.readRowHits 359880 # Number of row buffer hits during reads
> system.physmem.writeRowHits 130510 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 84.08 # Row buffer hit rate for writes
> system.physmem.avgGap 3435694.78 # Average gap between requests
> system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 1801057353000 # Time in different power states
> system.physmem.memoryStateTime::REF 64127180000 # Time in different power states
290c284
< system.physmem.memoryStateTime::ACT 55155300000 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 55239785750 # Time in different power states
292,453c286,303
< system.physmem.actEnergy::0 236499480 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 247272480 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 129042375 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 134920500 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 1564266600 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 1569867000 # Energy for read commands per rank (pJ)
< system.physmem.writeEnergy::0 370954080 # Energy for write commands per rank (pJ)
< system.physmem.writeEnergy::1 378814320 # Energy for write commands per rank (pJ)
< system.physmem.refreshEnergy::0 125368176960 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 125368176960 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 63948324510 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 64460493450 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1095566249250 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1095116978250 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1287183513255 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1287276522960 # Total energy per rank (pJ)
< system.physmem.averagePower::0 670.605262 # Core power per rank (mW)
< system.physmem.averagePower::1 670.653719 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 292357 # Transaction distribution
< system.membus.trans_dist::ReadResp 292357 # Transaction distribution
< system.membus.trans_dist::WriteReq 9649 # Transaction distribution
< system.membus.trans_dist::WriteResp 9649 # Transaction distribution
< system.membus.trans_dist::Writeback 74180 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
< system.membus.trans_dist::ReadExReq 116726 # Transaction distribution
< system.membus.trans_dist::ReadExResp 116726 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878404 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911562 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 994854 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474240 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30518796 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 33179084 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 158 # Total snoops (count)
< system.membus.snoop_fanout::samples 518029 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 518029 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
< system.membus.snoop_fanout::max_value 1 # Request fanout histogram
< system.membus.snoop_fanout::total 518029 # Request fanout histogram
< system.membus.reqLayer0.occupancy 30371000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer1.occupancy 1451093000 # Layer occupancy (ticks)
< system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3752017868 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
< system.membus.respLayer2.occupancy 43114250 # Layer occupancy (ticks)
< system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
< system.iocache.tags.replacements 41685 # number of replacements
< system.iocache.tags.tagsinuse 1.344808 # Cycle average of tags in use
< system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
< system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
< system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
< system.iocache.tags.warmup_cycle 1753524972000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.344808 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.084051 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.084051 # Average percentage of cache occupancy
< system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
< system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
< system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
< system.iocache.tags.tag_accesses 375557 # Number of tag accesses
< system.iocache.tags.data_accesses 375557 # Number of data accesses
< system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
< system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
< system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
< system.iocache.WriteInvalidateReq_misses::tsunami.ide 4 # number of WriteInvalidateReq misses
< system.iocache.WriteInvalidateReq_misses::total 4 # number of WriteInvalidateReq misses
< system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
< system.iocache.demand_misses::total 173 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
< system.iocache.overall_misses::total 173 # number of overall misses
< system.iocache.ReadReq_miss_latency::tsunami.ide 24523133 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 24523133 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 24523133 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 24523133 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 24523133 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 24523133 # number of overall miss cycles
< system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41556 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::total 41556 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
< system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
< system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
< system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000096 # miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_miss_rate::total 0.000096 # miss rate for WriteInvalidateReq accesses
< system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
< system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
< system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
< system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 141752.213873 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 141752.213873 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 141752.213873 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 141752.213873 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.iocache.blocked::no_targets 0 # number of cycles access was blocked
< system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.iocache.fast_writes 41552 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
< system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
< system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 15526633 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512178304 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512178304 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 15526633 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 15526633 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
< system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
< system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
< system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
< system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
< system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
< system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
< system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
< system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
< system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
< system.disk0.dma_write_txs 395 # Number of DMA write transactions.
< system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
< system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
< system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
< system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
< system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
< system.disk2.dma_write_txs 1 # Number of DMA write transactions.
---
> system.physmem.actEnergy::0 245964600 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 256238640 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 134206875 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 139812750 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 1563634800 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 1568970000 # Energy for read commands per rank (pJ)
> system.physmem.writeEnergy::0 496866960 # Energy for write commands per rank (pJ)
> system.physmem.writeEnergy::1 508848480 # Energy for write commands per rank (pJ)
> system.physmem.refreshEnergy::0 125432764080 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 125432764080 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 64118860245 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 64485707400 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1096009968750 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1095688173000 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1288002266310 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1288080514350 # Total energy per rank (pJ)
> system.physmem.averagePower::0 670.686297 # Core power per rank (mW)
> system.physmem.averagePower::1 670.727042 # Core power per rank (mW)
459,460c309,310
< system.cpu.dtb.read_hits 9052455 # DTB read hits
< system.cpu.dtb.read_misses 10357 # DTB read misses
---
> system.cpu.dtb.read_hits 9053154 # DTB read hits
> system.cpu.dtb.read_misses 10325 # DTB read misses
462,464c312,314
< system.cpu.dtb.read_accesses 728916 # DTB read accesses
< system.cpu.dtb.write_hits 6349129 # DTB write hits
< system.cpu.dtb.write_misses 1143 # DTB write misses
---
> system.cpu.dtb.read_accesses 728854 # DTB read accesses
> system.cpu.dtb.write_hits 6349573 # DTB write hits
> system.cpu.dtb.write_misses 1142 # DTB write misses
466,468c316,318
< system.cpu.dtb.write_accesses 291932 # DTB write accesses
< system.cpu.dtb.data_hits 15401584 # DTB hits
< system.cpu.dtb.data_misses 11500 # DTB misses
---
> system.cpu.dtb.write_accesses 291931 # DTB write accesses
> system.cpu.dtb.data_hits 15402727 # DTB hits
> system.cpu.dtb.data_misses 11467 # DTB misses
470,471c320,321
< system.cpu.dtb.data_accesses 1020848 # DTB accesses
< system.cpu.itb.fetch_hits 4974880 # ITB hits
---
> system.cpu.dtb.data_accesses 1020785 # DTB accesses
> system.cpu.itb.fetch_hits 4974627 # ITB hits
474c324
< system.cpu.itb.fetch_accesses 4979890 # ITB accesses
---
> system.cpu.itb.fetch_accesses 4979637 # ITB accesses
487c337
< system.cpu.numCycles 3838878050 # number of cpu cycles simulated
---
> system.cpu.numCycles 3840855754 # number of cpu cycles simulated
490,512c340,362
< system.cpu.committedInsts 56102180 # Number of instructions committed
< system.cpu.committedOps 56102180 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 51977296 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses
< system.cpu.num_func_calls 1481232 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 6461044 # number of instructions that are conditional controls
< system.cpu.num_int_insts 51977296 # number of integer instructions
< system.cpu.num_fp_insts 324326 # number of float instructions
< system.cpu.num_int_register_reads 71206831 # number of times the integer registers were read
< system.cpu.num_int_register_writes 38459262 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read
< system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written
< system.cpu.num_mem_refs 15454224 # number of memory refs
< system.cpu.num_load_insts 9089337 # Number of load instructions
< system.cpu.num_store_insts 6364887 # Number of store instructions
< system.cpu.num_idle_cycles 3587231475.998131 # Number of idle cycles
< system.cpu.num_busy_cycles 251646574.001869 # Number of busy cycles
< system.cpu.not_idle_fraction 0.065552 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.934448 # Percentage of idle cycles
< system.cpu.Branches 8412776 # Number of branches fetched
< system.cpu.op_class::No_OpClass 3197684 5.70% 5.70% # Class of executed instruction
< system.cpu.op_class::IntAlu 36172751 64.46% 70.16% # Class of executed instruction
< system.cpu.op_class::IntMult 60997 0.11% 70.27% # Class of executed instruction
---
> system.cpu.committedInsts 56105324 # Number of instructions committed
> system.cpu.committedOps 56105324 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 51980283 # Number of integer alu accesses
> system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses
> system.cpu.num_func_calls 1481352 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 6461346 # number of instructions that are conditional controls
> system.cpu.num_int_insts 51980283 # number of integer instructions
> system.cpu.num_fp_insts 324527 # number of float instructions
> system.cpu.num_int_register_reads 71211532 # number of times the integer registers were read
> system.cpu.num_int_register_writes 38461399 # number of times the integer registers were written
> system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read
> system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written
> system.cpu.num_mem_refs 15455353 # number of memory refs
> system.cpu.num_load_insts 9090013 # Number of load instructions
> system.cpu.num_store_insts 6365340 # Number of store instructions
> system.cpu.num_idle_cycles 3589191785.998131 # Number of idle cycles
> system.cpu.num_busy_cycles 251663968.001869 # Number of busy cycles
> system.cpu.not_idle_fraction 0.065523 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.934477 # Percentage of idle cycles
> system.cpu.Branches 8413247 # Number of branches fetched
> system.cpu.op_class::No_OpClass 3197750 5.70% 5.70% # Class of executed instruction
> system.cpu.op_class::IntAlu 36174854 64.46% 70.16% # Class of executed instruction
> system.cpu.op_class::IntMult 61015 0.11% 70.27% # Class of executed instruction
514c364
< system.cpu.op_class::FloatAdd 38083 0.07% 70.34% # Class of executed instruction
---
> system.cpu.op_class::FloatAdd 38089 0.07% 70.34% # Class of executed instruction
540,542c390,392
< system.cpu.op_class::MemRead 9316413 16.60% 86.95% # Class of executed instruction
< system.cpu.op_class::MemWrite 6370959 11.35% 98.30% # Class of executed instruction
< system.cpu.op_class::IprAccess 953524 1.70% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 9317103 16.60% 86.95% # Class of executed instruction
> system.cpu.op_class::MemWrite 6371414 11.35% 98.30% # Class of executed instruction
> system.cpu.op_class::IprAccess 953297 1.70% 100.00% # Class of executed instruction
544c394
< system.cpu.op_class::total 56114047 # Class of executed instruction
---
> system.cpu.op_class::total 56117158 # Class of executed instruction
546,548c396,398
< system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl
---
> system.cpu.kern.inst.quiesce 6382 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 212003 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74898 40.89% 40.89% # number of times we switched to this ipl
550,553c400,403
< system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 106211 57.99% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73531 49.31% 49.31% # number of times we switched to this ipl from a different ipl
555,563c405,413
< system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1857251860000 96.76% 96.76% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 91366000 0.00% 96.76% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 736784000 0.04% 96.80% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 61358281000 3.20% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1919438291000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73531 49.31% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 149125 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1858233349500 96.76% 96.76% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 91228000 0.00% 96.77% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 737074000 0.04% 96.80% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 61365491500 3.20% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1920427143000 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
566,567c416,417
< system.cpu.kern.ipl_used::31 0.692282 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814105 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.692239 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814077 # fraction of swpipl calls that actually changed the ipl
603,604c453,454
< system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed
< system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
---
> system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed
> system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
606,607c456,457
< system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed
< system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175962 91.21% 93.41% # number of callpals executed
> system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed
610c460
< system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
---
> system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
612c462
< system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
---
> system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed
615,622c465,472
< system.cpu.kern.callpal::total 192892 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
< system.cpu.kern.mode_switch::user 1742 # number of protection mode switches
< system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
< system.cpu.kern.mode_good::kernel 1911
< system.cpu.kern.mode_good::user 1742
< system.cpu.kern.mode_good::idle 169
< system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches
---
> system.cpu.kern.callpal::total 192910 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches
> system.cpu.kern.mode_switch::user 1743 # number of protection mode switches
> system.cpu.kern.mode_switch::idle 2100 # number of protection mode switches
> system.cpu.kern.mode_good::kernel 1914
> system.cpu.kern.mode_good::user 1743
> system.cpu.kern.mode_good::idle 171
> system.cpu.kern.mode_switch_good::kernel 0.324352 # fraction of useful protection mode switches
624,732c474,627
< system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.392443 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 46142250000 2.40% 2.40% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 5192719000 0.27% 2.67% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1868103320000 97.33% 100.00% # number of ticks spent at the given mode
< system.cpu.kern.swap_context 4176 # number of times the context was actually changed
< system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
< system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
< system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
< system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
< system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
< system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
< system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
< system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
< system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
< system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
< system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
< system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
< system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
< system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
< system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
< system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
< system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
< system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
< system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
< system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
< system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
< system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
< system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
< system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
< system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
< system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
< system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
< system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
< system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
< system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
< system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
< system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
< system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
< system.iobus.trans_dist::WriteReq 51197 # Transaction distribution
< system.iobus.trans_dist::WriteResp 51201 # Transaction distribution
< system.iobus.trans_dist::WriteInvalidateReq 4 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
< system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
< system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
< system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
< system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
< system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
< system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
< system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
< system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
< system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
< system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
< system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer29.occupancy 374412187 # Layer occupancy (ticks)
< system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
< system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
< system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks)
< system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
< system.iobus.respLayer1.occupancy 42016750 # Layer occupancy (ticks)
< system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
< system.cpu.icache.tags.replacements 927651 # number of replacements
< system.cpu.icache.tags.tagsinuse 508.304035 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 55185726 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 928162 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 59.456998 # Average number of references to valid blocks.
---
> system.cpu.kern.mode_switch_good::idle 0.081429 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.392857 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 46106755000 2.40% 2.40% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 5190620000 0.27% 2.67% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1869129766000 97.33% 100.00% # number of ticks spent at the given mode
> system.cpu.kern.swap_context 4179 # number of times the context was actually changed
> system.cpu.dcache.tags.replacements 1390139 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 14031130 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1390651 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 10.089613 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 63077780 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63077780 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 7803062 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7803062 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5845783 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5845783 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 13648845 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13648845 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13648845 # number of overall hits
> system.cpu.dcache.overall_hits::total 13648845 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1069228 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1069228 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 304213 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 304213 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 17228 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17228 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1373441 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1373441 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1373441 # number of overall misses
> system.cpu.dcache.overall_misses::total 1373441 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 29002641750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 29002641750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10915376130 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10915376130 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228802500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 228802500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 39918017880 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 39918017880 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 39918017880 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 39918017880 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 8872290 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 8872290 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6149996 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6149996 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200258 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200258 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15022286 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15022286 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15022286 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15022286 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120513 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.120513 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049466 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.049466 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086029 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086029 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.091427 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.091427 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27124.843111 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 27124.843111 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35880.702435 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35880.702435 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13280.850940 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13280.850940 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 29064.239294 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29064.239294 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 29064.239294 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 29064.239294 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 834534 # number of writebacks
> system.cpu.dcache.writebacks::total 834534 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069228 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1069228 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304213 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304213 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17228 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17228 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1373441 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1373441 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1373441 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1373441 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26738553250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 26738553250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10254282870 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10254282870 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194333500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194333500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36992836120 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 36992836120 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36992836120 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 36992836120 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424273000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009400000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009400000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433673000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433673000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120513 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120513 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049466 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049466 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086029 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086029 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25007.344785 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25007.344785 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33707.576172 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33707.576172 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11280.096355 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11280.096355 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26934.419549 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26934.419549 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26934.419549 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26934.419549 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.icache.tags.replacements 927958 # number of replacements
> system.cpu.icache.tags.tagsinuse 508.305941 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 55188530 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 928469 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 59.440358 # Average number of references to valid blocks.
734,736c629,631
< system.cpu.icache.tags.occ_blocks::cpu.inst 508.304035 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 508.305941 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.992785 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.992785 # Average percentage of cache occupancy
743,780c638,675
< system.cpu.icache.tags.tag_accesses 57042370 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 57042370 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 55185726 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 55185726 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 55185726 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 55185726 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 55185726 # number of overall hits
< system.cpu.icache.overall_hits::total 55185726 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 928322 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 928322 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 928322 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 928322 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 928322 # number of overall misses
< system.cpu.icache.overall_misses::total 928322 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12909129000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12909129000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12909129000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12909129000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12909129000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12909129000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 56114048 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 56114048 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 56114048 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 56114048 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 56114048 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 56114048 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016543 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.016543 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.016543 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.016543 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.016543 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.016543 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13905.874255 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13905.874255 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13905.874255 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13905.874255 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 57045788 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 57045788 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 55188530 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 55188530 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 55188530 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 55188530 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 55188530 # number of overall hits
> system.cpu.icache.overall_hits::total 55188530 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 928629 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 928629 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 928629 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 928629 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 928629 # number of overall misses
> system.cpu.icache.overall_misses::total 928629 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12911718500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12911718500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12911718500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12911718500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12911718500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12911718500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 56117159 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 56117159 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 56117159 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 56117159 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 56117159 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 56117159 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016548 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.016548 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.016548 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.016548 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.016548 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.016548 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13904.065563 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13904.065563 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13904.065563 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13904.065563 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13904.065563 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13904.065563 # average overall miss latency
789,812c684,707
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928322 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 928322 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 928322 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 928322 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 928322 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 928322 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11047351000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 11047351000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11047351000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 11047351000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11047351000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 11047351000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11900.343846 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11900.343846 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928629 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 928629 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 928629 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 928629 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 928629 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 928629 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11049312500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 11049312500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11049312500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 11049312500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11049312500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 11049312500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016548 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016548 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016548 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.016548 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016548 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.016548 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.521907 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.521907 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.521907 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.521907 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.521907 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.521907 # average overall mshr miss latency
814,818c709,713
< system.cpu.l2cache.tags.replacements 336238 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65296.035696 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2445623 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 401399 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.092748 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 336233 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65296.128852 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2446119 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 401395 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.094045 # Average number of references to valid blocks.
820,828c715,723
< system.cpu.l2cache.tags.occ_blocks::writebacks 55554.100042 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 4767.074149 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 4974.861505 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.847688 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072740 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.075910 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996338 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65161 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 55552.665832 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 4768.375008 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.088012 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.847666 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.075914 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996340 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
831,840c726,735
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3263 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55775 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994278 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 25932255 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 25932255 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 915008 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 814389 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1729397 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 834448 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 834448 # number of Writeback hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3259 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55779 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 25936314 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 25936314 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 915316 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 814497 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1729813 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 834534 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 834534 # number of Writeback hits
843,853c738,748
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187344 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187344 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 915008 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1001733 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1916741 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 915008 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1001733 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1916741 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 13294 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 271960 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 285254 # number of ReadReq misses
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187354 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187354 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 915316 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1001851 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1917167 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 915316 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1001851 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1917167 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 13293 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 271959 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 285252 # number of ReadReq misses
856,881c751,776
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116845 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116845 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 13294 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 388805 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 402099 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 13294 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 388805 # number of overall misses
< system.cpu.l2cache.overall_misses::total 402099 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 968929000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17693938000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 18662867000 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 93496 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 93496 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8083085881 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8083085881 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 968929000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 25777023881 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 26745952881 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 968929000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 25777023881 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 26745952881 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 928302 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1086349 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2014651 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 834448 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 834448 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116842 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116842 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 13293 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 388801 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 402094 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 13293 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 388801 # number of overall misses
> system.cpu.l2cache.overall_misses::total 402094 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 967503500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17701460750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 18668964250 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8076097381 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8076097381 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 967503500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 25777558131 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 26745061631 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 967503500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 25777558131 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 26745061631 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 928609 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1086456 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2015065 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 834534 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 834534 # number of Writeback accesses(hits+misses)
884,894c779,789
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 304189 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304189 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 928302 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1390538 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2318840 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 928302 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1390538 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2318840 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014321 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250343 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.141590 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 304196 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304196 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 928609 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1390652 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2319261 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 928609 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1390652 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2319261 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014315 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250318 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.141560 # miss rate for ReadReq accesses
897,917c792,812
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384120 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.384120 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014321 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.279608 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.173405 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014321 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.279608 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.173405 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72884.684820 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65060.810413 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 65425.434876 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7192 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7192 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69177.849981 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69177.849981 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72884.684820 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66298.077136 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 66515.840330 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72884.684820 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66298.077136 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 66515.840330 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384101 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.384101 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014315 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.279582 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.173372 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014315 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.279582 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.173372 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72782.930866 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65088.710982 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 65447.268556 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69119.814630 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69119.814630 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72782.930866 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66300.133310 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 66514.450927 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72782.930866 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66300.133310 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 66514.450927 # average overall miss latency
926,930c821,825
< system.cpu.l2cache.writebacks::writebacks 74180 # number of writebacks
< system.cpu.l2cache.writebacks::total 74180 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13294 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271960 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 74177 # number of writebacks
> system.cpu.l2cache.writebacks::total 74177 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13293 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271959 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 285252 # number of ReadReq MSHR misses
933,953c828,848
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116845 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116845 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 13294 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 388805 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 402099 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 13294 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 388805 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 402099 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 802368000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14293948000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15096316000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 130013 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 130013 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6622079619 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6622079619 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802368000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20916027619 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 21718395619 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802368000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20916027619 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 21718395619 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116842 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116842 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 13293 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 388801 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 402094 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 13293 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 388801 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 402094 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 800925500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14301564750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15102490250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6615159119 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6615159119 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 800925500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20916723869 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 21717649369 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 800925500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20916723869 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 21717649369 # number of overall MSHR miss cycles
956,962c851,857
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893390000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893390000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227573000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227573000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250343 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141590 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893600000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893600000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227783000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227783000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250318 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141560 # mshr miss rate for ReadReq accesses
965,985c860,880
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384120 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384120 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.173405 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.173405 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60355.649165 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52559.008678 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52922.363928 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56674.052112 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56674.052112 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384101 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384101 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279582 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.173372 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279582 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.173372 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60251.673813 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52587.208918 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52944.379882 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56616.277700 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56616.277700 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60251.673813 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53798.019730 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54011.373880 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60251.673813 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53798.019730 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54011.373880 # average overall mshr miss latency
993,1141c888,893
< system.cpu.dcache.tags.replacements 1390025 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.978881 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 14030084 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1390537 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 10.089688 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.978881 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 63073026 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63073026 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 7802461 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7802461 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5845351 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5845351 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 13647812 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13647812 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13647812 # number of overall hits
< system.cpu.dcache.overall_hits::total 13647812 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1069134 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1069134 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 304206 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 304206 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 17215 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17215 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1373340 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1373340 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1373340 # number of overall misses
< system.cpu.dcache.overall_misses::total 1373340 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 28994287250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 28994287250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922192632 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10922192632 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228270750 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 228270750 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 39916479882 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 39916479882 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 39916479882 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 39916479882 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 8871595 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 8871595 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6149557 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6149557 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15021152 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15021152 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15021152 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15021152 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120512 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.120512 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.091427 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.091427 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27119.413703 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 27119.413703 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35903.935596 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 35903.935596 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13259.991287 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13259.991287 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29065.256879 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 29065.256879 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 834448 # number of writebacks
< system.cpu.dcache.writebacks::total 834448 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069134 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1069134 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304206 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304206 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17215 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17215 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1373340 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1373340 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1373340 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1373340 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26730348750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 26730348750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10261067368 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10261067368 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193828250 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193828250 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36991416118 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 36991416118 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36991416118 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 36991416118 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424273000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009178000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009178000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433451000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433451000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120512 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120512 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049468 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049468 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25001.869504 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25001.869504 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33730.654123 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33730.654123 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11259.265176 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11259.265176 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.toL2Bus.trans_dist::ReadReq 2021774 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2021757 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 834448 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41564 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2022188 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2022171 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 834534 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
1144,1155c896,907
< system.cpu.toL2Bus.trans_dist::ReadExReq 304189 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 304189 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856624 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648872 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 5505496 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59411328 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142453644 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 201864972 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 41913 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3195062 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.013063 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.113544 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 304196 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 304196 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857238 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649188 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 5506426 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59430976 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142466452 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 201897428 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 41901 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3195557 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.013057 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.113520 # Request fanout histogram
1158,1159c910,911
< system.cpu.toL2Bus.snoop_fanout::1 3153325 98.69% 98.69% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 41737 1.31% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 3153832 98.69% 98.69% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram
1163,1164c915,916
< system.cpu.toL2Bus.snoop_fanout::total 3195062 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2424224500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 3195557 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2424565000 # Layer occupancy (ticks)
1168c920
< system.cpu.toL2Bus.respLayer0.occupancy 1395050000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1395517500 # Layer occupancy (ticks)
1170c922
< system.cpu.toL2Bus.respLayer1.occupancy 2186768132 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2186897880 # Layer occupancy (ticks)
1171a924,1173
> system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
> system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
> system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
> system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
> system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
> system.disk0.dma_write_txs 395 # Number of DMA write transactions.
> system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
> system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
> system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
> system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
> system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
> system.disk2.dma_write_txs 1 # Number of DMA write transactions.
> system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
> system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
> system.iobus.trans_dist::WriteReq 51202 # Transaction distribution
> system.iobus.trans_dist::WriteResp 9650 # Transaction distribution
> system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks)
> system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
> system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
> system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
> system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
> system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
> system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
> system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
> system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
> system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
> system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
> system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer29.occupancy 406189794 # Layer occupancy (ticks)
> system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
> system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
> system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
> system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
> system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks)
> system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
> system.iocache.tags.replacements 41685 # number of replacements
> system.iocache.tags.tagsinuse 1.352352 # Cycle average of tags in use
> system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
> system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
> system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
> system.iocache.tags.warmup_cycle 1753525032000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.352352 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.084522 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.084522 # Average percentage of cache occupancy
> system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
> system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
> system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
> system.iocache.tags.tag_accesses 375525 # Number of tag accesses
> system.iocache.tags.data_accesses 375525 # Number of data accesses
> system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
> system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
> system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
> system.iocache.demand_misses::total 173 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
> system.iocache.overall_misses::total 173 # number of overall misses
> system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634918911 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 13634918911 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
> system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
> system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
> system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
> system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
> system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
> system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
> system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328141.098166 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 328141.098166 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 206323 # number of cycles access was blocked
> system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked
> system.iocache.blocked::no_targets 0 # number of cycles access was blocked
> system.iocache.avg_blocked_cycles::no_mshrs 8.756971 # average number of cycles each access was blocked
> system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.iocache.fast_writes 0 # number of fast writes performed
> system.iocache.cache_copies 0 # number of cache copies performed
> system.iocache.writebacks::writebacks 41512 # number of writebacks
> system.iocache.writebacks::total 41512 # number of writebacks
> system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
> system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
> system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
> system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474214911 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474214911 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
> system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
> system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
> system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
> system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
> system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
> system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276141.098166 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276141.098166 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
> system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.membus.trans_dist::ReadReq 292355 # Transaction distribution
> system.membus.trans_dist::ReadResp 292355 # Transaction distribution
> system.membus.trans_dist::WriteReq 9650 # Transaction distribution
> system.membus.trans_dist::WriteResp 9650 # Transaction distribution
> system.membus.trans_dist::Writeback 115689 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
> system.membus.trans_dist::ReadExReq 116723 # Transaction distribution
> system.membus.trans_dist::ReadExResp 116723 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878118 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911278 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1036082 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456384 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30500948 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 35818004 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 431 # Total snoops (count)
> system.membus.snoop_fanout::samples 559521 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 559521 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 559521 # Request fanout histogram
> system.membus.reqLayer0.occupancy 30373000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer1.occupancy 1824623000 # Layer occupancy (ticks)
> system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
> system.membus.respLayer1.occupancy 3751921620 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
> system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks)
> system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
> system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
> system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
> system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
> system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
> system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
> system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
> system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
> system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
> system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
> system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
> system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
> system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
> system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
> system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
> system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
> system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
> system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
> system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
> system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
> system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
> system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
> system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
> system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
> system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
> system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
> system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
> system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
> system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
> system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
> system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
> system.tsunami.ethernet.droppedPackets 0 # number of packets dropped