7,11c7,11
< host_inst_rate 960719 # Simulator instruction rate (inst/s)
< host_op_rate 960718 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 32869301826 # Simulator tick rate (ticks/s)
< host_mem_usage 317196 # Number of bytes of host memory used
< host_seconds 58.40 # Real time elapsed on the host
---
> host_inst_rate 1406989 # Simulator instruction rate (inst/s)
> host_op_rate 1406988 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 48137648137 # Simulator tick rate (ticks/s)
> host_mem_usage 309300 # Number of bytes of host memory used
> host_seconds 39.87 # Real time elapsed on the host
415,416d414
< system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
< system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
431,432d428
< system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999904 # mshr miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999904 # mshr miss rate for WriteInvalidateReq accesses
439,440c435,436
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60458.661533 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60458.661533 # average WriteInvalidateReq mshr miss latency
---
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency