4,5c4,5
< sim_ticks 1919438772000 # Number of ticks simulated
< final_tick 1919438772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 1919439025000 # Number of ticks simulated
> final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1398299 # Simulator instruction rate (inst/s)
< host_op_rate 1398299 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 47840414078 # Simulator tick rate (ticks/s)
< host_mem_usage 314348 # Number of bytes of host memory used
< host_seconds 40.12 # Real time elapsed on the host
< sim_insts 56102112 # Number of instructions simulated
< sim_ops 56102112 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1426339 # Simulator instruction rate (inst/s)
> host_op_rate 1426339 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 48799693433 # Simulator tick rate (ticks/s)
> host_mem_usage 367228 # Number of bytes of host memory used
> host_seconds 39.33 # Real time elapsed on the host
> sim_insts 56102180 # Number of instructions simulated
> sim_ops 56102180 # Number of ops (including micro ops) simulated
17c17
< system.physmem.bytes_read::cpu.data 24875968 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory
19c19
< system.physmem.bytes_read::total 25727744 # Number of bytes read from this memory
---
> system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory
22c22
< system.physmem.bytes_written::writebacks 4747712 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 4747520 # Number of bytes written to this memory
24c24
< system.physmem.bytes_written::total 7407040 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 7406848 # Number of bytes written to this memory
26c26
< system.physmem.num_reads::cpu.data 388687 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 388686 # Number of read requests responded to by this memory
28,29c28,29
< system.physmem.num_reads::total 401996 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 74183 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 401995 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 74180 # Number of write requests responded to by this memory
31c31
< system.physmem.num_writes::total 115735 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 115732 # Number of write requests responded to by this memory
33c33
< system.physmem.bw_read::cpu.data 12960022 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 12959987 # Total read bandwidth from this memory (bytes/s)
35c35
< system.physmem.bw_read::total 13403785 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 13403750 # Total read bandwidth from this memory (bytes/s)
38,41c38,41
< system.physmem.bw_write::writebacks 2473490 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::tsunami.ide 1385472 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3858961 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2473490 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 2473389 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::tsunami.ide 1385471 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3858861 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2473389 # Total bandwidth to/from this memory (bytes/s)
43c43
< system.physmem.bw_total::cpu.data 12960022 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 12959987 # Total bandwidth to/from this memory (bytes/s)
45,55c45,55
< system.physmem.bw_total::total 17262746 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 401996 # Number of read requests accepted
< system.physmem.writeReqs 115735 # Number of write requests accepted
< system.physmem.readBursts 401996 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 115735 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 25716224 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 11520 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7405312 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 25727744 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7407040 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 180 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 17262610 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 401995 # Number of read requests accepted
> system.physmem.writeReqs 115732 # Number of write requests accepted
> system.physmem.readBursts 401995 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 115732 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 25715968 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7405120 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 25727680 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7406848 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue
59c59
< system.physmem.perBankRdBursts::1 25541 # Per bank write bursts
---
> system.physmem.perBankRdBursts::1 25539 # Per bank write bursts
61,63c61,63
< system.physmem.perBankRdBursts::3 25537 # Per bank write bursts
< system.physmem.perBankRdBursts::4 24981 # Per bank write bursts
< system.physmem.perBankRdBursts::5 24976 # Per bank write bursts
---
> system.physmem.perBankRdBursts::3 25536 # Per bank write bursts
> system.physmem.perBankRdBursts::4 24982 # Per bank write bursts
> system.physmem.perBankRdBursts::5 24977 # Per bank write bursts
66,67c66,67
< system.physmem.perBankRdBursts::8 25159 # Per bank write bursts
< system.physmem.perBankRdBursts::9 24820 # Per bank write bursts
---
> system.physmem.perBankRdBursts::8 25158 # Per bank write bursts
> system.physmem.perBankRdBursts::9 24823 # Per bank write bursts
69,70c69,70
< system.physmem.perBankRdBursts::11 24840 # Per bank write bursts
< system.physmem.perBankRdBursts::12 24420 # Per bank write bursts
---
> system.physmem.perBankRdBursts::11 24839 # Per bank write bursts
> system.physmem.perBankRdBursts::12 24418 # Per bank write bursts
73c73
< system.physmem.perBankRdBursts::15 25483 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 25481 # Per bank write bursts
81c81
< system.physmem.perBankWrBursts::7 6319 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 6315 # Per bank write bursts
83c83
< system.physmem.perBankWrBursts::9 6554 # Per bank write bursts
---
> system.physmem.perBankWrBursts::9 6555 # Per bank write bursts
91,92c91,92
< system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
< system.physmem.totGap 1919426851000 # Total gap between requests
---
> system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
> system.physmem.totGap 1919427104000 # Total gap between requests
99c99
< system.physmem.readPktSize::6 401996 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 401995 # Read request sizes (log2)
106,107c106,107
< system.physmem.writePktSize::6 115735 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 401802 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 115732 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 401798 # What read queue length does an incoming req see
154,181c154,181
< system.physmem.wrQLenPdf::15 1859 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2606 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5607 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5735 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5978 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6706 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6976 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8149 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8460 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8432 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8281 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6824 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6355 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5592 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5334 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5330 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5306 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 213 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 128 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 1803 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2465 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5623 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5839 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6566 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6884 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8073 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8473 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 8504 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8199 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6888 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6495 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5617 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5359 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5332 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5312 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 198 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 177 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see
183,220c183,220
< system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 205 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 146 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 111 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 70 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 63869 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 518.585480 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 313.979775 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 413.923527 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 14875 23.29% 23.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11515 18.03% 41.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 4721 7.39% 48.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3142 4.92% 53.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3018 4.73% 58.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1863 2.92% 61.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1301 2.04% 63.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1404 2.20% 65.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 22030 34.49% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 63869 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5101 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 78.768477 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2955.016496 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 5098 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 216 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 208 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 197 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 176 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 112 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 63991 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 517.589786 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 312.394273 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 414.375602 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 15074 23.56% 23.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11584 18.10% 41.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4587 7.17% 48.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3091 4.83% 53.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3045 4.76% 58.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1807 2.82% 61.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1323 2.07% 63.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1474 2.30% 65.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 22006 34.39% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63991 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5109 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 78.644353 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2952.702952 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 5106 99.94% 99.94% # Reads before turning the bus around for writes
224,269c224,268
< system.physmem.rdPerTurnAround::total 5101 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5101 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.683395 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.235797 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 21.276820 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 4452 87.28% 87.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 22 0.43% 87.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 15 0.29% 88.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 224 4.39% 92.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 41 0.80% 93.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 6 0.12% 93.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 9 0.18% 93.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 7 0.14% 93.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 19 0.37% 94.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 2 0.04% 94.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 4 0.08% 94.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 2 0.04% 94.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 11 0.22% 94.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 3 0.06% 94.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 7 0.14% 94.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 30 0.59% 95.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 13 0.25% 95.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 3 0.06% 95.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 1 0.02% 95.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 166 3.25% 98.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 10 0.20% 98.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.04% 98.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 6 0.12% 99.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 4 0.08% 99.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 2 0.04% 99.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 6 0.12% 99.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 9 0.18% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 9 0.18% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.02% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 3 0.06% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 2 0.04% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 3 0.06% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.02% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-171 1 0.02% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::220-223 1 0.02% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-227 4 0.08% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5101 # Writes before turning the bus around for reads
< system.physmem.totQLat 2117396500 # Total ticks spent queuing
< system.physmem.totMemAccLat 9651446500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2009080000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 5269.57 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 5109 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5109 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.647289 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 19.199358 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 21.195525 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 4460 87.30% 87.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 21 0.41% 87.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 12 0.23% 87.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 224 4.38% 92.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 41 0.80% 93.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 20 0.39% 93.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 7 0.14% 93.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 6 0.12% 93.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 14 0.27% 94.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 4 0.08% 94.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 3 0.06% 94.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 1 0.02% 94.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 9 0.18% 94.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 5 0.10% 94.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 4 0.08% 94.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 25 0.49% 95.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 9 0.18% 95.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 15 0.29% 95.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 168 3.29% 98.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 2 0.04% 98.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 1 0.02% 98.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 2 0.04% 98.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 1 0.02% 98.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 2 0.04% 98.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 8 0.16% 99.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 5 0.10% 99.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 5 0.10% 99.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 9 0.18% 99.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 13 0.25% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 1 0.02% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 1 0.02% 99.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 2 0.04% 99.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 5 0.10% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 1 0.02% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5109 # Writes before turning the bus around for reads
> system.physmem.totQLat 2129492750 # Total ticks spent queuing
> system.physmem.totMemAccLat 9663467750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2009060000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 5299.72 # Average queueing delay per DRAM burst
271c270
< system.physmem.avgMemAccLat 24019.57 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 24049.72 # Average memory access latency per DRAM burst
281,284c280,283
< system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing
< system.physmem.readRowHits 360116 # Number of row buffer hits during reads
< system.physmem.writeRowHits 93539 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads
---
> system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing
> system.physmem.readRowHits 359991 # Number of row buffer hits during reads
> system.physmem.writeRowHits 93535 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads
286,288c285,287
< system.physmem.avgGap 3707382.50 # Average gap between requests
< system.physmem.pageHitRate 87.65 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 1800046548500 # Time in different power states
---
> system.physmem.avgGap 3707411.64 # Average gap between requests
> system.physmem.pageHitRate 87.63 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 1800186005000 # Time in different power states
291c290
< system.physmem.memoryStateTime::ACT 55294756500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 55155300000 # Time in different power states
293d291
< system.membus.throughput 17291227 # Throughput (bytes/s)
298c296
< system.membus.trans_dist::Writeback 74183 # Transaction distribution
---
> system.membus.trans_dist::Writeback 74180 # Transaction distribution
303,304c301,302
< system.membus.trans_dist::ReadExReq 116727 # Transaction distribution
< system.membus.trans_dist::ReadExResp 116727 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 116726 # Transaction distribution
> system.membus.trans_dist::ReadExResp 116726 # Transaction distribution
306,307c304,305
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878409 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911567 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878404 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911562 # Packet count per connected master and slave (bytes)
310,319c308,327
< system.membus.pkt_count::total 994859 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474496 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30519052 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 33179340 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 33179340 # Total data (bytes)
< system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 32375500 # Layer occupancy (ticks)
---
> system.membus.pkt_count::total 994854 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474240 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30518796 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 33179084 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 158 # Total snoops (count)
> system.membus.snoop_fanout::samples 518029 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 518029 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 518029 # Request fanout histogram
> system.membus.reqLayer0.occupancy 30371000 # Layer occupancy (ticks)
321c329
< system.membus.reqLayer1.occupancy 1450892000 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1451093000 # Layer occupancy (ticks)
323c331
< system.membus.respLayer1.occupancy 3751806368 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 3752017868 # Layer occupancy (ticks)
325c333
< system.membus.respLayer2.occupancy 43113000 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 43114250 # Layer occupancy (ticks)
328c336
< system.iocache.tags.tagsinuse 1.344805 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.344808 # Cycle average of tags in use
332,335c340,343
< system.iocache.tags.warmup_cycle 1753524887000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.344805 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.084050 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.084050 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1753524972000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.344808 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.084051 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.084051 # Average percentage of cache occupancy
339,340c347,348
< system.iocache.tags.tag_accesses 375525 # Number of tag accesses
< system.iocache.tags.data_accesses 375525 # Number of data accesses
---
> system.iocache.tags.tag_accesses 375557 # Number of tag accesses
> system.iocache.tags.data_accesses 375557 # Number of data accesses
344a353,354
> system.iocache.WriteInvalidateReq_misses::tsunami.ide 4 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 4 # number of WriteInvalidateReq misses
349,354c359,364
< system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 24523133 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 24523133 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 24523133 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 24523133 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 24523133 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 24523133 # number of overall miss cycles
357,358c367,368
< system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
---
> system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41556 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::total 41556 # number of WriteInvalidateReq accesses(hits+misses)
364a375,376
> system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000096 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 0.000096 # miss rate for WriteInvalidateReq accesses
369,374c381,386
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 141752.213873 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 141752.213873 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 141752.213873 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 141752.213873 # average overall miss latency
391,398c403,410
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2506570306 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2506570306 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 15526633 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512178304 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512178304 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 15526633 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 15526633 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles
401,402c413,414
< system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
---
> system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999904 # mshr miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999904 # mshr miss rate for WriteInvalidateReq accesses
407,414c419,426
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60323.698161 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60323.698161 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60458.661533 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60458.661533 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency
433,434c445,446
< system.cpu.dtb.read_hits 9052614 # DTB read hits
< system.cpu.dtb.read_misses 10356 # DTB read misses
---
> system.cpu.dtb.read_hits 9052455 # DTB read hits
> system.cpu.dtb.read_misses 10357 # DTB read misses
436,438c448,450
< system.cpu.dtb.read_accesses 728915 # DTB read accesses
< system.cpu.dtb.write_hits 6349217 # DTB write hits
< system.cpu.dtb.write_misses 1144 # DTB write misses
---
> system.cpu.dtb.read_accesses 728916 # DTB read accesses
> system.cpu.dtb.write_hits 6349129 # DTB write hits
> system.cpu.dtb.write_misses 1143 # DTB write misses
440,441c452,453
< system.cpu.dtb.write_accesses 291933 # DTB write accesses
< system.cpu.dtb.data_hits 15401831 # DTB hits
---
> system.cpu.dtb.write_accesses 291932 # DTB write accesses
> system.cpu.dtb.data_hits 15401584 # DTB hits
445c457
< system.cpu.itb.fetch_hits 4974960 # ITB hits
---
> system.cpu.itb.fetch_hits 4974880 # ITB hits
448c460
< system.cpu.itb.fetch_accesses 4979970 # ITB accesses
---
> system.cpu.itb.fetch_accesses 4979890 # ITB accesses
461c473
< system.cpu.numCycles 3838877544 # number of cpu cycles simulated
---
> system.cpu.numCycles 3838878050 # number of cpu cycles simulated
464,486c476,498
< system.cpu.committedInsts 56102112 # Number of instructions committed
< system.cpu.committedOps 56102112 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 51977185 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
< system.cpu.num_func_calls 1481236 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 6460933 # number of instructions that are conditional controls
< system.cpu.num_int_insts 51977185 # number of integer instructions
< system.cpu.num_fp_insts 324460 # number of float instructions
< system.cpu.num_int_register_reads 71206533 # number of times the integer registers were read
< system.cpu.num_int_register_writes 38459103 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
< system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
< system.cpu.num_mem_refs 15454487 # number of memory refs
< system.cpu.num_load_insts 9089505 # Number of load instructions
< system.cpu.num_store_insts 6364982 # Number of store instructions
< system.cpu.num_idle_cycles 3587234430.998131 # Number of idle cycles
< system.cpu.num_busy_cycles 251643113.001869 # Number of busy cycles
< system.cpu.not_idle_fraction 0.065551 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.934449 # Percentage of idle cycles
< system.cpu.Branches 8412678 # Number of branches fetched
< system.cpu.op_class::No_OpClass 3197715 5.70% 5.70% # Class of executed instruction
< system.cpu.op_class::IntAlu 36172357 64.46% 70.16% # Class of executed instruction
< system.cpu.op_class::IntMult 61004 0.11% 70.27% # Class of executed instruction
---
> system.cpu.committedInsts 56102180 # Number of instructions committed
> system.cpu.committedOps 56102180 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 51977296 # Number of integer alu accesses
> system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses
> system.cpu.num_func_calls 1481232 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 6461044 # number of instructions that are conditional controls
> system.cpu.num_int_insts 51977296 # number of integer instructions
> system.cpu.num_fp_insts 324326 # number of float instructions
> system.cpu.num_int_register_reads 71206831 # number of times the integer registers were read
> system.cpu.num_int_register_writes 38459262 # number of times the integer registers were written
> system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read
> system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written
> system.cpu.num_mem_refs 15454224 # number of memory refs
> system.cpu.num_load_insts 9089337 # Number of load instructions
> system.cpu.num_store_insts 6364887 # Number of store instructions
> system.cpu.num_idle_cycles 3587231475.998131 # Number of idle cycles
> system.cpu.num_busy_cycles 251646574.001869 # Number of busy cycles
> system.cpu.not_idle_fraction 0.065552 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.934448 # Percentage of idle cycles
> system.cpu.Branches 8412776 # Number of branches fetched
> system.cpu.op_class::No_OpClass 3197684 5.70% 5.70% # Class of executed instruction
> system.cpu.op_class::IntAlu 36172751 64.46% 70.16% # Class of executed instruction
> system.cpu.op_class::IntMult 60997 0.11% 70.27% # Class of executed instruction
488c500
< system.cpu.op_class::FloatAdd 38087 0.07% 70.34% # Class of executed instruction
---
> system.cpu.op_class::FloatAdd 38083 0.07% 70.34% # Class of executed instruction
514,516c526,528
< system.cpu.op_class::MemRead 9316582 16.60% 86.95% # Class of executed instruction
< system.cpu.op_class::MemWrite 6371054 11.35% 98.30% # Class of executed instruction
< system.cpu.op_class::IprAccess 953544 1.70% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 9316413 16.60% 86.95% # Class of executed instruction
> system.cpu.op_class::MemWrite 6370959 11.35% 98.30% # Class of executed instruction
> system.cpu.op_class::IprAccess 953524 1.70% 100.00% # Class of executed instruction
518c530
< system.cpu.op_class::total 56113979 # Class of executed instruction
---
> system.cpu.op_class::total 56114047 # Class of executed instruction
520,521c532,533
< system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed
< system.cpu.kern.inst.hwrei 212019 # number of hwrei instructions executed
---
> system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed
> system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed
532,536c544,548
< system.cpu.kern.ipl_ticks::0 1857248521000 96.76% 96.76% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 91287500 0.00% 96.76% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 737179000 0.04% 96.80% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 61361050500 3.20% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1919438038000 # number of cycles we spent at this ipl
---
> system.cpu.kern.ipl_ticks::0 1857251860000 96.76% 96.76% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 91366000 0.00% 96.76% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 736784000 0.04% 96.80% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 61358281000 3.20% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1919438291000 # number of cycles we spent at this ipl
577,578c589,590
< system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
< system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
---
> system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed
> system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
589,590c601,602
< system.cpu.kern.callpal::total 192894 # number of callpals executed
< system.cpu.kern.mode_switch::kernel 5902 # number of protection mode switches
---
> system.cpu.kern.callpal::total 192892 # number of callpals executed
> system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
592,593c604,605
< system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
< system.cpu.kern.mode_good::kernel 1912
---
> system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
> system.cpu.kern.mode_good::kernel 1911
595,596c607,608
< system.cpu.kern.mode_good::idle 170
< system.cpu.kern.mode_switch_good::kernel 0.323958 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_good::idle 169
> system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches
598,603c610,615
< system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.392567 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 46116573000 2.40% 2.40% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 5192895500 0.27% 2.67% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1868128567500 97.33% 100.00% # number of ticks spent at the given mode
< system.cpu.kern.swap_context 4178 # number of times the context was actually changed
---
> system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.392443 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 46142250000 2.40% 2.40% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 5192719000 0.27% 2.67% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1868103320000 97.33% 100.00% # number of ticks spent at the given mode
> system.cpu.kern.swap_context 4176 # number of times the context was actually changed
635d646
< system.iobus.throughput 1409873 # Throughput (bytes/s)
638c649
< system.iobus.trans_dist::WriteReq 51201 # Transaction distribution
---
> system.iobus.trans_dist::WriteReq 51197 # Transaction distribution
639a651
> system.iobus.trans_dist::WriteInvalidateReq 4 # Transaction distribution
656,672c668,683
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 2706164 # Total data (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
695c706
< system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 374412187 # Layer occupancy (ticks)
701c712
< system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 42016750 # Layer occupancy (ticks)
703,709c714,720
< system.cpu.icache.tags.replacements 927724 # number of replacements
< system.cpu.icache.tags.tagsinuse 508.304001 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 55185585 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 928235 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 59.452170 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 39855277250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 508.304001 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.replacements 927651 # number of replacements
> system.cpu.icache.tags.tagsinuse 508.304035 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 55185726 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 928162 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 59.456998 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 508.304035 # Average occupied blocks per requestor
718,755c729,766
< system.cpu.icache.tags.tag_accesses 57042375 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 57042375 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 55185585 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 55185585 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 55185585 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 55185585 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 55185585 # number of overall hits
< system.cpu.icache.overall_hits::total 55185585 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 928395 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 928395 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 928395 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 928395 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 928395 # number of overall misses
< system.cpu.icache.overall_misses::total 928395 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12914246500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12914246500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12914246500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12914246500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12914246500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12914246500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 56113980 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 56113980 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 56113980 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 56113980 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 56113980 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 56113980 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016545 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.016545 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.016545 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.016545 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.016545 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.016545 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13910.293033 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13910.293033 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13910.293033 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13910.293033 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 57042370 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 57042370 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 55185726 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 55185726 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 55185726 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 55185726 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 55185726 # number of overall hits
> system.cpu.icache.overall_hits::total 55185726 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 928322 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 928322 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 928322 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 928322 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 928322 # number of overall misses
> system.cpu.icache.overall_misses::total 928322 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12909129000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12909129000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12909129000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12909129000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12909129000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12909129000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 56114048 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 56114048 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 56114048 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 56114048 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 56114048 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 56114048 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016543 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.016543 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.016543 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.016543 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.016543 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.016543 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13905.874255 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13905.874255 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13905.874255 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13905.874255 # average overall miss latency
764,787c775,798
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928395 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 928395 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 928395 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 928395 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 928395 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 928395 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11052282500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 11052282500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11052282500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 11052282500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11052282500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 11052282500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016545 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.016545 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.016545 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.719974 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.719974 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.719974 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.719974 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.719974 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.719974 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928322 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 928322 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 928322 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 928322 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 928322 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 928322 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11047351000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 11047351000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11047351000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 11047351000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11047351000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 11047351000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11900.343846 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11900.343846 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency
789,793c800,804
< system.cpu.l2cache.tags.replacements 336239 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65296.333666 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2445823 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 401400 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.093231 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 336238 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65296.035696 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2445623 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 401399 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.092748 # Average number of references to valid blocks.
795,798c806,809
< system.cpu.l2cache.tags.occ_blocks::writebacks 55553.405547 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 4767.094279 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.833840 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.847678 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 55554.100042 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 4767.074149 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 4974.861505 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.847688 # Average percentage of cache occupancy
800,801c811,812
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.075925 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996343 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.075910 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996338 # Average percentage of cache occupancy
806,807c817,818
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3266 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55772 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3263 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55775 # Occupied blocks per task id
809,815c820,826
< system.cpu.l2cache.tags.tag_accesses 25933937 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 25933937 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 915081 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 814447 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1729528 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 834526 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 834526 # number of Writeback hits
---
> system.cpu.l2cache.tags.tag_accesses 25932255 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 25932255 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 915008 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 814389 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1729397 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 834448 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 834448 # number of Writeback hits
820,825c831,836
< system.cpu.l2cache.demand_hits::cpu.inst 915081 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1001791 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1916872 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 915081 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1001791 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1916872 # number of overall hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 915008 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1001733 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1916741 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 915008 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1001733 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1916741 # number of overall hits
831,832c842,843
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116846 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116846 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116845 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116845 # number of ReadExReq misses
834,835c845,846
< system.cpu.l2cache.demand_misses::cpu.data 388806 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 402100 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 388805 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 402099 # number of demand (read+write) misses
837,841c848,852
< system.cpu.l2cache.overall_misses::cpu.data 388806 # number of overall misses
< system.cpu.l2cache.overall_misses::total 402100 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 973057500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17696986250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 18670043750 # number of ReadReq miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.data 388805 # number of overall misses
> system.cpu.l2cache.overall_misses::total 402099 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 968929000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17693938000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 18662867000 # number of ReadReq miss cycles
844,856c855,867
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8067144131 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8067144131 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 973057500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 25764130381 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 26737187881 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 973057500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 25764130381 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 26737187881 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 928375 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1086407 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2014782 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 834526 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 834526 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8083085881 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8083085881 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 968929000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 25777023881 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 26745952881 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 968929000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 25777023881 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 26745952881 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 928302 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1086349 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2014651 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 834448 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 834448 # number of Writeback accesses(hits+misses)
859,869c870,880
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 304190 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304190 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 928375 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1390597 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2318972 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 928375 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1390597 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2318972 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014320 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250330 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.141581 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 304189 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304189 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 928302 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1390538 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2318840 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 928302 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1390538 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2318840 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014321 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250343 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.141590 # miss rate for ReadReq accesses
872,882c883,893
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384122 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.384122 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014320 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.279596 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.173396 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014320 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.279596 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.173396 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73195.238453 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65072.018863 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 65450.594032 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384120 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.384120 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014321 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.279608 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.173405 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014321 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.279608 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.173405 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72884.684820 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65060.810413 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 65425.434876 # average ReadReq miss latency
885,892c896,903
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69040.824085 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69040.824085 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73195.238453 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66264.744837 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 66493.876849 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73195.238453 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66264.744837 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 66493.876849 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69177.849981 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69177.849981 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72884.684820 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66298.077136 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 66515.840330 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72884.684820 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66298.077136 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 66515.840330 # average overall miss latency
901,902c912,913
< system.cpu.l2cache.writebacks::writebacks 74183 # number of writebacks
< system.cpu.l2cache.writebacks::total 74183 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 74180 # number of writebacks
> system.cpu.l2cache.writebacks::total 74180 # number of writebacks
908,909c919,920
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116846 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116846 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116845 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116845 # number of ReadExReq MSHR misses
911,912c922,923
< system.cpu.l2cache.demand_mshr_misses::cpu.data 388806 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 402100 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 388805 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 402099 # number of demand (read+write) MSHR misses
914,918c925,929
< system.cpu.l2cache.overall_mshr_misses::cpu.data 388806 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 402100 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 806506000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14297020250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15103526250 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 388805 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 402099 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 802368000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14293948000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15096316000 # number of ReadReq MSHR miss cycles
921,937c932,948
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6606288869 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6606288869 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 806506000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20903309119 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 21709815119 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 806506000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20903309119 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 21709815119 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895431500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895431500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229577500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229577500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250330 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141581 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6622079619 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6622079619 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802368000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20916027619 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 21718395619 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802368000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20916027619 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 21718395619 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334183000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334183000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893390000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893390000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227573000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227573000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250343 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141590 # mshr miss rate for ReadReq accesses
940,950c951,961
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384122 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384122 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.173396 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.173396 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60666.917406 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52570.305376 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52947.640524 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384120 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384120 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.173405 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.173405 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60355.649165 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52559.008678 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52922.363928 # average ReadReq mshr miss latency
953,960c964,971
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56538.425526 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.425526 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56674.052112 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56674.052112 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency
968c979
< system.cpu.dcache.tags.replacements 1390084 # number of replacements
---
> system.cpu.dcache.tags.replacements 1390025 # number of replacements
970,972c981,983
< system.cpu.dcache.tags.total_refs 14030288 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1390596 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 10.089406 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 14030084 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1390537 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 10.089688 # Average number of references to valid blocks.
982,1047c993,1058
< system.cpu.dcache.tags.tag_accesses 63074137 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63074137 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 7802568 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7802568 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5845442 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5845442 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 183034 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 183034 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 199227 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 199227 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 13648010 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13648010 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13648010 # number of overall hits
< system.cpu.dcache.overall_hits::total 13648010 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1069193 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1069193 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 304207 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 304207 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 17214 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17214 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1373400 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1373400 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1373400 # number of overall misses
< system.cpu.dcache.overall_misses::total 1373400 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 28998201750 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 28998201750 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906246382 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10906246382 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228174000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 228174000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 39904448132 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 39904448132 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 39904448132 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 39904448132 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 8871761 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 8871761 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6149649 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6149649 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 199227 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 199227 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15021410 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15021410 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15021410 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15021410 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120516 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.120516 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049467 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.049467 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085963 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085963 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.091429 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.091429 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.091429 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.091429 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27121.578377 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 27121.578377 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35851.398495 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 35851.398495 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.141164 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.141164 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29055.226541 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 29055.226541 # average overall miss latency
---
> system.cpu.dcache.tags.tag_accesses 63073026 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63073026 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 7802461 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7802461 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5845351 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5845351 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 13647812 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13647812 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13647812 # number of overall hits
> system.cpu.dcache.overall_hits::total 13647812 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1069134 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1069134 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 304206 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 304206 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 17215 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17215 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1373340 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1373340 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1373340 # number of overall misses
> system.cpu.dcache.overall_misses::total 1373340 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 28994287250 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 28994287250 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922192632 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10922192632 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228270750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 228270750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 39916479882 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 39916479882 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 39916479882 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 39916479882 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 8871595 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 8871595 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6149557 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6149557 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15021152 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15021152 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15021152 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15021152 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120512 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.120512 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.091427 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.091427 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27119.413703 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 27119.413703 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35903.935596 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35903.935596 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13259.991287 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13259.991287 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29065.256879 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 29065.256879 # average overall miss latency
1056,1103c1067,1114
< system.cpu.dcache.writebacks::writebacks 834526 # number of writebacks
< system.cpu.dcache.writebacks::total 834526 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069193 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1069193 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304207 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304207 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17214 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17214 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1373400 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1373400 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1373400 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1373400 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26734131250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 26734131250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245126618 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245126618 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36979257868 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 36979257868 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36979257868 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 36979257868 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435455500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435455500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120516 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120516 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049467 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049467 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085963 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085963 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.091429 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.091429 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25004.027570 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25004.027570 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33678.142245 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33678.142245 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11254.327873 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11254.327873 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 834448 # number of writebacks
> system.cpu.dcache.writebacks::total 834448 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069134 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1069134 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304206 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304206 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17215 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17215 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1373340 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1373340 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1373340 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1373340 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26730348750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 26730348750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10261067368 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10261067368 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193828250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193828250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36991416118 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 36991416118 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36991416118 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 36991416118 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424273000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009178000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009178000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433451000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433451000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120512 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120512 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049468 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049468 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25001.869504 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25001.869504 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33730.654123 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33730.654123 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11259.265176 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11259.265176 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency
1111,1113c1122,1123
< system.cpu.toL2Bus.throughput 106562255 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 2021905 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2021888 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2021774 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2021757 # Transaction distribution
1116,1117c1126,1127
< system.cpu.toL2Bus.trans_dist::Writeback 834526 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41563 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 834448 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41564 # Transaction distribution
1120,1130c1130,1150
< system.cpu.toL2Bus.trans_dist::ReadExReq 304190 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 304190 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856770 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649068 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 5505838 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59416000 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142462412 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 201878412 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 201868428 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 2671296 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 2424407500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 304189 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 304189 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856624 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648872 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 5505496 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59411328 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142453644 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 201864972 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 41913 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3195062 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.013063 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.113544 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 3153325 98.69% 98.69% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 41737 1.31% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3195062 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2424224500 # Layer occupancy (ticks)
1134c1154
< system.cpu.toL2Bus.respLayer0.occupancy 1395179500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1395050000 # Layer occupancy (ticks)
1136c1156
< system.cpu.toL2Bus.respLayer1.occupancy 2186860632 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2186768132 # Layer occupancy (ticks)