3,5c3,5
< sim_seconds 1.920416 # Number of seconds simulated
< sim_ticks 1920416181000 # Number of ticks simulated
< final_tick 1920416181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.919447 # Number of seconds simulated
> sim_ticks 1919446558000 # Number of ticks simulated
> final_tick 1919446558000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1752736 # Simulator instruction rate (inst/s)
< host_op_rate 1752735 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 59896862792 # Simulator tick rate (ticks/s)
< host_mem_usage 308520 # Number of bytes of host memory used
< host_seconds 32.06 # Real time elapsed on the host
< sim_insts 56196255 # Number of instructions simulated
< sim_ops 56196255 # Number of ops (including micro ops) simulated
---
> host_inst_rate 885398 # Simulator instruction rate (inst/s)
> host_op_rate 885398 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 30291378157 # Simulator tick rate (ticks/s)
> host_mem_usage 344696 # Number of bytes of host memory used
> host_seconds 63.37 # Real time elapsed on the host
> sim_insts 56104177 # Number of instructions simulated
> sim_ops 56104177 # Number of ops (including micro ops) simulated
17c17
< system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 24858240 # Number of bytes read from this memory
19c19
< system.physmem.bytes_read::total 28363328 # Number of bytes read from this memory
---
> system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory
22,23c22,23
< system.physmem.bytes_written::writebacks 7405888 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7405888 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 7404032 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7404032 # Number of bytes written to this memory
25c25
< system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 388410 # Number of read requests responded to by this memory
27,52c27,52
< system.physmem.num_reads::total 443177 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 115717 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 115717 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 443004 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 12945227 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 1381134 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 14769365 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 443004 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 443004 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3856397 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3856397 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3856397 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 443004 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 12945227 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1381134 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 18625763 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 443177 # Number of read requests accepted
< system.physmem.writeReqs 115717 # Number of write requests accepted
< system.physmem.readBursts 443177 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 115717 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 28355584 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7404416 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 28363328 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7405888 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 115688 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 115688 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 443228 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 12950733 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 1381832 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 14775792 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 443228 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 443228 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3857379 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3857379 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3857379 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 443228 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 12950733 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 1381832 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 18633171 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 443146 # Number of read requests accepted
> system.physmem.writeReqs 115688 # Number of write requests accepted
> system.physmem.readBursts 443146 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 115688 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 28353856 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7402304 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 28361344 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7404032 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue
55,86c55,86
< system.physmem.perBankRdBursts::0 27851 # Per bank write bursts
< system.physmem.perBankRdBursts::1 28132 # Per bank write bursts
< system.physmem.perBankRdBursts::2 28319 # Per bank write bursts
< system.physmem.perBankRdBursts::3 28010 # Per bank write bursts
< system.physmem.perBankRdBursts::4 27531 # Per bank write bursts
< system.physmem.perBankRdBursts::5 27552 # Per bank write bursts
< system.physmem.perBankRdBursts::6 26732 # Per bank write bursts
< system.physmem.perBankRdBursts::7 26855 # Per bank write bursts
< system.physmem.perBankRdBursts::8 27890 # Per bank write bursts
< system.physmem.perBankRdBursts::9 27110 # Per bank write bursts
< system.physmem.perBankRdBursts::10 27744 # Per bank write bursts
< system.physmem.perBankRdBursts::11 27465 # Per bank write bursts
< system.physmem.perBankRdBursts::12 27482 # Per bank write bursts
< system.physmem.perBankRdBursts::13 28199 # Per bank write bursts
< system.physmem.perBankRdBursts::14 28116 # Per bank write bursts
< system.physmem.perBankRdBursts::15 28068 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7630 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7636 # Per bank write bursts
< system.physmem.perBankWrBursts::2 7854 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7535 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7127 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6994 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6317 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6319 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7309 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6529 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7110 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6915 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7060 # Per bank write bursts
< system.physmem.perBankWrBursts::13 7819 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7860 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7680 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 27768 # Per bank write bursts
> system.physmem.perBankRdBursts::1 28019 # Per bank write bursts
> system.physmem.perBankRdBursts::2 28336 # Per bank write bursts
> system.physmem.perBankRdBursts::3 28020 # Per bank write bursts
> system.physmem.perBankRdBursts::4 27518 # Per bank write bursts
> system.physmem.perBankRdBursts::5 27546 # Per bank write bursts
> system.physmem.perBankRdBursts::6 26737 # Per bank write bursts
> system.physmem.perBankRdBursts::7 26852 # Per bank write bursts
> system.physmem.perBankRdBursts::8 27860 # Per bank write bursts
> system.physmem.perBankRdBursts::9 27104 # Per bank write bursts
> system.physmem.perBankRdBursts::10 27841 # Per bank write bursts
> system.physmem.perBankRdBursts::11 27413 # Per bank write bursts
> system.physmem.perBankRdBursts::12 27378 # Per bank write bursts
> system.physmem.perBankRdBursts::13 28201 # Per bank write bursts
> system.physmem.perBankRdBursts::14 28236 # Per bank write bursts
> system.physmem.perBankRdBursts::15 28200 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7550 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7529 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7869 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7540 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7115 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6983 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6321 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6313 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7293 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6538 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7205 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6861 # Per bank write bursts
> system.physmem.perBankWrBursts::12 6964 # Per bank write bursts
> system.physmem.perBankWrBursts::13 7821 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7979 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7780 # Per bank write bursts
89c89
< system.physmem.totGap 1920404309000 # Total gap between requests
---
> system.physmem.totGap 1919434637000 # Total gap between requests
96c96
< system.physmem.readPktSize::6 443177 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 443146 # Read request sizes (log2)
103,124c103,124
< system.physmem.writePktSize::6 115717 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 402196 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 1714 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 1586 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 1056 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 1122 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 4268 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 3790 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 3793 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3969 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2575 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 2119 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 2033 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1897 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1793 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 1556 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1524 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 1560 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 1710 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 1268 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 115688 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 401962 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 1642 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 2685 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1248 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 1966 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 3974 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 2507 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 2187 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 2134 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 2102 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1622 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 1616 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 1907 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 1876 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 2136 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 1224 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 966 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 883 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see
151,274c151,271
< system.physmem.wrQLenPdf::15 1547 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 1870 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 2302 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4388 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4414 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4425 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4435 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 4520 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 4492 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 4550 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 6087 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 4874 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6417 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5284 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5514 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5555 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5389 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1138 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 1092 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 1057 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 1105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 1067 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1057 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 1183 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1517 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1561 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1644 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1709 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 1772 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 1718 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 1911 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 1872 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 1806 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 1830 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 1705 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 1482 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 1269 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 917 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 667 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 286 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 25 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 46117 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 658.429646 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 435.074403 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 420.347464 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 7559 16.39% 16.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 6338 13.74% 30.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 2663 5.77% 35.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1600 3.47% 39.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 1319 2.86% 42.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 861 1.87% 44.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 594 1.29% 45.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 461 1.00% 46.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 24722 53.61% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 46117 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6598 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 67.149288 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2598.278449 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-8191 6595 99.95% 99.95% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6598 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6598 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.534707 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.278859 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 3.820387 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 4179 63.34% 63.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 322 4.88% 68.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 428 6.49% 74.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 1303 19.75% 94.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 22 0.33% 94.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 17 0.26% 95.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 11 0.17% 95.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 27 0.41% 95.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 43 0.65% 96.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 28 0.42% 96.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 21 0.32% 97.01% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::27 25 0.38% 97.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28 19 0.29% 97.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::29 43 0.65% 98.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::30 4 0.06% 98.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::31 12 0.18% 98.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32 10 0.15% 98.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::33 1 0.02% 98.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::34 5 0.08% 98.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::35 4 0.06% 98.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::37 5 0.08% 99.01% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::38 2 0.03% 99.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::39 9 0.14% 99.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40 4 0.06% 99.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::41 4 0.06% 99.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::42 1 0.02% 99.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::43 2 0.03% 99.35% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44 3 0.05% 99.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::45 1 0.02% 99.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::46 1 0.02% 99.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::47 6 0.09% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48 8 0.12% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::49 5 0.08% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::50 6 0.09% 99.80% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52 3 0.05% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::53 1 0.02% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::54 4 0.06% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::55 2 0.03% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56 1 0.02% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::57 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::58 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6598 # Writes before turning the bus around for reads
< system.physmem.totQLat 7790286250 # Total ticks spent queuing
< system.physmem.totMemAccLat 16274878750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2215280000 # Total ticks spent in databus transfers
< system.physmem.totBankLat 6269312500 # Total ticks spent accessing banks
< system.physmem.avgQLat 17583.07 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 14150.16 # Average bank access latency per DRAM burst
---
> system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1478 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4562 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4579 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4593 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4592 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4608 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 4699 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 4858 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 4946 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 5128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 5326 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 5448 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5540 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5685 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5621 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5715 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 897 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 915 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 934 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 861 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 945 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1033 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 949 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1139 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1162 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1146 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1232 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1390 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1625 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1897 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 2098 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 1909 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 1878 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 1683 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 1684 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 1800 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 1629 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 867 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 418 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 235 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 155 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 538.261302 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 328.855989 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 417.099114 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 14887 22.41% 22.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 11472 17.27% 39.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 4684 7.05% 46.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3132 4.71% 51.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3072 4.62% 56.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1874 2.82% 58.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1342 2.02% 60.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1444 2.17% 63.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 24522 36.91% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6775 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 65.389077 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 16.529238 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2564.130292 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-8191 6772 99.96% 99.96% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6775 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6775 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.071734 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.848509 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 3.695111 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 5062 74.72% 74.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 127 1.87% 76.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 1207 17.82% 94.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 25 0.37% 94.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 12 0.18% 94.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 16 0.24% 95.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 18 0.27% 95.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 98 1.45% 96.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 41 0.61% 97.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 20 0.30% 98.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::27 8 0.12% 98.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28 7 0.10% 98.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::29 8 0.12% 98.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::30 7 0.10% 98.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::31 15 0.22% 98.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32 9 0.13% 98.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::33 1 0.01% 98.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::34 1 0.01% 98.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::35 1 0.01% 98.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::37 1 0.01% 98.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::38 1 0.01% 99.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::39 4 0.06% 99.06% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40 9 0.13% 99.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::41 8 0.12% 99.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::42 2 0.03% 99.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::43 2 0.03% 99.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44 2 0.03% 99.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::45 1 0.01% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::47 8 0.12% 99.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48 7 0.10% 99.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::49 1 0.01% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::50 2 0.03% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::51 2 0.03% 99.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52 1 0.01% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::54 1 0.01% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56 7 0.10% 99.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::57 9 0.13% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::59 1 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6775 # Writes before turning the bus around for reads
> system.physmem.totQLat 7315796250 # Total ticks spent queuing
> system.physmem.totMemAccLat 15622590000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2215145000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 16513.13 # Average queueing delay per DRAM burst
276c273
< system.physmem.avgMemAccLat 36733.23 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 35263.13 # Average memory access latency per DRAM burst
279c276
< system.physmem.avgRdBWSys 14.77 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 14.78 # Average system read bandwidth in MiByte/s
286,299c283,300
< system.physmem.avgWrQLen 24.59 # Average write queue length when enqueuing
< system.physmem.readRowHits 398457 # Number of row buffer hits during reads
< system.physmem.writeRowHits 94179 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 81.39 # Row buffer hit rate for writes
< system.physmem.avgGap 3436079.67 # Average gap between requests
< system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined
< system.physmem.prechargeAllPercent 0.57 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 18667397 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 292363 # Transaction distribution
< system.membus.trans_dist::ReadResp 292363 # Transaction distribution
< system.membus.trans_dist::WriteReq 9650 # Transaction distribution
< system.membus.trans_dist::WriteResp 9650 # Transaction distribution
< system.membus.trans_dist::Writeback 115717 # Transaction distribution
---
> system.physmem.avgWrQLen 23.40 # Average write queue length when enqueuing
> system.physmem.readRowHits 398273 # Number of row buffer hits during reads
> system.physmem.writeRowHits 93988 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 81.24 # Row buffer hit rate for writes
> system.physmem.avgGap 3434713.42 # Average gap between requests
> system.physmem.pageHitRate 88.11 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 1800016178000 # Time in different power states
> system.physmem.memoryStateTime::REF 64094420000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 55332653250 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 18674823 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 292356 # Transaction distribution
> system.membus.trans_dist::ReadResp 292356 # Transaction distribution
> system.membus.trans_dist::WriteReq 9649 # Transaction distribution
> system.membus.trans_dist::WriteResp 9649 # Transaction distribution
> system.membus.trans_dist::Writeback 115688 # Transaction distribution
302,306c303,307
< system.membus.trans_dist::ReadExReq 158297 # Transaction distribution
< system.membus.trans_dist::ReadExResp 158297 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878206 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911366 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadExReq 158273 # Transaction distribution
> system.membus.trans_dist::ReadExResp 158273 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878115 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911273 # Packet count per connected master and slave (bytes)
309,312c310,313
< system.membus.pkt_count::total 1036046 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30460096 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30504660 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1035953 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456256 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30500812 # Cumulative packet size per connected master and slave (bytes)
315,316c316,317
< system.membus.tot_pkt_size::total 35813780 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 35813780 # Total data (bytes)
---
> system.membus.tot_pkt_size::total 35809932 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 35809932 # Total data (bytes)
318c319
< system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 32376000 # Layer occupancy (ticks)
320c321
< system.membus.reqLayer1.occupancy 1492987250 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1491996000 # Layer occupancy (ticks)
322c323
< system.membus.respLayer1.occupancy 3752965347 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 3751677600 # Layer occupancy (ticks)
324c325
< system.membus.respLayer2.occupancy 376688000 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 376660500 # Layer occupancy (ticks)
327c328
< system.iocache.tags.tagsinuse 1.344147 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.344872 # Cycle average of tags in use
331,334c332,335
< system.iocache.tags.warmup_cycle 1754500427000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 1.344147 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.084009 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.084009 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1753525004000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 1.344872 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.084054 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.084054 # Average percentage of cache occupancy
348,355c349,356
< system.iocache.ReadReq_miss_latency::tsunami.ide 21134633 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21134633 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::tsunami.ide 13148459442 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 13148459442 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 13169594075 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 13169594075 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 13169594075 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 13169594075 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21253133 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21253133 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::tsunami.ide 12447285431 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 12447285431 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 12468538564 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 12468538564 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 12468538564 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 12468538564 # number of overall miss cycles
372,380c373,381
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122165.508671 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 122165.508671 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316433.852570 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 316433.852570 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 315628.378071 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 315628.378071 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 393896 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122850.479769 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 122850.479769 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299559.237365 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 299559.237365 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 298826.568340 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 298826.568340 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 365803 # number of cycles access was blocked
382c383
< system.iocache.blocked::no_mshrs 28296 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 28265 # number of cycles access was blocked
384c385
< system.iocache.avg_blocked_cycles::no_mshrs 13.920554 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 12.941907 # average number of cycles each access was blocked
398,405c399,406
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137633 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12137633 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10985430442 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 10985430442 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 10997568075 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 10997568075 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 10997568075 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 10997568075 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12255133 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12255133 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10284312431 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 10284312431 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 10296567564 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 10296567564 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 10296567564 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 10296567564 # number of overall MSHR miss cycles
414,421c415,422
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70159.728324 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 70159.728324 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264377.898585 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 264377.898585 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70838.919075 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 70838.919075 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247504.631089 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 247504.631089 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency
440,441c441,442
< system.cpu.dtb.read_hits 9066711 # DTB read hits
< system.cpu.dtb.read_misses 10324 # DTB read misses
---
> system.cpu.dtb.read_hits 9052923 # DTB read hits
> system.cpu.dtb.read_misses 10354 # DTB read misses
443,445c444,446
< system.cpu.dtb.read_accesses 728853 # DTB read accesses
< system.cpu.dtb.write_hits 6357503 # DTB write hits
< system.cpu.dtb.write_misses 1142 # DTB write misses
---
> system.cpu.dtb.read_accesses 728911 # DTB read accesses
> system.cpu.dtb.write_hits 6349403 # DTB write hits
> system.cpu.dtb.write_misses 1143 # DTB write misses
447,449c448,450
< system.cpu.dtb.write_accesses 291931 # DTB write accesses
< system.cpu.dtb.data_hits 15424214 # DTB hits
< system.cpu.dtb.data_misses 11466 # DTB misses
---
> system.cpu.dtb.write_accesses 291932 # DTB write accesses
> system.cpu.dtb.data_hits 15402326 # DTB hits
> system.cpu.dtb.data_misses 11497 # DTB misses
451,452c452,453
< system.cpu.dtb.data_accesses 1020784 # DTB accesses
< system.cpu.itb.fetch_hits 4974520 # ITB hits
---
> system.cpu.dtb.data_accesses 1020843 # DTB accesses
> system.cpu.itb.fetch_hits 4974965 # ITB hits
455c456
< system.cpu.itb.fetch_accesses 4979530 # ITB accesses
---
> system.cpu.itb.fetch_accesses 4979975 # ITB accesses
468c469
< system.cpu.numCycles 3840832362 # number of cpu cycles simulated
---
> system.cpu.numCycles 3838893116 # number of cpu cycles simulated
471,490c472,526
< system.cpu.committedInsts 56196255 # Number of instructions committed
< system.cpu.committedOps 56196255 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 52067788 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses
< system.cpu.num_func_calls 1483738 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 6469789 # number of instructions that are conditional controls
< system.cpu.num_int_insts 52067788 # number of integer instructions
< system.cpu.num_fp_insts 324393 # number of float instructions
< system.cpu.num_int_register_reads 71342399 # number of times the integer registers were read
< system.cpu.num_int_register_writes 38531411 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read
< system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written
< system.cpu.num_mem_refs 15476821 # number of memory refs
< system.cpu.num_load_insts 9103557 # Number of load instructions
< system.cpu.num_store_insts 6373264 # Number of store instructions
< system.cpu.num_idle_cycles 3589010980.998131 # Number of idle cycles
< system.cpu.num_busy_cycles 251821381.001869 # Number of busy cycles
< system.cpu.not_idle_fraction 0.065564 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.934436 # Percentage of idle cycles
< system.cpu.Branches 8424076 # Number of branches fetched
---
> system.cpu.committedInsts 56104177 # Number of instructions committed
> system.cpu.committedOps 56104177 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 51979169 # Number of integer alu accesses
> system.cpu.num_fp_alu_accesses 324594 # Number of float alu accesses
> system.cpu.num_func_calls 1481286 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 6461218 # number of instructions that are conditional controls
> system.cpu.num_int_insts 51979169 # number of integer instructions
> system.cpu.num_fp_insts 324594 # number of float instructions
> system.cpu.num_int_register_reads 71209746 # number of times the integer registers were read
> system.cpu.num_int_register_writes 38460532 # number of times the integer registers were written
> system.cpu.num_fp_register_reads 163708 # number of times the floating registers were read
> system.cpu.num_fp_register_writes 166588 # number of times the floating registers were written
> system.cpu.num_mem_refs 15454993 # number of memory refs
> system.cpu.num_load_insts 9089820 # Number of load instructions
> system.cpu.num_store_insts 6365173 # Number of store instructions
> system.cpu.num_idle_cycles 3587243859.498131 # Number of idle cycles
> system.cpu.num_busy_cycles 251649256.501869 # Number of busy cycles
> system.cpu.not_idle_fraction 0.065553 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.934447 # Percentage of idle cycles
> system.cpu.Branches 8413035 # Number of branches fetched
> system.cpu.op_class::No_OpClass 3197761 5.70% 5.70% # Class of executed instruction
> system.cpu.op_class::IntAlu 36186344 64.48% 70.18% # Class of executed instruction
> system.cpu.op_class::IntMult 61011 0.11% 70.29% # Class of executed instruction
> system.cpu.op_class::IntDiv 0 0.00% 70.29% # Class of executed instruction
> system.cpu.op_class::FloatAdd 25613 0.05% 70.34% # Class of executed instruction
> system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction
> system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction
> system.cpu.op_class::MemRead 9316905 16.60% 86.95% # Class of executed instruction
> system.cpu.op_class::MemWrite 6371245 11.35% 98.30% # Class of executed instruction
> system.cpu.op_class::IprAccess 953526 1.70% 100.00% # Class of executed instruction
> system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
> system.cpu.op_class::total 56116041 # Class of executed instruction
493,494c529,530
< system.cpu.kern.inst.hwrei 212001 # number of hwrei instructions executed
< system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl
---
> system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed
> system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl
496,499c532,535
< system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl
< system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl
< system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl
---
> system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::31 106210 57.99% 100.00% # number of times we switched to this ipl
> system.cpu.kern.ipl_count::total 183167 # number of times we switched to this ipl
> system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl
501,509c537,545
< system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl
< system.cpu.kern.ipl_ticks::0 1858066400000 96.75% 96.75% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::21 91407000 0.00% 96.76% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::22 737349500 0.04% 96.80% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::31 61520290500 3.20% 100.00% # number of cycles we spent at this ipl
< system.cpu.kern.ipl_ticks::total 1920415447000 # number of cycles we spent at this ipl
< system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl
> system.cpu.kern.ipl_ticks::0 1857252195000 96.76% 96.76% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::21 91387500 0.00% 96.76% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::22 737178000 0.04% 96.80% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::31 61365063500 3.20% 100.00% # number of cycles we spent at this ipl
> system.cpu.kern.ipl_ticks::total 1919445824000 # number of cycles we spent at this ipl
> system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl
512,513c548,549
< system.cpu.kern.ipl_used::31 0.692248 # fraction of swpipl calls that actually changed the ipl
< system.cpu.kern.ipl_used::total 0.814083 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu.kern.ipl_used::31 0.692289 # fraction of swpipl calls that actually changed the ipl
> system.cpu.kern.ipl_used::total 0.814110 # fraction of swpipl calls that actually changed the ipl
549,550c585,586
< system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed
< system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
---
> system.cpu.kern.callpal::swpctx 4179 2.17% 2.17% # number of callpals executed
> system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
552,553c588,589
< system.cpu.kern.callpal::swpipl 175963 91.22% 93.41% # number of callpals executed
< system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed
---
> system.cpu.kern.callpal::swpipl 175948 91.21% 93.41% # number of callpals executed
> system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
556c592
< system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
---
> system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
558c594
< system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed
---
> system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
561c597
< system.cpu.kern.callpal::total 192909 # number of callpals executed
---
> system.cpu.kern.callpal::total 192895 # number of callpals executed
564,565c600,601
< system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
< system.cpu.kern.mode_good::kernel 1911
---
> system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
> system.cpu.kern.mode_good::kernel 1912
567,568c603,604
< system.cpu.kern.mode_good::idle 170
< system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches
---
> system.cpu.kern.mode_good::idle 171
> system.cpu.kern.mode_switch_good::kernel 0.323848 # fraction of useful protection mode switches
570,575c606,611
< system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
< system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches
< system.cpu.kern.mode_ticks::kernel 46067941500 2.40% 2.40% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::user 5182686000 0.27% 2.67% # number of ticks spent at the given mode
< system.cpu.kern.mode_ticks::idle 1869164817500 97.33% 100.00% # number of ticks spent at the given mode
< system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---
> system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
> system.cpu.kern.mode_switch_good::total 0.392527 # fraction of useful protection mode switches
> system.cpu.kern.mode_ticks::kernel 46108525500 2.40% 2.40% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::user 5189217000 0.27% 2.67% # number of ticks spent at the given mode
> system.cpu.kern.mode_ticks::idle 1868148079500 97.33% 100.00% # number of ticks spent at the given mode
> system.cpu.kern.swap_context 4180 # number of times the context was actually changed
607c643
< system.iobus.throughput 1409159 # Throughput (bytes/s)
---
> system.iobus.throughput 1409867 # Throughput (bytes/s)
610,612c646,648
< system.iobus.trans_dist::WriteReq 51202 # Transaction distribution
< system.iobus.trans_dist::WriteResp 51202 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::WriteReq 51201 # Transaction distribution
> system.iobus.trans_dist::WriteResp 51201 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes)
624c660
< system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes)
627,628c663,664
< system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
640c676
< system.iobus.tot_pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes)
643,645c679,681
< system.iobus.tot_pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 2706172 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks)
---
> system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 2706164 # Total data (bytes)
> system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
667c703
< system.iobus.reqLayer29.occupancy 380034075 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 380199064 # Layer occupancy (ticks)
671c707
< system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks)
673c709
< system.iobus.respLayer1.occupancy 43162000 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 43233500 # Layer occupancy (ticks)
675,683c711,719
< system.cpu.icache.tags.replacements 928494 # number of replacements
< system.cpu.icache.tags.tagsinuse 508.301721 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 55278924 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 929005 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 59.503365 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 39895254250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 508.301721 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.992777 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.992777 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 927875 # number of replacements
> system.cpu.icache.tags.tagsinuse 508.303976 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 55187496 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 928386 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 59.444559 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 39855277250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 508.303976 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy
686,687c722,723
< system.cpu.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id
690,727c726,763
< system.cpu.icache.tags.tag_accesses 57137254 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 57137254 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 55278924 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 55278924 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 55278924 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 55278924 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 55278924 # number of overall hits
< system.cpu.icache.overall_hits::total 55278924 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 929165 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 929165 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 929165 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 929165 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 929165 # number of overall misses
< system.cpu.icache.overall_misses::total 929165 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12919006759 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12919006759 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12919006759 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12919006759 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12919006759 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12919006759 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 56208089 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 56208089 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 56208089 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 56208089 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 56208089 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 56208089 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016531 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.016531 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.016531 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.016531 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.016531 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.016531 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.888716 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13903.888716 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13903.888716 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13903.888716 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 57044588 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 57044588 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 55187496 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 55187496 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 55187496 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 55187496 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 55187496 # number of overall hits
> system.cpu.icache.overall_hits::total 55187496 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 928546 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 928546 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 928546 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 928546 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 928546 # number of overall misses
> system.cpu.icache.overall_misses::total 928546 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12910342260 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12910342260 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12910342260 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12910342260 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12910342260 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12910342260 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 56116042 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 56116042 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 56116042 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 56116042 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 56116042 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 56116042 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016547 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.016547 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.016547 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.016547 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.016547 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.016547 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.826262 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13903.826262 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13903.826262 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13903.826262 # average overall miss latency
736,759c772,795
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929165 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 929165 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 929165 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 929165 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 929165 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 929165 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11055577241 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 11055577241 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11055577241 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 11055577241 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11055577241 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 11055577241 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016531 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.016531 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.016531 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.400436 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.400436 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928546 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 928546 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 928546 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 928546 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 928546 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 928546 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048086740 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 11048086740 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048086740 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 11048086740 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11048086740 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 11048086740 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016547 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.016547 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.016547 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.265396 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.265396 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency
761,775c797,811
< system.cpu.l2cache.tags.replacements 336265 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65295.577509 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2447728 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 401427 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 6.097567 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 6793166750 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 55588.679267 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 4757.001179 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 4949.897063 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.848216 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072586 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.075529 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.996331 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.replacements 336232 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65296.289611 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2446119 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 401393 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 6.094075 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 55555.447127 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 4766.385283 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 4974.457201 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.847709 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072729 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.075904 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.996342 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65161 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
777,787c813,823
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4882 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3251 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55777 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 25952661 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 25952661 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 915852 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 814775 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1730627 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 835359 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 835359 # number of Writeback hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4875 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3257 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55778 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994278 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 25936539 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 25936539 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 915233 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 814520 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1729753 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 834591 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 834591 # number of Writeback hits
790,797c826,833
< system.cpu.l2cache.ReadExReq_hits::cpu.data 187681 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 187681 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 915852 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1002456 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1918308 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 915852 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1002456 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1918308 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 187383 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 187383 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 915233 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1001903 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1917136 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 915233 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1001903 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1917136 # number of overall hits
799,800c835,836
< system.cpu.l2cache.ReadReq_misses::cpu.data 271967 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 285260 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.data 271960 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 285253 # number of ReadReq misses
803,804c839,840
< system.cpu.l2cache.ReadExReq_misses::cpu.data 116864 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 116864 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 116840 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 116840 # number of ReadExReq misses
806,807c842,843
< system.cpu.l2cache.demand_misses::cpu.data 388831 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 402124 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 388800 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 402093 # number of demand (read+write) misses
809,813c845,849
< system.cpu.l2cache.overall_misses::cpu.data 388831 # number of overall misses
< system.cpu.l2cache.overall_misses::total 402124 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 967872241 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17714808491 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 18682680732 # number of ReadReq miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.data 388800 # number of overall misses
> system.cpu.l2cache.overall_misses::total 402093 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 967190740 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17699357246 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 18666547986 # number of ReadReq miss cycles
816,828c852,864
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8011039626 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 8011039626 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 967872241 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 25725848117 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 26693720358 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 967872241 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 25725848117 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 26693720358 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 929145 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1086742 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2015887 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 835359 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 835359 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8068029125 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 8068029125 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 967190740 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 25767386371 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 26734577111 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 967190740 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 25767386371 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 26734577111 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 928526 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1086480 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2015006 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 834591 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 834591 # number of Writeback accesses(hits+misses)
831,841c867,877
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 304545 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 304545 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 929145 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1391287 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2320432 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 929145 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1391287 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2320432 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014307 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250259 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.141506 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 304223 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 304223 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 928526 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1390703 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2319229 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 928526 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1390703 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2319229 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014316 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250313 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.141564 # miss rate for ReadReq accesses
844,854c880,890
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383733 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.383733 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014307 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.279476 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.173297 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014307 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.279476 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.173297 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72810.670353 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65135.874908 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 65493.517254 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384060 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.384060 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014316 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.279571 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.173374 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014316 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.279571 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.173374 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72759.402693 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65080.737042 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 65438.568520 # average ReadReq miss latency
857,864c893,900
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68550.106329 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68550.106329 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72810.670353 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66162.029563 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 66381.813465 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72810.670353 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66162.029563 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 66381.813465 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69051.943898 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69051.943898 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72759.402693 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66274.141901 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 66488.541484 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72759.402693 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66274.141901 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 66488.541484 # average overall miss latency
873,874c909,910
< system.cpu.l2cache.writebacks::writebacks 74205 # number of writebacks
< system.cpu.l2cache.writebacks::total 74205 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 74176 # number of writebacks
> system.cpu.l2cache.writebacks::total 74176 # number of writebacks
876,877c912,913
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271967 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 285260 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271960 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 285253 # number of ReadReq MSHR misses
880,881c916,917
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116864 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 116864 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116840 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 116840 # number of ReadExReq MSHR misses
883,884c919,920
< system.cpu.l2cache.demand_mshr_misses::cpu.data 388831 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 402124 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 388800 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 402093 # number of demand (read+write) MSHR misses
886,890c922,926
< system.cpu.l2cache.overall_mshr_misses::cpu.data 388831 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 402124 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 801329759 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14314442009 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15115771768 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 388800 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 402093 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 800656260 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14299493254 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15100149514 # number of ReadReq MSHR miss cycles
893,909c929,945
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6549827374 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6549827374 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 801329759 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20864269383 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 21665599142 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 801329759 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20864269383 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 21665599142 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895641500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895641500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141506 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607242375 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607242375 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 800656260 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20906735629 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 21707391889 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 800656260 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20906735629 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 21707391889 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895432500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895432500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229578000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229578000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250313 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141564 # mshr miss rate for ReadReq accesses
912,922c948,958
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383733 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383733 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.173297 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.173297 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60282.085233 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52633.010656 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52989.454421 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384060 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384060 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.173374 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279571 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.173374 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60231.419544 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52579.398640 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52935.988452 # average ReadReq mshr miss latency
925,932c961,968
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56046.578707 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56046.578707 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56549.489687 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56549.489687 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency
940,946c976,982
< system.cpu.dcache.tags.replacements 1390774 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.978892 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 14051964 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1391286 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 10.099982 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 107796250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.978892 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.replacements 1390190 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.978877 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 14030691 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1390702 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 10.088927 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.978877 # Average occupied blocks per requestor
954,1019c990,1055
< system.cpu.dcache.tags.tag_accesses 63164291 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 63164291 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 7816324 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 7816324 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 5853358 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 5853358 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 183027 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 183027 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 13669682 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 13669682 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 13669682 # number of overall hits
< system.cpu.dcache.overall_hits::total 13669682 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1069509 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1069509 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 304562 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 304562 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 17233 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 17233 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 1374071 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1374071 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1374071 # number of overall misses
< system.cpu.dcache.overall_misses::total 1374071 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 29019471009 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 29019471009 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10854033885 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10854033885 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228736500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 228736500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 39873504894 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 39873504894 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 39873504894 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 39873504894 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 8885833 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 8885833 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 6157920 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 6157920 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200260 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 200260 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 15043753 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 15043753 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 15043753 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 15043753 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120361 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.120361 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086053 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086053 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27133.451901 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 27133.451901 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35638.175101 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 35638.175101 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.167760 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.167760 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29018.518617 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 29018.518617 # average overall miss latency
---
> system.cpu.dcache.tags.tag_accesses 63076279 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 63076279 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 7802806 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 7802806 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 5845593 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 5845593 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 183040 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 183040 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 199235 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 199235 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 13648399 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 13648399 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 13648399 # number of overall hits
> system.cpu.dcache.overall_hits::total 13648399 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1069264 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1069264 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 304240 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 304240 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 17216 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 17216 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 1373504 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1373504 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1373504 # number of overall misses
> system.cpu.dcache.overall_misses::total 1373504 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 29001409504 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 29001409504 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 10907701386 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 10907701386 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228213250 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 228213250 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 39909110890 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 39909110890 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 39909110890 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 39909110890 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 8872070 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 8872070 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 6149833 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 6149833 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200256 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 200256 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 199235 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 199235 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 15021903 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 15021903 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 15021903 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 15021903 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120520 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.120520 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049471 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.049471 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.091433 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.091433 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.091433 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.091433 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27122.777447 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 27122.777447 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35852.292223 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35852.292223 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.881157 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.881157 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29056.421306 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 29056.421306 # average overall miss latency
1028,1075c1064,1111
< system.cpu.dcache.writebacks::writebacks 835359 # number of writebacks
< system.cpu.dcache.writebacks::total 835359 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069509 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1069509 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304562 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 304562 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17233 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 17233 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1374071 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1374071 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1374071 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1374071 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26755042991 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 26755042991 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10192844115 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10192844115 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194257500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194257500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36947887106 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 36947887106 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36947887106 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 36947887106 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011441500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011441500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120361 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120361 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086053 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086053 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25016.192469 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25016.192469 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33467.222158 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33467.222158 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.413393 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.413393 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 834591 # number of writebacks
> system.cpu.dcache.writebacks::total 834591 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069264 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1069264 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304240 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 304240 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17216 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 17216 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1373504 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1373504 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1373504 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1373504 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26737269496 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 26737269496 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10246531614 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10246531614 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193767750 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193767750 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36983801110 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 36983801110 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36983801110 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 36983801110 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011220500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011220500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435456000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435456000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120520 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120520 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049471 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.091433 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.091433 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25005.302242 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25005.302242 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33679.107330 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33679.107330 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11255.097003 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11255.097003 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency
1083,1088c1119,1124
< system.cpu.toL2Bus.throughput 105199341 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 2023010 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2022993 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 835359 # Transaction distribution
---
> system.cpu.toL2Bus.throughput 105186760 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 2022129 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2022112 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 834591 # Transaction distribution
1091,1099c1127,1135
< system.cpu.toL2Bus.trans_dist::ReadExReq 346097 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 304546 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858310 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651284 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 5509594 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59465280 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142559956 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 202025236 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 202015188 # Total data (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 345775 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 304224 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857072 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649346 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 5506418 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59425664 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142473420 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size::total 201899084 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 201889036 # Total data (bytes)
1101c1137
< system.cpu.toL2Bus.reqLayer0.occupancy 2426388000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.reqLayer0.occupancy 2424633500 # Layer occupancy (ticks)
1105c1141
< system.cpu.toL2Bus.respLayer0.occupancy 1396297259 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1395400760 # Layer occupancy (ticks)
1107c1143
< system.cpu.toL2Bus.respLayer1.occupancy 2187438394 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2186975140 # Layer occupancy (ticks)