1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.915549 # Number of seconds simulated
4sim_ticks 1915548867000 # Number of ticks simulated
5final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.915549 # Number of seconds simulated
4sim_ticks 1915548867000 # Number of ticks simulated
5final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1998214 # Simulator instruction rate (inst/s)
8host_op_rate 1998212 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 68184353129 # Simulator tick rate (ticks/s)
10host_mem_usage 288188 # Number of bytes of host memory used
11host_seconds 28.09 # Real time elapsed on the host
| 7host_inst_rate 646342 # Simulator instruction rate (inst/s)
8host_op_rate 646342 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 22054916762 # Simulator tick rate (ticks/s)
10host_mem_usage 292620 # Number of bytes of host memory used
11host_seconds 86.85 # Real time elapsed on the host
|
12sim_insts 56137087 # Number of instructions simulated
13sim_ops 56137087 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 29663360 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 10122368 # Number of bytes written to this memory
17system.physmem.num_reads 463490 # Number of read requests responded to by this memory
18system.physmem.num_writes 158162 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 15485567 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 492308 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 5284317 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 20769884 # Total bandwidth to/from this memory (bytes/s)
24system.l2c.replacements 389289 # number of replacements
25system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use
26system.l2c.total_refs 2311163 # Total number of references to valid blocks.
27system.l2c.sampled_refs 421794 # Sample count of references to valid blocks.
28system.l2c.avg_refs 5.479364 # Average number of references to valid blocks.
29system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit.
30system.l2c.occ_blocks::writebacks 23110.665097 # Average occupied blocks per requestor
31system.l2c.occ_blocks::cpu.inst 3746.363547 # Average occupied blocks per requestor
32system.l2c.occ_blocks::cpu.data 7495.009700 # Average occupied blocks per requestor
33system.l2c.occ_percent::writebacks 0.352641 # Average percentage of cache occupancy
34system.l2c.occ_percent::cpu.inst 0.057165 # Average percentage of cache occupancy
35system.l2c.occ_percent::cpu.data 0.114365 # Average percentage of cache occupancy
36system.l2c.occ_percent::total 0.524171 # Average percentage of cache occupancy
37system.l2c.ReadReq_hits::cpu.inst 913599 # number of ReadReq hits
38system.l2c.ReadReq_hits::cpu.data 796862 # number of ReadReq hits
39system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits
40system.l2c.Writeback_hits::writebacks 826671 # number of Writeback hits
41system.l2c.Writeback_hits::total 826671 # number of Writeback hits
42system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits
43system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits
44system.l2c.ReadExReq_hits::cpu.data 185878 # number of ReadExReq hits
45system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits
46system.l2c.demand_hits::cpu.inst 913599 # number of demand (read+write) hits
47system.l2c.demand_hits::cpu.data 982740 # number of demand (read+write) hits
48system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits
49system.l2c.overall_hits::cpu.inst 913599 # number of overall hits
50system.l2c.overall_hits::cpu.data 982740 # number of overall hits
51system.l2c.overall_hits::total 1896339 # number of overall hits
52system.l2c.ReadReq_misses::cpu.inst 14735 # number of ReadReq misses
53system.l2c.ReadReq_misses::cpu.data 289403 # number of ReadReq misses
54system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses
55system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses
56system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses
57system.l2c.ReadExReq_misses::cpu.data 118294 # number of ReadExReq misses
58system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses
59system.l2c.demand_misses::cpu.inst 14735 # number of demand (read+write) misses
60system.l2c.demand_misses::cpu.data 407697 # number of demand (read+write) misses
61system.l2c.demand_misses::total 422432 # number of demand (read+write) misses
62system.l2c.overall_misses::cpu.inst 14735 # number of overall misses
63system.l2c.overall_misses::cpu.data 407697 # number of overall misses
64system.l2c.overall_misses::total 422432 # number of overall misses
65system.l2c.ReadReq_miss_latency::cpu.inst 766261500 # number of ReadReq miss cycles
66system.l2c.ReadReq_miss_latency::cpu.data 15053945000 # number of ReadReq miss cycles
67system.l2c.ReadReq_miss_latency::total 15820206500 # number of ReadReq miss cycles
68system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles
69system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles
70system.l2c.ReadExReq_miss_latency::cpu.data 6151753000 # number of ReadExReq miss cycles
71system.l2c.ReadExReq_miss_latency::total 6151753000 # number of ReadExReq miss cycles
72system.l2c.demand_miss_latency::cpu.inst 766261500 # number of demand (read+write) miss cycles
73system.l2c.demand_miss_latency::cpu.data 21205698000 # number of demand (read+write) miss cycles
74system.l2c.demand_miss_latency::total 21971959500 # number of demand (read+write) miss cycles
75system.l2c.overall_miss_latency::cpu.inst 766261500 # number of overall miss cycles
76system.l2c.overall_miss_latency::cpu.data 21205698000 # number of overall miss cycles
77system.l2c.overall_miss_latency::total 21971959500 # number of overall miss cycles
78system.l2c.ReadReq_accesses::cpu.inst 928334 # number of ReadReq accesses(hits+misses)
79system.l2c.ReadReq_accesses::cpu.data 1086265 # number of ReadReq accesses(hits+misses)
80system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses)
81system.l2c.Writeback_accesses::writebacks 826671 # number of Writeback accesses(hits+misses)
82system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses)
83system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
84system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
85system.l2c.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses)
86system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
87system.l2c.demand_accesses::cpu.inst 928334 # number of demand (read+write) accesses
88system.l2c.demand_accesses::cpu.data 1390437 # number of demand (read+write) accesses
89system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses
90system.l2c.overall_accesses::cpu.inst 928334 # number of overall (read+write) accesses
91system.l2c.overall_accesses::cpu.data 1390437 # number of overall (read+write) accesses
92system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses
93system.l2c.ReadReq_miss_rate::cpu.inst 0.015873 # miss rate for ReadReq accesses
94system.l2c.ReadReq_miss_rate::cpu.data 0.266420 # miss rate for ReadReq accesses
95system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses
96system.l2c.ReadExReq_miss_rate::cpu.data 0.388905 # miss rate for ReadExReq accesses
97system.l2c.demand_miss_rate::cpu.inst 0.015873 # miss rate for demand accesses
98system.l2c.demand_miss_rate::cpu.data 0.293215 # miss rate for demand accesses
99system.l2c.overall_miss_rate::cpu.inst 0.015873 # miss rate for overall accesses
100system.l2c.overall_miss_rate::cpu.data 0.293215 # miss rate for overall accesses
101system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423 # average ReadReq miss latency
102system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937 # average ReadReq miss latency
103system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency
104system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884 # average ReadExReq miss latency
105system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
106system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
107system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
108system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
109system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
110system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
111system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
112system.l2c.blocked::no_targets 0 # number of cycles access was blocked
| 12sim_insts 56137087 # Number of instructions simulated
13sim_ops 56137087 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 29663360 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 10122368 # Number of bytes written to this memory
17system.physmem.num_reads 463490 # Number of read requests responded to by this memory
18system.physmem.num_writes 158162 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 15485567 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 492308 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 5284317 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 20769884 # Total bandwidth to/from this memory (bytes/s)
24system.l2c.replacements 389289 # number of replacements
25system.l2c.tagsinuse 34352.038344 # Cycle average of tags in use
26system.l2c.total_refs 2311163 # Total number of references to valid blocks.
27system.l2c.sampled_refs 421794 # Sample count of references to valid blocks.
28system.l2c.avg_refs 5.479364 # Average number of references to valid blocks.
29system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit.
30system.l2c.occ_blocks::writebacks 23110.665097 # Average occupied blocks per requestor
31system.l2c.occ_blocks::cpu.inst 3746.363547 # Average occupied blocks per requestor
32system.l2c.occ_blocks::cpu.data 7495.009700 # Average occupied blocks per requestor
33system.l2c.occ_percent::writebacks 0.352641 # Average percentage of cache occupancy
34system.l2c.occ_percent::cpu.inst 0.057165 # Average percentage of cache occupancy
35system.l2c.occ_percent::cpu.data 0.114365 # Average percentage of cache occupancy
36system.l2c.occ_percent::total 0.524171 # Average percentage of cache occupancy
37system.l2c.ReadReq_hits::cpu.inst 913599 # number of ReadReq hits
38system.l2c.ReadReq_hits::cpu.data 796862 # number of ReadReq hits
39system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits
40system.l2c.Writeback_hits::writebacks 826671 # number of Writeback hits
41system.l2c.Writeback_hits::total 826671 # number of Writeback hits
42system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits
43system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits
44system.l2c.ReadExReq_hits::cpu.data 185878 # number of ReadExReq hits
45system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits
46system.l2c.demand_hits::cpu.inst 913599 # number of demand (read+write) hits
47system.l2c.demand_hits::cpu.data 982740 # number of demand (read+write) hits
48system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits
49system.l2c.overall_hits::cpu.inst 913599 # number of overall hits
50system.l2c.overall_hits::cpu.data 982740 # number of overall hits
51system.l2c.overall_hits::total 1896339 # number of overall hits
52system.l2c.ReadReq_misses::cpu.inst 14735 # number of ReadReq misses
53system.l2c.ReadReq_misses::cpu.data 289403 # number of ReadReq misses
54system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses
55system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses
56system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses
57system.l2c.ReadExReq_misses::cpu.data 118294 # number of ReadExReq misses
58system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses
59system.l2c.demand_misses::cpu.inst 14735 # number of demand (read+write) misses
60system.l2c.demand_misses::cpu.data 407697 # number of demand (read+write) misses
61system.l2c.demand_misses::total 422432 # number of demand (read+write) misses
62system.l2c.overall_misses::cpu.inst 14735 # number of overall misses
63system.l2c.overall_misses::cpu.data 407697 # number of overall misses
64system.l2c.overall_misses::total 422432 # number of overall misses
65system.l2c.ReadReq_miss_latency::cpu.inst 766261500 # number of ReadReq miss cycles
66system.l2c.ReadReq_miss_latency::cpu.data 15053945000 # number of ReadReq miss cycles
67system.l2c.ReadReq_miss_latency::total 15820206500 # number of ReadReq miss cycles
68system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles
69system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles
70system.l2c.ReadExReq_miss_latency::cpu.data 6151753000 # number of ReadExReq miss cycles
71system.l2c.ReadExReq_miss_latency::total 6151753000 # number of ReadExReq miss cycles
72system.l2c.demand_miss_latency::cpu.inst 766261500 # number of demand (read+write) miss cycles
73system.l2c.demand_miss_latency::cpu.data 21205698000 # number of demand (read+write) miss cycles
74system.l2c.demand_miss_latency::total 21971959500 # number of demand (read+write) miss cycles
75system.l2c.overall_miss_latency::cpu.inst 766261500 # number of overall miss cycles
76system.l2c.overall_miss_latency::cpu.data 21205698000 # number of overall miss cycles
77system.l2c.overall_miss_latency::total 21971959500 # number of overall miss cycles
78system.l2c.ReadReq_accesses::cpu.inst 928334 # number of ReadReq accesses(hits+misses)
79system.l2c.ReadReq_accesses::cpu.data 1086265 # number of ReadReq accesses(hits+misses)
80system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses)
81system.l2c.Writeback_accesses::writebacks 826671 # number of Writeback accesses(hits+misses)
82system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses)
83system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses)
84system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
85system.l2c.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses)
86system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
87system.l2c.demand_accesses::cpu.inst 928334 # number of demand (read+write) accesses
88system.l2c.demand_accesses::cpu.data 1390437 # number of demand (read+write) accesses
89system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses
90system.l2c.overall_accesses::cpu.inst 928334 # number of overall (read+write) accesses
91system.l2c.overall_accesses::cpu.data 1390437 # number of overall (read+write) accesses
92system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses
93system.l2c.ReadReq_miss_rate::cpu.inst 0.015873 # miss rate for ReadReq accesses
94system.l2c.ReadReq_miss_rate::cpu.data 0.266420 # miss rate for ReadReq accesses
95system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses
96system.l2c.ReadExReq_miss_rate::cpu.data 0.388905 # miss rate for ReadExReq accesses
97system.l2c.demand_miss_rate::cpu.inst 0.015873 # miss rate for demand accesses
98system.l2c.demand_miss_rate::cpu.data 0.293215 # miss rate for demand accesses
99system.l2c.overall_miss_rate::cpu.inst 0.015873 # miss rate for overall accesses
100system.l2c.overall_miss_rate::cpu.data 0.293215 # miss rate for overall accesses
101system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423 # average ReadReq miss latency
102system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937 # average ReadReq miss latency
103system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency
104system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884 # average ReadExReq miss latency
105system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
106system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
107system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency
108system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency
109system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
110system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
111system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
112system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
113system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
114system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 113system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
114system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
115system.l2c.fast_writes 0 # number of fast writes performed
116system.l2c.cache_copies 0 # number of cache copies performed
117system.l2c.writebacks::writebacks 116650 # number of writebacks
118system.l2c.writebacks::total 116650 # number of writebacks
119system.l2c.ReadReq_mshr_misses::cpu.inst 14735 # number of ReadReq MSHR misses
120system.l2c.ReadReq_mshr_misses::cpu.data 289403 # number of ReadReq MSHR misses
121system.l2c.ReadReq_mshr_misses::total 304138 # number of ReadReq MSHR misses
122system.l2c.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses
123system.l2c.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses
124system.l2c.ReadExReq_mshr_misses::cpu.data 118294 # number of ReadExReq MSHR misses
125system.l2c.ReadExReq_mshr_misses::total 118294 # number of ReadExReq MSHR misses
126system.l2c.demand_mshr_misses::cpu.inst 14735 # number of demand (read+write) MSHR misses
127system.l2c.demand_mshr_misses::cpu.data 407697 # number of demand (read+write) MSHR misses
128system.l2c.demand_mshr_misses::total 422432 # number of demand (read+write) MSHR misses
129system.l2c.overall_mshr_misses::cpu.inst 14735 # number of overall MSHR misses
130system.l2c.overall_mshr_misses::cpu.data 407697 # number of overall MSHR misses
131system.l2c.overall_mshr_misses::total 422432 # number of overall MSHR misses
132system.l2c.ReadReq_mshr_miss_latency::cpu.inst 589436000 # number of ReadReq MSHR miss cycles
133system.l2c.ReadReq_mshr_miss_latency::cpu.data 11581109000 # number of ReadReq MSHR miss cycles
134system.l2c.ReadReq_mshr_miss_latency::total 12170545000 # number of ReadReq MSHR miss cycles
135system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 320000 # number of UpgradeReq MSHR miss cycles
136system.l2c.UpgradeReq_mshr_miss_latency::total 320000 # number of UpgradeReq MSHR miss cycles
137system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4732225000 # number of ReadExReq MSHR miss cycles
138system.l2c.ReadExReq_mshr_miss_latency::total 4732225000 # number of ReadExReq MSHR miss cycles
139system.l2c.demand_mshr_miss_latency::cpu.inst 589436000 # number of demand (read+write) MSHR miss cycles
140system.l2c.demand_mshr_miss_latency::cpu.data 16313334000 # number of demand (read+write) MSHR miss cycles
141system.l2c.demand_mshr_miss_latency::total 16902770000 # number of demand (read+write) MSHR miss cycles
142system.l2c.overall_mshr_miss_latency::cpu.inst 589436000 # number of overall MSHR miss cycles
143system.l2c.overall_mshr_miss_latency::cpu.data 16313334000 # number of overall MSHR miss cycles
144system.l2c.overall_mshr_miss_latency::total 16902770000 # number of overall MSHR miss cycles
145system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772673000 # number of ReadReq MSHR uncacheable cycles
146system.l2c.ReadReq_mshr_uncacheable_latency::total 772673000 # number of ReadReq MSHR uncacheable cycles
147system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1083819500 # number of WriteReq MSHR uncacheable cycles
148system.l2c.WriteReq_mshr_uncacheable_latency::total 1083819500 # number of WriteReq MSHR uncacheable cycles
149system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 # number of overall MSHR uncacheable cycles
150system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles
151system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses
152system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses
153system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses
154system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses
155system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses
156system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses
157system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses
158system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses
159system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency
160system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency
161system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency
162system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency
163system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
164system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
165system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
166system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
167system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
168system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
169system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
170system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
171system.iocache.replacements 41685 # number of replacements
172system.iocache.tagsinuse 1.340325 # Cycle average of tags in use
173system.iocache.total_refs 0 # Total number of references to valid blocks.
174system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
175system.iocache.avg_refs 0 # Average number of references to valid blocks.
176system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit.
177system.iocache.occ_blocks::tsunami.ide 1.340325 # Average occupied blocks per requestor
178system.iocache.occ_percent::tsunami.ide 0.083770 # Average percentage of cache occupancy
179system.iocache.occ_percent::total 0.083770 # Average percentage of cache occupancy
180system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
181system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
182system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
183system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
184system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
185system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
186system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
187system.iocache.overall_misses::total 41725 # number of overall misses
188system.iocache.ReadReq_miss_latency::tsunami.ide 19940998 # number of ReadReq miss cycles
189system.iocache.ReadReq_miss_latency::total 19940998 # number of ReadReq miss cycles
190system.iocache.WriteReq_miss_latency::tsunami.ide 5722300806 # number of WriteReq miss cycles
191system.iocache.WriteReq_miss_latency::total 5722300806 # number of WriteReq miss cycles
192system.iocache.demand_miss_latency::tsunami.ide 5742241804 # number of demand (read+write) miss cycles
193system.iocache.demand_miss_latency::total 5742241804 # number of demand (read+write) miss cycles
194system.iocache.overall_miss_latency::tsunami.ide 5742241804 # number of overall miss cycles
195system.iocache.overall_miss_latency::total 5742241804 # number of overall miss cycles
196system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
197system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
198system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
199system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
200system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
201system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
202system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
203system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
204system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
205system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
206system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
207system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
208system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency
209system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency
210system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
211system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
212system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked
213system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
214system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
215system.iocache.blocked::no_targets 0 # number of cycles access was blocked
216system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked
| 115system.l2c.fast_writes 0 # number of fast writes performed
116system.l2c.cache_copies 0 # number of cache copies performed
117system.l2c.writebacks::writebacks 116650 # number of writebacks
118system.l2c.writebacks::total 116650 # number of writebacks
119system.l2c.ReadReq_mshr_misses::cpu.inst 14735 # number of ReadReq MSHR misses
120system.l2c.ReadReq_mshr_misses::cpu.data 289403 # number of ReadReq MSHR misses
121system.l2c.ReadReq_mshr_misses::total 304138 # number of ReadReq MSHR misses
122system.l2c.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses
123system.l2c.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses
124system.l2c.ReadExReq_mshr_misses::cpu.data 118294 # number of ReadExReq MSHR misses
125system.l2c.ReadExReq_mshr_misses::total 118294 # number of ReadExReq MSHR misses
126system.l2c.demand_mshr_misses::cpu.inst 14735 # number of demand (read+write) MSHR misses
127system.l2c.demand_mshr_misses::cpu.data 407697 # number of demand (read+write) MSHR misses
128system.l2c.demand_mshr_misses::total 422432 # number of demand (read+write) MSHR misses
129system.l2c.overall_mshr_misses::cpu.inst 14735 # number of overall MSHR misses
130system.l2c.overall_mshr_misses::cpu.data 407697 # number of overall MSHR misses
131system.l2c.overall_mshr_misses::total 422432 # number of overall MSHR misses
132system.l2c.ReadReq_mshr_miss_latency::cpu.inst 589436000 # number of ReadReq MSHR miss cycles
133system.l2c.ReadReq_mshr_miss_latency::cpu.data 11581109000 # number of ReadReq MSHR miss cycles
134system.l2c.ReadReq_mshr_miss_latency::total 12170545000 # number of ReadReq MSHR miss cycles
135system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 320000 # number of UpgradeReq MSHR miss cycles
136system.l2c.UpgradeReq_mshr_miss_latency::total 320000 # number of UpgradeReq MSHR miss cycles
137system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4732225000 # number of ReadExReq MSHR miss cycles
138system.l2c.ReadExReq_mshr_miss_latency::total 4732225000 # number of ReadExReq MSHR miss cycles
139system.l2c.demand_mshr_miss_latency::cpu.inst 589436000 # number of demand (read+write) MSHR miss cycles
140system.l2c.demand_mshr_miss_latency::cpu.data 16313334000 # number of demand (read+write) MSHR miss cycles
141system.l2c.demand_mshr_miss_latency::total 16902770000 # number of demand (read+write) MSHR miss cycles
142system.l2c.overall_mshr_miss_latency::cpu.inst 589436000 # number of overall MSHR miss cycles
143system.l2c.overall_mshr_miss_latency::cpu.data 16313334000 # number of overall MSHR miss cycles
144system.l2c.overall_mshr_miss_latency::total 16902770000 # number of overall MSHR miss cycles
145system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772673000 # number of ReadReq MSHR uncacheable cycles
146system.l2c.ReadReq_mshr_uncacheable_latency::total 772673000 # number of ReadReq MSHR uncacheable cycles
147system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1083819500 # number of WriteReq MSHR uncacheable cycles
148system.l2c.WriteReq_mshr_uncacheable_latency::total 1083819500 # number of WriteReq MSHR uncacheable cycles
149system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 # number of overall MSHR uncacheable cycles
150system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles
151system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses
152system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses
153system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses
154system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses
155system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses
156system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses
157system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses
158system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses
159system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency
160system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency
161system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency
162system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency
163system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
164system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
165system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency
166system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency
167system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
168system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
169system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
170system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
171system.iocache.replacements 41685 # number of replacements
172system.iocache.tagsinuse 1.340325 # Cycle average of tags in use
173system.iocache.total_refs 0 # Total number of references to valid blocks.
174system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
175system.iocache.avg_refs 0 # Average number of references to valid blocks.
176system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit.
177system.iocache.occ_blocks::tsunami.ide 1.340325 # Average occupied blocks per requestor
178system.iocache.occ_percent::tsunami.ide 0.083770 # Average percentage of cache occupancy
179system.iocache.occ_percent::total 0.083770 # Average percentage of cache occupancy
180system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
181system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
182system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
183system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
184system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
185system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
186system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
187system.iocache.overall_misses::total 41725 # number of overall misses
188system.iocache.ReadReq_miss_latency::tsunami.ide 19940998 # number of ReadReq miss cycles
189system.iocache.ReadReq_miss_latency::total 19940998 # number of ReadReq miss cycles
190system.iocache.WriteReq_miss_latency::tsunami.ide 5722300806 # number of WriteReq miss cycles
191system.iocache.WriteReq_miss_latency::total 5722300806 # number of WriteReq miss cycles
192system.iocache.demand_miss_latency::tsunami.ide 5742241804 # number of demand (read+write) miss cycles
193system.iocache.demand_miss_latency::total 5742241804 # number of demand (read+write) miss cycles
194system.iocache.overall_miss_latency::tsunami.ide 5742241804 # number of overall miss cycles
195system.iocache.overall_miss_latency::total 5742241804 # number of overall miss cycles
196system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
197system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
198system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
199system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
200system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
201system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
202system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
203system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
204system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
205system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
206system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
207system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
208system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency
209system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency
210system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
211system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency
212system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked
213system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
214system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked
215system.iocache.blocked::no_targets 0 # number of cycles access was blocked
216system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # average number of cycles each access was blocked
|
217system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 217system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
218system.iocache.fast_writes 0 # number of fast writes performed
219system.iocache.cache_copies 0 # number of cache copies performed
220system.iocache.writebacks::writebacks 41512 # number of writebacks
221system.iocache.writebacks::total 41512 # number of writebacks
222system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
223system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
224system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
225system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
226system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
227system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
228system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
229system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
230system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10944998 # number of ReadReq MSHR miss cycles
231system.iocache.ReadReq_mshr_miss_latency::total 10944998 # number of ReadReq MSHR miss cycles
232system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561447990 # number of WriteReq MSHR miss cycles
233system.iocache.WriteReq_mshr_miss_latency::total 3561447990 # number of WriteReq MSHR miss cycles
234system.iocache.demand_mshr_miss_latency::tsunami.ide 3572392988 # number of demand (read+write) MSHR miss cycles
235system.iocache.demand_mshr_miss_latency::total 3572392988 # number of demand (read+write) MSHR miss cycles
236system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles
237system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles
238system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
239system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
240system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
241system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
242system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency
243system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency
244system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
245system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
246system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
247system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
248system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
249system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
250system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
251system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
252system.disk0.dma_write_txs 395 # Number of DMA write transactions.
253system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
254system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
255system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
256system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
257system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
258system.disk2.dma_write_txs 1 # Number of DMA write transactions.
259system.cpu.dtb.fetch_hits 0 # ITB hits
260system.cpu.dtb.fetch_misses 0 # ITB misses
261system.cpu.dtb.fetch_acv 0 # ITB acv
262system.cpu.dtb.fetch_accesses 0 # ITB accesses
263system.cpu.dtb.read_hits 9057511 # DTB read hits
264system.cpu.dtb.read_misses 10312 # DTB read misses
265system.cpu.dtb.read_acv 210 # DTB read access violations
266system.cpu.dtb.read_accesses 728817 # DTB read accesses
267system.cpu.dtb.write_hits 6352446 # DTB write hits
268system.cpu.dtb.write_misses 1140 # DTB write misses
269system.cpu.dtb.write_acv 157 # DTB write access violations
270system.cpu.dtb.write_accesses 291929 # DTB write accesses
271system.cpu.dtb.data_hits 15409957 # DTB hits
272system.cpu.dtb.data_misses 11452 # DTB misses
273system.cpu.dtb.data_acv 367 # DTB access violations
274system.cpu.dtb.data_accesses 1020746 # DTB accesses
275system.cpu.itb.fetch_hits 4973520 # ITB hits
276system.cpu.itb.fetch_misses 4997 # ITB misses
277system.cpu.itb.fetch_acv 184 # ITB acv
278system.cpu.itb.fetch_accesses 4978517 # ITB accesses
279system.cpu.itb.read_hits 0 # DTB read hits
280system.cpu.itb.read_misses 0 # DTB read misses
281system.cpu.itb.read_acv 0 # DTB read access violations
282system.cpu.itb.read_accesses 0 # DTB read accesses
283system.cpu.itb.write_hits 0 # DTB write hits
284system.cpu.itb.write_misses 0 # DTB write misses
285system.cpu.itb.write_acv 0 # DTB write access violations
286system.cpu.itb.write_accesses 0 # DTB write accesses
287system.cpu.itb.data_hits 0 # DTB hits
288system.cpu.itb.data_misses 0 # DTB misses
289system.cpu.itb.data_acv 0 # DTB access violations
290system.cpu.itb.data_accesses 0 # DTB accesses
291system.cpu.numCycles 3831097734 # number of cpu cycles simulated
292system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
293system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
294system.cpu.committedInsts 56137087 # Number of instructions committed
295system.cpu.committedOps 56137087 # Number of ops (including micro ops) committed
296system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses
297system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses
298system.cpu.num_func_calls 1482242 # number of times a function call or return occured
299system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls
300system.cpu.num_int_insts 52011214 # number of integer instructions
301system.cpu.num_fp_insts 324192 # number of float instructions
302system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read
303system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written
304system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read
305system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written
306system.cpu.num_mem_refs 15462519 # number of memory refs
307system.cpu.num_load_insts 9094324 # Number of load instructions
308system.cpu.num_store_insts 6368195 # Number of store instructions
309system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles
310system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles
311system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles
312system.cpu.idle_fraction 0.936531 # Percentage of idle cycles
313system.cpu.kern.inst.arm 0 # number of arm instructions executed
314system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
315system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed
316system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl
317system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
318system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl
319system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl
320system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl
321system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl
322system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
323system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl
324system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl
325system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl
326system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl
327system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl
328system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl
329system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl
330system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl
331system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl
332system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
333system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
334system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl
335system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
336system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
337system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
338system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
339system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
340system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
341system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
342system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
343system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
344system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
345system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
346system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
347system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
348system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
349system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
350system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
351system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
352system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
353system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
354system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
355system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
356system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
357system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
358system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
359system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
360system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
361system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
362system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
363system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
364system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
365system.cpu.kern.syscall::total 326 # number of syscalls executed
366system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
367system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
368system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
369system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
370system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed
371system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
372system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
373system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed
374system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
375system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
376system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
377system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
378system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
379system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
380system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
381system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
382system.cpu.kern.callpal::total 192868 # number of callpals executed
383system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
384system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
385system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches
386system.cpu.kern.mode_good::kernel 1906
387system.cpu.kern.mode_good::user 1738
388system.cpu.kern.mode_good::idle 168
389system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches
390system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
391system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches
392system.cpu.kern.mode_switch_good::total 1.403193 # fraction of useful protection mode switches
393system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode
394system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode
395system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode
396system.cpu.kern.swap_context 4174 # number of times the context was actually changed
397system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
398system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
399system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
400system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
401system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
| 218system.iocache.fast_writes 0 # number of fast writes performed
219system.iocache.cache_copies 0 # number of cache copies performed
220system.iocache.writebacks::writebacks 41512 # number of writebacks
221system.iocache.writebacks::total 41512 # number of writebacks
222system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
223system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
224system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
225system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
226system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
227system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
228system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
229system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
230system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10944998 # number of ReadReq MSHR miss cycles
231system.iocache.ReadReq_mshr_miss_latency::total 10944998 # number of ReadReq MSHR miss cycles
232system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561447990 # number of WriteReq MSHR miss cycles
233system.iocache.WriteReq_mshr_miss_latency::total 3561447990 # number of WriteReq MSHR miss cycles
234system.iocache.demand_mshr_miss_latency::tsunami.ide 3572392988 # number of demand (read+write) MSHR miss cycles
235system.iocache.demand_mshr_miss_latency::total 3572392988 # number of demand (read+write) MSHR miss cycles
236system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles
237system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles
238system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
239system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
240system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
241system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
242system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency
243system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency
244system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
245system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency
246system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
247system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
248system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
249system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
250system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
251system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
252system.disk0.dma_write_txs 395 # Number of DMA write transactions.
253system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
254system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
255system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
256system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
257system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
258system.disk2.dma_write_txs 1 # Number of DMA write transactions.
259system.cpu.dtb.fetch_hits 0 # ITB hits
260system.cpu.dtb.fetch_misses 0 # ITB misses
261system.cpu.dtb.fetch_acv 0 # ITB acv
262system.cpu.dtb.fetch_accesses 0 # ITB accesses
263system.cpu.dtb.read_hits 9057511 # DTB read hits
264system.cpu.dtb.read_misses 10312 # DTB read misses
265system.cpu.dtb.read_acv 210 # DTB read access violations
266system.cpu.dtb.read_accesses 728817 # DTB read accesses
267system.cpu.dtb.write_hits 6352446 # DTB write hits
268system.cpu.dtb.write_misses 1140 # DTB write misses
269system.cpu.dtb.write_acv 157 # DTB write access violations
270system.cpu.dtb.write_accesses 291929 # DTB write accesses
271system.cpu.dtb.data_hits 15409957 # DTB hits
272system.cpu.dtb.data_misses 11452 # DTB misses
273system.cpu.dtb.data_acv 367 # DTB access violations
274system.cpu.dtb.data_accesses 1020746 # DTB accesses
275system.cpu.itb.fetch_hits 4973520 # ITB hits
276system.cpu.itb.fetch_misses 4997 # ITB misses
277system.cpu.itb.fetch_acv 184 # ITB acv
278system.cpu.itb.fetch_accesses 4978517 # ITB accesses
279system.cpu.itb.read_hits 0 # DTB read hits
280system.cpu.itb.read_misses 0 # DTB read misses
281system.cpu.itb.read_acv 0 # DTB read access violations
282system.cpu.itb.read_accesses 0 # DTB read accesses
283system.cpu.itb.write_hits 0 # DTB write hits
284system.cpu.itb.write_misses 0 # DTB write misses
285system.cpu.itb.write_acv 0 # DTB write access violations
286system.cpu.itb.write_accesses 0 # DTB write accesses
287system.cpu.itb.data_hits 0 # DTB hits
288system.cpu.itb.data_misses 0 # DTB misses
289system.cpu.itb.data_acv 0 # DTB access violations
290system.cpu.itb.data_accesses 0 # DTB accesses
291system.cpu.numCycles 3831097734 # number of cpu cycles simulated
292system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
293system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
294system.cpu.committedInsts 56137087 # Number of instructions committed
295system.cpu.committedOps 56137087 # Number of ops (including micro ops) committed
296system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses
297system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses
298system.cpu.num_func_calls 1482242 # number of times a function call or return occured
299system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls
300system.cpu.num_int_insts 52011214 # number of integer instructions
301system.cpu.num_fp_insts 324192 # number of float instructions
302system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read
303system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written
304system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read
305system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written
306system.cpu.num_mem_refs 15462519 # number of memory refs
307system.cpu.num_load_insts 9094324 # Number of load instructions
308system.cpu.num_store_insts 6368195 # Number of store instructions
309system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles
310system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles
311system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles
312system.cpu.idle_fraction 0.936531 # Percentage of idle cycles
313system.cpu.kern.inst.arm 0 # number of arm instructions executed
314system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
315system.cpu.kern.inst.hwrei 211932 # number of hwrei instructions executed
316system.cpu.kern.ipl_count::0 74887 40.89% 40.89% # number of times we switched to this ipl
317system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
318system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl
319system.cpu.kern.ipl_count::31 106197 57.98% 100.00% # number of times we switched to this ipl
320system.cpu.kern.ipl_count::total 183146 # number of times we switched to this ipl
321system.cpu.kern.ipl_good::0 73520 49.31% 49.31% # number of times we switched to this ipl from a different ipl
322system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
323system.cpu.kern.ipl_good::22 1931 1.30% 50.69% # number of times we switched to this ipl from a different ipl
324system.cpu.kern.ipl_good::31 73520 49.31% 100.00% # number of times we switched to this ipl from a different ipl
325system.cpu.kern.ipl_good::total 149102 # number of times we switched to this ipl from a different ipl
326system.cpu.kern.ipl_ticks::0 1857816228500 96.99% 96.99% # number of cycles we spent at this ipl
327system.cpu.kern.ipl_ticks::21 79988500 0.00% 96.99% # number of cycles we spent at this ipl
328system.cpu.kern.ipl_ticks::22 554693000 0.03% 97.02% # number of cycles we spent at this ipl
329system.cpu.kern.ipl_ticks::31 57097199000 2.98% 100.00% # number of cycles we spent at this ipl
330system.cpu.kern.ipl_ticks::total 1915548109000 # number of cycles we spent at this ipl
331system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl
332system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
333system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
334system.cpu.kern.ipl_used::31 0.692298 # fraction of swpipl calls that actually changed the ipl
335system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
336system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
337system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
338system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
339system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
340system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
341system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
342system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
343system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
344system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
345system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
346system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
347system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
348system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
349system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
350system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
351system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
352system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
353system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
354system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
355system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
356system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
357system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
358system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
359system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
360system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
361system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
362system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
363system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
364system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
365system.cpu.kern.syscall::total 326 # number of syscalls executed
366system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
367system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
368system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
369system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
370system.cpu.kern.callpal::swpctx 4173 2.16% 2.17% # number of callpals executed
371system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
372system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
373system.cpu.kern.callpal::swpipl 175927 91.22% 93.41% # number of callpals executed
374system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
375system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
376system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
377system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
378system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
379system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
380system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
381system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
382system.cpu.kern.callpal::total 192868 # number of callpals executed
383system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches
384system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
385system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches
386system.cpu.kern.mode_good::kernel 1906
387system.cpu.kern.mode_good::user 1738
388system.cpu.kern.mode_good::idle 168
389system.cpu.kern.mode_switch_good::kernel 0.322887 # fraction of useful protection mode switches
390system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
391system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches
392system.cpu.kern.mode_switch_good::total 1.403193 # fraction of useful protection mode switches
393system.cpu.kern.mode_ticks::kernel 45253274000 2.36% 2.36% # number of ticks spent at the given mode
394system.cpu.kern.mode_ticks::user 5124228000 0.27% 2.63% # number of ticks spent at the given mode
395system.cpu.kern.mode_ticks::idle 1865170605000 97.37% 100.00% # number of ticks spent at the given mode
396system.cpu.kern.swap_context 4174 # number of times the context was actually changed
397system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
398system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
399system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
400system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
401system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
402system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
| 402system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
403system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
404system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
| 403system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
404system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
405system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
| 405system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
406system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
407system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
| 406system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
407system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
408system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
| 408system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
409system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
410system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
| 409system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
410system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
411system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
| 411system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
412system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
413system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
| 412system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
413system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
414system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
| 414system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
415system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
416system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
| 415system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
416system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
417system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
| 417system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
418system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
419system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
| 418system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
419system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
420system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
| 420system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
421system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
422system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
| 421system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
422system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
423system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
| 423system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
424system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
| 424system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
425system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
| 425system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
426system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
427system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
428system.cpu.icache.replacements 927683 # number of replacements
429system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use
430system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks.
431system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks.
432system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks.
433system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit.
434system.cpu.icache.occ_blocks::cpu.inst 508.721464 # Average occupied blocks per requestor
435system.cpu.icache.occ_percent::cpu.inst 0.993597 # Average percentage of cache occupancy
436system.cpu.icache.occ_percent::total 0.993597 # Average percentage of cache occupancy
437system.cpu.icache.ReadReq_hits::cpu.inst 55220553 # number of ReadReq hits
438system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits
439system.cpu.icache.demand_hits::cpu.inst 55220553 # number of demand (read+write) hits
440system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits
441system.cpu.icache.overall_hits::cpu.inst 55220553 # number of overall hits
442system.cpu.icache.overall_hits::total 55220553 # number of overall hits
443system.cpu.icache.ReadReq_misses::cpu.inst 928354 # number of ReadReq misses
444system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses
445system.cpu.icache.demand_misses::cpu.inst 928354 # number of demand (read+write) misses
446system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses
447system.cpu.icache.overall_misses::cpu.inst 928354 # number of overall misses
448system.cpu.icache.overall_misses::total 928354 # number of overall misses
449system.cpu.icache.ReadReq_miss_latency::cpu.inst 13616370500 # number of ReadReq miss cycles
450system.cpu.icache.ReadReq_miss_latency::total 13616370500 # number of ReadReq miss cycles
451system.cpu.icache.demand_miss_latency::cpu.inst 13616370500 # number of demand (read+write) miss cycles
452system.cpu.icache.demand_miss_latency::total 13616370500 # number of demand (read+write) miss cycles
453system.cpu.icache.overall_miss_latency::cpu.inst 13616370500 # number of overall miss cycles
454system.cpu.icache.overall_miss_latency::total 13616370500 # number of overall miss cycles
455system.cpu.icache.ReadReq_accesses::cpu.inst 56148907 # number of ReadReq accesses(hits+misses)
456system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses)
457system.cpu.icache.demand_accesses::cpu.inst 56148907 # number of demand (read+write) accesses
458system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses
459system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses
460system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses
461system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses
462system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses
463system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses
464system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency
465system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
466system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
467system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
468system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
469system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
470system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
| 426system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
427system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
428system.cpu.icache.replacements 927683 # number of replacements
429system.cpu.icache.tagsinuse 508.721464 # Cycle average of tags in use
430system.cpu.icache.total_refs 55220553 # Total number of references to valid blocks.
431system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks.
432system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks.
433system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit.
434system.cpu.icache.occ_blocks::cpu.inst 508.721464 # Average occupied blocks per requestor
435system.cpu.icache.occ_percent::cpu.inst 0.993597 # Average percentage of cache occupancy
436system.cpu.icache.occ_percent::total 0.993597 # Average percentage of cache occupancy
437system.cpu.icache.ReadReq_hits::cpu.inst 55220553 # number of ReadReq hits
438system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits
439system.cpu.icache.demand_hits::cpu.inst 55220553 # number of demand (read+write) hits
440system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits
441system.cpu.icache.overall_hits::cpu.inst 55220553 # number of overall hits
442system.cpu.icache.overall_hits::total 55220553 # number of overall hits
443system.cpu.icache.ReadReq_misses::cpu.inst 928354 # number of ReadReq misses
444system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses
445system.cpu.icache.demand_misses::cpu.inst 928354 # number of demand (read+write) misses
446system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses
447system.cpu.icache.overall_misses::cpu.inst 928354 # number of overall misses
448system.cpu.icache.overall_misses::total 928354 # number of overall misses
449system.cpu.icache.ReadReq_miss_latency::cpu.inst 13616370500 # number of ReadReq miss cycles
450system.cpu.icache.ReadReq_miss_latency::total 13616370500 # number of ReadReq miss cycles
451system.cpu.icache.demand_miss_latency::cpu.inst 13616370500 # number of demand (read+write) miss cycles
452system.cpu.icache.demand_miss_latency::total 13616370500 # number of demand (read+write) miss cycles
453system.cpu.icache.overall_miss_latency::cpu.inst 13616370500 # number of overall miss cycles
454system.cpu.icache.overall_miss_latency::total 13616370500 # number of overall miss cycles
455system.cpu.icache.ReadReq_accesses::cpu.inst 56148907 # number of ReadReq accesses(hits+misses)
456system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses)
457system.cpu.icache.demand_accesses::cpu.inst 56148907 # number of demand (read+write) accesses
458system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses
459system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses
460system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses
461system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses
462system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses
463system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses
464system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency
465system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
466system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency
467system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
468system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
469system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
470system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
471system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
472system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 471system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
472system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
473system.cpu.icache.fast_writes 0 # number of fast writes performed
474system.cpu.icache.cache_copies 0 # number of cache copies performed
475system.cpu.icache.writebacks::writebacks 85 # number of writebacks
476system.cpu.icache.writebacks::total 85 # number of writebacks
477system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses
478system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses
479system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # number of demand (read+write) MSHR misses
480system.cpu.icache.demand_mshr_misses::total 928354 # number of demand (read+write) MSHR misses
481system.cpu.icache.overall_mshr_misses::cpu.inst 928354 # number of overall MSHR misses
482system.cpu.icache.overall_mshr_misses::total 928354 # number of overall MSHR misses
483system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10830625500 # number of ReadReq MSHR miss cycles
484system.cpu.icache.ReadReq_mshr_miss_latency::total 10830625500 # number of ReadReq MSHR miss cycles
485system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10830625500 # number of demand (read+write) MSHR miss cycles
486system.cpu.icache.demand_mshr_miss_latency::total 10830625500 # number of demand (read+write) MSHR miss cycles
487system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles
488system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles
489system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses
490system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses
491system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses
492system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency
493system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
494system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
495system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
496system.cpu.dcache.replacements 1390115 # number of replacements
497system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use
498system.cpu.dcache.total_refs 14038335 # Total number of references to valid blocks.
499system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks.
500system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks.
501system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit.
502system.cpu.dcache.occ_blocks::cpu.data 511.984023 # Average occupied blocks per requestor
503system.cpu.dcache.occ_percent::cpu.data 0.999969 # Average percentage of cache occupancy
504system.cpu.dcache.occ_percent::total 0.999969 # Average percentage of cache occupancy
505system.cpu.dcache.ReadReq_hits::cpu.data 7807536 # number of ReadReq hits
506system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits
507system.cpu.dcache.WriteReq_hits::cpu.data 5848554 # number of WriteReq hits
508system.cpu.dcache.WriteReq_hits::total 5848554 # number of WriteReq hits
509system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits
510system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits
511system.cpu.dcache.StoreCondReq_hits::cpu.data 199203 # number of StoreCondReq hits
512system.cpu.dcache.StoreCondReq_hits::total 199203 # number of StoreCondReq hits
513system.cpu.dcache.demand_hits::cpu.data 13656090 # number of demand (read+write) hits
514system.cpu.dcache.demand_hits::total 13656090 # number of demand (read+write) hits
515system.cpu.dcache.overall_hits::cpu.data 13656090 # number of overall hits
516system.cpu.dcache.overall_hits::total 13656090 # number of overall hits
517system.cpu.dcache.ReadReq_misses::cpu.data 1069110 # number of ReadReq misses
518system.cpu.dcache.ReadReq_misses::total 1069110 # number of ReadReq misses
519system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses
520system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses
521system.cpu.dcache.LoadLockedReq_misses::cpu.data 17201 # number of LoadLockedReq misses
522system.cpu.dcache.LoadLockedReq_misses::total 17201 # number of LoadLockedReq misses
523system.cpu.dcache.demand_misses::cpu.data 1373445 # number of demand (read+write) misses
524system.cpu.dcache.demand_misses::total 1373445 # number of demand (read+write) misses
525system.cpu.dcache.overall_misses::cpu.data 1373445 # number of overall misses
526system.cpu.dcache.overall_misses::total 1373445 # number of overall misses
527system.cpu.dcache.ReadReq_miss_latency::cpu.data 27121920500 # number of ReadReq miss cycles
528system.cpu.dcache.ReadReq_miss_latency::total 27121920500 # number of ReadReq miss cycles
529system.cpu.dcache.WriteReq_miss_latency::cpu.data 9228484000 # number of WriteReq miss cycles
530system.cpu.dcache.WriteReq_miss_latency::total 9228484000 # number of WriteReq miss cycles
531system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245980000 # number of LoadLockedReq miss cycles
532system.cpu.dcache.LoadLockedReq_miss_latency::total 245980000 # number of LoadLockedReq miss cycles
533system.cpu.dcache.demand_miss_latency::cpu.data 36350404500 # number of demand (read+write) miss cycles
534system.cpu.dcache.demand_miss_latency::total 36350404500 # number of demand (read+write) miss cycles
535system.cpu.dcache.overall_miss_latency::cpu.data 36350404500 # number of overall miss cycles
536system.cpu.dcache.overall_miss_latency::total 36350404500 # number of overall miss cycles
537system.cpu.dcache.ReadReq_accesses::cpu.data 8876646 # number of ReadReq accesses(hits+misses)
538system.cpu.dcache.ReadReq_accesses::total 8876646 # number of ReadReq accesses(hits+misses)
539system.cpu.dcache.WriteReq_accesses::cpu.data 6152889 # number of WriteReq accesses(hits+misses)
540system.cpu.dcache.WriteReq_accesses::total 6152889 # number of WriteReq accesses(hits+misses)
541system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200226 # number of LoadLockedReq accesses(hits+misses)
542system.cpu.dcache.LoadLockedReq_accesses::total 200226 # number of LoadLockedReq accesses(hits+misses)
543system.cpu.dcache.StoreCondReq_accesses::cpu.data 199203 # number of StoreCondReq accesses(hits+misses)
544system.cpu.dcache.StoreCondReq_accesses::total 199203 # number of StoreCondReq accesses(hits+misses)
545system.cpu.dcache.demand_accesses::cpu.data 15029535 # number of demand (read+write) accesses
546system.cpu.dcache.demand_accesses::total 15029535 # number of demand (read+write) accesses
547system.cpu.dcache.overall_accesses::cpu.data 15029535 # number of overall (read+write) accesses
548system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses
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550system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049462 # miss rate for WriteReq accesses
551system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085908 # miss rate for LoadLockedReq accesses
552system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses
553system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses
554system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313 # average ReadReq miss latency
555system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency
556system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency
557system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
558system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
559system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
560system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
561system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
562system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
| 473system.cpu.icache.fast_writes 0 # number of fast writes performed
474system.cpu.icache.cache_copies 0 # number of cache copies performed
475system.cpu.icache.writebacks::writebacks 85 # number of writebacks
476system.cpu.icache.writebacks::total 85 # number of writebacks
477system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses
478system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses
479system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # number of demand (read+write) MSHR misses
480system.cpu.icache.demand_mshr_misses::total 928354 # number of demand (read+write) MSHR misses
481system.cpu.icache.overall_mshr_misses::cpu.inst 928354 # number of overall MSHR misses
482system.cpu.icache.overall_mshr_misses::total 928354 # number of overall MSHR misses
483system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10830625500 # number of ReadReq MSHR miss cycles
484system.cpu.icache.ReadReq_mshr_miss_latency::total 10830625500 # number of ReadReq MSHR miss cycles
485system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10830625500 # number of demand (read+write) MSHR miss cycles
486system.cpu.icache.demand_mshr_miss_latency::total 10830625500 # number of demand (read+write) MSHR miss cycles
487system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles
488system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles
489system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses
490system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses
491system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses
492system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency
493system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
494system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
495system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
496system.cpu.dcache.replacements 1390115 # number of replacements
497system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use
498system.cpu.dcache.total_refs 14038335 # Total number of references to valid blocks.
499system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks.
500system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks.
501system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit.
502system.cpu.dcache.occ_blocks::cpu.data 511.984023 # Average occupied blocks per requestor
503system.cpu.dcache.occ_percent::cpu.data 0.999969 # Average percentage of cache occupancy
504system.cpu.dcache.occ_percent::total 0.999969 # Average percentage of cache occupancy
505system.cpu.dcache.ReadReq_hits::cpu.data 7807536 # number of ReadReq hits
506system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits
507system.cpu.dcache.WriteReq_hits::cpu.data 5848554 # number of WriteReq hits
508system.cpu.dcache.WriteReq_hits::total 5848554 # number of WriteReq hits
509system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits
510system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits
511system.cpu.dcache.StoreCondReq_hits::cpu.data 199203 # number of StoreCondReq hits
512system.cpu.dcache.StoreCondReq_hits::total 199203 # number of StoreCondReq hits
513system.cpu.dcache.demand_hits::cpu.data 13656090 # number of demand (read+write) hits
514system.cpu.dcache.demand_hits::total 13656090 # number of demand (read+write) hits
515system.cpu.dcache.overall_hits::cpu.data 13656090 # number of overall hits
516system.cpu.dcache.overall_hits::total 13656090 # number of overall hits
517system.cpu.dcache.ReadReq_misses::cpu.data 1069110 # number of ReadReq misses
518system.cpu.dcache.ReadReq_misses::total 1069110 # number of ReadReq misses
519system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses
520system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses
521system.cpu.dcache.LoadLockedReq_misses::cpu.data 17201 # number of LoadLockedReq misses
522system.cpu.dcache.LoadLockedReq_misses::total 17201 # number of LoadLockedReq misses
523system.cpu.dcache.demand_misses::cpu.data 1373445 # number of demand (read+write) misses
524system.cpu.dcache.demand_misses::total 1373445 # number of demand (read+write) misses
525system.cpu.dcache.overall_misses::cpu.data 1373445 # number of overall misses
526system.cpu.dcache.overall_misses::total 1373445 # number of overall misses
527system.cpu.dcache.ReadReq_miss_latency::cpu.data 27121920500 # number of ReadReq miss cycles
528system.cpu.dcache.ReadReq_miss_latency::total 27121920500 # number of ReadReq miss cycles
529system.cpu.dcache.WriteReq_miss_latency::cpu.data 9228484000 # number of WriteReq miss cycles
530system.cpu.dcache.WriteReq_miss_latency::total 9228484000 # number of WriteReq miss cycles
531system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245980000 # number of LoadLockedReq miss cycles
532system.cpu.dcache.LoadLockedReq_miss_latency::total 245980000 # number of LoadLockedReq miss cycles
533system.cpu.dcache.demand_miss_latency::cpu.data 36350404500 # number of demand (read+write) miss cycles
534system.cpu.dcache.demand_miss_latency::total 36350404500 # number of demand (read+write) miss cycles
535system.cpu.dcache.overall_miss_latency::cpu.data 36350404500 # number of overall miss cycles
536system.cpu.dcache.overall_miss_latency::total 36350404500 # number of overall miss cycles
537system.cpu.dcache.ReadReq_accesses::cpu.data 8876646 # number of ReadReq accesses(hits+misses)
538system.cpu.dcache.ReadReq_accesses::total 8876646 # number of ReadReq accesses(hits+misses)
539system.cpu.dcache.WriteReq_accesses::cpu.data 6152889 # number of WriteReq accesses(hits+misses)
540system.cpu.dcache.WriteReq_accesses::total 6152889 # number of WriteReq accesses(hits+misses)
541system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200226 # number of LoadLockedReq accesses(hits+misses)
542system.cpu.dcache.LoadLockedReq_accesses::total 200226 # number of LoadLockedReq accesses(hits+misses)
543system.cpu.dcache.StoreCondReq_accesses::cpu.data 199203 # number of StoreCondReq accesses(hits+misses)
544system.cpu.dcache.StoreCondReq_accesses::total 199203 # number of StoreCondReq accesses(hits+misses)
545system.cpu.dcache.demand_accesses::cpu.data 15029535 # number of demand (read+write) accesses
546system.cpu.dcache.demand_accesses::total 15029535 # number of demand (read+write) accesses
547system.cpu.dcache.overall_accesses::cpu.data 15029535 # number of overall (read+write) accesses
548system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses
549system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120441 # miss rate for ReadReq accesses
550system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049462 # miss rate for WriteReq accesses
551system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085908 # miss rate for LoadLockedReq accesses
552system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses
553system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses
554system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313 # average ReadReq miss latency
555system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency
556system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency
557system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
558system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency
559system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
560system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
561system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
562system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
563system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
564system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 563system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
564system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
565system.cpu.dcache.fast_writes 0 # number of fast writes performed
566system.cpu.dcache.cache_copies 0 # number of cache copies performed
567system.cpu.dcache.writebacks::writebacks 826586 # number of writebacks
568system.cpu.dcache.writebacks::total 826586 # number of writebacks
569system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069110 # number of ReadReq MSHR misses
570system.cpu.dcache.ReadReq_mshr_misses::total 1069110 # number of ReadReq MSHR misses
571system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses
572system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses
573system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17201 # number of LoadLockedReq MSHR misses
574system.cpu.dcache.LoadLockedReq_mshr_misses::total 17201 # number of LoadLockedReq MSHR misses
575system.cpu.dcache.demand_mshr_misses::cpu.data 1373445 # number of demand (read+write) MSHR misses
576system.cpu.dcache.demand_mshr_misses::total 1373445 # number of demand (read+write) MSHR misses
577system.cpu.dcache.overall_mshr_misses::cpu.data 1373445 # number of overall MSHR misses
578system.cpu.dcache.overall_mshr_misses::total 1373445 # number of overall MSHR misses
579system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23914545000 # number of ReadReq MSHR miss cycles
580system.cpu.dcache.ReadReq_mshr_miss_latency::total 23914545000 # number of ReadReq MSHR miss cycles
581system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8315479000 # number of WriteReq MSHR miss cycles
582system.cpu.dcache.WriteReq_mshr_miss_latency::total 8315479000 # number of WriteReq MSHR miss cycles
583system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194377000 # number of LoadLockedReq MSHR miss cycles
584system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194377000 # number of LoadLockedReq MSHR miss cycles
585system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32230024000 # number of demand (read+write) MSHR miss cycles
586system.cpu.dcache.demand_mshr_miss_latency::total 32230024000 # number of demand (read+write) MSHR miss cycles
587system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32230024000 # number of overall MSHR miss cycles
588system.cpu.dcache.overall_mshr_miss_latency::total 32230024000 # number of overall MSHR miss cycles
589system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles
590system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles
591system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199607500 # number of WriteReq MSHR uncacheable cycles
592system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 # number of WriteReq MSHR uncacheable cycles
593system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles
594system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles
595system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses
596system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses
597system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses
598system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses
599system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses
600system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency
601system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency
602system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency
603system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
604system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
605system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
606system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
607system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
608system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
609
610---------- End Simulation Statistics ----------
| 565system.cpu.dcache.fast_writes 0 # number of fast writes performed
566system.cpu.dcache.cache_copies 0 # number of cache copies performed
567system.cpu.dcache.writebacks::writebacks 826586 # number of writebacks
568system.cpu.dcache.writebacks::total 826586 # number of writebacks
569system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069110 # number of ReadReq MSHR misses
570system.cpu.dcache.ReadReq_mshr_misses::total 1069110 # number of ReadReq MSHR misses
571system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses
572system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses
573system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17201 # number of LoadLockedReq MSHR misses
574system.cpu.dcache.LoadLockedReq_mshr_misses::total 17201 # number of LoadLockedReq MSHR misses
575system.cpu.dcache.demand_mshr_misses::cpu.data 1373445 # number of demand (read+write) MSHR misses
576system.cpu.dcache.demand_mshr_misses::total 1373445 # number of demand (read+write) MSHR misses
577system.cpu.dcache.overall_mshr_misses::cpu.data 1373445 # number of overall MSHR misses
578system.cpu.dcache.overall_mshr_misses::total 1373445 # number of overall MSHR misses
579system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23914545000 # number of ReadReq MSHR miss cycles
580system.cpu.dcache.ReadReq_mshr_miss_latency::total 23914545000 # number of ReadReq MSHR miss cycles
581system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8315479000 # number of WriteReq MSHR miss cycles
582system.cpu.dcache.WriteReq_mshr_miss_latency::total 8315479000 # number of WriteReq MSHR miss cycles
583system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194377000 # number of LoadLockedReq MSHR miss cycles
584system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194377000 # number of LoadLockedReq MSHR miss cycles
585system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32230024000 # number of demand (read+write) MSHR miss cycles
586system.cpu.dcache.demand_mshr_miss_latency::total 32230024000 # number of demand (read+write) MSHR miss cycles
587system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32230024000 # number of overall MSHR miss cycles
588system.cpu.dcache.overall_mshr_miss_latency::total 32230024000 # number of overall MSHR miss cycles
589system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles
590system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles
591system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199607500 # number of WriteReq MSHR uncacheable cycles
592system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 # number of WriteReq MSHR uncacheable cycles
593system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles
594system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles
595system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses
596system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses
597system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses
598system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses
599system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses
600system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency
601system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency
602system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency
603system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
604system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
605system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
606system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
607system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
608system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
609
610---------- End Simulation Statistics ----------
|