Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.922414 # Number of seconds simulated
4sim_ticks 1922413663500 # Number of ticks simulated
5final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1122927 # Simulator instruction rate (inst/s)
8host_op_rate 1122927 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 38428929684 # Simulator tick rate (ticks/s)
10host_mem_usage 370248 # Number of bytes of host memory used
11host_seconds 50.03 # Real time elapsed on the host

7host_inst_rate 912210 # Simulator instruction rate (inst/s)
8host_op_rate 912209 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 31217732593 # Simulator tick rate (ticks/s)
10host_mem_usage 318584 # Number of bytes of host memory used
11host_seconds 61.58 # Real time elapsed on the host

12sim_insts 56174594 # Number of instructions simulated
13sim_ops 56174594 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 388431 # Number of read requests responded to by this memory
26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 401737 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 442477 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 12931444 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 13374420 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 442477 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 442477 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 3851591 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 3851591 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 3851591 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 442477 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 12931444 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 17226012 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 401737 # Number of read requests accepted
44system.physmem.writeReqs 157245 # Number of write requests accepted
45system.physmem.readBursts 401737 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 157245 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 25705152 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue
49system.physmem.bytesWritten 8387264 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 25711168 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 10063680 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 26167 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 25230 # Per bank write bursts
56system.physmem.perBankRdBursts::1 25660 # Per bank write bursts
57system.physmem.perBankRdBursts::2 25603 # Per bank write bursts
58system.physmem.perBankRdBursts::3 25523 # Per bank write bursts
59system.physmem.perBankRdBursts::4 24970 # Per bank write bursts
60system.physmem.perBankRdBursts::5 24976 # Per bank write bursts
61system.physmem.perBankRdBursts::6 24206 # Per bank write bursts
62system.physmem.perBankRdBursts::7 24492 # Per bank write bursts
63system.physmem.perBankRdBursts::8 25173 # Per bank write bursts
64system.physmem.perBankRdBursts::9 24777 # Per bank write bursts
65system.physmem.perBankRdBursts::10 25267 # Per bank write bursts
66system.physmem.perBankRdBursts::11 24875 # Per bank write bursts
67system.physmem.perBankRdBursts::12 24505 # Per bank write bursts
68system.physmem.perBankRdBursts::13 25378 # Per bank write bursts
69system.physmem.perBankRdBursts::14 25651 # Per bank write bursts
70system.physmem.perBankRdBursts::15 25357 # Per bank write bursts
71system.physmem.perBankWrBursts::0 8677 # Per bank write bursts
72system.physmem.perBankWrBursts::1 8490 # Per bank write bursts
73system.physmem.perBankWrBursts::2 8972 # Per bank write bursts
74system.physmem.perBankWrBursts::3 8549 # Per bank write bursts
75system.physmem.perBankWrBursts::4 8030 # Per bank write bursts
76system.physmem.perBankWrBursts::5 7962 # Per bank write bursts
77system.physmem.perBankWrBursts::6 7256 # Per bank write bursts
78system.physmem.perBankWrBursts::7 7133 # Per bank write bursts
79system.physmem.perBankWrBursts::8 8241 # Per bank write bursts
80system.physmem.perBankWrBursts::9 7447 # Per bank write bursts
81system.physmem.perBankWrBursts::10 7887 # Per bank write bursts
82system.physmem.perBankWrBursts::11 7738 # Per bank write bursts
83system.physmem.perBankWrBursts::12 8187 # Per bank write bursts
84system.physmem.perBankWrBursts::13 8962 # Per bank write bursts
85system.physmem.perBankWrBursts::14 8876 # Per bank write bursts
86system.physmem.perBankWrBursts::15 8644 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
89system.physmem.totGap 1922401791500 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 401737 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 157245 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 401629 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 1447 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 2050 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 5797 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 5431 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 5499 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 5256 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 5198 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 5228 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 5522 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 5548 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 6794 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 5788 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 6388 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 7612 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 6420 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 6113 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 5573 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 1278 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 786 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 1151 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 1489 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 1383 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 874 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 1604 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 2104 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 1549 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 1761 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 1892 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 1974 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 1877 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 2468 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 2834 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 2127 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 1812 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 1264 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 1177 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 712 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 482 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 281 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 175 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 133 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 93 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 50 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 64754 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 526.491275 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 319.634857 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 416.364161 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 14682 22.67% 22.67% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 11626 17.95% 40.63% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 5040 7.78% 48.41% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 3263 5.04% 53.45% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 2595 4.01% 57.46% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 1540 2.38% 59.84% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 1251 1.93% 61.77% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 1707 2.64% 64.40% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 23050 35.60% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 64754 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 4707 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 85.326110 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::stdev 3076.141166 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::0-8191 4704 99.94% 99.94% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::total 4707 # Reads before turning the bus around for writes
222system.physmem.wrPerTurnAround::samples 4707 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::mean 27.841725 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::gmean 18.684188 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::stdev 62.214453 # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::16-31 4459 94.73% 94.73% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::32-47 47 1.00% 95.73% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::48-63 10 0.21% 95.94% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::64-79 2 0.04% 95.98% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::80-95 12 0.25% 96.24% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::96-111 3 0.06% 96.30% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::128-143 7 0.15% 96.45% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::144-159 17 0.36% 96.81% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::160-175 21 0.45% 97.26% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::176-191 12 0.25% 97.51% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::192-207 17 0.36% 97.88% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::208-223 2 0.04% 97.92% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::224-239 5 0.11% 98.02% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::240-255 3 0.06% 98.09% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::272-287 1 0.02% 98.11% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::288-303 2 0.04% 98.15% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::304-319 4 0.08% 98.24% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::320-335 11 0.23% 98.47% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::336-351 21 0.45% 98.92% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::352-367 6 0.13% 99.04% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::368-383 6 0.13% 99.17% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::384-399 6 0.13% 99.30% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::448-463 1 0.02% 99.32% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::464-479 8 0.17% 99.49% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::480-495 2 0.04% 99.53% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::496-511 2 0.04% 99.58% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::512-527 5 0.11% 99.68% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::528-543 2 0.04% 99.72% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::544-559 3 0.06% 99.79% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::560-575 1 0.02% 99.81% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::640-655 1 0.02% 99.83% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::672-687 3 0.06% 99.89% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::688-703 1 0.02% 99.92% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::720-735 2 0.04% 99.96% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::800-815 1 0.02% 99.98% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::832-847 1 0.02% 100.00% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::total 4707 # Writes before turning the bus around for reads
263system.physmem.totQLat 2057087750 # Total ticks spent queuing
264system.physmem.totMemAccLat 9587894000 # Total ticks spent from burst creation until serviced by the DRAM
265system.physmem.totBusLat 2008215000 # Total ticks spent in databus transfers
266system.physmem.avgQLat 5121.68 # Average queueing delay per DRAM burst
267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
268system.physmem.avgMemAccLat 23871.68 # Average memory access latency per DRAM burst
269system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s
270system.physmem.avgWrBW 4.36 # Average achieved write bandwidth in MiByte/s
271system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s
272system.physmem.avgWrBWSys 5.23 # Average system write bandwidth in MiByte/s
273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
274system.physmem.busUtil 0.14 # Data bus utilization in percentage
275system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
276system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
277system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
278system.physmem.avgWrQLen 25.61 # Average write queue length when enqueuing
279system.physmem.readRowHits 360176 # Number of row buffer hits during reads
280system.physmem.writeRowHits 107764 # Number of row buffer hits during writes
281system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads
282system.physmem.writeRowHitRate 82.21 # Row buffer hit rate for writes
283system.physmem.avgGap 3439112.16 # Average gap between requests
284system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined
285system.physmem_0.actEnergy 240309720 # Energy for activate commands per rank (pJ)
286system.physmem_0.preEnergy 131121375 # Energy for precharge commands per rank (pJ)
287system.physmem_0.readEnergy 1565148000 # Energy for read commands per rank (pJ)
288system.physmem_0.writeEnergy 421647120 # Energy for write commands per rank (pJ)
289system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ)
290system.physmem_0.actBackEnergy 64744742475 # Energy for active background per rank (pJ)
291system.physmem_0.preBackEnergy 1096652245500 # Energy for precharge background per rank (pJ)
292system.physmem_0.totalEnergy 1289317661070 # Total energy per rank (pJ)
293system.physmem_0.averagePower 670.677845 # Core power per rank (mW)
294system.physmem_0.memoryStateTime::IDLE 1824141880650 # Time in different power states
295system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states
296system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
297system.physmem_0.memoryStateTime::ACT 34074451850 # Time in different power states
298system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
299system.physmem_1.actEnergy 249230520 # Energy for activate commands per rank (pJ)
300system.physmem_1.preEnergy 135988875 # Energy for precharge commands per rank (pJ)
301system.physmem_1.readEnergy 1567667400 # Energy for read commands per rank (pJ)
302system.physmem_1.writeEnergy 427563360 # Energy for write commands per rank (pJ)
303system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ)
304system.physmem_1.actBackEnergy 65411599725 # Energy for active background per rank (pJ)
305system.physmem_1.preBackEnergy 1096067283000 # Energy for precharge background per rank (pJ)
306system.physmem_1.totalEnergy 1289421779760 # Total energy per rank (pJ)
307system.physmem_1.averagePower 670.732006 # Core power per rank (mW)
308system.physmem_1.memoryStateTime::IDLE 1823167298902 # Time in different power states
309system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states
310system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
311system.physmem_1.memoryStateTime::ACT 35049033598 # Time in different power states
312system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
313system.cpu_clk_domain.clock 500 # Clock period in ticks
314system.cpu.dtb.fetch_hits 0 # ITB hits
315system.cpu.dtb.fetch_misses 0 # ITB misses
316system.cpu.dtb.fetch_acv 0 # ITB acv
317system.cpu.dtb.fetch_accesses 0 # ITB accesses
318system.cpu.dtb.read_hits 9063642 # DTB read hits
319system.cpu.dtb.read_misses 10324 # DTB read misses
320system.cpu.dtb.read_acv 210 # DTB read access violations
321system.cpu.dtb.read_accesses 728853 # DTB read accesses
322system.cpu.dtb.write_hits 6355525 # DTB write hits
323system.cpu.dtb.write_misses 1142 # DTB write misses
324system.cpu.dtb.write_acv 157 # DTB write access violations
325system.cpu.dtb.write_accesses 291931 # DTB write accesses
326system.cpu.dtb.data_hits 15419167 # DTB hits
327system.cpu.dtb.data_misses 11466 # DTB misses
328system.cpu.dtb.data_acv 367 # DTB access violations
329system.cpu.dtb.data_accesses 1020784 # DTB accesses
330system.cpu.itb.fetch_hits 4974414 # ITB hits
331system.cpu.itb.fetch_misses 5010 # ITB misses
332system.cpu.itb.fetch_acv 184 # ITB acv
333system.cpu.itb.fetch_accesses 4979424 # ITB accesses
334system.cpu.itb.read_hits 0 # DTB read hits
335system.cpu.itb.read_misses 0 # DTB read misses
336system.cpu.itb.read_acv 0 # DTB read access violations
337system.cpu.itb.read_accesses 0 # DTB read accesses
338system.cpu.itb.write_hits 0 # DTB write hits
339system.cpu.itb.write_misses 0 # DTB write misses
340system.cpu.itb.write_acv 0 # DTB write access violations
341system.cpu.itb.write_accesses 0 # DTB write accesses
342system.cpu.itb.data_hits 0 # DTB hits
343system.cpu.itb.data_misses 0 # DTB misses
344system.cpu.itb.data_acv 0 # DTB access violations
345system.cpu.itb.data_accesses 0 # DTB accesses
346system.cpu.numCycles 3844827327 # number of cpu cycles simulated
347system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
348system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
349system.cpu.committedInsts 56174594 # Number of instructions committed
350system.cpu.committedOps 56174594 # Number of ops (including micro ops) committed
351system.cpu.num_int_alu_accesses 52047018 # Number of integer alu accesses
352system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
353system.cpu.num_func_calls 1483106 # number of times a function call or return occured
354system.cpu.num_conditional_control_insts 6467546 # number of instructions that are conditional controls
355system.cpu.num_int_insts 52047018 # number of integer instructions
356system.cpu.num_fp_insts 324460 # number of float instructions
357system.cpu.num_int_register_reads 71310653 # number of times the integer registers were read
358system.cpu.num_int_register_writes 38515122 # number of times the integer registers were written
359system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
360system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
361system.cpu.num_mem_refs 15471782 # number of memory refs
362system.cpu.num_load_insts 9100493 # Number of load instructions
363system.cpu.num_store_insts 6371289 # Number of store instructions
364system.cpu.num_idle_cycles 3587399919.998134 # Number of idle cycles
365system.cpu.num_busy_cycles 257427407.001866 # Number of busy cycles
366system.cpu.not_idle_fraction 0.066954 # Percentage of non-idle cycles
367system.cpu.idle_fraction 0.933046 # Percentage of idle cycles
368system.cpu.Branches 8421188 # Number of branches fetched
369system.cpu.op_class::No_OpClass 3200330 5.70% 5.70% # Class of executed instruction
370system.cpu.op_class::IntAlu 36225212 64.47% 70.17% # Class of executed instruction
371system.cpu.op_class::IntMult 61016 0.11% 70.28% # Class of executed instruction
372system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction
373system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction
374system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction
375system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction
376system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction
377system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction
378system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction
379system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction
380system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction
381system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction
382system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction
383system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction
384system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction
385system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction
386system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction
387system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction
388system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction
389system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction
390system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction
391system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction
392system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction
393system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction
394system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction
395system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction
396system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction
397system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction
398system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction
399system.cpu.op_class::MemRead 9327578 16.60% 86.95% # Class of executed instruction
400system.cpu.op_class::MemWrite 6377363 11.35% 98.30% # Class of executed instruction
401system.cpu.op_class::IprAccess 953205 1.70% 100.00% # Class of executed instruction
402system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
403system.cpu.op_class::total 56186427 # Class of executed instruction
404system.cpu.kern.inst.arm 0 # number of arm instructions executed
405system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
406system.cpu.kern.inst.hwrei 211986 # number of hwrei instructions executed
407system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl
408system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
409system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl
410system.cpu.kern.ipl_count::31 106213 57.99% 100.00% # number of times we switched to this ipl
411system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl
412system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl
413system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
414system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
415system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl
416system.cpu.kern.ipl_good::total 149113 # number of times we switched to this ipl from a different ipl
417system.cpu.kern.ipl_ticks::0 1857939859000 96.65% 96.65% # number of cycles we spent at this ipl
418system.cpu.kern.ipl_ticks::21 91692000 0.00% 96.65% # number of cycles we spent at this ipl
419system.cpu.kern.ipl_ticks::22 740049500 0.04% 96.69% # number of cycles we spent at this ipl
420system.cpu.kern.ipl_ticks::31 63641329000 3.31% 100.00% # number of cycles we spent at this ipl
421system.cpu.kern.ipl_ticks::total 1922412929500 # number of cycles we spent at this ipl
422system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl
423system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
424system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
425system.cpu.kern.ipl_used::31 0.692241 # fraction of swpipl calls that actually changed the ipl
426system.cpu.kern.ipl_used::total 0.814078 # fraction of swpipl calls that actually changed the ipl
427system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
428system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
429system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
430system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
431system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
432system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
433system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
434system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
435system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
436system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
437system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
438system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
439system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
440system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
441system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
442system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
443system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
444system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
445system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
446system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
447system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
448system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
449system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
450system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
451system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
452system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
453system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
454system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
455system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
456system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
457system.cpu.kern.syscall::total 326 # number of syscalls executed
458system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
459system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
460system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
461system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
462system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
463system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
464system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
465system.cpu.kern.callpal::swpipl 175947 91.21% 93.41% # number of callpals executed
466system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed
467system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
468system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
469system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
470system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
471system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed
472system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
473system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
474system.cpu.kern.callpal::total 192894 # number of callpals executed
475system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches
476system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
477system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
478system.cpu.kern.mode_good::kernel 1910
479system.cpu.kern.mode_good::user 1740
480system.cpu.kern.mode_good::idle 170
481system.cpu.kern.mode_switch_good::kernel 0.323455 # fraction of useful protection mode switches
482system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
483system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
484system.cpu.kern.mode_switch_good::total 0.392197 # fraction of useful protection mode switches
485system.cpu.kern.mode_ticks::kernel 46428613000 2.42% 2.42% # number of ticks spent at the given mode
486system.cpu.kern.mode_ticks::user 5237727500 0.27% 2.69% # number of ticks spent at the given mode
487system.cpu.kern.mode_ticks::idle 1870746587000 97.31% 100.00% # number of ticks spent at the given mode
488system.cpu.kern.swap_context 4178 # number of times the context was actually changed
489system.cpu.dcache.tags.replacements 1391374 # number of replacements
490system.cpu.dcache.tags.tagsinuse 511.978196 # Cycle average of tags in use
491system.cpu.dcache.tags.total_refs 14046325 # Total number of references to valid blocks.
492system.cpu.dcache.tags.sampled_refs 1391886 # Sample count of references to valid blocks.
493system.cpu.dcache.tags.avg_refs 10.091577 # Average number of references to valid blocks.
494system.cpu.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit.
495system.cpu.dcache.tags.occ_blocks::cpu.data 511.978196 # Average occupied blocks per requestor
496system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy
497system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy
498system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
499system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
500system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
501system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
502system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
503system.cpu.dcache.tags.tag_accesses 63144735 # Number of tag accesses
504system.cpu.dcache.tags.data_accesses 63144735 # Number of data accesses
505system.cpu.dcache.ReadReq_hits::cpu.data 7812525 # number of ReadReq hits
506system.cpu.dcache.ReadReq_hits::total 7812525 # number of ReadReq hits
507system.cpu.dcache.WriteReq_hits::cpu.data 5851580 # number of WriteReq hits
508system.cpu.dcache.WriteReq_hits::total 5851580 # number of WriteReq hits
509system.cpu.dcache.LoadLockedReq_hits::cpu.data 182969 # number of LoadLockedReq hits
510system.cpu.dcache.LoadLockedReq_hits::total 182969 # number of LoadLockedReq hits
511system.cpu.dcache.StoreCondReq_hits::cpu.data 199234 # number of StoreCondReq hits
512system.cpu.dcache.StoreCondReq_hits::total 199234 # number of StoreCondReq hits
513system.cpu.dcache.demand_hits::cpu.data 13664105 # number of demand (read+write) hits
514system.cpu.dcache.demand_hits::total 13664105 # number of demand (read+write) hits
515system.cpu.dcache.overall_hits::cpu.data 13664105 # number of overall hits
516system.cpu.dcache.overall_hits::total 13664105 # number of overall hits
517system.cpu.dcache.ReadReq_misses::cpu.data 1070248 # number of ReadReq misses
518system.cpu.dcache.ReadReq_misses::total 1070248 # number of ReadReq misses
519system.cpu.dcache.WriteReq_misses::cpu.data 304369 # number of WriteReq misses
520system.cpu.dcache.WriteReq_misses::total 304369 # number of WriteReq misses
521system.cpu.dcache.LoadLockedReq_misses::cpu.data 17287 # number of LoadLockedReq misses
522system.cpu.dcache.LoadLockedReq_misses::total 17287 # number of LoadLockedReq misses
523system.cpu.dcache.demand_misses::cpu.data 1374617 # number of demand (read+write) misses
524system.cpu.dcache.demand_misses::total 1374617 # number of demand (read+write) misses
525system.cpu.dcache.overall_misses::cpu.data 1374617 # number of overall misses
526system.cpu.dcache.overall_misses::total 1374617 # number of overall misses
527system.cpu.dcache.ReadReq_miss_latency::cpu.data 30897353500 # number of ReadReq miss cycles
528system.cpu.dcache.ReadReq_miss_latency::total 30897353500 # number of ReadReq miss cycles
529system.cpu.dcache.WriteReq_miss_latency::cpu.data 11699394130 # number of WriteReq miss cycles
530system.cpu.dcache.WriteReq_miss_latency::total 11699394130 # number of WriteReq miss cycles
531system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229714500 # number of LoadLockedReq miss cycles
532system.cpu.dcache.LoadLockedReq_miss_latency::total 229714500 # number of LoadLockedReq miss cycles
533system.cpu.dcache.demand_miss_latency::cpu.data 42596747630 # number of demand (read+write) miss cycles
534system.cpu.dcache.demand_miss_latency::total 42596747630 # number of demand (read+write) miss cycles
535system.cpu.dcache.overall_miss_latency::cpu.data 42596747630 # number of overall miss cycles
536system.cpu.dcache.overall_miss_latency::total 42596747630 # number of overall miss cycles
537system.cpu.dcache.ReadReq_accesses::cpu.data 8882773 # number of ReadReq accesses(hits+misses)
538system.cpu.dcache.ReadReq_accesses::total 8882773 # number of ReadReq accesses(hits+misses)
539system.cpu.dcache.WriteReq_accesses::cpu.data 6155949 # number of WriteReq accesses(hits+misses)
540system.cpu.dcache.WriteReq_accesses::total 6155949 # number of WriteReq accesses(hits+misses)
541system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200256 # number of LoadLockedReq accesses(hits+misses)
542system.cpu.dcache.LoadLockedReq_accesses::total 200256 # number of LoadLockedReq accesses(hits+misses)
543system.cpu.dcache.StoreCondReq_accesses::cpu.data 199234 # number of StoreCondReq accesses(hits+misses)
544system.cpu.dcache.StoreCondReq_accesses::total 199234 # number of StoreCondReq accesses(hits+misses)
545system.cpu.dcache.demand_accesses::cpu.data 15038722 # number of demand (read+write) accesses
546system.cpu.dcache.demand_accesses::total 15038722 # number of demand (read+write) accesses
547system.cpu.dcache.overall_accesses::cpu.data 15038722 # number of overall (read+write) accesses
548system.cpu.dcache.overall_accesses::total 15038722 # number of overall (read+write) accesses
549system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120486 # miss rate for ReadReq accesses
550system.cpu.dcache.ReadReq_miss_rate::total 0.120486 # miss rate for ReadReq accesses
551system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049443 # miss rate for WriteReq accesses
552system.cpu.dcache.WriteReq_miss_rate::total 0.049443 # miss rate for WriteReq accesses
553system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086325 # miss rate for LoadLockedReq accesses
554system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086325 # miss rate for LoadLockedReq accesses
555system.cpu.dcache.demand_miss_rate::cpu.data 0.091405 # miss rate for demand accesses
556system.cpu.dcache.demand_miss_rate::total 0.091405 # miss rate for demand accesses
557system.cpu.dcache.overall_miss_rate::cpu.data 0.091405 # miss rate for overall accesses
558system.cpu.dcache.overall_miss_rate::total 0.091405 # miss rate for overall accesses
559system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28869.340097 # average ReadReq miss latency
560system.cpu.dcache.ReadReq_avg_miss_latency::total 28869.340097 # average ReadReq miss latency
561system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38438.192227 # average WriteReq miss latency
562system.cpu.dcache.WriteReq_avg_miss_latency::total 38438.192227 # average WriteReq miss latency
563system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13288.280211 # average LoadLockedReq miss latency
564system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13288.280211 # average LoadLockedReq miss latency
565system.cpu.dcache.demand_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency
566system.cpu.dcache.demand_avg_miss_latency::total 30988.084412 # average overall miss latency
567system.cpu.dcache.overall_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency
568system.cpu.dcache.overall_avg_miss_latency::total 30988.084412 # average overall miss latency
569system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
570system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
571system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
572system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
573system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
574system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
575system.cpu.dcache.fast_writes 0 # number of fast writes performed
576system.cpu.dcache.cache_copies 0 # number of cache copies performed
577system.cpu.dcache.writebacks::writebacks 835634 # number of writebacks
578system.cpu.dcache.writebacks::total 835634 # number of writebacks
579system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1070248 # number of ReadReq MSHR misses
580system.cpu.dcache.ReadReq_mshr_misses::total 1070248 # number of ReadReq MSHR misses
581system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304369 # number of WriteReq MSHR misses
582system.cpu.dcache.WriteReq_mshr_misses::total 304369 # number of WriteReq MSHR misses
583system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17287 # number of LoadLockedReq MSHR misses
584system.cpu.dcache.LoadLockedReq_mshr_misses::total 17287 # number of LoadLockedReq MSHR misses
585system.cpu.dcache.demand_mshr_misses::cpu.data 1374617 # number of demand (read+write) MSHR misses
586system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses
587system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses
588system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses

589system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
590system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
591system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable
592system.cpu.dcache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable
593system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses
594system.cpu.dcache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses

589system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles
590system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles
591system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles
592system.cpu.dcache.WriteReq_mshr_miss_latency::total 11190140370 # number of WriteReq MSHR miss cycles
593system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 203771000 # number of LoadLockedReq MSHR miss cycles
594system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 203771000 # number of LoadLockedReq MSHR miss cycles
595system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40356234870 # number of demand (read+write) MSHR miss cycles
596system.cpu.dcache.demand_mshr_miss_latency::total 40356234870 # number of demand (read+write) MSHR miss cycles
597system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40356234870 # number of overall MSHR miss cycles
598system.cpu.dcache.overall_mshr_miss_latency::total 40356234870 # number of overall MSHR miss cycles
599system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1432759000 # number of ReadReq MSHR uncacheable cycles
600system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1432759000 # number of ReadReq MSHR uncacheable cycles
601system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2025445000 # number of WriteReq MSHR uncacheable cycles
602system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2025445000 # number of WriteReq MSHR uncacheable cycles
603system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3458204000 # number of overall MSHR uncacheable cycles
604system.cpu.dcache.overall_mshr_uncacheable_latency::total 3458204000 # number of overall MSHR uncacheable cycles
605system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120486 # mshr miss rate for ReadReq accesses
606system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120486 # mshr miss rate for ReadReq accesses
607system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses
608system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses
609system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086325 # mshr miss rate for LoadLockedReq accesses
610system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086325 # mshr miss rate for LoadLockedReq accesses
611system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for demand accesses
612system.cpu.dcache.demand_mshr_miss_rate::total 0.091405 # mshr miss rate for demand accesses
613system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for overall accesses
614system.cpu.dcache.overall_mshr_miss_rate::total 0.091405 # mshr miss rate for overall accesses
615system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27251.715957 # average ReadReq mshr miss latency
616system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27251.715957 # average ReadReq mshr miss latency
617system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36765.046276 # average WriteReq mshr miss latency
618system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36765.046276 # average WriteReq mshr miss latency
619system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11787.528200 # average LoadLockedReq mshr miss latency
620system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11787.528200 # average LoadLockedReq mshr miss latency
621system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency
622system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
623system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency
624system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency

595system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles
596system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles
597system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles
598system.cpu.dcache.WriteReq_mshr_miss_latency::total 11190140370 # number of WriteReq MSHR miss cycles
599system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 203771000 # number of LoadLockedReq MSHR miss cycles
600system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 203771000 # number of LoadLockedReq MSHR miss cycles
601system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40356234870 # number of demand (read+write) MSHR miss cycles
602system.cpu.dcache.demand_mshr_miss_latency::total 40356234870 # number of demand (read+write) MSHR miss cycles
603system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40356234870 # number of overall MSHR miss cycles
604system.cpu.dcache.overall_mshr_miss_latency::total 40356234870 # number of overall MSHR miss cycles
605system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1432759000 # number of ReadReq MSHR uncacheable cycles
606system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1432759000 # number of ReadReq MSHR uncacheable cycles
607system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2025445000 # number of WriteReq MSHR uncacheable cycles
608system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2025445000 # number of WriteReq MSHR uncacheable cycles
609system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3458204000 # number of overall MSHR uncacheable cycles
610system.cpu.dcache.overall_mshr_uncacheable_latency::total 3458204000 # number of overall MSHR uncacheable cycles
611system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120486 # mshr miss rate for ReadReq accesses
612system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120486 # mshr miss rate for ReadReq accesses
613system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses
614system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses
615system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086325 # mshr miss rate for LoadLockedReq accesses
616system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086325 # mshr miss rate for LoadLockedReq accesses
617system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for demand accesses
618system.cpu.dcache.demand_mshr_miss_rate::total 0.091405 # mshr miss rate for demand accesses
619system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for overall accesses
620system.cpu.dcache.overall_mshr_miss_rate::total 0.091405 # mshr miss rate for overall accesses
621system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27251.715957 # average ReadReq mshr miss latency
622system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27251.715957 # average ReadReq mshr miss latency
623system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36765.046276 # average WriteReq mshr miss latency
624system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36765.046276 # average WriteReq mshr miss latency
625system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11787.528200 # average LoadLockedReq mshr miss latency
626system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11787.528200 # average LoadLockedReq mshr miss latency
627system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency
628system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
629system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency
630system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency

625system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
626system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
627system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
628system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
629system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
630system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

631system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206747.330447 # average ReadReq mshr uncacheable latency
632system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206747.330447 # average ReadReq mshr uncacheable latency
633system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209890.673575 # average WriteReq mshr uncacheable latency
634system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209890.673575 # average WriteReq mshr uncacheable latency
635system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208576.839566 # average overall mshr uncacheable latency
636system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208576.839566 # average overall mshr uncacheable latency

631system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
632system.cpu.icache.tags.replacements 928205 # number of replacements
633system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use
634system.cpu.icache.tags.total_refs 55257552 # Total number of references to valid blocks.
635system.cpu.icache.tags.sampled_refs 928716 # Sample count of references to valid blocks.
636system.cpu.icache.tags.avg_refs 59.498869 # Average number of references to valid blocks.
637system.cpu.icache.tags.warmup_cycle 42087191250 # Cycle when the warmup percentage was hit.
638system.cpu.icache.tags.occ_blocks::cpu.inst 508.070911 # Average occupied blocks per requestor
639system.cpu.icache.tags.occ_percent::cpu.inst 0.992326 # Average percentage of cache occupancy
640system.cpu.icache.tags.occ_percent::total 0.992326 # Average percentage of cache occupancy
641system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
642system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
643system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
644system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id
645system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
646system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
647system.cpu.icache.tags.tag_accesses 57115304 # Number of tag accesses
648system.cpu.icache.tags.data_accesses 57115304 # Number of data accesses
649system.cpu.icache.ReadReq_hits::cpu.inst 55257552 # number of ReadReq hits
650system.cpu.icache.ReadReq_hits::total 55257552 # number of ReadReq hits
651system.cpu.icache.demand_hits::cpu.inst 55257552 # number of demand (read+write) hits
652system.cpu.icache.demand_hits::total 55257552 # number of demand (read+write) hits
653system.cpu.icache.overall_hits::cpu.inst 55257552 # number of overall hits
654system.cpu.icache.overall_hits::total 55257552 # number of overall hits
655system.cpu.icache.ReadReq_misses::cpu.inst 928876 # number of ReadReq misses
656system.cpu.icache.ReadReq_misses::total 928876 # number of ReadReq misses
657system.cpu.icache.demand_misses::cpu.inst 928876 # number of demand (read+write) misses
658system.cpu.icache.demand_misses::total 928876 # number of demand (read+write) misses
659system.cpu.icache.overall_misses::cpu.inst 928876 # number of overall misses
660system.cpu.icache.overall_misses::total 928876 # number of overall misses
661system.cpu.icache.ReadReq_miss_latency::cpu.inst 13004894000 # number of ReadReq miss cycles
662system.cpu.icache.ReadReq_miss_latency::total 13004894000 # number of ReadReq miss cycles
663system.cpu.icache.demand_miss_latency::cpu.inst 13004894000 # number of demand (read+write) miss cycles
664system.cpu.icache.demand_miss_latency::total 13004894000 # number of demand (read+write) miss cycles
665system.cpu.icache.overall_miss_latency::cpu.inst 13004894000 # number of overall miss cycles
666system.cpu.icache.overall_miss_latency::total 13004894000 # number of overall miss cycles
667system.cpu.icache.ReadReq_accesses::cpu.inst 56186428 # number of ReadReq accesses(hits+misses)
668system.cpu.icache.ReadReq_accesses::total 56186428 # number of ReadReq accesses(hits+misses)
669system.cpu.icache.demand_accesses::cpu.inst 56186428 # number of demand (read+write) accesses
670system.cpu.icache.demand_accesses::total 56186428 # number of demand (read+write) accesses
671system.cpu.icache.overall_accesses::cpu.inst 56186428 # number of overall (read+write) accesses
672system.cpu.icache.overall_accesses::total 56186428 # number of overall (read+write) accesses
673system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses
674system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses
675system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses
676system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses
677system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses
678system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses
679system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14000.678239 # average ReadReq miss latency
680system.cpu.icache.ReadReq_avg_miss_latency::total 14000.678239 # average ReadReq miss latency
681system.cpu.icache.demand_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency
682system.cpu.icache.demand_avg_miss_latency::total 14000.678239 # average overall miss latency
683system.cpu.icache.overall_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency
684system.cpu.icache.overall_avg_miss_latency::total 14000.678239 # average overall miss latency
685system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
686system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
687system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
688system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
689system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
690system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
691system.cpu.icache.fast_writes 0 # number of fast writes performed
692system.cpu.icache.cache_copies 0 # number of cache copies performed
693system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928876 # number of ReadReq MSHR misses
694system.cpu.icache.ReadReq_mshr_misses::total 928876 # number of ReadReq MSHR misses
695system.cpu.icache.demand_mshr_misses::cpu.inst 928876 # number of demand (read+write) MSHR misses
696system.cpu.icache.demand_mshr_misses::total 928876 # number of demand (read+write) MSHR misses
697system.cpu.icache.overall_mshr_misses::cpu.inst 928876 # number of overall MSHR misses
698system.cpu.icache.overall_mshr_misses::total 928876 # number of overall MSHR misses
699system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11606411000 # number of ReadReq MSHR miss cycles
700system.cpu.icache.ReadReq_mshr_miss_latency::total 11606411000 # number of ReadReq MSHR miss cycles
701system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11606411000 # number of demand (read+write) MSHR miss cycles
702system.cpu.icache.demand_mshr_miss_latency::total 11606411000 # number of demand (read+write) MSHR miss cycles
703system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11606411000 # number of overall MSHR miss cycles
704system.cpu.icache.overall_mshr_miss_latency::total 11606411000 # number of overall MSHR miss cycles
705system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses
706system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses
707system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses
708system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses
709system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses
710system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses
711system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12495.113449 # average ReadReq mshr miss latency
712system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12495.113449 # average ReadReq mshr miss latency
713system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency
714system.cpu.icache.demand_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency
715system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency
716system.cpu.icache.overall_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency
717system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
718system.cpu.l2cache.tags.replacements 336253 # number of replacements
719system.cpu.l2cache.tags.tagsinuse 65287.674931 # Cycle average of tags in use
720system.cpu.l2cache.tags.total_refs 2448546 # Total number of references to valid blocks.
721system.cpu.l2cache.tags.sampled_refs 401415 # Sample count of references to valid blocks.
722system.cpu.l2cache.tags.avg_refs 6.099787 # Average number of references to valid blocks.
723system.cpu.l2cache.tags.warmup_cycle 7245222750 # Cycle when the warmup percentage was hit.
724system.cpu.l2cache.tags.occ_blocks::writebacks 55515.781465 # Average occupied blocks per requestor
725system.cpu.l2cache.tags.occ_blocks::cpu.inst 4753.205077 # Average occupied blocks per requestor
726system.cpu.l2cache.tags.occ_blocks::cpu.data 5018.688389 # Average occupied blocks per requestor
727system.cpu.l2cache.tags.occ_percent::writebacks 0.847104 # Average percentage of cache occupancy
728system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072528 # Average percentage of cache occupancy
729system.cpu.l2cache.tags.occ_percent::cpu.data 0.076579 # Average percentage of cache occupancy
730system.cpu.l2cache.tags.occ_percent::total 0.996211 # Average percentage of cache occupancy
731system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
732system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
733system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id
734system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4937 # Occupied blocks per task id
735system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3234 # Occupied blocks per task id
736system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55805 # Occupied blocks per task id
737system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
738system.cpu.l2cache.tags.tag_accesses 25957144 # Number of tag accesses
739system.cpu.l2cache.tags.data_accesses 25957144 # Number of data accesses
740system.cpu.l2cache.ReadReq_hits::cpu.inst 915565 # number of ReadReq hits
741system.cpu.l2cache.ReadReq_hits::cpu.data 815571 # number of ReadReq hits
742system.cpu.l2cache.ReadReq_hits::total 1731136 # number of ReadReq hits
743system.cpu.l2cache.Writeback_hits::writebacks 835634 # number of Writeback hits
744system.cpu.l2cache.Writeback_hits::total 835634 # number of Writeback hits
745system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
746system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
747system.cpu.l2cache.ReadExReq_hits::cpu.data 187495 # number of ReadExReq hits
748system.cpu.l2cache.ReadExReq_hits::total 187495 # number of ReadExReq hits
749system.cpu.l2cache.demand_hits::cpu.inst 915565 # number of demand (read+write) hits
750system.cpu.l2cache.demand_hits::cpu.data 1003066 # number of demand (read+write) hits
751system.cpu.l2cache.demand_hits::total 1918631 # number of demand (read+write) hits
752system.cpu.l2cache.overall_hits::cpu.inst 915565 # number of overall hits
753system.cpu.l2cache.overall_hits::cpu.data 1003066 # number of overall hits
754system.cpu.l2cache.overall_hits::total 1918631 # number of overall hits
755system.cpu.l2cache.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses
756system.cpu.l2cache.ReadReq_misses::cpu.data 271964 # number of ReadReq misses
757system.cpu.l2cache.ReadReq_misses::total 285255 # number of ReadReq misses
758system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
759system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
760system.cpu.l2cache.ReadExReq_misses::cpu.data 116857 # number of ReadExReq misses
761system.cpu.l2cache.ReadExReq_misses::total 116857 # number of ReadExReq misses
762system.cpu.l2cache.demand_misses::cpu.inst 13291 # number of demand (read+write) misses
763system.cpu.l2cache.demand_misses::cpu.data 388821 # number of demand (read+write) misses
764system.cpu.l2cache.demand_misses::total 402112 # number of demand (read+write) misses
765system.cpu.l2cache.overall_misses::cpu.inst 13291 # number of overall misses
766system.cpu.l2cache.overall_misses::cpu.data 388821 # number of overall misses
767system.cpu.l2cache.overall_misses::total 402112 # number of overall misses
768system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1064072500 # number of ReadReq miss cycles
769system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19718835000 # number of ReadReq miss cycles
770system.cpu.l2cache.ReadReq_miss_latency::total 20782907500 # number of ReadReq miss cycles
771system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 220998 # number of UpgradeReq miss cycles
772system.cpu.l2cache.UpgradeReq_miss_latency::total 220998 # number of UpgradeReq miss cycles
773system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8916531881 # number of ReadExReq miss cycles
774system.cpu.l2cache.ReadExReq_miss_latency::total 8916531881 # number of ReadExReq miss cycles
775system.cpu.l2cache.demand_miss_latency::cpu.inst 1064072500 # number of demand (read+write) miss cycles
776system.cpu.l2cache.demand_miss_latency::cpu.data 28635366881 # number of demand (read+write) miss cycles
777system.cpu.l2cache.demand_miss_latency::total 29699439381 # number of demand (read+write) miss cycles
778system.cpu.l2cache.overall_miss_latency::cpu.inst 1064072500 # number of overall miss cycles
779system.cpu.l2cache.overall_miss_latency::cpu.data 28635366881 # number of overall miss cycles
780system.cpu.l2cache.overall_miss_latency::total 29699439381 # number of overall miss cycles
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782system.cpu.l2cache.ReadReq_accesses::cpu.data 1087535 # number of ReadReq accesses(hits+misses)
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785system.cpu.l2cache.Writeback_accesses::total 835634 # number of Writeback accesses(hits+misses)
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798system.cpu.l2cache.ReadReq_miss_rate::total 0.141468 # miss rate for ReadReq accesses
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800system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses
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803system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014309 # miss rate for demand accesses
804system.cpu.l2cache.demand_miss_rate::cpu.data 0.279348 # miss rate for demand accesses
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806system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014309 # miss rate for overall accesses
807system.cpu.l2cache.overall_miss_rate::cpu.data 0.279348 # miss rate for overall accesses
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810system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72505.313203 # average ReadReq miss latency
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814system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76302.933337 # average ReadExReq miss latency
815system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76302.933337 # average ReadExReq miss latency
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719system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency
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721system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency
722system.cpu.icache.overall_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency
723system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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725system.cpu.l2cache.tags.tagsinuse 65287.674931 # Cycle average of tags in use
726system.cpu.l2cache.tags.total_refs 2448546 # Total number of references to valid blocks.
727system.cpu.l2cache.tags.sampled_refs 401415 # Sample count of references to valid blocks.
728system.cpu.l2cache.tags.avg_refs 6.099787 # Average number of references to valid blocks.
729system.cpu.l2cache.tags.warmup_cycle 7245222750 # Cycle when the warmup percentage was hit.
730system.cpu.l2cache.tags.occ_blocks::writebacks 55515.781465 # Average occupied blocks per requestor
731system.cpu.l2cache.tags.occ_blocks::cpu.inst 4753.205077 # Average occupied blocks per requestor
732system.cpu.l2cache.tags.occ_blocks::cpu.data 5018.688389 # Average occupied blocks per requestor
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737system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
738system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
739system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id
740system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4937 # Occupied blocks per task id
741system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3234 # Occupied blocks per task id
742system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55805 # Occupied blocks per task id
743system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
744system.cpu.l2cache.tags.tag_accesses 25957144 # Number of tag accesses
745system.cpu.l2cache.tags.data_accesses 25957144 # Number of data accesses
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749system.cpu.l2cache.Writeback_hits::writebacks 835634 # number of Writeback hits
750system.cpu.l2cache.Writeback_hits::total 835634 # number of Writeback hits
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752system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
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791system.cpu.l2cache.Writeback_accesses::total 835634 # number of Writeback accesses(hits+misses)
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825system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80059.626815 # average overall miss latency
826system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73646.657153 # average overall miss latency
827system.cpu.l2cache.overall_avg_miss_latency::total 73858.624913 # average overall miss latency
828system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
829system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
830system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
831system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
832system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
833system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
834system.cpu.l2cache.fast_writes 0 # number of fast writes performed
835system.cpu.l2cache.cache_copies 0 # number of cache copies performed
836system.cpu.l2cache.writebacks::writebacks 74181 # number of writebacks
837system.cpu.l2cache.writebacks::total 74181 # number of writebacks
838system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses
839system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271964 # number of ReadReq MSHR misses
840system.cpu.l2cache.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses
841system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
842system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
843system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116857 # number of ReadExReq MSHR misses
844system.cpu.l2cache.ReadExReq_mshr_misses::total 116857 # number of ReadExReq MSHR misses
845system.cpu.l2cache.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses
846system.cpu.l2cache.demand_mshr_misses::cpu.data 388821 # number of demand (read+write) MSHR misses
847system.cpu.l2cache.demand_mshr_misses::total 402112 # number of demand (read+write) MSHR misses
848system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses
849system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses
850system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses

851system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
852system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
853system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable
854system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable
855system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses
856system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses

845system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles
846system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles
847system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles
848system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles
849system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles
850system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles
851system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles
852system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles
853system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23773879119 # number of demand (read+write) MSHR miss cycles
854system.cpu.l2cache.demand_mshr_miss_latency::total 24671360619 # number of demand (read+write) MSHR miss cycles
855system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 897481500 # number of overall MSHR miss cycles
856system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23773879119 # number of overall MSHR miss cycles
857system.cpu.l2cache.overall_mshr_miss_latency::total 24671360619 # number of overall MSHR miss cycles
858system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1335739000 # number of ReadReq MSHR uncacheable cycles
859system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1335739000 # number of ReadReq MSHR uncacheable cycles
860system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1899995000 # number of WriteReq MSHR uncacheable cycles
861system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1899995000 # number of WriteReq MSHR uncacheable cycles
862system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3235734000 # number of overall MSHR uncacheable cycles
863system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3235734000 # number of overall MSHR uncacheable cycles
864system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for ReadReq accesses
865system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250074 # mshr miss rate for ReadReq accesses
866system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141468 # mshr miss rate for ReadReq accesses
867system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
868system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
869system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383953 # mshr miss rate for ReadExReq accesses
870system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383953 # mshr miss rate for ReadExReq accesses
871system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for demand accesses
872system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for demand accesses
873system.cpu.l2cache.demand_mshr_miss_rate::total 0.173269 # mshr miss rate for demand accesses
874system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for overall accesses
875system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for overall accesses
876system.cpu.l2cache.overall_mshr_miss_rate::total 0.173269 # mshr miss rate for overall accesses
877system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981 # average ReadReq mshr miss latency
878system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238 # average ReadReq mshr miss latency
879system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183 # average ReadReq mshr miss latency
880system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846 # average UpgradeReq mshr miss latency
881system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846 # average UpgradeReq mshr miss latency
882system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency
883system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency
884system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
885system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
886system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency
887system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
888system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
889system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency

857system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles
858system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles
859system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles
860system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles
861system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles
862system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles
863system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles
864system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles
865system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23773879119 # number of demand (read+write) MSHR miss cycles
866system.cpu.l2cache.demand_mshr_miss_latency::total 24671360619 # number of demand (read+write) MSHR miss cycles
867system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 897481500 # number of overall MSHR miss cycles
868system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23773879119 # number of overall MSHR miss cycles
869system.cpu.l2cache.overall_mshr_miss_latency::total 24671360619 # number of overall MSHR miss cycles
870system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1335739000 # number of ReadReq MSHR uncacheable cycles
871system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1335739000 # number of ReadReq MSHR uncacheable cycles
872system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1899995000 # number of WriteReq MSHR uncacheable cycles
873system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1899995000 # number of WriteReq MSHR uncacheable cycles
874system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3235734000 # number of overall MSHR uncacheable cycles
875system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3235734000 # number of overall MSHR uncacheable cycles
876system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for ReadReq accesses
877system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250074 # mshr miss rate for ReadReq accesses
878system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141468 # mshr miss rate for ReadReq accesses
879system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
880system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
881system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383953 # mshr miss rate for ReadExReq accesses
882system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383953 # mshr miss rate for ReadExReq accesses
883system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for demand accesses
884system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for demand accesses
885system.cpu.l2cache.demand_mshr_miss_rate::total 0.173269 # mshr miss rate for demand accesses
886system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for overall accesses
887system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for overall accesses
888system.cpu.l2cache.overall_mshr_miss_rate::total 0.173269 # mshr miss rate for overall accesses
889system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981 # average ReadReq mshr miss latency
890system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238 # average ReadReq mshr miss latency
891system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183 # average ReadReq mshr miss latency
892system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846 # average UpgradeReq mshr miss latency
893system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846 # average UpgradeReq mshr miss latency
894system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency
895system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency
896system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
897system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
898system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency
899system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
900system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
901system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency

890system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
891system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
892system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
893system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
894system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
895system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

902system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192747.330447 # average ReadReq mshr uncacheable latency
903system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192747.330447 # average ReadReq mshr uncacheable latency
904system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196890.673575 # average WriteReq mshr uncacheable latency
905system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196890.673575 # average WriteReq mshr uncacheable latency
906system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195158.866104 # average overall mshr uncacheable latency
907system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195158.866104 # average overall mshr uncacheable latency

896system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
897system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution
898system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution
899system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
900system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
901system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution
902system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution
903system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
904system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
905system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution
906system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution
907system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes)
908system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes)
909system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes)
910system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes)
911system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes)
912system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes)
913system.cpu.toL2Bus.snoops 41937 # Total snoops (count)

908system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
909system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution
910system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution
911system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
912system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
913system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution
914system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution
915system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
916system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
917system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution
918system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution
919system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes)
920system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes)
921system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes)
922system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes)
923system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes)
924system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes)
925system.cpu.toL2Bus.snoops 41937 # Total snoops (count)

914system.cpu.toL2Bus.snoop_fanout::samples 3198175 # Request fanout histogram
915system.cpu.toL2Bus.snoop_fanout::mean 1.013058 # Request fanout histogram
916system.cpu.toL2Bus.snoop_fanout::stdev 0.113522 # Request fanout histogram

926system.cpu.toL2Bus.snoop_fanout::samples 3214755 # Request fanout histogram
927system.cpu.toL2Bus.snoop_fanout::mean 1.012990 # Request fanout histogram
928system.cpu.toL2Bus.snoop_fanout::stdev 0.113233 # Request fanout histogram

917system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
918system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

929system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
930system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

919system.cpu.toL2Bus.snoop_fanout::1 3156414 98.69% 98.69% # Request fanout histogram
920system.cpu.toL2Bus.snoop_fanout::2 41761 1.31% 100.00% # Request fanout histogram

931system.cpu.toL2Bus.snoop_fanout::1 3172994 98.70% 98.70% # Request fanout histogram
932system.cpu.toL2Bus.snoop_fanout::2 41761 1.30% 100.00% # Request fanout histogram

921system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
922system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
923system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

933system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
934system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
935system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram

924system.cpu.toL2Bus.snoop_fanout::total 3198175 # Request fanout histogram

936system.cpu.toL2Bus.snoop_fanout::total 3214755 # Request fanout histogram

925system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks)
926system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
927system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
928system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
929system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks)
930system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
931system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks)
932system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
933system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
934system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
935system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
936system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
937system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
938system.disk0.dma_write_txs 395 # Number of DMA write transactions.
939system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
940system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
941system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
942system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
943system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
944system.disk2.dma_write_txs 1 # Number of DMA write transactions.
945system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
946system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
947system.iobus.trans_dist::WriteReq 51202 # Transaction distribution
948system.iobus.trans_dist::WriteResp 9650 # Transaction distribution
949system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
950system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes)
951system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
952system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
953system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
954system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
955system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
956system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
957system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
958system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
959system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
960system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
961system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
962system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes)
963system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
964system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
965system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes)
966system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes)
967system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
968system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
969system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
970system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
971system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
972system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
973system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
974system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
975system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
976system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
977system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
978system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes)
979system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
980system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
981system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes)
982system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks)
983system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
984system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
985system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
986system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
987system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
988system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
989system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
990system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
991system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
992system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
993system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
994system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
995system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
996system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
997system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
998system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
999system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1000system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1001system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1002system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1003system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1004system.iobus.reqLayer29.occupancy 242042219 # Layer occupancy (ticks)
1005system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1006system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1007system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1008system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
1009system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1010system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks)
1011system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1012system.iocache.tags.replacements 41685 # number of replacements
1013system.iocache.tags.tagsinuse 1.342966 # Cycle average of tags in use
1014system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1015system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1016system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1017system.iocache.tags.warmup_cycle 1756462668000 # Cycle when the warmup percentage was hit.
1018system.iocache.tags.occ_blocks::tsunami.ide 1.342966 # Average occupied blocks per requestor
1019system.iocache.tags.occ_percent::tsunami.ide 0.083935 # Average percentage of cache occupancy
1020system.iocache.tags.occ_percent::total 0.083935 # Average percentage of cache occupancy
1021system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1022system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1023system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1024system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1025system.iocache.tags.data_accesses 375525 # Number of data accesses
1026system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1027system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1028system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
1029system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
1030system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
1031system.iocache.demand_misses::total 173 # number of demand (read+write) misses
1032system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
1033system.iocache.overall_misses::total 173 # number of overall misses
1034system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles
1035system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles
1036system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8755465836 # number of WriteInvalidateReq miss cycles
1037system.iocache.WriteInvalidateReq_miss_latency::total 8755465836 # number of WriteInvalidateReq miss cycles
1038system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles
1039system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles
1040system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles
1041system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles
1042system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
1043system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
1044system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
1045system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
1046system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
1047system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
1048system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
1049system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
1050system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1051system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1052system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
1053system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1054system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1055system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1056system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1057system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1058system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency
1059system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency
1060system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893 # average WriteInvalidateReq miss latency
1061system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893 # average WriteInvalidateReq miss latency
1062system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
1063system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency
1064system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
1065system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency
1066system.iocache.blocked_cycles::no_mshrs 72960 # number of cycles access was blocked
1067system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1068system.iocache.blocked::no_mshrs 9989 # number of cycles access was blocked
1069system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1070system.iocache.avg_blocked_cycles::no_mshrs 7.304034 # average number of cycles each access was blocked
1071system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1072system.iocache.fast_writes 0 # number of fast writes performed
1073system.iocache.cache_copies 0 # number of cache copies performed
1074system.iocache.writebacks::writebacks 41512 # number of writebacks
1075system.iocache.writebacks::total 41512 # number of writebacks
1076system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
1077system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
1078system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
1079system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
1080system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
1081system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
1082system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
1083system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
1084system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles
1085system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles
1086system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6594761836 # number of WriteInvalidateReq MSHR miss cycles
1087system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6594761836 # number of WriteInvalidateReq MSHR miss cycles
1088system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles
1089system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles
1090system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles
1091system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles
1092system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1093system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1094system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1095system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1096system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1097system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1098system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1099system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1100system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency
1101system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency
1102system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893 # average WriteInvalidateReq mshr miss latency
1103system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893 # average WriteInvalidateReq mshr miss latency
1104system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
1105system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
1106system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
1107system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
1108system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1109system.membus.trans_dist::ReadReq 292358 # Transaction distribution
1110system.membus.trans_dist::ReadResp 292358 # Transaction distribution
1111system.membus.trans_dist::WriteReq 9650 # Transaction distribution
1112system.membus.trans_dist::WriteResp 9650 # Transaction distribution
1113system.membus.trans_dist::Writeback 115693 # Transaction distribution
1114system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
1115system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
1116system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
1117system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
1118system.membus.trans_dist::ReadExReq 116738 # Transaction distribution
1119system.membus.trans_dist::ReadExResp 116738 # Transaction distribution
1120system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
1121system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878158 # Packet count per connected master and slave (bytes)
1122system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911318 # Packet count per connected master and slave (bytes)
1123system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
1124system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
1125system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes)
1126system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
1127system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes)
1128system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes)
1129system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes)
1130system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
1131system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes)
1132system.membus.snoops 431 # Total snoops (count)

937system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks)
938system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
939system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
940system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
941system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks)
942system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
943system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks)
944system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
945system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
946system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
947system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
948system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
949system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
950system.disk0.dma_write_txs 395 # Number of DMA write transactions.
951system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
952system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
953system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
954system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
955system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
956system.disk2.dma_write_txs 1 # Number of DMA write transactions.
957system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
958system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
959system.iobus.trans_dist::WriteReq 51202 # Transaction distribution
960system.iobus.trans_dist::WriteResp 9650 # Transaction distribution
961system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
962system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes)
963system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
964system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
965system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
966system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
967system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
968system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
969system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
970system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
971system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
972system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
973system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
974system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes)
975system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
976system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
977system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes)
978system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes)
979system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
980system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
981system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
982system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
983system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
984system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
985system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
986system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
987system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
988system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
989system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
990system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes)
991system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
992system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
993system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes)
994system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks)
995system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
996system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
997system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
998system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
999system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1000system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1001system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1002system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
1003system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1004system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
1005system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1006system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
1007system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1008system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1009system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1010system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1011system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1012system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1013system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1014system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1015system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1016system.iobus.reqLayer29.occupancy 242042219 # Layer occupancy (ticks)
1017system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1018system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1019system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1020system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
1021system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1022system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks)
1023system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1024system.iocache.tags.replacements 41685 # number of replacements
1025system.iocache.tags.tagsinuse 1.342966 # Cycle average of tags in use
1026system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1027system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1028system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1029system.iocache.tags.warmup_cycle 1756462668000 # Cycle when the warmup percentage was hit.
1030system.iocache.tags.occ_blocks::tsunami.ide 1.342966 # Average occupied blocks per requestor
1031system.iocache.tags.occ_percent::tsunami.ide 0.083935 # Average percentage of cache occupancy
1032system.iocache.tags.occ_percent::total 0.083935 # Average percentage of cache occupancy
1033system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1034system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1035system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1036system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1037system.iocache.tags.data_accesses 375525 # Number of data accesses
1038system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1039system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1040system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
1041system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
1042system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
1043system.iocache.demand_misses::total 173 # number of demand (read+write) misses
1044system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
1045system.iocache.overall_misses::total 173 # number of overall misses
1046system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles
1047system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles
1048system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8755465836 # number of WriteInvalidateReq miss cycles
1049system.iocache.WriteInvalidateReq_miss_latency::total 8755465836 # number of WriteInvalidateReq miss cycles
1050system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles
1051system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles
1052system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles
1053system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles
1054system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
1055system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
1056system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
1057system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
1058system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
1059system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
1060system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
1061system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
1062system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1063system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1064system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
1065system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1066system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1067system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1068system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1069system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1070system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency
1071system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency
1072system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893 # average WriteInvalidateReq miss latency
1073system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893 # average WriteInvalidateReq miss latency
1074system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
1075system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency
1076system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
1077system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency
1078system.iocache.blocked_cycles::no_mshrs 72960 # number of cycles access was blocked
1079system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1080system.iocache.blocked::no_mshrs 9989 # number of cycles access was blocked
1081system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1082system.iocache.avg_blocked_cycles::no_mshrs 7.304034 # average number of cycles each access was blocked
1083system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1084system.iocache.fast_writes 0 # number of fast writes performed
1085system.iocache.cache_copies 0 # number of cache copies performed
1086system.iocache.writebacks::writebacks 41512 # number of writebacks
1087system.iocache.writebacks::total 41512 # number of writebacks
1088system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
1089system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
1090system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
1091system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
1092system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
1093system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
1094system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
1095system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
1096system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles
1097system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles
1098system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6594761836 # number of WriteInvalidateReq MSHR miss cycles
1099system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6594761836 # number of WriteInvalidateReq MSHR miss cycles
1100system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles
1101system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles
1102system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles
1103system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles
1104system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1105system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1106system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1107system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1108system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1109system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1110system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1111system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1112system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency
1113system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency
1114system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893 # average WriteInvalidateReq mshr miss latency
1115system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893 # average WriteInvalidateReq mshr miss latency
1116system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
1117system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
1118system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
1119system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
1120system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1121system.membus.trans_dist::ReadReq 292358 # Transaction distribution
1122system.membus.trans_dist::ReadResp 292358 # Transaction distribution
1123system.membus.trans_dist::WriteReq 9650 # Transaction distribution
1124system.membus.trans_dist::WriteResp 9650 # Transaction distribution
1125system.membus.trans_dist::Writeback 115693 # Transaction distribution
1126system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
1127system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
1128system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
1129system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
1130system.membus.trans_dist::ReadExReq 116738 # Transaction distribution
1131system.membus.trans_dist::ReadExResp 116738 # Transaction distribution
1132system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
1133system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878158 # Packet count per connected master and slave (bytes)
1134system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911318 # Packet count per connected master and slave (bytes)
1135system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
1136system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
1137system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes)
1138system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
1139system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes)
1140system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes)
1141system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes)
1142system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
1143system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes)
1144system.membus.snoops 431 # Total snoops (count)

1133system.membus.snoop_fanout::samples 559589 # Request fanout histogram

1145system.membus.snoop_fanout::samples 576169 # Request fanout histogram

1134system.membus.snoop_fanout::mean 1 # Request fanout histogram
1135system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1136system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1137system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1146system.membus.snoop_fanout::mean 1 # Request fanout histogram
1147system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1148system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1149system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1138system.membus.snoop_fanout::1 559589 100.00% 100.00% # Request fanout histogram

1150system.membus.snoop_fanout::1 576169 100.00% 100.00% # Request fanout histogram

1139system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1140system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1141system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1142system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1151system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1152system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1153system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1154system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1143system.membus.snoop_fanout::total 559589 # Request fanout histogram

1155system.membus.snoop_fanout::total 576169 # Request fanout histogram