1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.941276 # Number of seconds simulated
4sim_ticks 1941275996000 # Number of ticks simulated
5final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 855166 # Simulator instruction rate (inst/s)
8host_op_rate 855166 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 29548473540 # Simulator tick rate (ticks/s)
10host_mem_usage 325188 # Number of bytes of host memory used
11host_seconds 65.70 # Real time elapsed on the host
12sim_insts 56182685 # Number of instructions simulated
13sim_ops 56182685 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 844800 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 844800 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 7410752 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7410752 # Number of bytes written to this memory
--- 269 unchanged lines hidden (view full) ---
293system.physmem_1.preBackEnergy 1101055791000 # Energy for precharge background per rank (pJ)
294system.physmem_1.totalEnergy 1302809128905 # Total energy per rank (pJ)
295system.physmem_1.averagePower 671.109728 # Core power per rank (mW)
296system.physmem_1.memoryStateTime::IDLE 1831423384000 # Time in different power states
297system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states
298system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
299system.physmem_1.memoryStateTime::ACT 45029052250 # Time in different power states
300system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
301system.cpu_clk_domain.clock 500 # Clock period in ticks
302system.cpu.dtb.fetch_hits 0 # ITB hits
303system.cpu.dtb.fetch_misses 0 # ITB misses
304system.cpu.dtb.fetch_acv 0 # ITB acv
305system.cpu.dtb.fetch_accesses 0 # ITB accesses
306system.cpu.dtb.read_hits 9064642 # DTB read hits
307system.cpu.dtb.read_misses 10324 # DTB read misses
308system.cpu.dtb.read_acv 210 # DTB read access violations
--- 17 unchanged lines hidden (view full) ---
326system.cpu.itb.write_hits 0 # DTB write hits
327system.cpu.itb.write_misses 0 # DTB write misses
328system.cpu.itb.write_acv 0 # DTB write access violations
329system.cpu.itb.write_accesses 0 # DTB write accesses
330system.cpu.itb.data_hits 0 # DTB hits
331system.cpu.itb.data_misses 0 # DTB misses
332system.cpu.itb.data_acv 0 # DTB access violations
333system.cpu.itb.data_accesses 0 # DTB accesses
334system.cpu.numCycles 3882551992 # number of cpu cycles simulated
335system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
336system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
337system.cpu.kern.inst.arm 0 # number of arm instructions executed
338system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed
339system.cpu.kern.inst.hwrei 212050 # number of hwrei instructions executed
340system.cpu.kern.ipl_count::0 74912 40.88% 40.88% # number of times we switched to this ipl
341system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
--- 127 unchanged lines hidden (view full) ---
469system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction
470system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction
471system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction
472system.cpu.op_class::MemRead 9328618 16.60% 86.95% # Class of executed instruction
473system.cpu.op_class::MemWrite 6378045 11.35% 98.30% # Class of executed instruction
474system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction
475system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
476system.cpu.op_class::total 56194518 # Class of executed instruction
477system.cpu.dcache.tags.replacements 1390402 # number of replacements
478system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use
479system.cpu.dcache.tags.total_refs 14048961 # Total number of references to valid blocks.
480system.cpu.dcache.tags.sampled_refs 1390914 # Sample count of references to valid blocks.
481system.cpu.dcache.tags.avg_refs 10.100525 # Average number of references to valid blocks.
482system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit.
483system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor
484system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy
485system.cpu.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy
486system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
487system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
488system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
489system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
490system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
491system.cpu.dcache.tags.tag_accesses 63150419 # Number of tag accesses
492system.cpu.dcache.tags.data_accesses 63150419 # Number of data accesses
493system.cpu.dcache.ReadReq_hits::cpu.data 7814383 # number of ReadReq hits
494system.cpu.dcache.ReadReq_hits::total 7814383 # number of ReadReq hits
495system.cpu.dcache.WriteReq_hits::cpu.data 5852265 # number of WriteReq hits
496system.cpu.dcache.WriteReq_hits::total 5852265 # number of WriteReq hits
497system.cpu.dcache.LoadLockedReq_hits::cpu.data 183036 # number of LoadLockedReq hits
498system.cpu.dcache.LoadLockedReq_hits::total 183036 # number of LoadLockedReq hits
499system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits
500system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits
--- 110 unchanged lines hidden (view full) ---
611system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency
612system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency
613system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency
614system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency
615system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency
616system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency
617system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401 # average overall mshr uncacheable latency
618system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401 # average overall mshr uncacheable latency
619system.cpu.icache.tags.replacements 928931 # number of replacements
620system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use
621system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks.
622system.cpu.icache.tags.sampled_refs 929442 # Sample count of references to valid blocks.
623system.cpu.icache.tags.avg_refs 59.460318 # Average number of references to valid blocks.
624system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit.
625system.cpu.icache.tags.occ_blocks::cpu.inst 506.355616 # Average occupied blocks per requestor
626system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy
627system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy
628system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
629system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
630system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
631system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id
632system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
633system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
634system.cpu.icache.tags.tag_accesses 57124121 # Number of tag accesses
635system.cpu.icache.tags.data_accesses 57124121 # Number of data accesses
636system.cpu.icache.ReadReq_hits::cpu.inst 55264917 # number of ReadReq hits
637system.cpu.icache.ReadReq_hits::total 55264917 # number of ReadReq hits
638system.cpu.icache.demand_hits::cpu.inst 55264917 # number of demand (read+write) hits
639system.cpu.icache.demand_hits::total 55264917 # number of demand (read+write) hits
640system.cpu.icache.overall_hits::cpu.inst 55264917 # number of overall hits
641system.cpu.icache.overall_hits::total 55264917 # number of overall hits
642system.cpu.icache.ReadReq_misses::cpu.inst 929602 # number of ReadReq misses
643system.cpu.icache.ReadReq_misses::total 929602 # number of ReadReq misses
--- 52 unchanged lines hidden (view full) ---
696system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses
697system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses
698system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459 # average ReadReq mshr miss latency
699system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459 # average ReadReq mshr miss latency
700system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency
701system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency
702system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency
703system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency
704system.cpu.l2cache.tags.replacements 336393 # number of replacements
705system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use
706system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks.
707system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks.
708system.cpu.l2cache.tags.avg_refs 9.787932 # Average number of references to valid blocks.
709system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit.
710system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820493 # Average occupied blocks per requestor
711system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.121272 # Average occupied blocks per requestor
--- 6 unchanged lines hidden (view full) ---
718system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
719system.cpu.l2cache.tags.age_task_id_blocks_1024::1 722 # Occupied blocks per task id
720system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id
721system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id
722system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id
723system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
724system.cpu.l2cache.tags.tag_accesses 37812972 # Number of tag accesses
725system.cpu.l2cache.tags.data_accesses 37812972 # Number of data accesses
726system.cpu.l2cache.WritebackDirty_hits::writebacks 834944 # number of WritebackDirty hits
727system.cpu.l2cache.WritebackDirty_hits::total 834944 # number of WritebackDirty hits
728system.cpu.l2cache.WritebackClean_hits::writebacks 928709 # number of WritebackClean hits
729system.cpu.l2cache.WritebackClean_hits::total 928709 # number of WritebackClean hits
730system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
731system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
732system.cpu.l2cache.ReadExReq_hits::cpu.data 187490 # number of ReadExReq hits
733system.cpu.l2cache.ReadExReq_hits::total 187490 # number of ReadExReq hits
--- 160 unchanged lines hidden (view full) ---
894system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927 # average overall mshr uncacheable latency
895system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927 # average overall mshr uncacheable latency
896system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter.
897system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data.
898system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
899system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter.
900system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
901system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
902system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
903system.cpu.toL2Bus.trans_dist::ReadResp 2023294 # Transaction distribution
904system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution
905system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution
906system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution
907system.cpu.toL2Bus.trans_dist::WritebackClean 928931 # Transaction distribution
908system.cpu.toL2Bus.trans_dist::CleanEvict 817743 # Transaction distribution
909system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
--- 36 unchanged lines hidden (view full) ---
946system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
947system.disk0.dma_write_txs 395 # Number of DMA write transactions.
948system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
949system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
950system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
951system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
952system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
953system.disk2.dma_write_txs 1 # Number of DMA write transactions.
954system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
955system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
956system.iobus.trans_dist::WriteReq 51205 # Transaction distribution
957system.iobus.trans_dist::WriteResp 51205 # Transaction distribution
958system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes)
959system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
960system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
961system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
--- 38 unchanged lines hidden (view full) ---
1000system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks)
1001system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1002system.iobus.reqLayer27.occupancy 215662167 # Layer occupancy (ticks)
1003system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1004system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks)
1005system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1006system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
1007system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1008system.iocache.tags.replacements 41685 # number of replacements
1009system.iocache.tags.tagsinuse 1.339384 # Cycle average of tags in use
1010system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1011system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1012system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1013system.iocache.tags.warmup_cycle 1774106669000 # Cycle when the warmup percentage was hit.
1014system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor
1015system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy
1016system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy
1017system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1018system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1019system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1020system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1021system.iocache.tags.data_accesses 375525 # Number of data accesses
1022system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1023system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1024system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1025system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1026system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
1027system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
1028system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
1029system.iocache.overall_misses::total 41725 # number of overall misses
--- 64 unchanged lines hidden (view full) ---
1094system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency
1095system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency
1096system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency
1097system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency
1098system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency
1099system.iocache.demand_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency
1100system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency
1101system.iocache.overall_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency
1102system.membus.trans_dist::ReadReq 6930 # Transaction distribution
1103system.membus.trans_dist::ReadResp 292274 # Transaction distribution
1104system.membus.trans_dist::WriteReq 9653 # Transaction distribution
1105system.membus.trans_dist::WriteResp 9653 # Transaction distribution
1106system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution
1107system.membus.trans_dist::CleanEvict 261560 # Transaction distribution
1108system.membus.trans_dist::UpgradeReq 150 # Transaction distribution
1109system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
--- 28 unchanged lines hidden (view full) ---
1138system.membus.reqLayer0.occupancy 30122500 # Layer occupancy (ticks)
1139system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1140system.membus.reqLayer1.occupancy 1287200967 # Layer occupancy (ticks)
1141system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1142system.membus.respLayer1.occupancy 2143013000 # Layer occupancy (ticks)
1143system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1144system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks)
1145system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1146system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1147system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1148system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1149system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1150system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1151system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1152system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1153system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
--- 15 unchanged lines hidden (view full) ---
1169system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1170system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1171system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1172system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1173system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1174system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1175system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1176system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
1177
1178---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.941276 # Number of seconds simulated
4sim_ticks 1941275996000 # Number of ticks simulated
5final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 855166 # Simulator instruction rate (inst/s)
8host_op_rate 855166 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 29548473540 # Simulator tick rate (ticks/s)
10host_mem_usage 325188 # Number of bytes of host memory used
11host_seconds 65.70 # Real time elapsed on the host
12sim_insts 56182685 # Number of instructions simulated
13sim_ops 56182685 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 844800 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 844800 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 7410752 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7410752 # Number of bytes written to this memory
--- 269 unchanged lines hidden (view full) ---
293system.physmem_1.preBackEnergy 1101055791000 # Energy for precharge background per rank (pJ)
294system.physmem_1.totalEnergy 1302809128905 # Total energy per rank (pJ)
295system.physmem_1.averagePower 671.109728 # Core power per rank (mW)
296system.physmem_1.memoryStateTime::IDLE 1831423384000 # Time in different power states
297system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states
298system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
299system.physmem_1.memoryStateTime::ACT 45029052250 # Time in different power states
300system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
301system.cpu_clk_domain.clock 500 # Clock period in ticks
302system.cpu.dtb.fetch_hits 0 # ITB hits
303system.cpu.dtb.fetch_misses 0 # ITB misses
304system.cpu.dtb.fetch_acv 0 # ITB acv
305system.cpu.dtb.fetch_accesses 0 # ITB accesses
306system.cpu.dtb.read_hits 9064642 # DTB read hits
307system.cpu.dtb.read_misses 10324 # DTB read misses
308system.cpu.dtb.read_acv 210 # DTB read access violations
--- 17 unchanged lines hidden (view full) ---
326system.cpu.itb.write_hits 0 # DTB write hits
327system.cpu.itb.write_misses 0 # DTB write misses
328system.cpu.itb.write_acv 0 # DTB write access violations
329system.cpu.itb.write_accesses 0 # DTB write accesses
330system.cpu.itb.data_hits 0 # DTB hits
331system.cpu.itb.data_misses 0 # DTB misses
332system.cpu.itb.data_acv 0 # DTB access violations
333system.cpu.itb.data_accesses 0 # DTB accesses
334system.cpu.numCycles 3882551992 # number of cpu cycles simulated
335system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
336system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
337system.cpu.kern.inst.arm 0 # number of arm instructions executed
338system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed
339system.cpu.kern.inst.hwrei 212050 # number of hwrei instructions executed
340system.cpu.kern.ipl_count::0 74912 40.88% 40.88% # number of times we switched to this ipl
341system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
--- 127 unchanged lines hidden (view full) ---
469system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction
470system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction
471system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction
472system.cpu.op_class::MemRead 9328618 16.60% 86.95% # Class of executed instruction
473system.cpu.op_class::MemWrite 6378045 11.35% 98.30% # Class of executed instruction
474system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction
475system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
476system.cpu.op_class::total 56194518 # Class of executed instruction
477system.cpu.dcache.tags.replacements 1390402 # number of replacements
478system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use
479system.cpu.dcache.tags.total_refs 14048961 # Total number of references to valid blocks.
480system.cpu.dcache.tags.sampled_refs 1390914 # Sample count of references to valid blocks.
481system.cpu.dcache.tags.avg_refs 10.100525 # Average number of references to valid blocks.
482system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit.
483system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor
484system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy
485system.cpu.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy
486system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
487system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
488system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
489system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
490system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
491system.cpu.dcache.tags.tag_accesses 63150419 # Number of tag accesses
492system.cpu.dcache.tags.data_accesses 63150419 # Number of data accesses
493system.cpu.dcache.ReadReq_hits::cpu.data 7814383 # number of ReadReq hits
494system.cpu.dcache.ReadReq_hits::total 7814383 # number of ReadReq hits
495system.cpu.dcache.WriteReq_hits::cpu.data 5852265 # number of WriteReq hits
496system.cpu.dcache.WriteReq_hits::total 5852265 # number of WriteReq hits
497system.cpu.dcache.LoadLockedReq_hits::cpu.data 183036 # number of LoadLockedReq hits
498system.cpu.dcache.LoadLockedReq_hits::total 183036 # number of LoadLockedReq hits
499system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits
500system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits
--- 110 unchanged lines hidden (view full) ---
611system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency
612system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency
613system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency
614system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency
615system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency
616system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency
617system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401 # average overall mshr uncacheable latency
618system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401 # average overall mshr uncacheable latency
619system.cpu.icache.tags.replacements 928931 # number of replacements
620system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use
621system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks.
622system.cpu.icache.tags.sampled_refs 929442 # Sample count of references to valid blocks.
623system.cpu.icache.tags.avg_refs 59.460318 # Average number of references to valid blocks.
624system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit.
625system.cpu.icache.tags.occ_blocks::cpu.inst 506.355616 # Average occupied blocks per requestor
626system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy
627system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy
628system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
629system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
630system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
631system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id
632system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
633system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
634system.cpu.icache.tags.tag_accesses 57124121 # Number of tag accesses
635system.cpu.icache.tags.data_accesses 57124121 # Number of data accesses
636system.cpu.icache.ReadReq_hits::cpu.inst 55264917 # number of ReadReq hits
637system.cpu.icache.ReadReq_hits::total 55264917 # number of ReadReq hits
638system.cpu.icache.demand_hits::cpu.inst 55264917 # number of demand (read+write) hits
639system.cpu.icache.demand_hits::total 55264917 # number of demand (read+write) hits
640system.cpu.icache.overall_hits::cpu.inst 55264917 # number of overall hits
641system.cpu.icache.overall_hits::total 55264917 # number of overall hits
642system.cpu.icache.ReadReq_misses::cpu.inst 929602 # number of ReadReq misses
643system.cpu.icache.ReadReq_misses::total 929602 # number of ReadReq misses
--- 52 unchanged lines hidden (view full) ---
696system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses
697system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses
698system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459 # average ReadReq mshr miss latency
699system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459 # average ReadReq mshr miss latency
700system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency
701system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency
702system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency
703system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency
704system.cpu.l2cache.tags.replacements 336393 # number of replacements
705system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use
706system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks.
707system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks.
708system.cpu.l2cache.tags.avg_refs 9.787932 # Average number of references to valid blocks.
709system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit.
710system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820493 # Average occupied blocks per requestor
711system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.121272 # Average occupied blocks per requestor
--- 6 unchanged lines hidden (view full) ---
718system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
719system.cpu.l2cache.tags.age_task_id_blocks_1024::1 722 # Occupied blocks per task id
720system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id
721system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id
722system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id
723system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
724system.cpu.l2cache.tags.tag_accesses 37812972 # Number of tag accesses
725system.cpu.l2cache.tags.data_accesses 37812972 # Number of data accesses
726system.cpu.l2cache.WritebackDirty_hits::writebacks 834944 # number of WritebackDirty hits
727system.cpu.l2cache.WritebackDirty_hits::total 834944 # number of WritebackDirty hits
728system.cpu.l2cache.WritebackClean_hits::writebacks 928709 # number of WritebackClean hits
729system.cpu.l2cache.WritebackClean_hits::total 928709 # number of WritebackClean hits
730system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
731system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
732system.cpu.l2cache.ReadExReq_hits::cpu.data 187490 # number of ReadExReq hits
733system.cpu.l2cache.ReadExReq_hits::total 187490 # number of ReadExReq hits
--- 160 unchanged lines hidden (view full) ---
894system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927 # average overall mshr uncacheable latency
895system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927 # average overall mshr uncacheable latency
896system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter.
897system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data.
898system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
899system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter.
900system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
901system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
902system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution
903system.cpu.toL2Bus.trans_dist::ReadResp 2023294 # Transaction distribution
904system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution
905system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution
906system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution
907system.cpu.toL2Bus.trans_dist::WritebackClean 928931 # Transaction distribution
908system.cpu.toL2Bus.trans_dist::CleanEvict 817743 # Transaction distribution
909system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
--- 36 unchanged lines hidden (view full) ---
946system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
947system.disk0.dma_write_txs 395 # Number of DMA write transactions.
948system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
949system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
950system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
951system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
952system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
953system.disk2.dma_write_txs 1 # Number of DMA write transactions.
954system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
955system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
956system.iobus.trans_dist::WriteReq 51205 # Transaction distribution
957system.iobus.trans_dist::WriteResp 51205 # Transaction distribution
958system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes)
959system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
960system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
961system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
--- 38 unchanged lines hidden (view full) ---
1000system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks)
1001system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1002system.iobus.reqLayer27.occupancy 215662167 # Layer occupancy (ticks)
1003system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1004system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks)
1005system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1006system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
1007system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1008system.iocache.tags.replacements 41685 # number of replacements
1009system.iocache.tags.tagsinuse 1.339384 # Cycle average of tags in use
1010system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1011system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1012system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1013system.iocache.tags.warmup_cycle 1774106669000 # Cycle when the warmup percentage was hit.
1014system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor
1015system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy
1016system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy
1017system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1018system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1019system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1020system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1021system.iocache.tags.data_accesses 375525 # Number of data accesses
1022system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1023system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1024system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1025system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1026system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
1027system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
1028system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
1029system.iocache.overall_misses::total 41725 # number of overall misses
--- 64 unchanged lines hidden (view full) ---
1094system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency
1095system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency
1096system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency
1097system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency
1098system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency
1099system.iocache.demand_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency
1100system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency
1101system.iocache.overall_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency
1102system.membus.trans_dist::ReadReq 6930 # Transaction distribution
1103system.membus.trans_dist::ReadResp 292274 # Transaction distribution
1104system.membus.trans_dist::WriteReq 9653 # Transaction distribution
1105system.membus.trans_dist::WriteResp 9653 # Transaction distribution
1106system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution
1107system.membus.trans_dist::CleanEvict 261560 # Transaction distribution
1108system.membus.trans_dist::UpgradeReq 150 # Transaction distribution
1109system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
--- 28 unchanged lines hidden (view full) ---
1138system.membus.reqLayer0.occupancy 30122500 # Layer occupancy (ticks)
1139system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1140system.membus.reqLayer1.occupancy 1287200967 # Layer occupancy (ticks)
1141system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1142system.membus.respLayer1.occupancy 2143013000 # Layer occupancy (ticks)
1143system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1144system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks)
1145system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1146system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1147system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1148system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1149system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1150system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1151system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1152system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1153system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
--- 15 unchanged lines hidden (view full) ---
1169system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1170system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1171system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1172system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1173system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1174system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1175system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1176system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
1177
1178---------- End Simulation Statistics ----------