1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.920419 # Number of seconds simulated
4sim_ticks 1920418772000 # Number of ticks simulated
5final_tick 1920418772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1235696 # Simulator instruction rate (inst/s)
8host_op_rate 1235696 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 42298287542 # Simulator tick rate (ticks/s)
10host_mem_usage 370580 # Number of bytes of host memory used
11host_seconds 45.40 # Real time elapsed on the host
12sim_insts 56102800 # Number of instructions simulated
13sim_ops 56102800 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::total 25709504 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 7403648 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7403648 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory
26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 401711 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 115682 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 115682 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 442903 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 12944043 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 13387447 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 442903 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 442903 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 3855226 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 3855226 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 3855226 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 442903 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 12944043 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 17242673 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 401711 # Number of read requests accepted
44system.physmem.writeReqs 157234 # Number of write requests accepted
45system.physmem.readBursts 401711 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 157234 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 25703040 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 6464 # Total number of bytes read from write queue
49system.physmem.bytesWritten 9922432 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 25709504 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 10062976 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 2169 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 25160 # Per bank write bursts
56system.physmem.perBankRdBursts::1 25539 # Per bank write bursts
57system.physmem.perBankRdBursts::2 25602 # Per bank write bursts
58system.physmem.perBankRdBursts::3 25523 # Per bank write bursts
59system.physmem.perBankRdBursts::4 24974 # Per bank write bursts
60system.physmem.perBankRdBursts::5 24969 # Per bank write bursts
61system.physmem.perBankRdBursts::6 24210 # Per bank write bursts
62system.physmem.perBankRdBursts::7 24487 # Per bank write bursts
63system.physmem.perBankRdBursts::8 25140 # Per bank write bursts
64system.physmem.perBankRdBursts::9 24800 # Per bank write bursts
65system.physmem.perBankRdBursts::10 25360 # Per bank write bursts
66system.physmem.perBankRdBursts::11 24834 # Per bank write bursts
67system.physmem.perBankRdBursts::12 24395 # Per bank write bursts
68system.physmem.perBankRdBursts::13 25368 # Per bank write bursts
69system.physmem.perBankRdBursts::14 25772 # Per bank write bursts
70system.physmem.perBankRdBursts::15 25477 # Per bank write bursts
71system.physmem.perBankWrBursts::0 10048 # Per bank write bursts
72system.physmem.perBankWrBursts::1 9910 # Per bank write bursts
73system.physmem.perBankWrBursts::2 10442 # Per bank write bursts
74system.physmem.perBankWrBursts::3 9959 # Per bank write bursts
75system.physmem.perBankWrBursts::4 9552 # Per bank write bursts
76system.physmem.perBankWrBursts::5 9342 # Per bank write bursts
77system.physmem.perBankWrBursts::6 8789 # Per bank write bursts
78system.physmem.perBankWrBursts::7 8561 # Per bank write bursts
79system.physmem.perBankWrBursts::8 9905 # Per bank write bursts
80system.physmem.perBankWrBursts::9 8742 # Per bank write bursts
81system.physmem.perBankWrBursts::10 9526 # Per bank write bursts
82system.physmem.perBankWrBursts::11 9262 # Per bank write bursts
83system.physmem.perBankWrBursts::12 9811 # Per bank write bursts
84system.physmem.perBankWrBursts::13 10568 # Per bank write bursts
85system.physmem.perBankWrBursts::14 10305 # Per bank write bursts
86system.physmem.perBankWrBursts::15 10316 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89system.physmem.totGap 1920406851000 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 401711 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 157234 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 401596 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see

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143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 4336 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 7978 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 9053 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 9729 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 10585 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 11129 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 12018 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 11559 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 11623 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 10445 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 9597 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 8159 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 7669 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 6479 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 6050 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 5940 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 5895 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 361 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 365 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 246 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 254 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 229 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 216 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 135 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 66451 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 536.116417 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 326.833533 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 417.088244 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 15015 22.60% 22.60% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 11499 17.30% 39.90% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 4712 7.09% 46.99% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 3144 4.73% 51.72% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 3072 4.62% 56.35% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 1860 2.80% 59.14% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 1297 1.95% 61.10% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 1463 2.20% 63.30% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 24389 36.70% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 66451 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 5539 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 72.502618 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::stdev 2835.834060 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::0-8191 5536 99.95% 99.95% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::total 5539 # Reads before turning the bus around for writes
222system.physmem.wrPerTurnAround::samples 5539 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::mean 27.990251 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::gmean 21.086567 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::stdev 34.704660 # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::16-23 4497 81.19% 81.19% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::24-31 178 3.21% 84.40% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::32-39 301 5.43% 89.84% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::40-47 51 0.92% 90.76% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::48-55 99 1.79% 92.54% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::56-63 47 0.85% 93.39% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::64-71 17 0.31% 93.70% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::72-79 11 0.20% 93.90% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::80-87 12 0.22% 94.11% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::88-95 4 0.07% 94.19% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::96-103 17 0.31% 94.49% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::104-111 7 0.13% 94.62% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::112-119 14 0.25% 94.87% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::120-127 6 0.11% 94.98% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::128-135 9 0.16% 95.14% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::136-143 38 0.69% 95.83% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::144-151 16 0.29% 96.12% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::152-159 19 0.34% 96.46% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::160-167 88 1.59% 98.05% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::168-175 43 0.78% 98.83% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::176-183 11 0.20% 99.03% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::184-191 20 0.36% 99.39% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::192-199 10 0.18% 99.57% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::200-207 3 0.05% 99.62% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::208-215 3 0.05% 99.68% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::216-223 4 0.07% 99.75% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::224-231 4 0.07% 99.82% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::232-239 5 0.09% 99.91% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::240-247 3 0.05% 99.96% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::total 5539 # Writes before turning the bus around for reads
258system.physmem.totQLat 2115529750 # Total ticks spent queuing
259system.physmem.totMemAccLat 9645717250 # Total ticks spent from burst creation until serviced by the DRAM
260system.physmem.totBusLat 2008050000 # Total ticks spent in databus transfers
261system.physmem.avgQLat 5267.62 # Average queueing delay per DRAM burst
262system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
263system.physmem.avgMemAccLat 24017.62 # Average memory access latency per DRAM burst
264system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s
265system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s
266system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s
267system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s
268system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
269system.physmem.busUtil 0.14 # Data bus utilization in percentage
270system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
271system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
272system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
273system.physmem.avgWrQLen 25.84 # Average write queue length when enqueuing
274system.physmem.readRowHits 359951 # Number of row buffer hits during reads
275system.physmem.writeRowHits 130246 # Number of row buffer hits during writes
276system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads
277system.physmem.writeRowHitRate 83.99 # Row buffer hit rate for writes
278system.physmem.avgGap 3435770.69 # Average gap between requests
279system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined
280system.physmem_0.actEnergy 245601720 # Energy for activate commands per rank (pJ)
281system.physmem_0.preEnergy 134008875 # Energy for precharge commands per rank (pJ)
282system.physmem_0.readEnergy 1563619200 # Energy for read commands per rank (pJ)
283system.physmem_0.writeEnergy 496387440 # Energy for write commands per rank (pJ)
284system.physmem_0.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ)
285system.physmem_0.actBackEnergy 64124070615 # Energy for active background per rank (pJ)
286system.physmem_0.preBackEnergy 1096000726500 # Energy for precharge background per rank (pJ)
287system.physmem_0.totalEnergy 1287996669870 # Total energy per rank (pJ)
288system.physmem_0.averagePower 670.686102 # Core power per rank (mW)
289system.physmem_0.memoryStateTime::IDLE 1823056528000 # Time in different power states
290system.physmem_0.memoryStateTime::REF 64126920000 # Time in different power states
291system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
292system.physmem_0.memoryStateTime::ACT 33233084500 # Time in different power states
293system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
294system.physmem_1.actEnergy 256767840 # Energy for activate commands per rank (pJ)
295system.physmem_1.preEnergy 140101500 # Energy for precharge commands per rank (pJ)
296system.physmem_1.readEnergy 1568938800 # Energy for read commands per rank (pJ)
297system.physmem_1.writeEnergy 508258800 # Energy for write commands per rank (pJ)
298system.physmem_1.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ)
299system.physmem_1.actBackEnergy 64541926215 # Energy for active background per rank (pJ)
300system.physmem_1.preBackEnergy 1095634186500 # Energy for precharge background per rank (pJ)
301system.physmem_1.totalEnergy 1288082435175 # Total energy per rank (pJ)
302system.physmem_1.averagePower 670.730762 # Core power per rank (mW)
303system.physmem_1.memoryStateTime::IDLE 1822448681750 # Time in different power states
304system.physmem_1.memoryStateTime::REF 64126920000 # Time in different power states
305system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
306system.physmem_1.memoryStateTime::ACT 33840930750 # Time in different power states
307system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
308system.cpu_clk_domain.clock 500 # Clock period in ticks
309system.cpu.dtb.fetch_hits 0 # ITB hits
310system.cpu.dtb.fetch_misses 0 # ITB misses
311system.cpu.dtb.fetch_acv 0 # ITB acv
312system.cpu.dtb.fetch_accesses 0 # ITB accesses
313system.cpu.dtb.read_hits 9052701 # DTB read hits
314system.cpu.dtb.read_misses 10312 # DTB read misses
315system.cpu.dtb.read_acv 210 # DTB read access violations
316system.cpu.dtb.read_accesses 728817 # DTB read accesses
317system.cpu.dtb.write_hits 6349364 # DTB write hits
318system.cpu.dtb.write_misses 1140 # DTB write misses
319system.cpu.dtb.write_acv 157 # DTB write access violations
320system.cpu.dtb.write_accesses 291929 # DTB write accesses
321system.cpu.dtb.data_hits 15402065 # DTB hits
322system.cpu.dtb.data_misses 11452 # DTB misses
323system.cpu.dtb.data_acv 367 # DTB access violations
324system.cpu.dtb.data_accesses 1020746 # DTB accesses
325system.cpu.itb.fetch_hits 4973977 # ITB hits
326system.cpu.itb.fetch_misses 4997 # ITB misses
327system.cpu.itb.fetch_acv 184 # ITB acv
328system.cpu.itb.fetch_accesses 4978974 # ITB accesses
329system.cpu.itb.read_hits 0 # DTB read hits
330system.cpu.itb.read_misses 0 # DTB read misses
331system.cpu.itb.read_acv 0 # DTB read access violations
332system.cpu.itb.read_accesses 0 # DTB read accesses
333system.cpu.itb.write_hits 0 # DTB write hits
334system.cpu.itb.write_misses 0 # DTB write misses
335system.cpu.itb.write_acv 0 # DTB write access violations
336system.cpu.itb.write_accesses 0 # DTB write accesses
337system.cpu.itb.data_hits 0 # DTB hits
338system.cpu.itb.data_misses 0 # DTB misses
339system.cpu.itb.data_acv 0 # DTB access violations
340system.cpu.itb.data_accesses 0 # DTB accesses
341system.cpu.numCycles 3840837544 # number of cpu cycles simulated
342system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
343system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
344system.cpu.committedInsts 56102800 # Number of instructions committed
345system.cpu.committedOps 56102800 # Number of ops (including micro ops) committed
346system.cpu.num_int_alu_accesses 51978055 # Number of integer alu accesses
347system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses
348system.cpu.num_func_calls 1481300 # number of times a function call or return occured
349system.cpu.num_conditional_control_insts 6461124 # number of instructions that are conditional controls
350system.cpu.num_int_insts 51978055 # number of integer instructions
351system.cpu.num_fp_insts 324393 # number of float instructions
352system.cpu.num_int_register_reads 71208426 # number of times the integer registers were read
353system.cpu.num_int_register_writes 38459690 # number of times the integer registers were written
354system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read
355system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written
356system.cpu.num_mem_refs 15454652 # number of memory refs
357system.cpu.num_load_insts 9089529 # Number of load instructions
358system.cpu.num_store_insts 6365123 # Number of store instructions
359system.cpu.num_idle_cycles 3589204507.998131 # Number of idle cycles
360system.cpu.num_busy_cycles 251633036.001869 # Number of busy cycles
361system.cpu.not_idle_fraction 0.065515 # Percentage of non-idle cycles
362system.cpu.idle_fraction 0.934485 # Percentage of idle cycles
363system.cpu.Branches 8412940 # Number of branches fetched
364system.cpu.op_class::No_OpClass 3197536 5.70% 5.70% # Class of executed instruction
365system.cpu.op_class::IntAlu 36173540 64.46% 70.16% # Class of executed instruction
366system.cpu.op_class::IntMult 60992 0.11% 70.27% # Class of executed instruction
367system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction
368system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction
369system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction
370system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction
371system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction
372system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction
373system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction
374system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction
375system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction
376system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction
377system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction
378system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction
379system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction
380system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction
381system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction
382system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction
383system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction
384system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction
385system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction
386system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction
387system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction
388system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction
389system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction
390system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction
391system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction
392system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction
393system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction
394system.cpu.op_class::MemRead 9316603 16.60% 86.95% # Class of executed instruction
395system.cpu.op_class::MemWrite 6371197 11.35% 98.30% # Class of executed instruction
396system.cpu.op_class::IprAccess 953030 1.70% 100.00% # Class of executed instruction
397system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
398system.cpu.op_class::total 56114619 # Class of executed instruction
399system.cpu.kern.inst.arm 0 # number of arm instructions executed
400system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
401system.cpu.kern.inst.hwrei 211965 # number of hwrei instructions executed
402system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl
403system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
404system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl
405system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl
406system.cpu.kern.ipl_count::total 183175 # number of times we switched to this ipl
407system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl
408system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
409system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
410system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl
411system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl
412system.cpu.kern.ipl_ticks::0 1858230927500 96.76% 96.76% # number of cycles we spent at this ipl
413system.cpu.kern.ipl_ticks::21 91348000 0.00% 96.77% # number of cycles we spent at this ipl
414system.cpu.kern.ipl_ticks::22 737130000 0.04% 96.80% # number of cycles we spent at this ipl
415system.cpu.kern.ipl_ticks::31 61358632500 3.20% 100.00% # number of cycles we spent at this ipl
416system.cpu.kern.ipl_ticks::total 1920418038000 # number of cycles we spent at this ipl
417system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl
418system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
419system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
420system.cpu.kern.ipl_used::31 0.692243 # fraction of swpipl calls that actually changed the ipl
421system.cpu.kern.ipl_used::total 0.814079 # fraction of swpipl calls that actually changed the ipl
422system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
423system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
424system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
425system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
426system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
427system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
428system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
429system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed

--- 19 unchanged lines hidden (view full) ---

449system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
450system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
451system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
452system.cpu.kern.syscall::total 326 # number of syscalls executed
453system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
454system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
455system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
456system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
457system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed
458system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
459system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
460system.cpu.kern.callpal::swpipl 175954 91.22% 93.41% # number of callpals executed
461system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed
462system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
463system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
464system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
465system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
466system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed
467system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
468system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
469system.cpu.kern.callpal::total 192900 # number of callpals executed
470system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches
471system.cpu.kern.mode_switch::user 1743 # number of protection mode switches
472system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
473system.cpu.kern.mode_good::kernel 1913
474system.cpu.kern.mode_good::user 1743
475system.cpu.kern.mode_good::idle 170
476system.cpu.kern.mode_switch_good::kernel 0.324182 # fraction of useful protection mode switches
477system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
478system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches
479system.cpu.kern.mode_switch_good::total 0.392732 # fraction of useful protection mode switches
480system.cpu.kern.mode_ticks::kernel 46109911500 2.40% 2.40% # number of ticks spent at the given mode
481system.cpu.kern.mode_ticks::user 5189208000 0.27% 2.67% # number of ticks spent at the given mode
482system.cpu.kern.mode_ticks::idle 1869118916500 97.33% 100.00% # number of ticks spent at the given mode
483system.cpu.kern.swap_context 4177 # number of times the context was actually changed
484system.cpu.dcache.tags.replacements 1389979 # number of replacements
485system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use
486system.cpu.dcache.tags.total_refs 14030604 # Total number of references to valid blocks.
487system.cpu.dcache.tags.sampled_refs 1390491 # Sample count of references to valid blocks.
488system.cpu.dcache.tags.avg_refs 10.090395 # Average number of references to valid blocks.
489system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit.
490system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor
491system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
492system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
493system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
494system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
495system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
496system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
497system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
498system.cpu.dcache.tags.tag_accesses 63074876 # Number of tag accesses
499system.cpu.dcache.tags.data_accesses 63074876 # Number of data accesses
500system.cpu.dcache.ReadReq_hits::cpu.data 7802731 # number of ReadReq hits
501system.cpu.dcache.ReadReq_hits::total 7802731 # number of ReadReq hits
502system.cpu.dcache.WriteReq_hits::cpu.data 5845607 # number of WriteReq hits
503system.cpu.dcache.WriteReq_hits::total 5845607 # number of WriteReq hits
504system.cpu.dcache.LoadLockedReq_hits::cpu.data 183026 # number of LoadLockedReq hits
505system.cpu.dcache.LoadLockedReq_hits::total 183026 # number of LoadLockedReq hits
506system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits
507system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits
508system.cpu.dcache.demand_hits::cpu.data 13648338 # number of demand (read+write) hits
509system.cpu.dcache.demand_hits::total 13648338 # number of demand (read+write) hits
510system.cpu.dcache.overall_hits::cpu.data 13648338 # number of overall hits
511system.cpu.dcache.overall_hits::total 13648338 # number of overall hits
512system.cpu.dcache.ReadReq_misses::cpu.data 1069103 # number of ReadReq misses
513system.cpu.dcache.ReadReq_misses::total 1069103 # number of ReadReq misses
514system.cpu.dcache.WriteReq_misses::cpu.data 304189 # number of WriteReq misses
515system.cpu.dcache.WriteReq_misses::total 304189 # number of WriteReq misses
516system.cpu.dcache.LoadLockedReq_misses::cpu.data 17217 # number of LoadLockedReq misses
517system.cpu.dcache.LoadLockedReq_misses::total 17217 # number of LoadLockedReq misses
518system.cpu.dcache.demand_misses::cpu.data 1373292 # number of demand (read+write) misses
519system.cpu.dcache.demand_misses::total 1373292 # number of demand (read+write) misses
520system.cpu.dcache.overall_misses::cpu.data 1373292 # number of overall misses
521system.cpu.dcache.overall_misses::total 1373292 # number of overall misses
522system.cpu.dcache.ReadReq_miss_latency::cpu.data 29000817500 # number of ReadReq miss cycles
523system.cpu.dcache.ReadReq_miss_latency::total 29000817500 # number of ReadReq miss cycles
524system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906930630 # number of WriteReq miss cycles
525system.cpu.dcache.WriteReq_miss_latency::total 10906930630 # number of WriteReq miss cycles
526system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228178000 # number of LoadLockedReq miss cycles
527system.cpu.dcache.LoadLockedReq_miss_latency::total 228178000 # number of LoadLockedReq miss cycles
528system.cpu.dcache.demand_miss_latency::cpu.data 39907748130 # number of demand (read+write) miss cycles
529system.cpu.dcache.demand_miss_latency::total 39907748130 # number of demand (read+write) miss cycles
530system.cpu.dcache.overall_miss_latency::cpu.data 39907748130 # number of overall miss cycles
531system.cpu.dcache.overall_miss_latency::total 39907748130 # number of overall miss cycles
532system.cpu.dcache.ReadReq_accesses::cpu.data 8871834 # number of ReadReq accesses(hits+misses)
533system.cpu.dcache.ReadReq_accesses::total 8871834 # number of ReadReq accesses(hits+misses)
534system.cpu.dcache.WriteReq_accesses::cpu.data 6149796 # number of WriteReq accesses(hits+misses)
535system.cpu.dcache.WriteReq_accesses::total 6149796 # number of WriteReq accesses(hits+misses)
536system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses)
537system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses)
538system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses)
539system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses)
540system.cpu.dcache.demand_accesses::cpu.data 15021630 # number of demand (read+write) accesses
541system.cpu.dcache.demand_accesses::total 15021630 # number of demand (read+write) accesses
542system.cpu.dcache.overall_accesses::cpu.data 15021630 # number of overall (read+write) accesses
543system.cpu.dcache.overall_accesses::total 15021630 # number of overall (read+write) accesses
544system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120505 # miss rate for ReadReq accesses
545system.cpu.dcache.ReadReq_miss_rate::total 0.120505 # miss rate for ReadReq accesses
546system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049463 # miss rate for WriteReq accesses
547system.cpu.dcache.WriteReq_miss_rate::total 0.049463 # miss rate for WriteReq accesses
548system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085981 # miss rate for LoadLockedReq accesses
549system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085981 # miss rate for LoadLockedReq accesses
550system.cpu.dcache.demand_miss_rate::cpu.data 0.091421 # miss rate for demand accesses
551system.cpu.dcache.demand_miss_rate::total 0.091421 # miss rate for demand accesses
552system.cpu.dcache.overall_miss_rate::cpu.data 0.091421 # miss rate for overall accesses
553system.cpu.dcache.overall_miss_rate::total 0.091421 # miss rate for overall accesses
554system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27126.308223 # average ReadReq miss latency
555system.cpu.dcache.ReadReq_avg_miss_latency::total 27126.308223 # average ReadReq miss latency
556system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.769374 # average WriteReq miss latency
557system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.769374 # average WriteReq miss latency
558system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13253.063832 # average LoadLockedReq miss latency
559system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13253.063832 # average LoadLockedReq miss latency
560system.cpu.dcache.demand_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency
561system.cpu.dcache.demand_avg_miss_latency::total 29059.914519 # average overall miss latency
562system.cpu.dcache.overall_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency
563system.cpu.dcache.overall_avg_miss_latency::total 29059.914519 # average overall miss latency
564system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
565system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
566system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
567system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
568system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
569system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
570system.cpu.dcache.fast_writes 0 # number of fast writes performed
571system.cpu.dcache.cache_copies 0 # number of cache copies performed
572system.cpu.dcache.writebacks::writebacks 834368 # number of writebacks
573system.cpu.dcache.writebacks::total 834368 # number of writebacks
574system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069103 # number of ReadReq MSHR misses
575system.cpu.dcache.ReadReq_mshr_misses::total 1069103 # number of ReadReq MSHR misses
576system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304189 # number of WriteReq MSHR misses
577system.cpu.dcache.WriteReq_mshr_misses::total 304189 # number of WriteReq MSHR misses
578system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17217 # number of LoadLockedReq MSHR misses
579system.cpu.dcache.LoadLockedReq_mshr_misses::total 17217 # number of LoadLockedReq MSHR misses
580system.cpu.dcache.demand_mshr_misses::cpu.data 1373292 # number of demand (read+write) MSHR misses
581system.cpu.dcache.demand_mshr_misses::total 1373292 # number of demand (read+write) MSHR misses
582system.cpu.dcache.overall_mshr_misses::cpu.data 1373292 # number of overall MSHR misses
583system.cpu.dcache.overall_mshr_misses::total 1373292 # number of overall MSHR misses
584system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26736955500 # number of ReadReq MSHR miss cycles
585system.cpu.dcache.ReadReq_mshr_miss_latency::total 26736955500 # number of ReadReq MSHR miss cycles
586system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245884370 # number of WriteReq MSHR miss cycles
587system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245884370 # number of WriteReq MSHR miss cycles
588system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles
589system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles
590system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36982839870 # number of demand (read+write) MSHR miss cycles
591system.cpu.dcache.demand_mshr_miss_latency::total 36982839870 # number of demand (read+write) MSHR miss cycles
592system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36982839870 # number of overall MSHR miss cycles
593system.cpu.dcache.overall_mshr_miss_latency::total 36982839870 # number of overall MSHR miss cycles
594system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424272500 # number of ReadReq MSHR uncacheable cycles
595system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424272500 # number of ReadReq MSHR uncacheable cycles
596system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009399000 # number of WriteReq MSHR uncacheable cycles
597system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009399000 # number of WriteReq MSHR uncacheable cycles
598system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433671500 # number of overall MSHR uncacheable cycles
599system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433671500 # number of overall MSHR uncacheable cycles
600system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120505 # mshr miss rate for ReadReq accesses
601system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120505 # mshr miss rate for ReadReq accesses
602system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049463 # mshr miss rate for WriteReq accesses
603system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049463 # mshr miss rate for WriteReq accesses
604system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085981 # mshr miss rate for LoadLockedReq accesses
605system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085981 # mshr miss rate for LoadLockedReq accesses
606system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091421 # mshr miss rate for demand accesses
607system.cpu.dcache.demand_mshr_miss_rate::total 0.091421 # mshr miss rate for demand accesses
608system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091421 # mshr miss rate for overall accesses
609system.cpu.dcache.overall_mshr_miss_rate::total 0.091421 # mshr miss rate for overall accesses
610system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25008.774178 # average ReadReq mshr miss latency
611system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25008.774178 # average ReadReq mshr miss latency
612system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33682.626163 # average WriteReq mshr miss latency
613system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33682.626163 # average WriteReq mshr miss latency
614system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11252.366847 # average LoadLockedReq mshr miss latency
615system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11252.366847 # average LoadLockedReq mshr miss latency
616system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency
617system.cpu.dcache.demand_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency
618system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency
619system.cpu.dcache.overall_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency
620system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
621system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
622system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
623system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
624system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
625system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
626system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
627system.cpu.icache.tags.replacements 927664 # number of replacements
628system.cpu.icache.tags.tagsinuse 508.305908 # Cycle average of tags in use
629system.cpu.icache.tags.total_refs 55186285 # Total number of references to valid blocks.
630system.cpu.icache.tags.sampled_refs 928175 # Sample count of references to valid blocks.
631system.cpu.icache.tags.avg_refs 59.456767 # Average number of references to valid blocks.
632system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit.
633system.cpu.icache.tags.occ_blocks::cpu.inst 508.305908 # Average occupied blocks per requestor
634system.cpu.icache.tags.occ_percent::cpu.inst 0.992785 # Average percentage of cache occupancy
635system.cpu.icache.tags.occ_percent::total 0.992785 # Average percentage of cache occupancy
636system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
637system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
638system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
639system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id
640system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
641system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
642system.cpu.icache.tags.tag_accesses 57042955 # Number of tag accesses
643system.cpu.icache.tags.data_accesses 57042955 # Number of data accesses
644system.cpu.icache.ReadReq_hits::cpu.inst 55186285 # number of ReadReq hits
645system.cpu.icache.ReadReq_hits::total 55186285 # number of ReadReq hits
646system.cpu.icache.demand_hits::cpu.inst 55186285 # number of demand (read+write) hits
647system.cpu.icache.demand_hits::total 55186285 # number of demand (read+write) hits
648system.cpu.icache.overall_hits::cpu.inst 55186285 # number of overall hits
649system.cpu.icache.overall_hits::total 55186285 # number of overall hits
650system.cpu.icache.ReadReq_misses::cpu.inst 928335 # number of ReadReq misses
651system.cpu.icache.ReadReq_misses::total 928335 # number of ReadReq misses
652system.cpu.icache.demand_misses::cpu.inst 928335 # number of demand (read+write) misses
653system.cpu.icache.demand_misses::total 928335 # number of demand (read+write) misses
654system.cpu.icache.overall_misses::cpu.inst 928335 # number of overall misses
655system.cpu.icache.overall_misses::total 928335 # number of overall misses
656system.cpu.icache.ReadReq_miss_latency::cpu.inst 12909899750 # number of ReadReq miss cycles
657system.cpu.icache.ReadReq_miss_latency::total 12909899750 # number of ReadReq miss cycles
658system.cpu.icache.demand_miss_latency::cpu.inst 12909899750 # number of demand (read+write) miss cycles
659system.cpu.icache.demand_miss_latency::total 12909899750 # number of demand (read+write) miss cycles
660system.cpu.icache.overall_miss_latency::cpu.inst 12909899750 # number of overall miss cycles
661system.cpu.icache.overall_miss_latency::total 12909899750 # number of overall miss cycles
662system.cpu.icache.ReadReq_accesses::cpu.inst 56114620 # number of ReadReq accesses(hits+misses)
663system.cpu.icache.ReadReq_accesses::total 56114620 # number of ReadReq accesses(hits+misses)
664system.cpu.icache.demand_accesses::cpu.inst 56114620 # number of demand (read+write) accesses
665system.cpu.icache.demand_accesses::total 56114620 # number of demand (read+write) accesses
666system.cpu.icache.overall_accesses::cpu.inst 56114620 # number of overall (read+write) accesses
667system.cpu.icache.overall_accesses::total 56114620 # number of overall (read+write) accesses
668system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016544 # miss rate for ReadReq accesses
669system.cpu.icache.ReadReq_miss_rate::total 0.016544 # miss rate for ReadReq accesses
670system.cpu.icache.demand_miss_rate::cpu.inst 0.016544 # miss rate for demand accesses
671system.cpu.icache.demand_miss_rate::total 0.016544 # miss rate for demand accesses
672system.cpu.icache.overall_miss_rate::cpu.inst 0.016544 # miss rate for overall accesses
673system.cpu.icache.overall_miss_rate::total 0.016544 # miss rate for overall accesses
674system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13906.509773 # average ReadReq miss latency
675system.cpu.icache.ReadReq_avg_miss_latency::total 13906.509773 # average ReadReq miss latency
676system.cpu.icache.demand_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency
677system.cpu.icache.demand_avg_miss_latency::total 13906.509773 # average overall miss latency
678system.cpu.icache.overall_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency
679system.cpu.icache.overall_avg_miss_latency::total 13906.509773 # average overall miss latency
680system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
681system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
682system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
683system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
684system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
685system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
686system.cpu.icache.fast_writes 0 # number of fast writes performed
687system.cpu.icache.cache_copies 0 # number of cache copies performed
688system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928335 # number of ReadReq MSHR misses
689system.cpu.icache.ReadReq_mshr_misses::total 928335 # number of ReadReq MSHR misses
690system.cpu.icache.demand_mshr_misses::cpu.inst 928335 # number of demand (read+write) MSHR misses
691system.cpu.icache.demand_mshr_misses::total 928335 # number of demand (read+write) MSHR misses
692system.cpu.icache.overall_mshr_misses::cpu.inst 928335 # number of overall MSHR misses
693system.cpu.icache.overall_mshr_misses::total 928335 # number of overall MSHR misses
694system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048066250 # number of ReadReq MSHR miss cycles
695system.cpu.icache.ReadReq_mshr_miss_latency::total 11048066250 # number of ReadReq MSHR miss cycles
696system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048066250 # number of demand (read+write) MSHR miss cycles
697system.cpu.icache.demand_mshr_miss_latency::total 11048066250 # number of demand (read+write) MSHR miss cycles
698system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11048066250 # number of overall MSHR miss cycles
699system.cpu.icache.overall_mshr_miss_latency::total 11048066250 # number of overall MSHR miss cycles
700system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for ReadReq accesses
701system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016544 # mshr miss rate for ReadReq accesses
702system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for demand accesses
703system.cpu.icache.demand_mshr_miss_rate::total 0.016544 # mshr miss rate for demand accesses
704system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for overall accesses
705system.cpu.icache.overall_mshr_miss_rate::total 0.016544 # mshr miss rate for overall accesses
706system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11900.947664 # average ReadReq mshr miss latency
707system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11900.947664 # average ReadReq mshr miss latency
708system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11900.947664 # average overall mshr miss latency
709system.cpu.icache.demand_avg_mshr_miss_latency::total 11900.947664 # average overall mshr miss latency
710system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11900.947664 # average overall mshr miss latency
711system.cpu.icache.overall_avg_mshr_miss_latency::total 11900.947664 # average overall mshr miss latency
712system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
713system.cpu.l2cache.tags.replacements 336225 # number of replacements
714system.cpu.l2cache.tags.tagsinuse 65295.018505 # Cycle average of tags in use
715system.cpu.l2cache.tags.total_refs 2445535 # Total number of references to valid blocks.
716system.cpu.l2cache.tags.sampled_refs 401387 # Sample count of references to valid blocks.
717system.cpu.l2cache.tags.avg_refs 6.092711 # Average number of references to valid blocks.
718system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit.
719system.cpu.l2cache.tags.occ_blocks::writebacks 55550.770505 # Average occupied blocks per requestor
720system.cpu.l2cache.tags.occ_blocks::cpu.inst 4768.438466 # Average occupied blocks per requestor
721system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.809535 # Average occupied blocks per requestor
722system.cpu.l2cache.tags.occ_percent::writebacks 0.847637 # Average percentage of cache occupancy
723system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072761 # Average percentage of cache occupancy
724system.cpu.l2cache.tags.occ_percent::cpu.data 0.075925 # Average percentage of cache occupancy
725system.cpu.l2cache.tags.occ_percent::total 0.996323 # Average percentage of cache occupancy
726system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
727system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
728system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id
729system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4873 # Occupied blocks per task id
730system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3256 # Occupied blocks per task id
731system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55781 # Occupied blocks per task id
732system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
733system.cpu.l2cache.tags.tag_accesses 25931322 # Number of tag accesses
734system.cpu.l2cache.tags.data_accesses 25931322 # Number of data accesses
735system.cpu.l2cache.ReadReq_hits::cpu.inst 915025 # number of ReadReq hits
736system.cpu.l2cache.ReadReq_hits::cpu.data 814362 # number of ReadReq hits
737system.cpu.l2cache.ReadReq_hits::total 1729387 # number of ReadReq hits
738system.cpu.l2cache.Writeback_hits::writebacks 834368 # number of Writeback hits
739system.cpu.l2cache.Writeback_hits::total 834368 # number of Writeback hits
740system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
741system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
742system.cpu.l2cache.ReadExReq_hits::cpu.data 187334 # number of ReadExReq hits
743system.cpu.l2cache.ReadExReq_hits::total 187334 # number of ReadExReq hits
744system.cpu.l2cache.demand_hits::cpu.inst 915025 # number of demand (read+write) hits
745system.cpu.l2cache.demand_hits::cpu.data 1001696 # number of demand (read+write) hits
746system.cpu.l2cache.demand_hits::total 1916721 # number of demand (read+write) hits
747system.cpu.l2cache.overall_hits::cpu.inst 915025 # number of overall hits
748system.cpu.l2cache.overall_hits::cpu.data 1001696 # number of overall hits
749system.cpu.l2cache.overall_hits::total 1916721 # number of overall hits
750system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses
751system.cpu.l2cache.ReadReq_misses::cpu.data 271958 # number of ReadReq misses
752system.cpu.l2cache.ReadReq_misses::total 285248 # number of ReadReq misses
753system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
754system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
755system.cpu.l2cache.ReadExReq_misses::cpu.data 116838 # number of ReadExReq misses
756system.cpu.l2cache.ReadExReq_misses::total 116838 # number of ReadExReq misses
757system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses
758system.cpu.l2cache.demand_misses::cpu.data 388796 # number of demand (read+write) misses
759system.cpu.l2cache.demand_misses::total 402086 # number of demand (read+write) misses
760system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses
761system.cpu.l2cache.overall_misses::cpu.data 388796 # number of overall misses
762system.cpu.l2cache.overall_misses::total 402086 # number of overall misses
763system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 969461250 # number of ReadReq miss cycles
764system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17700747500 # number of ReadReq miss cycles
765system.cpu.l2cache.ReadReq_miss_latency::total 18670208750 # number of ReadReq miss cycles
766system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles
767system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles
768system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8067922881 # number of ReadExReq miss cycles
769system.cpu.l2cache.ReadExReq_miss_latency::total 8067922881 # number of ReadExReq miss cycles
770system.cpu.l2cache.demand_miss_latency::cpu.inst 969461250 # number of demand (read+write) miss cycles
771system.cpu.l2cache.demand_miss_latency::cpu.data 25768670381 # number of demand (read+write) miss cycles
772system.cpu.l2cache.demand_miss_latency::total 26738131631 # number of demand (read+write) miss cycles
773system.cpu.l2cache.overall_miss_latency::cpu.inst 969461250 # number of overall miss cycles
774system.cpu.l2cache.overall_miss_latency::cpu.data 25768670381 # number of overall miss cycles
775system.cpu.l2cache.overall_miss_latency::total 26738131631 # number of overall miss cycles
776system.cpu.l2cache.ReadReq_accesses::cpu.inst 928315 # number of ReadReq accesses(hits+misses)
777system.cpu.l2cache.ReadReq_accesses::cpu.data 1086320 # number of ReadReq accesses(hits+misses)
778system.cpu.l2cache.ReadReq_accesses::total 2014635 # number of ReadReq accesses(hits+misses)
779system.cpu.l2cache.Writeback_accesses::writebacks 834368 # number of Writeback accesses(hits+misses)
780system.cpu.l2cache.Writeback_accesses::total 834368 # number of Writeback accesses(hits+misses)
781system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
782system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
783system.cpu.l2cache.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses)
784system.cpu.l2cache.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
785system.cpu.l2cache.demand_accesses::cpu.inst 928315 # number of demand (read+write) accesses
786system.cpu.l2cache.demand_accesses::cpu.data 1390492 # number of demand (read+write) accesses
787system.cpu.l2cache.demand_accesses::total 2318807 # number of demand (read+write) accesses
788system.cpu.l2cache.overall_accesses::cpu.inst 928315 # number of overall (read+write) accesses
789system.cpu.l2cache.overall_accesses::cpu.data 1390492 # number of overall (read+write) accesses
790system.cpu.l2cache.overall_accesses::total 2318807 # number of overall (read+write) accesses
791system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014316 # miss rate for ReadReq accesses
792system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250348 # miss rate for ReadReq accesses
793system.cpu.l2cache.ReadReq_miss_rate::total 0.141588 # miss rate for ReadReq accesses
794system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses
795system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses
796system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384118 # miss rate for ReadExReq accesses
797system.cpu.l2cache.ReadExReq_miss_rate::total 0.384118 # miss rate for ReadExReq accesses
798system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014316 # miss rate for demand accesses
799system.cpu.l2cache.demand_miss_rate::cpu.data 0.279610 # miss rate for demand accesses
800system.cpu.l2cache.demand_miss_rate::total 0.173402 # miss rate for demand accesses
801system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014316 # miss rate for overall accesses
802system.cpu.l2cache.overall_miss_rate::cpu.data 0.279610 # miss rate for overall accesses
803system.cpu.l2cache.overall_miss_rate::total 0.173402 # miss rate for overall accesses
804system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72946.670429 # average ReadReq miss latency
805system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65086.327668 # average ReadReq miss latency
806system.cpu.l2cache.ReadReq_avg_miss_latency::total 65452.549185 # average ReadReq miss latency
807system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency
808system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency
809system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69052.216582 # average ReadExReq miss latency
810system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69052.216582 # average ReadExReq miss latency
811system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72946.670429 # average overall miss latency
812system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66278.126269 # average overall miss latency
813system.cpu.l2cache.demand_avg_miss_latency::total 66498.539196 # average overall miss latency
814system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72946.670429 # average overall miss latency
815system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66278.126269 # average overall miss latency
816system.cpu.l2cache.overall_avg_miss_latency::total 66498.539196 # average overall miss latency
817system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
818system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
819system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
820system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
821system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
822system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
823system.cpu.l2cache.fast_writes 0 # number of fast writes performed
824system.cpu.l2cache.cache_copies 0 # number of cache copies performed
825system.cpu.l2cache.writebacks::writebacks 74170 # number of writebacks
826system.cpu.l2cache.writebacks::total 74170 # number of writebacks
827system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses
828system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271958 # number of ReadReq MSHR misses
829system.cpu.l2cache.ReadReq_mshr_misses::total 285248 # number of ReadReq MSHR misses
830system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
831system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
832system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116838 # number of ReadExReq MSHR misses
833system.cpu.l2cache.ReadExReq_mshr_misses::total 116838 # number of ReadExReq MSHR misses
834system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses
835system.cpu.l2cache.demand_mshr_misses::cpu.data 388796 # number of demand (read+write) MSHR misses
836system.cpu.l2cache.demand_mshr_misses::total 402086 # number of demand (read+write) MSHR misses
837system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses
838system.cpu.l2cache.overall_mshr_misses::cpu.data 388796 # number of overall MSHR misses
839system.cpu.l2cache.overall_mshr_misses::total 402086 # number of overall MSHR misses
840system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 802917750 # number of ReadReq MSHR miss cycles
841system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14300848500 # number of ReadReq MSHR miss cycles
842system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15103766250 # number of ReadReq MSHR miss cycles
843system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles
844system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles
845system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607051619 # number of ReadExReq MSHR miss cycles
846system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607051619 # number of ReadExReq MSHR miss cycles
847system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802917750 # number of demand (read+write) MSHR miss cycles
848system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20907900119 # number of demand (read+write) MSHR miss cycles
849system.cpu.l2cache.demand_mshr_miss_latency::total 21710817869 # number of demand (read+write) MSHR miss cycles
850system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802917750 # number of overall MSHR miss cycles
851system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20907900119 # number of overall MSHR miss cycles
852system.cpu.l2cache.overall_mshr_miss_latency::total 21710817869 # number of overall MSHR miss cycles
853system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334182500 # number of ReadReq MSHR uncacheable cycles
854system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334182500 # number of ReadReq MSHR uncacheable cycles
855system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893599000 # number of WriteReq MSHR uncacheable cycles
856system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893599000 # number of WriteReq MSHR uncacheable cycles
857system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227781500 # number of overall MSHR uncacheable cycles
858system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227781500 # number of overall MSHR uncacheable cycles
859system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses
860system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250348 # mshr miss rate for ReadReq accesses
861system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141588 # mshr miss rate for ReadReq accesses
862system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
863system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
864system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384118 # mshr miss rate for ReadExReq accesses
865system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384118 # mshr miss rate for ReadExReq accesses
866system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses
867system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for demand accesses
868system.cpu.l2cache.demand_mshr_miss_rate::total 0.173402 # mshr miss rate for demand accesses
869system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses
870system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for overall accesses
871system.cpu.l2cache.overall_mshr_miss_rate::total 0.173402 # mshr miss rate for overall accesses
872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60415.180587 # average ReadReq mshr miss latency
873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52584.768604 # average ReadReq mshr miss latency
874system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52949.595615 # average ReadReq mshr miss latency
875system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency
876system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency
877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56548.825031 # average ReadExReq mshr miss latency
878system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56548.825031 # average ReadExReq mshr miss latency
879system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency
880system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency
881system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency
882system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency
883system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency
884system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency
885system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
886system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
887system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
888system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
889system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
890system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
891system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
892system.cpu.toL2Bus.trans_dist::ReadReq 2021758 # Transaction distribution
893system.cpu.toL2Bus.trans_dist::ReadResp 2021741 # Transaction distribution
894system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
895system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
896system.cpu.toL2Bus.trans_dist::Writeback 834368 # Transaction distribution
897system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
898system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
899system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
900system.cpu.toL2Bus.trans_dist::ReadExReq 304172 # Transaction distribution
901system.cpu.toL2Bus.trans_dist::ReadExResp 304172 # Transaction distribution
902system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856650 # Packet count per connected master and slave (bytes)
903system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648702 # Packet count per connected master and slave (bytes)
904system.cpu.toL2Bus.pkt_count::total 5505352 # Packet count per connected master and slave (bytes)
905system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59412160 # Cumulative packet size per connected master and slave (bytes)
906system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142445588 # Cumulative packet size per connected master and slave (bytes)
907system.cpu.toL2Bus.pkt_size::total 201857748 # Cumulative packet size per connected master and slave (bytes)
908system.cpu.toL2Bus.snoops 41901 # Total snoops (count)
909system.cpu.toL2Bus.snoop_fanout::samples 3194937 # Request fanout histogram
910system.cpu.toL2Bus.snoop_fanout::mean 1.013060 # Request fanout histogram
911system.cpu.toL2Bus.snoop_fanout::stdev 0.113530 # Request fanout histogram
912system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
913system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
914system.cpu.toL2Bus.snoop_fanout::1 3153212 98.69% 98.69% # Request fanout histogram
915system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram
916system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
917system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
918system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
919system.cpu.toL2Bus.snoop_fanout::total 3194937 # Request fanout histogram
920system.cpu.toL2Bus.reqLayer0.occupancy 2424089000 # Layer occupancy (ticks)
921system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
922system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
923system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
924system.cpu.toL2Bus.respLayer0.occupancy 1395084250 # Layer occupancy (ticks)
925system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
926system.cpu.toL2Bus.respLayer1.occupancy 2186669630 # Layer occupancy (ticks)
927system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
928system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
929system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
930system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
931system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
932system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
933system.disk0.dma_write_txs 395 # Number of DMA write transactions.
934system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).

--- 56 unchanged lines hidden (view full) ---

991system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
992system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
993system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
994system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
995system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
996system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
997system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
998system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
999system.iobus.reqLayer29.occupancy 406198788 # Layer occupancy (ticks)
1000system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1001system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1002system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1003system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
1004system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1005system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks)
1006system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1007system.iocache.tags.replacements 41685 # number of replacements
1008system.iocache.tags.tagsinuse 1.352284 # Cycle average of tags in use
1009system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1010system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
1011system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1012system.iocache.tags.warmup_cycle 1753525494000 # Cycle when the warmup percentage was hit.
1013system.iocache.tags.occ_blocks::tsunami.ide 1.352284 # Average occupied blocks per requestor
1014system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy
1015system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy
1016system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1017system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1018system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1019system.iocache.tags.tag_accesses 375525 # Number of tag accesses
1020system.iocache.tags.data_accesses 375525 # Number of data accesses
1021system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
1022system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
1023system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
1024system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
1025system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
1026system.iocache.demand_misses::total 173 # number of demand (read+write) misses
1027system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
1028system.iocache.overall_misses::total 173 # number of overall misses
1029system.iocache.ReadReq_miss_latency::tsunami.ide 23338383 # number of ReadReq miss cycles
1030system.iocache.ReadReq_miss_latency::total 23338383 # number of ReadReq miss cycles
1031system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635239905 # number of WriteInvalidateReq miss cycles
1032system.iocache.WriteInvalidateReq_miss_latency::total 13635239905 # number of WriteInvalidateReq miss cycles
1033system.iocache.demand_miss_latency::tsunami.ide 23338383 # number of demand (read+write) miss cycles
1034system.iocache.demand_miss_latency::total 23338383 # number of demand (read+write) miss cycles
1035system.iocache.overall_miss_latency::tsunami.ide 23338383 # number of overall miss cycles
1036system.iocache.overall_miss_latency::total 23338383 # number of overall miss cycles
1037system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
1038system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
1039system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
1040system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
1041system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
1042system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
1043system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
1044system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
1045system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1046system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1047system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
1048system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1049system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1050system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1051system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1052system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1053system.iocache.ReadReq_avg_miss_latency::tsunami.ide 134903.947977 # average ReadReq miss latency
1054system.iocache.ReadReq_avg_miss_latency::total 134903.947977 # average ReadReq miss latency
1055system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328148.823282 # average WriteInvalidateReq miss latency
1056system.iocache.WriteInvalidateReq_avg_miss_latency::total 328148.823282 # average WriteInvalidateReq miss latency
1057system.iocache.demand_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency
1058system.iocache.demand_avg_miss_latency::total 134903.947977 # average overall miss latency
1059system.iocache.overall_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency
1060system.iocache.overall_avg_miss_latency::total 134903.947977 # average overall miss latency
1061system.iocache.blocked_cycles::no_mshrs 206255 # number of cycles access was blocked
1062system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1063system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked
1064system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1065system.iocache.avg_blocked_cycles::no_mshrs 8.754085 # average number of cycles each access was blocked
1066system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1067system.iocache.fast_writes 0 # number of fast writes performed
1068system.iocache.cache_copies 0 # number of cache copies performed
1069system.iocache.writebacks::writebacks 41512 # number of writebacks
1070system.iocache.writebacks::total 41512 # number of writebacks
1071system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
1072system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
1073system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
1074system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
1075system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
1076system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
1077system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
1078system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
1079system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14341383 # number of ReadReq MSHR miss cycles
1080system.iocache.ReadReq_mshr_miss_latency::total 14341383 # number of ReadReq MSHR miss cycles
1081system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474535905 # number of WriteInvalidateReq MSHR miss cycles
1082system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474535905 # number of WriteInvalidateReq MSHR miss cycles
1083system.iocache.demand_mshr_miss_latency::tsunami.ide 14341383 # number of demand (read+write) MSHR miss cycles
1084system.iocache.demand_mshr_miss_latency::total 14341383 # number of demand (read+write) MSHR miss cycles
1085system.iocache.overall_mshr_miss_latency::tsunami.ide 14341383 # number of overall MSHR miss cycles
1086system.iocache.overall_mshr_miss_latency::total 14341383 # number of overall MSHR miss cycles
1087system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1088system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1089system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1090system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1091system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1092system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1093system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1094system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1095system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average ReadReq mshr miss latency
1096system.iocache.ReadReq_avg_mshr_miss_latency::total 82898.167630 # average ReadReq mshr miss latency
1097system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276148.823282 # average WriteInvalidateReq mshr miss latency
1098system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276148.823282 # average WriteInvalidateReq mshr miss latency
1099system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency
1100system.iocache.demand_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency
1101system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency
1102system.iocache.overall_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency
1103system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1104system.membus.trans_dist::ReadReq 292351 # Transaction distribution
1105system.membus.trans_dist::ReadResp 292351 # Transaction distribution
1106system.membus.trans_dist::WriteReq 9650 # Transaction distribution
1107system.membus.trans_dist::WriteResp 9650 # Transaction distribution
1108system.membus.trans_dist::Writeback 115682 # Transaction distribution
1109system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
1110system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
1111system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
1112system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
1113system.membus.trans_dist::ReadExReq 116719 # Transaction distribution
1114system.membus.trans_dist::ReadExResp 116719 # Transaction distribution
1115system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
1116system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878095 # Packet count per connected master and slave (bytes)
1117system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911255 # Packet count per connected master and slave (bytes)
1118system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
1119system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
1120system.membus.pkt_count::total 1036059 # Packet count per connected master and slave (bytes)
1121system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
1122system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455424 # Cumulative packet size per connected master and slave (bytes)
1123system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499988 # Cumulative packet size per connected master and slave (bytes)
1124system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes)
1125system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
1126system.membus.pkt_size::total 35817044 # Cumulative packet size per connected master and slave (bytes)
1127system.membus.snoops 431 # Total snoops (count)
1128system.membus.snoop_fanout::samples 559506 # Request fanout histogram
1129system.membus.snoop_fanout::mean 1 # Request fanout histogram
1130system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1131system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1132system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1133system.membus.snoop_fanout::1 559506 100.00% 100.00% # Request fanout histogram
1134system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1135system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1136system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1137system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1138system.membus.snoop_fanout::total 559506 # Request fanout histogram
1139system.membus.reqLayer0.occupancy 30371500 # Layer occupancy (ticks)
1140system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1141system.membus.reqLayer1.occupancy 1824515500 # Layer occupancy (ticks)
1142system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1143system.membus.respLayer1.occupancy 3751827620 # Layer occupancy (ticks)
1144system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
1145system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks)
1146system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1147system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1148system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1149system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1150system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1151system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1152system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1153system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR

--- 26 unchanged lines hidden ---