1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.920416 # Number of seconds simulated
4sim_ticks 1920416181000 # Number of ticks simulated
5final_tick 1920416181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1752736 # Simulator instruction rate (inst/s)
8host_op_rate 1752735 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 59896862792 # Simulator tick rate (ticks/s)
10host_mem_usage 308520 # Number of bytes of host memory used
11host_seconds 32.06 # Real time elapsed on the host
12sim_insts 56196255 # Number of instructions simulated
13sim_ops 56196255 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
19system.physmem.bytes_read::total 28363328 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 7405888 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7405888 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory
26system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 443177 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 115717 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 115717 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 443004 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 12945227 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::tsunami.ide 1381134 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 14769365 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 443004 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 443004 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 3856397 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 3856397 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 3856397 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 443004 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 12945227 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::tsunami.ide 1381134 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 18625763 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 443177 # Number of read requests accepted
44system.physmem.writeReqs 115717 # Number of write requests accepted
45system.physmem.readBursts 443177 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 115717 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 28355584 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue
49system.physmem.bytesWritten 7404416 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 28363328 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 7405888 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 27851 # Per bank write bursts
56system.physmem.perBankRdBursts::1 28132 # Per bank write bursts
57system.physmem.perBankRdBursts::2 28319 # Per bank write bursts
58system.physmem.perBankRdBursts::3 28010 # Per bank write bursts
59system.physmem.perBankRdBursts::4 27531 # Per bank write bursts
60system.physmem.perBankRdBursts::5 27552 # Per bank write bursts
61system.physmem.perBankRdBursts::6 26732 # Per bank write bursts
62system.physmem.perBankRdBursts::7 26855 # Per bank write bursts
63system.physmem.perBankRdBursts::8 27890 # Per bank write bursts
64system.physmem.perBankRdBursts::9 27110 # Per bank write bursts
65system.physmem.perBankRdBursts::10 27744 # Per bank write bursts
66system.physmem.perBankRdBursts::11 27465 # Per bank write bursts
67system.physmem.perBankRdBursts::12 27482 # Per bank write bursts
68system.physmem.perBankRdBursts::13 28199 # Per bank write bursts
69system.physmem.perBankRdBursts::14 28116 # Per bank write bursts
70system.physmem.perBankRdBursts::15 28068 # Per bank write bursts
71system.physmem.perBankWrBursts::0 7630 # Per bank write bursts
72system.physmem.perBankWrBursts::1 7636 # Per bank write bursts
73system.physmem.perBankWrBursts::2 7854 # Per bank write bursts
74system.physmem.perBankWrBursts::3 7535 # Per bank write bursts
75system.physmem.perBankWrBursts::4 7127 # Per bank write bursts
76system.physmem.perBankWrBursts::5 6994 # Per bank write bursts
77system.physmem.perBankWrBursts::6 6317 # Per bank write bursts
78system.physmem.perBankWrBursts::7 6319 # Per bank write bursts
79system.physmem.perBankWrBursts::8 7309 # Per bank write bursts
80system.physmem.perBankWrBursts::9 6529 # Per bank write bursts
81system.physmem.perBankWrBursts::10 7110 # Per bank write bursts
82system.physmem.perBankWrBursts::11 6915 # Per bank write bursts
83system.physmem.perBankWrBursts::12 7060 # Per bank write bursts
84system.physmem.perBankWrBursts::13 7819 # Per bank write bursts
85system.physmem.perBankWrBursts::14 7860 # Per bank write bursts
86system.physmem.perBankWrBursts::15 7680 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
89system.physmem.totGap 1920404309000 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 443177 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 115717 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 402196 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 1714 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 1586 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 1056 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 1122 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 4268 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 3790 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 3793 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 3969 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 2575 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 2119 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 2033 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 1897 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 1793 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 1556 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 1524 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 1560 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 1710 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 1268 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see

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143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 1547 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 1870 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 2302 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 4388 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 4414 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 4425 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 4435 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 4520 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 4492 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 4550 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 6087 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 4874 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 6417 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 5284 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 5514 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 5555 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 5389 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 1180 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 1138 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 1092 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 1057 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 1105 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 1067 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 1057 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 1183 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 1517 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 1561 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 1644 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 1709 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 1772 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 1718 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 1911 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 1872 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 1806 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 1830 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 1705 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 1482 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 1269 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 917 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 667 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 286 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 25 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 46117 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 658.429646 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 435.074403 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 420.347464 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 7559 16.39% 16.39% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 6338 13.74% 30.13% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 2663 5.77% 35.91% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 1600 3.47% 39.38% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 1319 2.86% 42.24% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 861 1.87% 44.11% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 594 1.29% 45.39% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 461 1.00% 46.39% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 24722 53.61% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 46117 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 6598 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 67.149288 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::stdev 2598.278449 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::0-8191 6595 99.95% 99.95% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::total 6598 # Reads before turning the bus around for writes
222system.physmem.wrPerTurnAround::samples 6598 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::mean 17.534707 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::gmean 17.278859 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::stdev 3.820387 # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::16 4179 63.34% 63.34% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::17 322 4.88% 68.22% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::18 428 6.49% 74.70% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::19 1303 19.75% 94.45% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::20 22 0.33% 94.79% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::21 17 0.26% 95.04% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::22 11 0.17% 95.21% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::23 27 0.41% 95.62% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::24 43 0.65% 96.27% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::25 28 0.42% 96.70% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::26 21 0.32% 97.01% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::27 25 0.38% 97.39% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::28 19 0.29% 97.68% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::29 43 0.65% 98.33% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::30 4 0.06% 98.39% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::31 12 0.18% 98.58% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::32 10 0.15% 98.73% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::33 1 0.02% 98.74% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::34 5 0.08% 98.82% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::35 4 0.06% 98.88% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::37 5 0.08% 99.01% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::38 2 0.03% 99.05% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::39 9 0.14% 99.18% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::40 4 0.06% 99.24% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::41 4 0.06% 99.30% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::42 1 0.02% 99.32% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::43 2 0.03% 99.35% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::44 3 0.05% 99.39% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::45 1 0.02% 99.41% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::46 1 0.02% 99.42% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::47 6 0.09% 99.52% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::48 8 0.12% 99.64% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::49 5 0.08% 99.71% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::50 6 0.09% 99.80% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::52 3 0.05% 99.85% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::53 1 0.02% 99.86% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::54 4 0.06% 99.92% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::55 2 0.03% 99.95% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::56 1 0.02% 99.97% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::57 1 0.02% 99.98% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::58 1 0.02% 100.00% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::total 6598 # Writes before turning the bus around for reads
269system.physmem.totQLat 7790286250 # Total ticks spent queuing
270system.physmem.totMemAccLat 16274878750 # Total ticks spent from burst creation until serviced by the DRAM
271system.physmem.totBusLat 2215280000 # Total ticks spent in databus transfers
272system.physmem.totBankLat 6269312500 # Total ticks spent accessing banks
273system.physmem.avgQLat 17583.07 # Average queueing delay per DRAM burst
274system.physmem.avgBankLat 14150.16 # Average bank access latency per DRAM burst
275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
276system.physmem.avgMemAccLat 36733.23 # Average memory access latency per DRAM burst
277system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s
278system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s
279system.physmem.avgRdBWSys 14.77 # Average system read bandwidth in MiByte/s
280system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s
281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
282system.physmem.busUtil 0.15 # Data bus utilization in percentage
283system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
284system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
285system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
286system.physmem.avgWrQLen 24.59 # Average write queue length when enqueuing
287system.physmem.readRowHits 398457 # Number of row buffer hits during reads
288system.physmem.writeRowHits 94179 # Number of row buffer hits during writes
289system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads
290system.physmem.writeRowHitRate 81.39 # Row buffer hit rate for writes
291system.physmem.avgGap 3436079.67 # Average gap between requests
292system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined
293system.physmem.prechargeAllPercent 0.57 # Percentage of time for which DRAM has all the banks in precharge state
294system.membus.throughput 18667397 # Throughput (bytes/s)
295system.membus.trans_dist::ReadReq 292363 # Transaction distribution
296system.membus.trans_dist::ReadResp 292363 # Transaction distribution
297system.membus.trans_dist::WriteReq 9650 # Transaction distribution
298system.membus.trans_dist::WriteResp 9650 # Transaction distribution
299system.membus.trans_dist::Writeback 115717 # Transaction distribution
300system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
301system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
302system.membus.trans_dist::ReadExReq 158297 # Transaction distribution
303system.membus.trans_dist::ReadExResp 158297 # Transaction distribution
304system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878206 # Packet count per connected master and slave (bytes)
306system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911366 # Packet count per connected master and slave (bytes)
307system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes)
308system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes)
309system.membus.pkt_count::total 1036046 # Packet count per connected master and slave (bytes)
310system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30460096 # Cumulative packet size per connected master and slave (bytes)
312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30504660 # Cumulative packet size per connected master and slave (bytes)
313system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes)
314system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes)
315system.membus.tot_pkt_size::total 35813780 # Cumulative packet size per connected master and slave (bytes)
316system.membus.data_through_bus 35813780 # Total data (bytes)
317system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes)
318system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks)
319system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
320system.membus.reqLayer1.occupancy 1492987250 # Layer occupancy (ticks)
321system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
322system.membus.respLayer1.occupancy 3752965347 # Layer occupancy (ticks)
323system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
324system.membus.respLayer2.occupancy 376688000 # Layer occupancy (ticks)
325system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
326system.iocache.tags.replacements 41685 # number of replacements
327system.iocache.tags.tagsinuse 1.344147 # Cycle average of tags in use
328system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
329system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
330system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
331system.iocache.tags.warmup_cycle 1754500427000 # Cycle when the warmup percentage was hit.
332system.iocache.tags.occ_blocks::tsunami.ide 1.344147 # Average occupied blocks per requestor
333system.iocache.tags.occ_percent::tsunami.ide 0.084009 # Average percentage of cache occupancy
334system.iocache.tags.occ_percent::total 0.084009 # Average percentage of cache occupancy
335system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
336system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
337system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
338system.iocache.tags.tag_accesses 375525 # Number of tag accesses
339system.iocache.tags.data_accesses 375525 # Number of data accesses
340system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
341system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
342system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
343system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
344system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses
345system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
346system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
347system.iocache.overall_misses::total 41725 # number of overall misses
348system.iocache.ReadReq_miss_latency::tsunami.ide 21134633 # number of ReadReq miss cycles
349system.iocache.ReadReq_miss_latency::total 21134633 # number of ReadReq miss cycles
350system.iocache.WriteReq_miss_latency::tsunami.ide 13148459442 # number of WriteReq miss cycles
351system.iocache.WriteReq_miss_latency::total 13148459442 # number of WriteReq miss cycles
352system.iocache.demand_miss_latency::tsunami.ide 13169594075 # number of demand (read+write) miss cycles
353system.iocache.demand_miss_latency::total 13169594075 # number of demand (read+write) miss cycles
354system.iocache.overall_miss_latency::tsunami.ide 13169594075 # number of overall miss cycles
355system.iocache.overall_miss_latency::total 13169594075 # number of overall miss cycles
356system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
357system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
358system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
359system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
360system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses
361system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
362system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses
363system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
364system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
365system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
366system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
367system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
368system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
369system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
370system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
371system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
372system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122165.508671 # average ReadReq miss latency
373system.iocache.ReadReq_avg_miss_latency::total 122165.508671 # average ReadReq miss latency
374system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316433.852570 # average WriteReq miss latency
375system.iocache.WriteReq_avg_miss_latency::total 316433.852570 # average WriteReq miss latency
376system.iocache.demand_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency
377system.iocache.demand_avg_miss_latency::total 315628.378071 # average overall miss latency
378system.iocache.overall_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency
379system.iocache.overall_avg_miss_latency::total 315628.378071 # average overall miss latency
380system.iocache.blocked_cycles::no_mshrs 393896 # number of cycles access was blocked
381system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
382system.iocache.blocked::no_mshrs 28296 # number of cycles access was blocked
383system.iocache.blocked::no_targets 0 # number of cycles access was blocked
384system.iocache.avg_blocked_cycles::no_mshrs 13.920554 # average number of cycles each access was blocked
385system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
386system.iocache.fast_writes 0 # number of fast writes performed
387system.iocache.cache_copies 0 # number of cache copies performed
388system.iocache.writebacks::writebacks 41512 # number of writebacks
389system.iocache.writebacks::total 41512 # number of writebacks
390system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
391system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
392system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
393system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
394system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses
395system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
396system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
397system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
398system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137633 # number of ReadReq MSHR miss cycles
399system.iocache.ReadReq_mshr_miss_latency::total 12137633 # number of ReadReq MSHR miss cycles
400system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10985430442 # number of WriteReq MSHR miss cycles
401system.iocache.WriteReq_mshr_miss_latency::total 10985430442 # number of WriteReq MSHR miss cycles
402system.iocache.demand_mshr_miss_latency::tsunami.ide 10997568075 # number of demand (read+write) MSHR miss cycles
403system.iocache.demand_mshr_miss_latency::total 10997568075 # number of demand (read+write) MSHR miss cycles
404system.iocache.overall_mshr_miss_latency::tsunami.ide 10997568075 # number of overall MSHR miss cycles
405system.iocache.overall_mshr_miss_latency::total 10997568075 # number of overall MSHR miss cycles
406system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
407system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
408system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
409system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
410system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
411system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
412system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
413system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
414system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70159.728324 # average ReadReq mshr miss latency
415system.iocache.ReadReq_avg_mshr_miss_latency::total 70159.728324 # average ReadReq mshr miss latency
416system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264377.898585 # average WriteReq mshr miss latency
417system.iocache.WriteReq_avg_mshr_miss_latency::total 264377.898585 # average WriteReq mshr miss latency
418system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency
419system.iocache.demand_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency
420system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency
421system.iocache.overall_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency
422system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
423system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
424system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
425system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
426system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
427system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
428system.disk0.dma_write_txs 395 # Number of DMA write transactions.
429system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
430system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
431system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
432system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
433system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
434system.disk2.dma_write_txs 1 # Number of DMA write transactions.
435system.cpu_clk_domain.clock 500 # Clock period in ticks
436system.cpu.dtb.fetch_hits 0 # ITB hits
437system.cpu.dtb.fetch_misses 0 # ITB misses
438system.cpu.dtb.fetch_acv 0 # ITB acv
439system.cpu.dtb.fetch_accesses 0 # ITB accesses
440system.cpu.dtb.read_hits 9066711 # DTB read hits
441system.cpu.dtb.read_misses 10324 # DTB read misses
442system.cpu.dtb.read_acv 210 # DTB read access violations
443system.cpu.dtb.read_accesses 728853 # DTB read accesses
444system.cpu.dtb.write_hits 6357503 # DTB write hits
445system.cpu.dtb.write_misses 1142 # DTB write misses
446system.cpu.dtb.write_acv 157 # DTB write access violations
447system.cpu.dtb.write_accesses 291931 # DTB write accesses
448system.cpu.dtb.data_hits 15424214 # DTB hits
449system.cpu.dtb.data_misses 11466 # DTB misses
450system.cpu.dtb.data_acv 367 # DTB access violations
451system.cpu.dtb.data_accesses 1020784 # DTB accesses
452system.cpu.itb.fetch_hits 4974520 # ITB hits
453system.cpu.itb.fetch_misses 5010 # ITB misses
454system.cpu.itb.fetch_acv 184 # ITB acv
455system.cpu.itb.fetch_accesses 4979530 # ITB accesses
456system.cpu.itb.read_hits 0 # DTB read hits
457system.cpu.itb.read_misses 0 # DTB read misses
458system.cpu.itb.read_acv 0 # DTB read access violations
459system.cpu.itb.read_accesses 0 # DTB read accesses
460system.cpu.itb.write_hits 0 # DTB write hits
461system.cpu.itb.write_misses 0 # DTB write misses
462system.cpu.itb.write_acv 0 # DTB write access violations
463system.cpu.itb.write_accesses 0 # DTB write accesses
464system.cpu.itb.data_hits 0 # DTB hits
465system.cpu.itb.data_misses 0 # DTB misses
466system.cpu.itb.data_acv 0 # DTB access violations
467system.cpu.itb.data_accesses 0 # DTB accesses
468system.cpu.numCycles 3840832362 # number of cpu cycles simulated
469system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
470system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
471system.cpu.committedInsts 56196255 # Number of instructions committed
472system.cpu.committedOps 56196255 # Number of ops (including micro ops) committed
473system.cpu.num_int_alu_accesses 52067788 # Number of integer alu accesses
474system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses
475system.cpu.num_func_calls 1483738 # number of times a function call or return occured
476system.cpu.num_conditional_control_insts 6469789 # number of instructions that are conditional controls
477system.cpu.num_int_insts 52067788 # number of integer instructions
478system.cpu.num_fp_insts 324393 # number of float instructions
479system.cpu.num_int_register_reads 71342399 # number of times the integer registers were read
480system.cpu.num_int_register_writes 38531411 # number of times the integer registers were written
481system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read
482system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written
483system.cpu.num_mem_refs 15476821 # number of memory refs
484system.cpu.num_load_insts 9103557 # Number of load instructions
485system.cpu.num_store_insts 6373264 # Number of store instructions
486system.cpu.num_idle_cycles 3589010980.998131 # Number of idle cycles
487system.cpu.num_busy_cycles 251821381.001869 # Number of busy cycles
488system.cpu.not_idle_fraction 0.065564 # Percentage of non-idle cycles
489system.cpu.idle_fraction 0.934436 # Percentage of idle cycles
490system.cpu.Branches 8424076 # Number of branches fetched
491system.cpu.kern.inst.arm 0 # number of arm instructions executed
492system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed
493system.cpu.kern.inst.hwrei 212001 # number of hwrei instructions executed
494system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl
495system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
496system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl
497system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl
498system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl
499system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl
500system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
501system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
502system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl
503system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl
504system.cpu.kern.ipl_ticks::0 1858066400000 96.75% 96.75% # number of cycles we spent at this ipl
505system.cpu.kern.ipl_ticks::21 91407000 0.00% 96.76% # number of cycles we spent at this ipl
506system.cpu.kern.ipl_ticks::22 737349500 0.04% 96.80% # number of cycles we spent at this ipl
507system.cpu.kern.ipl_ticks::31 61520290500 3.20% 100.00% # number of cycles we spent at this ipl
508system.cpu.kern.ipl_ticks::total 1920415447000 # number of cycles we spent at this ipl
509system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
510system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
511system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
512system.cpu.kern.ipl_used::31 0.692248 # fraction of swpipl calls that actually changed the ipl
513system.cpu.kern.ipl_used::total 0.814083 # fraction of swpipl calls that actually changed the ipl
514system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
515system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
516system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
517system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
518system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
519system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
520system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
521system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed

--- 19 unchanged lines hidden (view full) ---

541system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
542system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
543system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
544system.cpu.kern.syscall::total 326 # number of syscalls executed
545system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
546system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
547system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
548system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
549system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed
550system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
551system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
552system.cpu.kern.callpal::swpipl 175963 91.22% 93.41% # number of callpals executed
553system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed
554system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
555system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
556system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
557system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
558system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed
559system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
560system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
561system.cpu.kern.callpal::total 192909 # number of callpals executed
562system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches
563system.cpu.kern.mode_switch::user 1741 # number of protection mode switches
564system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
565system.cpu.kern.mode_good::kernel 1911
566system.cpu.kern.mode_good::user 1741
567system.cpu.kern.mode_good::idle 170
568system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches
569system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
570system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
571system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches
572system.cpu.kern.mode_ticks::kernel 46067941500 2.40% 2.40% # number of ticks spent at the given mode
573system.cpu.kern.mode_ticks::user 5182686000 0.27% 2.67% # number of ticks spent at the given mode
574system.cpu.kern.mode_ticks::idle 1869164817500 97.33% 100.00% # number of ticks spent at the given mode
575system.cpu.kern.swap_context 4177 # number of times the context was actually changed
576system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
577system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
578system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
579system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
580system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
581system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
582system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
583system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

599system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
600system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
601system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
602system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
603system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
604system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
605system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
606system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
607system.iobus.throughput 1409159 # Throughput (bytes/s)
608system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
609system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
610system.iobus.trans_dist::WriteReq 51202 # Transaction distribution
611system.iobus.trans_dist::WriteResp 51202 # Transaction distribution
612system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes)
613system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
614system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
615system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
616system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
617system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
618system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
619system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
620system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
621system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
622system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
623system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
624system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes)
625system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
626system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
627system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes)
628system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes)
629system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
630system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
631system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
632system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
633system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
634system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
635system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
636system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
637system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
638system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
639system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
640system.iobus.tot_pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes)
641system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
642system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
643system.iobus.tot_pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes)
644system.iobus.data_through_bus 2706172 # Total data (bytes)
645system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks)
646system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
647system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
648system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
649system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
650system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
651system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
652system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
653system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)

--- 5 unchanged lines hidden (view full) ---

659system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
660system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
661system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
662system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
663system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
664system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
665system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
666system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
667system.iobus.reqLayer29.occupancy 380034075 # Layer occupancy (ticks)
668system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
669system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
670system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
671system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
672system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
673system.iobus.respLayer1.occupancy 43162000 # Layer occupancy (ticks)
674system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
675system.cpu.icache.tags.replacements 928494 # number of replacements
676system.cpu.icache.tags.tagsinuse 508.301721 # Cycle average of tags in use
677system.cpu.icache.tags.total_refs 55278924 # Total number of references to valid blocks.
678system.cpu.icache.tags.sampled_refs 929005 # Sample count of references to valid blocks.
679system.cpu.icache.tags.avg_refs 59.503365 # Average number of references to valid blocks.
680system.cpu.icache.tags.warmup_cycle 39895254250 # Cycle when the warmup percentage was hit.
681system.cpu.icache.tags.occ_blocks::cpu.inst 508.301721 # Average occupied blocks per requestor
682system.cpu.icache.tags.occ_percent::cpu.inst 0.992777 # Average percentage of cache occupancy
683system.cpu.icache.tags.occ_percent::total 0.992777 # Average percentage of cache occupancy
684system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
685system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
686system.cpu.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
687system.cpu.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id
688system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
689system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
690system.cpu.icache.tags.tag_accesses 57137254 # Number of tag accesses
691system.cpu.icache.tags.data_accesses 57137254 # Number of data accesses
692system.cpu.icache.ReadReq_hits::cpu.inst 55278924 # number of ReadReq hits
693system.cpu.icache.ReadReq_hits::total 55278924 # number of ReadReq hits
694system.cpu.icache.demand_hits::cpu.inst 55278924 # number of demand (read+write) hits
695system.cpu.icache.demand_hits::total 55278924 # number of demand (read+write) hits
696system.cpu.icache.overall_hits::cpu.inst 55278924 # number of overall hits
697system.cpu.icache.overall_hits::total 55278924 # number of overall hits
698system.cpu.icache.ReadReq_misses::cpu.inst 929165 # number of ReadReq misses
699system.cpu.icache.ReadReq_misses::total 929165 # number of ReadReq misses
700system.cpu.icache.demand_misses::cpu.inst 929165 # number of demand (read+write) misses
701system.cpu.icache.demand_misses::total 929165 # number of demand (read+write) misses
702system.cpu.icache.overall_misses::cpu.inst 929165 # number of overall misses
703system.cpu.icache.overall_misses::total 929165 # number of overall misses
704system.cpu.icache.ReadReq_miss_latency::cpu.inst 12919006759 # number of ReadReq miss cycles
705system.cpu.icache.ReadReq_miss_latency::total 12919006759 # number of ReadReq miss cycles
706system.cpu.icache.demand_miss_latency::cpu.inst 12919006759 # number of demand (read+write) miss cycles
707system.cpu.icache.demand_miss_latency::total 12919006759 # number of demand (read+write) miss cycles
708system.cpu.icache.overall_miss_latency::cpu.inst 12919006759 # number of overall miss cycles
709system.cpu.icache.overall_miss_latency::total 12919006759 # number of overall miss cycles
710system.cpu.icache.ReadReq_accesses::cpu.inst 56208089 # number of ReadReq accesses(hits+misses)
711system.cpu.icache.ReadReq_accesses::total 56208089 # number of ReadReq accesses(hits+misses)
712system.cpu.icache.demand_accesses::cpu.inst 56208089 # number of demand (read+write) accesses
713system.cpu.icache.demand_accesses::total 56208089 # number of demand (read+write) accesses
714system.cpu.icache.overall_accesses::cpu.inst 56208089 # number of overall (read+write) accesses
715system.cpu.icache.overall_accesses::total 56208089 # number of overall (read+write) accesses
716system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016531 # miss rate for ReadReq accesses
717system.cpu.icache.ReadReq_miss_rate::total 0.016531 # miss rate for ReadReq accesses
718system.cpu.icache.demand_miss_rate::cpu.inst 0.016531 # miss rate for demand accesses
719system.cpu.icache.demand_miss_rate::total 0.016531 # miss rate for demand accesses
720system.cpu.icache.overall_miss_rate::cpu.inst 0.016531 # miss rate for overall accesses
721system.cpu.icache.overall_miss_rate::total 0.016531 # miss rate for overall accesses
722system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.888716 # average ReadReq miss latency
723system.cpu.icache.ReadReq_avg_miss_latency::total 13903.888716 # average ReadReq miss latency
724system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency
725system.cpu.icache.demand_avg_miss_latency::total 13903.888716 # average overall miss latency
726system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency
727system.cpu.icache.overall_avg_miss_latency::total 13903.888716 # average overall miss latency
728system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
729system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
730system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
731system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
732system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
733system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
734system.cpu.icache.fast_writes 0 # number of fast writes performed
735system.cpu.icache.cache_copies 0 # number of cache copies performed
736system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929165 # number of ReadReq MSHR misses
737system.cpu.icache.ReadReq_mshr_misses::total 929165 # number of ReadReq MSHR misses
738system.cpu.icache.demand_mshr_misses::cpu.inst 929165 # number of demand (read+write) MSHR misses
739system.cpu.icache.demand_mshr_misses::total 929165 # number of demand (read+write) MSHR misses
740system.cpu.icache.overall_mshr_misses::cpu.inst 929165 # number of overall MSHR misses
741system.cpu.icache.overall_mshr_misses::total 929165 # number of overall MSHR misses
742system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11055577241 # number of ReadReq MSHR miss cycles
743system.cpu.icache.ReadReq_mshr_miss_latency::total 11055577241 # number of ReadReq MSHR miss cycles
744system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11055577241 # number of demand (read+write) MSHR miss cycles
745system.cpu.icache.demand_mshr_miss_latency::total 11055577241 # number of demand (read+write) MSHR miss cycles
746system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11055577241 # number of overall MSHR miss cycles
747system.cpu.icache.overall_mshr_miss_latency::total 11055577241 # number of overall MSHR miss cycles
748system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for ReadReq accesses
749system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016531 # mshr miss rate for ReadReq accesses
750system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for demand accesses
751system.cpu.icache.demand_mshr_miss_rate::total 0.016531 # mshr miss rate for demand accesses
752system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for overall accesses
753system.cpu.icache.overall_mshr_miss_rate::total 0.016531 # mshr miss rate for overall accesses
754system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.400436 # average ReadReq mshr miss latency
755system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.400436 # average ReadReq mshr miss latency
756system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency
757system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency
758system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency
759system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency
760system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
761system.cpu.l2cache.tags.replacements 336265 # number of replacements
762system.cpu.l2cache.tags.tagsinuse 65295.577509 # Cycle average of tags in use
763system.cpu.l2cache.tags.total_refs 2447728 # Total number of references to valid blocks.
764system.cpu.l2cache.tags.sampled_refs 401427 # Sample count of references to valid blocks.
765system.cpu.l2cache.tags.avg_refs 6.097567 # Average number of references to valid blocks.
766system.cpu.l2cache.tags.warmup_cycle 6793166750 # Cycle when the warmup percentage was hit.
767system.cpu.l2cache.tags.occ_blocks::writebacks 55588.679267 # Average occupied blocks per requestor
768system.cpu.l2cache.tags.occ_blocks::cpu.inst 4757.001179 # Average occupied blocks per requestor
769system.cpu.l2cache.tags.occ_blocks::cpu.data 4949.897063 # Average occupied blocks per requestor
770system.cpu.l2cache.tags.occ_percent::writebacks 0.848216 # Average percentage of cache occupancy
771system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072586 # Average percentage of cache occupancy
772system.cpu.l2cache.tags.occ_percent::cpu.data 0.075529 # Average percentage of cache occupancy
773system.cpu.l2cache.tags.occ_percent::total 0.996331 # Average percentage of cache occupancy
774system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
775system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
776system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id
777system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4882 # Occupied blocks per task id
778system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3251 # Occupied blocks per task id
779system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55777 # Occupied blocks per task id
780system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
781system.cpu.l2cache.tags.tag_accesses 25952661 # Number of tag accesses
782system.cpu.l2cache.tags.data_accesses 25952661 # Number of data accesses
783system.cpu.l2cache.ReadReq_hits::cpu.inst 915852 # number of ReadReq hits
784system.cpu.l2cache.ReadReq_hits::cpu.data 814775 # number of ReadReq hits
785system.cpu.l2cache.ReadReq_hits::total 1730627 # number of ReadReq hits
786system.cpu.l2cache.Writeback_hits::writebacks 835359 # number of Writeback hits
787system.cpu.l2cache.Writeback_hits::total 835359 # number of Writeback hits
788system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
789system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
790system.cpu.l2cache.ReadExReq_hits::cpu.data 187681 # number of ReadExReq hits
791system.cpu.l2cache.ReadExReq_hits::total 187681 # number of ReadExReq hits
792system.cpu.l2cache.demand_hits::cpu.inst 915852 # number of demand (read+write) hits
793system.cpu.l2cache.demand_hits::cpu.data 1002456 # number of demand (read+write) hits
794system.cpu.l2cache.demand_hits::total 1918308 # number of demand (read+write) hits
795system.cpu.l2cache.overall_hits::cpu.inst 915852 # number of overall hits
796system.cpu.l2cache.overall_hits::cpu.data 1002456 # number of overall hits
797system.cpu.l2cache.overall_hits::total 1918308 # number of overall hits
798system.cpu.l2cache.ReadReq_misses::cpu.inst 13293 # number of ReadReq misses
799system.cpu.l2cache.ReadReq_misses::cpu.data 271967 # number of ReadReq misses
800system.cpu.l2cache.ReadReq_misses::total 285260 # number of ReadReq misses
801system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
802system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
803system.cpu.l2cache.ReadExReq_misses::cpu.data 116864 # number of ReadExReq misses
804system.cpu.l2cache.ReadExReq_misses::total 116864 # number of ReadExReq misses
805system.cpu.l2cache.demand_misses::cpu.inst 13293 # number of demand (read+write) misses
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807system.cpu.l2cache.demand_misses::total 402124 # number of demand (read+write) misses
808system.cpu.l2cache.overall_misses::cpu.inst 13293 # number of overall misses
809system.cpu.l2cache.overall_misses::cpu.data 388831 # number of overall misses
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812system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17714808491 # number of ReadReq miss cycles
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814system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles
815system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles
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825system.cpu.l2cache.ReadReq_accesses::cpu.data 1086742 # number of ReadReq accesses(hits+misses)
826system.cpu.l2cache.ReadReq_accesses::total 2015887 # number of ReadReq accesses(hits+misses)
827system.cpu.l2cache.Writeback_accesses::writebacks 835359 # number of Writeback accesses(hits+misses)
828system.cpu.l2cache.Writeback_accesses::total 835359 # number of Writeback accesses(hits+misses)
829system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
830system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
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838system.cpu.l2cache.overall_accesses::total 2320432 # number of overall (read+write) accesses
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840system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250259 # miss rate for ReadReq accesses
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842system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses
843system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses
844system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383733 # miss rate for ReadExReq accesses
845system.cpu.l2cache.ReadExReq_miss_rate::total 0.383733 # miss rate for ReadExReq accesses
846system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014307 # miss rate for demand accesses
847system.cpu.l2cache.demand_miss_rate::cpu.data 0.279476 # miss rate for demand accesses
848system.cpu.l2cache.demand_miss_rate::total 0.173297 # miss rate for demand accesses
849system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014307 # miss rate for overall accesses
850system.cpu.l2cache.overall_miss_rate::cpu.data 0.279476 # miss rate for overall accesses
851system.cpu.l2cache.overall_miss_rate::total 0.173297 # miss rate for overall accesses
852system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72810.670353 # average ReadReq miss latency
853system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65135.874908 # average ReadReq miss latency
854system.cpu.l2cache.ReadReq_avg_miss_latency::total 65493.517254 # average ReadReq miss latency
855system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency
856system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency
857system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68550.106329 # average ReadExReq miss latency
858system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68550.106329 # average ReadExReq miss latency
859system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72810.670353 # average overall miss latency
860system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66162.029563 # average overall miss latency
861system.cpu.l2cache.demand_avg_miss_latency::total 66381.813465 # average overall miss latency
862system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72810.670353 # average overall miss latency
863system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66162.029563 # average overall miss latency
864system.cpu.l2cache.overall_avg_miss_latency::total 66381.813465 # average overall miss latency
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866system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
867system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
868system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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870system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
871system.cpu.l2cache.fast_writes 0 # number of fast writes performed
872system.cpu.l2cache.cache_copies 0 # number of cache copies performed
873system.cpu.l2cache.writebacks::writebacks 74205 # number of writebacks
874system.cpu.l2cache.writebacks::total 74205 # number of writebacks
875system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13293 # number of ReadReq MSHR misses
876system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271967 # number of ReadReq MSHR misses
877system.cpu.l2cache.ReadReq_mshr_misses::total 285260 # number of ReadReq MSHR misses
878system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
879system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
880system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116864 # number of ReadExReq MSHR misses
881system.cpu.l2cache.ReadExReq_mshr_misses::total 116864 # number of ReadExReq MSHR misses
882system.cpu.l2cache.demand_mshr_misses::cpu.inst 13293 # number of demand (read+write) MSHR misses
883system.cpu.l2cache.demand_mshr_misses::cpu.data 388831 # number of demand (read+write) MSHR misses
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886system.cpu.l2cache.overall_mshr_misses::cpu.data 388831 # number of overall MSHR misses
887system.cpu.l2cache.overall_mshr_misses::total 402124 # number of overall MSHR misses
888system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 801329759 # number of ReadReq MSHR miss cycles
889system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14314442009 # number of ReadReq MSHR miss cycles
890system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15115771768 # number of ReadReq MSHR miss cycles
891system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles
892system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles
893system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6549827374 # number of ReadExReq MSHR miss cycles
894system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6549827374 # number of ReadExReq MSHR miss cycles
895system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 801329759 # number of demand (read+write) MSHR miss cycles
896system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20864269383 # number of demand (read+write) MSHR miss cycles
897system.cpu.l2cache.demand_mshr_miss_latency::total 21665599142 # number of demand (read+write) MSHR miss cycles
898system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 801329759 # number of overall MSHR miss cycles
899system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20864269383 # number of overall MSHR miss cycles
900system.cpu.l2cache.overall_mshr_miss_latency::total 21665599142 # number of overall MSHR miss cycles
901system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles
902system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles
903system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895641500 # number of WriteReq MSHR uncacheable cycles
904system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895641500 # number of WriteReq MSHR uncacheable cycles
905system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles
906system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles
907system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for ReadReq accesses
908system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses
909system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141506 # mshr miss rate for ReadReq accesses
910system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
911system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
912system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383733 # mshr miss rate for ReadExReq accesses
913system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383733 # mshr miss rate for ReadExReq accesses
914system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for demand accesses
915system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for demand accesses
916system.cpu.l2cache.demand_mshr_miss_rate::total 0.173297 # mshr miss rate for demand accesses
917system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for overall accesses
918system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for overall accesses
919system.cpu.l2cache.overall_mshr_miss_rate::total 0.173297 # mshr miss rate for overall accesses
920system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60282.085233 # average ReadReq mshr miss latency
921system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52633.010656 # average ReadReq mshr miss latency
922system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52989.454421 # average ReadReq mshr miss latency
923system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency
924system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency
925system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56046.578707 # average ReadExReq mshr miss latency
926system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56046.578707 # average ReadExReq mshr miss latency
927system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency
928system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency
929system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency
930system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency
931system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency
932system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency
933system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
934system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
935system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
936system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
937system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
938system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
939system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
940system.cpu.dcache.tags.replacements 1390774 # number of replacements
941system.cpu.dcache.tags.tagsinuse 511.978892 # Cycle average of tags in use
942system.cpu.dcache.tags.total_refs 14051964 # Total number of references to valid blocks.
943system.cpu.dcache.tags.sampled_refs 1391286 # Sample count of references to valid blocks.
944system.cpu.dcache.tags.avg_refs 10.099982 # Average number of references to valid blocks.
945system.cpu.dcache.tags.warmup_cycle 107796250 # Cycle when the warmup percentage was hit.
946system.cpu.dcache.tags.occ_blocks::cpu.data 511.978892 # Average occupied blocks per requestor
947system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
948system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
949system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
950system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
951system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
952system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
953system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
954system.cpu.dcache.tags.tag_accesses 63164291 # Number of tag accesses
955system.cpu.dcache.tags.data_accesses 63164291 # Number of data accesses
956system.cpu.dcache.ReadReq_hits::cpu.data 7816324 # number of ReadReq hits
957system.cpu.dcache.ReadReq_hits::total 7816324 # number of ReadReq hits
958system.cpu.dcache.WriteReq_hits::cpu.data 5853358 # number of WriteReq hits
959system.cpu.dcache.WriteReq_hits::total 5853358 # number of WriteReq hits
960system.cpu.dcache.LoadLockedReq_hits::cpu.data 183027 # number of LoadLockedReq hits
961system.cpu.dcache.LoadLockedReq_hits::total 183027 # number of LoadLockedReq hits
962system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits
963system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits
964system.cpu.dcache.demand_hits::cpu.data 13669682 # number of demand (read+write) hits
965system.cpu.dcache.demand_hits::total 13669682 # number of demand (read+write) hits
966system.cpu.dcache.overall_hits::cpu.data 13669682 # number of overall hits
967system.cpu.dcache.overall_hits::total 13669682 # number of overall hits
968system.cpu.dcache.ReadReq_misses::cpu.data 1069509 # number of ReadReq misses
969system.cpu.dcache.ReadReq_misses::total 1069509 # number of ReadReq misses
970system.cpu.dcache.WriteReq_misses::cpu.data 304562 # number of WriteReq misses
971system.cpu.dcache.WriteReq_misses::total 304562 # number of WriteReq misses
972system.cpu.dcache.LoadLockedReq_misses::cpu.data 17233 # number of LoadLockedReq misses
973system.cpu.dcache.LoadLockedReq_misses::total 17233 # number of LoadLockedReq misses
974system.cpu.dcache.demand_misses::cpu.data 1374071 # number of demand (read+write) misses
975system.cpu.dcache.demand_misses::total 1374071 # number of demand (read+write) misses
976system.cpu.dcache.overall_misses::cpu.data 1374071 # number of overall misses
977system.cpu.dcache.overall_misses::total 1374071 # number of overall misses
978system.cpu.dcache.ReadReq_miss_latency::cpu.data 29019471009 # number of ReadReq miss cycles
979system.cpu.dcache.ReadReq_miss_latency::total 29019471009 # number of ReadReq miss cycles
980system.cpu.dcache.WriteReq_miss_latency::cpu.data 10854033885 # number of WriteReq miss cycles
981system.cpu.dcache.WriteReq_miss_latency::total 10854033885 # number of WriteReq miss cycles
982system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228736500 # number of LoadLockedReq miss cycles
983system.cpu.dcache.LoadLockedReq_miss_latency::total 228736500 # number of LoadLockedReq miss cycles
984system.cpu.dcache.demand_miss_latency::cpu.data 39873504894 # number of demand (read+write) miss cycles
985system.cpu.dcache.demand_miss_latency::total 39873504894 # number of demand (read+write) miss cycles
986system.cpu.dcache.overall_miss_latency::cpu.data 39873504894 # number of overall miss cycles
987system.cpu.dcache.overall_miss_latency::total 39873504894 # number of overall miss cycles
988system.cpu.dcache.ReadReq_accesses::cpu.data 8885833 # number of ReadReq accesses(hits+misses)
989system.cpu.dcache.ReadReq_accesses::total 8885833 # number of ReadReq accesses(hits+misses)
990system.cpu.dcache.WriteReq_accesses::cpu.data 6157920 # number of WriteReq accesses(hits+misses)
991system.cpu.dcache.WriteReq_accesses::total 6157920 # number of WriteReq accesses(hits+misses)
992system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200260 # number of LoadLockedReq accesses(hits+misses)
993system.cpu.dcache.LoadLockedReq_accesses::total 200260 # number of LoadLockedReq accesses(hits+misses)
994system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses)
995system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses)
996system.cpu.dcache.demand_accesses::cpu.data 15043753 # number of demand (read+write) accesses
997system.cpu.dcache.demand_accesses::total 15043753 # number of demand (read+write) accesses
998system.cpu.dcache.overall_accesses::cpu.data 15043753 # number of overall (read+write) accesses
999system.cpu.dcache.overall_accesses::total 15043753 # number of overall (read+write) accesses
1000system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120361 # miss rate for ReadReq accesses
1001system.cpu.dcache.ReadReq_miss_rate::total 0.120361 # miss rate for ReadReq accesses
1002system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses
1003system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses
1004system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086053 # miss rate for LoadLockedReq accesses
1005system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086053 # miss rate for LoadLockedReq accesses
1006system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses
1007system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses
1008system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses
1009system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses
1010system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27133.451901 # average ReadReq miss latency
1011system.cpu.dcache.ReadReq_avg_miss_latency::total 27133.451901 # average ReadReq miss latency
1012system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35638.175101 # average WriteReq miss latency
1013system.cpu.dcache.WriteReq_avg_miss_latency::total 35638.175101 # average WriteReq miss latency
1014system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.167760 # average LoadLockedReq miss latency
1015system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.167760 # average LoadLockedReq miss latency
1016system.cpu.dcache.demand_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency
1017system.cpu.dcache.demand_avg_miss_latency::total 29018.518617 # average overall miss latency
1018system.cpu.dcache.overall_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency
1019system.cpu.dcache.overall_avg_miss_latency::total 29018.518617 # average overall miss latency
1020system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1021system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1022system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1023system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
1024system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1025system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1026system.cpu.dcache.fast_writes 0 # number of fast writes performed
1027system.cpu.dcache.cache_copies 0 # number of cache copies performed
1028system.cpu.dcache.writebacks::writebacks 835359 # number of writebacks
1029system.cpu.dcache.writebacks::total 835359 # number of writebacks
1030system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069509 # number of ReadReq MSHR misses
1031system.cpu.dcache.ReadReq_mshr_misses::total 1069509 # number of ReadReq MSHR misses
1032system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304562 # number of WriteReq MSHR misses
1033system.cpu.dcache.WriteReq_mshr_misses::total 304562 # number of WriteReq MSHR misses
1034system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17233 # number of LoadLockedReq MSHR misses
1035system.cpu.dcache.LoadLockedReq_mshr_misses::total 17233 # number of LoadLockedReq MSHR misses
1036system.cpu.dcache.demand_mshr_misses::cpu.data 1374071 # number of demand (read+write) MSHR misses
1037system.cpu.dcache.demand_mshr_misses::total 1374071 # number of demand (read+write) MSHR misses
1038system.cpu.dcache.overall_mshr_misses::cpu.data 1374071 # number of overall MSHR misses
1039system.cpu.dcache.overall_mshr_misses::total 1374071 # number of overall MSHR misses
1040system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26755042991 # number of ReadReq MSHR miss cycles
1041system.cpu.dcache.ReadReq_mshr_miss_latency::total 26755042991 # number of ReadReq MSHR miss cycles
1042system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10192844115 # number of WriteReq MSHR miss cycles
1043system.cpu.dcache.WriteReq_mshr_miss_latency::total 10192844115 # number of WriteReq MSHR miss cycles
1044system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194257500 # number of LoadLockedReq MSHR miss cycles
1045system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194257500 # number of LoadLockedReq MSHR miss cycles
1046system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36947887106 # number of demand (read+write) MSHR miss cycles
1047system.cpu.dcache.demand_mshr_miss_latency::total 36947887106 # number of demand (read+write) MSHR miss cycles
1048system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36947887106 # number of overall MSHR miss cycles
1049system.cpu.dcache.overall_mshr_miss_latency::total 36947887106 # number of overall MSHR miss cycles
1050system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles
1051system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles
1052system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011441500 # number of WriteReq MSHR uncacheable cycles
1053system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011441500 # number of WriteReq MSHR uncacheable cycles
1054system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles
1055system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles
1056system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120361 # mshr miss rate for ReadReq accesses
1057system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120361 # mshr miss rate for ReadReq accesses
1058system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses
1059system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses
1060system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086053 # mshr miss rate for LoadLockedReq accesses
1061system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086053 # mshr miss rate for LoadLockedReq accesses
1062system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses
1063system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses
1064system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses
1065system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses
1066system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25016.192469 # average ReadReq mshr miss latency
1067system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25016.192469 # average ReadReq mshr miss latency
1068system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33467.222158 # average WriteReq mshr miss latency
1069system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33467.222158 # average WriteReq mshr miss latency
1070system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.413393 # average LoadLockedReq mshr miss latency
1071system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.413393 # average LoadLockedReq mshr miss latency
1072system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency
1073system.cpu.dcache.demand_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency
1074system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency
1075system.cpu.dcache.overall_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency
1076system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1077system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1078system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1079system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1080system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1081system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1082system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1083system.cpu.toL2Bus.throughput 105199341 # Throughput (bytes/s)
1084system.cpu.toL2Bus.trans_dist::ReadReq 2023010 # Transaction distribution
1085system.cpu.toL2Bus.trans_dist::ReadResp 2022993 # Transaction distribution
1086system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
1087system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
1088system.cpu.toL2Bus.trans_dist::Writeback 835359 # Transaction distribution
1089system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
1090system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
1091system.cpu.toL2Bus.trans_dist::ReadExReq 346097 # Transaction distribution
1092system.cpu.toL2Bus.trans_dist::ReadExResp 304546 # Transaction distribution
1093system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858310 # Packet count per connected master and slave (bytes)
1094system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651284 # Packet count per connected master and slave (bytes)
1095system.cpu.toL2Bus.pkt_count::total 5509594 # Packet count per connected master and slave (bytes)
1096system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59465280 # Cumulative packet size per connected master and slave (bytes)
1097system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142559956 # Cumulative packet size per connected master and slave (bytes)
1098system.cpu.toL2Bus.tot_pkt_size::total 202025236 # Cumulative packet size per connected master and slave (bytes)
1099system.cpu.toL2Bus.data_through_bus 202015188 # Total data (bytes)
1100system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes)
1101system.cpu.toL2Bus.reqLayer0.occupancy 2426388000 # Layer occupancy (ticks)
1102system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1103system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
1104system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1105system.cpu.toL2Bus.respLayer0.occupancy 1396297259 # Layer occupancy (ticks)
1106system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1107system.cpu.toL2Bus.respLayer1.occupancy 2187438394 # Layer occupancy (ticks)
1108system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1109
1110---------- End Simulation Statistics ----------