| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20eventq_index=0 21exit_on_work_items=false 22init_param=0 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20eventq_index=0 21exit_on_work_items=false 22init_param=0 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing |
| 28mem_ranges=0:134217727 | 28mem_ranges=0:134217727:0:0:0:0 |
| 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal --- 18 unchanged lines hidden (view full) --- 55clk_domain=system.clk_domain 56default_p_state=UNDEFINED 57delay=50000 58eventq_index=0 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null | 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal --- 18 unchanged lines hidden (view full) --- 55clk_domain=system.clk_domain 56default_p_state=UNDEFINED 57delay=50000 58eventq_index=0 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null |
| 63ranges=8796093022208:18446744073709551615 | 63ranges=8796093022208:18446744073709551615:0:0:0:0 |
| 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain 71clock=1000 --- 38 unchanged lines hidden (view full) --- 110tracer=system.cpu.tracer 111workload= 112dcache_port=system.cpu.dcache.cpu_side 113icache_port=system.cpu.icache.cpu_side 114 115[system.cpu.dcache] 116type=Cache 117children=tags | 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain 71clock=1000 --- 38 unchanged lines hidden (view full) --- 110tracer=system.cpu.tracer 111workload= 112dcache_port=system.cpu.dcache.cpu_side 113icache_port=system.cpu.icache.cpu_side 114 115[system.cpu.dcache] 116type=Cache 117children=tags |
| 118addr_ranges=0:18446744073709551615 | 118addr_ranges=0:18446744073709551615:0:0:0:0 |
| 119assoc=4 120clk_domain=system.cpu_clk_domain 121clusivity=mostly_incl 122default_p_state=UNDEFINED 123demand_mshr_reserve=1 124eventq_index=0 125hit_latency=2 126is_read_only=false --- 34 unchanged lines hidden (view full) --- 161[system.cpu.dtb] 162type=AlphaTLB 163eventq_index=0 164size=64 165 166[system.cpu.icache] 167type=Cache 168children=tags | 119assoc=4 120clk_domain=system.cpu_clk_domain 121clusivity=mostly_incl 122default_p_state=UNDEFINED 123demand_mshr_reserve=1 124eventq_index=0 125hit_latency=2 126is_read_only=false --- 34 unchanged lines hidden (view full) --- 161[system.cpu.dtb] 162type=AlphaTLB 163eventq_index=0 164size=64 165 166[system.cpu.icache] 167type=Cache 168children=tags |
| 169addr_ranges=0:18446744073709551615 | 169addr_ranges=0:18446744073709551615:0:0:0:0 |
| 170assoc=1 171clk_domain=system.cpu_clk_domain 172clusivity=mostly_incl 173default_p_state=UNDEFINED 174demand_mshr_reserve=1 175eventq_index=0 176hit_latency=2 177is_read_only=true --- 43 unchanged lines hidden (view full) --- 221[system.cpu.itb] 222type=AlphaTLB 223eventq_index=0 224size=48 225 226[system.cpu.l2cache] 227type=Cache 228children=tags | 170assoc=1 171clk_domain=system.cpu_clk_domain 172clusivity=mostly_incl 173default_p_state=UNDEFINED 174demand_mshr_reserve=1 175eventq_index=0 176hit_latency=2 177is_read_only=true --- 43 unchanged lines hidden (view full) --- 221[system.cpu.itb] 222type=AlphaTLB 223eventq_index=0 224size=48 225 226[system.cpu.l2cache] 227type=Cache 228children=tags |
| 229addr_ranges=0:18446744073709551615 | 229addr_ranges=0:18446744073709551615:0:0:0:0 |
| 230assoc=8 231clk_domain=system.cpu_clk_domain 232clusivity=mostly_incl 233default_p_state=UNDEFINED 234demand_mshr_reserve=1 235eventq_index=0 236hit_latency=20 237is_read_only=false --- 146 unchanged lines hidden (view full) --- 384use_default_range=false 385width=16 386master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 387slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 388 389[system.iocache] 390type=Cache 391children=tags | 230assoc=8 231clk_domain=system.cpu_clk_domain 232clusivity=mostly_incl 233default_p_state=UNDEFINED 234demand_mshr_reserve=1 235eventq_index=0 236hit_latency=20 237is_read_only=false --- 146 unchanged lines hidden (view full) --- 384use_default_range=false 385width=16 386master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 387slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 388 389[system.iocache] 390type=Cache 391children=tags |
| 392addr_ranges=0:134217727 | 392addr_ranges=0:134217727:0:0:0:0 |
| 393assoc=8 394clk_domain=system.clk_domain 395clusivity=mostly_incl 396default_p_state=UNDEFINED 397demand_mshr_reserve=1 398eventq_index=0 399hit_latency=50 400is_read_only=false --- 28 unchanged lines hidden (view full) --- 429p_state_clk_gate_max=1000000000000 430p_state_clk_gate_min=1000 431power_model=Null 432sequential_access=false 433size=1024 434 435[system.membus] 436type=CoherentXBar | 393assoc=8 394clk_domain=system.clk_domain 395clusivity=mostly_incl 396default_p_state=UNDEFINED 397demand_mshr_reserve=1 398eventq_index=0 399hit_latency=50 400is_read_only=false --- 28 unchanged lines hidden (view full) --- 429p_state_clk_gate_max=1000000000000 430p_state_clk_gate_min=1000 431power_model=Null 432sequential_access=false 433size=1024 434 435[system.membus] 436type=CoherentXBar |
| 437children=badaddr_responder | 437children=badaddr_responder snoop_filter |
| 438clk_domain=system.clk_domain 439default_p_state=UNDEFINED 440eventq_index=0 441forward_latency=4 442frontend_latency=3 443p_state_clk_gate_bins=20 444p_state_clk_gate_max=1000000000000 445p_state_clk_gate_min=1000 446point_of_coherency=true 447power_model=Null 448response_latency=2 | 438clk_domain=system.clk_domain 439default_p_state=UNDEFINED 440eventq_index=0 441forward_latency=4 442frontend_latency=3 443p_state_clk_gate_bins=20 444p_state_clk_gate_max=1000000000000 445p_state_clk_gate_min=1000 446point_of_coherency=true 447power_model=Null 448response_latency=2 |
| 449snoop_filter=Null | 449snoop_filter=system.membus.snoop_filter |
| 450snoop_response_latency=4 451system=system 452use_default_range=false 453width=16 454default=system.membus.badaddr_responder.pio 455master=system.bridge.slave system.physmem.port 456slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 457 --- 15 unchanged lines hidden (view full) --- 473ret_data32=4294967295 474ret_data64=18446744073709551615 475ret_data8=255 476system=system 477update_data=false 478warn_access= 479pio=system.membus.default 480 | 450snoop_response_latency=4 451system=system 452use_default_range=false 453width=16 454default=system.membus.badaddr_responder.pio 455master=system.bridge.slave system.physmem.port 456slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 457 --- 15 unchanged lines hidden (view full) --- 473ret_data32=4294967295 474ret_data64=18446744073709551615 475ret_data8=255 476system=system 477update_data=false 478warn_access= 479pio=system.membus.default 480 |
| 481[system.membus.snoop_filter] 482type=SnoopFilter 483eventq_index=0 484lookup_latency=1 485max_capacity=8388608 486system=system 487 |
|
| 481[system.physmem] 482type=DRAMCtrl | 488[system.physmem] 489type=DRAMCtrl |
| 483IDD0=0.075000 | 490IDD0=0.055000 |
| 484IDD02=0.000000 | 491IDD02=0.000000 |
| 485IDD2N=0.050000 | 492IDD2N=0.032000 |
| 486IDD2N2=0.000000 487IDD2P0=0.000000 488IDD2P02=0.000000 | 493IDD2N2=0.000000 494IDD2P0=0.000000 495IDD2P02=0.000000 |
| 489IDD2P1=0.000000 | 496IDD2P1=0.032000 |
| 490IDD2P12=0.000000 | 497IDD2P12=0.000000 |
| 491IDD3N=0.057000 | 498IDD3N=0.038000 |
| 492IDD3N2=0.000000 493IDD3P0=0.000000 494IDD3P02=0.000000 | 499IDD3N2=0.000000 500IDD3P0=0.000000 501IDD3P02=0.000000 |
| 495IDD3P1=0.000000 | 502IDD3P1=0.038000 |
| 496IDD3P12=0.000000 | 503IDD3P12=0.000000 |
| 497IDD4R=0.187000 | 504IDD4R=0.157000 |
| 498IDD4R2=0.000000 | 505IDD4R2=0.000000 |
| 499IDD4W=0.165000 | 506IDD4W=0.125000 |
| 500IDD4W2=0.000000 | 507IDD4W2=0.000000 |
| 501IDD5=0.220000 | 508IDD5=0.235000 |
| 502IDD52=0.000000 | 509IDD52=0.000000 |
| 503IDD6=0.000000 | 510IDD6=0.020000 |
| 504IDD62=0.000000 505VDD=1.500000 506VDD2=0.000000 507activation_limit=4 508addr_mapping=RoRaBaCoCh 509bank_groups_per_rank=0 510banks_per_rank=8 511burst_length=8 512channels=1 513clk_domain=system.clk_domain 514conf_table_reported=true 515default_p_state=UNDEFINED 516device_bus_width=8 517device_rowbuffer_size=1024 518device_size=536870912 519devices_per_rank=8 520dll=true 521eventq_index=0 522in_addr_map=true | 511IDD62=0.000000 512VDD=1.500000 513VDD2=0.000000 514activation_limit=4 515addr_mapping=RoRaBaCoCh 516bank_groups_per_rank=0 517banks_per_rank=8 518burst_length=8 519channels=1 520clk_domain=system.clk_domain 521conf_table_reported=true 522default_p_state=UNDEFINED 523device_bus_width=8 524device_rowbuffer_size=1024 525device_size=536870912 526devices_per_rank=8 527dll=true 528eventq_index=0 529in_addr_map=true |
| 530kvm_map=true |
|
| 523max_accesses_per_row=16 524mem_sched_policy=frfcfs 525min_writes_per_switch=16 526null=false 527p_state_clk_gate_bins=20 528p_state_clk_gate_max=1000000000000 529p_state_clk_gate_min=1000 530page_policy=open_adaptive 531power_model=Null | 531max_accesses_per_row=16 532mem_sched_policy=frfcfs 533min_writes_per_switch=16 534null=false 535p_state_clk_gate_bins=20 536p_state_clk_gate_max=1000000000000 537p_state_clk_gate_min=1000 538page_policy=open_adaptive 539power_model=Null |
| 532range=0:134217727 | 540range=0:134217727:0:0:0:0 |
| 533ranks_per_channel=2 534read_buffer_size=32 535static_backend_latency=10000 536static_frontend_latency=10000 537tBURST=5000 538tCCD_L=0 539tCK=1250 540tCL=13750 --- 5 unchanged lines hidden (view full) --- 546tRP=13750 547tRRD=6000 548tRRD_L=0 549tRTP=7500 550tRTW=2500 551tWR=15000 552tWTR=7500 553tXAW=30000 | 541ranks_per_channel=2 542read_buffer_size=32 543static_backend_latency=10000 544static_frontend_latency=10000 545tBURST=5000 546tCCD_L=0 547tCK=1250 548tCL=13750 --- 5 unchanged lines hidden (view full) --- 554tRP=13750 555tRRD=6000 556tRRD_L=0 557tRTP=7500 558tRTW=2500 559tWR=15000 560tWTR=7500 561tXAW=30000 |
| 554tXP=0 | 562tXP=6000 |
| 555tXPDLL=0 | 563tXPDLL=0 |
| 556tXS=0 | 564tXS=270000 |
| 557tXSDLL=0 558write_buffer_size=64 559write_high_thresh_perc=85 560write_low_thresh_perc=50 561port=system.membus.master[1] 562 563[system.simple_disk] 564type=SimpleDisk --- 774 unchanged lines hidden --- | 565tXSDLL=0 566write_buffer_size=64 567write_high_thresh_perc=85 568write_low_thresh_perc=50 569port=system.membus.master[1] 570 571[system.simple_disk] 572type=SimpleDisk --- 774 unchanged lines hidden --- |