| config.ini (11440:76b5639162af) | config.ini (11570:4aac82f10951) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain |
| 18console=/dist/m5/system/binaries/console | 18console=/arm/projectscratch/randd/systems/dist/binaries/console 19default_p_state=UNDEFINED |
| 19eventq_index=0 20exit_on_work_items=false 21init_param=0 | 20eventq_index=0 21exit_on_work_items=false 22init_param=0 |
| 22kernel=/dist/m5/system/binaries/vmlinux | 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux |
| 23kernel_addr_check=true 24load_addr_mask=1099511627775 25load_offset=0 26mem_mode=timing 27mem_ranges=0:134217727 28memories=system.physmem 29mmap_using_noreserve=false 30multi_thread=false 31num_work_ids=16 | 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing 28mem_ranges=0:134217727 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 |
| 32pal=/dist/m5/system/binaries/ts_osfpal 33readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh | 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal 37power_model=Null 38readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh |
| 34symbolfile= 35system_rev=1024 36system_type=34 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.bridge] 49type=Bridge 50clk_domain=system.clk_domain | 39symbolfile= 40system_rev=1024 41system_type=34 42thermal_components= 43thermal_model=Null 44work_begin_ckpt_count=0 45work_begin_cpu_id_exit=-1 46work_begin_exit_count=0 47work_cpus_ckpt_count=0 48work_end_ckpt_count=0 49work_end_exit_count=0 50work_item_id=-1 51system_port=system.membus.slave[0] 52 53[system.bridge] 54type=Bridge 55clk_domain=system.clk_domain |
| 56default_p_state=UNDEFINED |
|
| 51delay=50000 52eventq_index=0 | 57delay=50000 58eventq_index=0 |
| 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null |
|
| 53ranges=8796093022208:18446744073709551615 54req_size=16 55resp_size=16 56master=system.iobus.slave[0] 57slave=system.membus.master[0] 58 59[system.clk_domain] 60type=SrcClockDomain --- 5 unchanged lines hidden (view full) --- 66 67[system.cpu] 68type=TimingSimpleCPU 69children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer 70branchPred=Null 71checker=Null 72clk_domain=system.cpu_clk_domain 73cpu_id=0 | 63ranges=8796093022208:18446744073709551615 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain --- 5 unchanged lines hidden (view full) --- 76 77[system.cpu] 78type=TimingSimpleCPU 79children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer 80branchPred=Null 81checker=Null 82clk_domain=system.cpu_clk_domain 83cpu_id=0 |
| 84default_p_state=UNDEFINED |
|
| 74do_checkpoint_insts=true 75do_quiesce=true 76do_statistics_insts=true 77dtb=system.cpu.dtb 78eventq_index=0 79function_trace=false 80function_trace_start=0 81interrupts=system.cpu.interrupts 82isa=system.cpu.isa 83itb=system.cpu.itb 84max_insts_all_threads=0 85max_insts_any_thread=0 86max_loads_all_threads=0 87max_loads_any_thread=0 88numThreads=1 | 85do_checkpoint_insts=true 86do_quiesce=true 87do_statistics_insts=true 88dtb=system.cpu.dtb 89eventq_index=0 90function_trace=false 91function_trace_start=0 92interrupts=system.cpu.interrupts 93isa=system.cpu.isa 94itb=system.cpu.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99numThreads=1 |
| 100p_state_clk_gate_bins=20 101p_state_clk_gate_max=1000000000000 102p_state_clk_gate_min=1000 103power_model=Null |
|
| 89profile=0 90progress_interval=0 91simpoint_start_insts= 92socket_id=0 93switched_out=false 94system=system 95tracer=system.cpu.tracer 96workload= 97dcache_port=system.cpu.dcache.cpu_side 98icache_port=system.cpu.icache.cpu_side 99 100[system.cpu.dcache] 101type=Cache 102children=tags 103addr_ranges=0:18446744073709551615 104assoc=4 105clk_domain=system.cpu_clk_domain 106clusivity=mostly_incl | 104profile=0 105progress_interval=0 106simpoint_start_insts= 107socket_id=0 108switched_out=false 109system=system 110tracer=system.cpu.tracer 111workload= 112dcache_port=system.cpu.dcache.cpu_side 113icache_port=system.cpu.icache.cpu_side 114 115[system.cpu.dcache] 116type=Cache 117children=tags 118addr_ranges=0:18446744073709551615 119assoc=4 120clk_domain=system.cpu_clk_domain 121clusivity=mostly_incl |
| 122default_p_state=UNDEFINED |
|
| 107demand_mshr_reserve=1 108eventq_index=0 109hit_latency=2 110is_read_only=false 111max_miss_count=0 112mshrs=4 | 123demand_mshr_reserve=1 124eventq_index=0 125hit_latency=2 126is_read_only=false 127max_miss_count=0 128mshrs=4 |
| 129p_state_clk_gate_bins=20 130p_state_clk_gate_max=1000000000000 131p_state_clk_gate_min=1000 132power_model=Null |
|
| 113prefetch_on_access=false 114prefetcher=Null 115response_latency=2 116sequential_access=false 117size=32768 118system=system 119tags=system.cpu.dcache.tags 120tgts_per_mshr=20 121write_buffers=8 122writeback_clean=false 123cpu_side=system.cpu.dcache_port 124mem_side=system.cpu.toL2Bus.slave[1] 125 126[system.cpu.dcache.tags] 127type=LRU 128assoc=4 129block_size=64 130clk_domain=system.cpu_clk_domain | 133prefetch_on_access=false 134prefetcher=Null 135response_latency=2 136sequential_access=false 137size=32768 138system=system 139tags=system.cpu.dcache.tags 140tgts_per_mshr=20 141write_buffers=8 142writeback_clean=false 143cpu_side=system.cpu.dcache_port 144mem_side=system.cpu.toL2Bus.slave[1] 145 146[system.cpu.dcache.tags] 147type=LRU 148assoc=4 149block_size=64 150clk_domain=system.cpu_clk_domain |
| 151default_p_state=UNDEFINED |
|
| 131eventq_index=0 132hit_latency=2 | 152eventq_index=0 153hit_latency=2 |
| 154p_state_clk_gate_bins=20 155p_state_clk_gate_max=1000000000000 156p_state_clk_gate_min=1000 157power_model=Null |
|
| 133sequential_access=false 134size=32768 135 136[system.cpu.dtb] 137type=AlphaTLB 138eventq_index=0 139size=64 140 141[system.cpu.icache] 142type=Cache 143children=tags 144addr_ranges=0:18446744073709551615 145assoc=1 146clk_domain=system.cpu_clk_domain 147clusivity=mostly_incl | 158sequential_access=false 159size=32768 160 161[system.cpu.dtb] 162type=AlphaTLB 163eventq_index=0 164size=64 165 166[system.cpu.icache] 167type=Cache 168children=tags 169addr_ranges=0:18446744073709551615 170assoc=1 171clk_domain=system.cpu_clk_domain 172clusivity=mostly_incl |
| 173default_p_state=UNDEFINED |
|
| 148demand_mshr_reserve=1 149eventq_index=0 150hit_latency=2 151is_read_only=true 152max_miss_count=0 153mshrs=4 | 174demand_mshr_reserve=1 175eventq_index=0 176hit_latency=2 177is_read_only=true 178max_miss_count=0 179mshrs=4 |
| 180p_state_clk_gate_bins=20 181p_state_clk_gate_max=1000000000000 182p_state_clk_gate_min=1000 183power_model=Null |
|
| 154prefetch_on_access=false 155prefetcher=Null 156response_latency=2 157sequential_access=false 158size=32768 159system=system 160tags=system.cpu.icache.tags 161tgts_per_mshr=20 162write_buffers=8 163writeback_clean=true 164cpu_side=system.cpu.icache_port 165mem_side=system.cpu.toL2Bus.slave[0] 166 167[system.cpu.icache.tags] 168type=LRU 169assoc=1 170block_size=64 171clk_domain=system.cpu_clk_domain | 184prefetch_on_access=false 185prefetcher=Null 186response_latency=2 187sequential_access=false 188size=32768 189system=system 190tags=system.cpu.icache.tags 191tgts_per_mshr=20 192write_buffers=8 193writeback_clean=true 194cpu_side=system.cpu.icache_port 195mem_side=system.cpu.toL2Bus.slave[0] 196 197[system.cpu.icache.tags] 198type=LRU 199assoc=1 200block_size=64 201clk_domain=system.cpu_clk_domain |
| 202default_p_state=UNDEFINED |
|
| 172eventq_index=0 173hit_latency=2 | 203eventq_index=0 204hit_latency=2 |
| 205p_state_clk_gate_bins=20 206p_state_clk_gate_max=1000000000000 207p_state_clk_gate_min=1000 208power_model=Null |
|
| 174sequential_access=false 175size=32768 176 177[system.cpu.interrupts] 178type=AlphaInterrupts 179eventq_index=0 180 181[system.cpu.isa] --- 8 unchanged lines hidden (view full) --- 190 191[system.cpu.l2cache] 192type=Cache 193children=tags 194addr_ranges=0:18446744073709551615 195assoc=8 196clk_domain=system.cpu_clk_domain 197clusivity=mostly_incl | 209sequential_access=false 210size=32768 211 212[system.cpu.interrupts] 213type=AlphaInterrupts 214eventq_index=0 215 216[system.cpu.isa] --- 8 unchanged lines hidden (view full) --- 225 226[system.cpu.l2cache] 227type=Cache 228children=tags 229addr_ranges=0:18446744073709551615 230assoc=8 231clk_domain=system.cpu_clk_domain 232clusivity=mostly_incl |
| 233default_p_state=UNDEFINED |
|
| 198demand_mshr_reserve=1 199eventq_index=0 200hit_latency=20 201is_read_only=false 202max_miss_count=0 203mshrs=20 | 234demand_mshr_reserve=1 235eventq_index=0 236hit_latency=20 237is_read_only=false 238max_miss_count=0 239mshrs=20 |
| 240p_state_clk_gate_bins=20 241p_state_clk_gate_max=1000000000000 242p_state_clk_gate_min=1000 243power_model=Null |
|
| 204prefetch_on_access=false 205prefetcher=Null 206response_latency=20 207sequential_access=false 208size=4194304 209system=system 210tags=system.cpu.l2cache.tags 211tgts_per_mshr=12 212write_buffers=8 213writeback_clean=false 214cpu_side=system.cpu.toL2Bus.master[0] 215mem_side=system.membus.slave[1] 216 217[system.cpu.l2cache.tags] 218type=LRU 219assoc=8 220block_size=64 221clk_domain=system.cpu_clk_domain | 244prefetch_on_access=false 245prefetcher=Null 246response_latency=20 247sequential_access=false 248size=4194304 249system=system 250tags=system.cpu.l2cache.tags 251tgts_per_mshr=12 252write_buffers=8 253writeback_clean=false 254cpu_side=system.cpu.toL2Bus.master[0] 255mem_side=system.membus.slave[1] 256 257[system.cpu.l2cache.tags] 258type=LRU 259assoc=8 260block_size=64 261clk_domain=system.cpu_clk_domain |
| 262default_p_state=UNDEFINED |
|
| 222eventq_index=0 223hit_latency=20 | 263eventq_index=0 264hit_latency=20 |
| 265p_state_clk_gate_bins=20 266p_state_clk_gate_max=1000000000000 267p_state_clk_gate_min=1000 268power_model=Null |
|
| 224sequential_access=false 225size=4194304 226 227[system.cpu.toL2Bus] 228type=CoherentXBar 229children=snoop_filter 230clk_domain=system.cpu_clk_domain | 269sequential_access=false 270size=4194304 271 272[system.cpu.toL2Bus] 273type=CoherentXBar 274children=snoop_filter 275clk_domain=system.cpu_clk_domain |
| 276default_p_state=UNDEFINED |
|
| 231eventq_index=0 232forward_latency=0 233frontend_latency=1 | 277eventq_index=0 278forward_latency=0 279frontend_latency=1 |
| 280p_state_clk_gate_bins=20 281p_state_clk_gate_max=1000000000000 282p_state_clk_gate_min=1000 |
|
| 234point_of_coherency=false | 283point_of_coherency=false |
| 284power_model=Null |
|
| 235response_latency=1 236snoop_filter=system.cpu.toL2Bus.snoop_filter 237snoop_response_latency=1 238system=system 239use_default_range=false 240width=32 241master=system.cpu.l2cache.cpu_side 242slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 32 unchanged lines hidden (view full) --- 275eventq_index=0 276image_file= 277read_only=false 278table_size=65536 279 280[system.disk0.image.child] 281type=RawDiskImage 282eventq_index=0 | 285response_latency=1 286snoop_filter=system.cpu.toL2Bus.snoop_filter 287snoop_response_latency=1 288system=system 289use_default_range=false 290width=32 291master=system.cpu.l2cache.cpu_side 292slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 32 unchanged lines hidden (view full) --- 325eventq_index=0 326image_file= 327read_only=false 328table_size=65536 329 330[system.disk0.image.child] 331type=RawDiskImage 332eventq_index=0 |
| 283image_file=/dist/m5/system/disks/linux-latest.img | 333image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img |
| 284read_only=true 285 286[system.disk2] 287type=IdeDisk 288children=image 289delay=1000000 290driveID=master 291eventq_index=0 --- 6 unchanged lines hidden (view full) --- 298eventq_index=0 299image_file= 300read_only=false 301table_size=65536 302 303[system.disk2.image.child] 304type=RawDiskImage 305eventq_index=0 | 334read_only=true 335 336[system.disk2] 337type=IdeDisk 338children=image 339delay=1000000 340driveID=master 341eventq_index=0 --- 6 unchanged lines hidden (view full) --- 348eventq_index=0 349image_file= 350read_only=false 351table_size=65536 352 353[system.disk2.image.child] 354type=RawDiskImage 355eventq_index=0 |
| 306image_file=/dist/m5/system/disks/linux-bigswap2.img | 356image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img |
| 307read_only=true 308 309[system.dvfs_handler] 310type=DVFSHandler 311domains= 312enable=false 313eventq_index=0 314sys_clk_domain=system.clk_domain 315transition_latency=100000000 316 317[system.intrctrl] 318type=IntrControl 319eventq_index=0 320sys=system 321 322[system.iobus] 323type=NoncoherentXBar 324clk_domain=system.clk_domain | 357read_only=true 358 359[system.dvfs_handler] 360type=DVFSHandler 361domains= 362enable=false 363eventq_index=0 364sys_clk_domain=system.clk_domain 365transition_latency=100000000 366 367[system.intrctrl] 368type=IntrControl 369eventq_index=0 370sys=system 371 372[system.iobus] 373type=NoncoherentXBar 374clk_domain=system.clk_domain |
| 375default_p_state=UNDEFINED |
|
| 325eventq_index=0 326forward_latency=1 327frontend_latency=2 | 376eventq_index=0 377forward_latency=1 378frontend_latency=2 |
| 379p_state_clk_gate_bins=20 380p_state_clk_gate_max=1000000000000 381p_state_clk_gate_min=1000 382power_model=Null |
|
| 328response_latency=2 329use_default_range=false 330width=16 331master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 332slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 333 334[system.iocache] 335type=Cache 336children=tags 337addr_ranges=0:134217727 338assoc=8 339clk_domain=system.clk_domain 340clusivity=mostly_incl | 383response_latency=2 384use_default_range=false 385width=16 386master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 387slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 388 389[system.iocache] 390type=Cache 391children=tags 392addr_ranges=0:134217727 393assoc=8 394clk_domain=system.clk_domain 395clusivity=mostly_incl |
| 396default_p_state=UNDEFINED |
|
| 341demand_mshr_reserve=1 342eventq_index=0 343hit_latency=50 344is_read_only=false 345max_miss_count=0 346mshrs=20 | 397demand_mshr_reserve=1 398eventq_index=0 399hit_latency=50 400is_read_only=false 401max_miss_count=0 402mshrs=20 |
| 403p_state_clk_gate_bins=20 404p_state_clk_gate_max=1000000000000 405p_state_clk_gate_min=1000 406power_model=Null |
|
| 347prefetch_on_access=false 348prefetcher=Null 349response_latency=50 350sequential_access=false 351size=1024 352system=system 353tags=system.iocache.tags 354tgts_per_mshr=12 355write_buffers=8 356writeback_clean=false 357cpu_side=system.iobus.master[27] 358mem_side=system.membus.slave[2] 359 360[system.iocache.tags] 361type=LRU 362assoc=8 363block_size=64 364clk_domain=system.clk_domain | 407prefetch_on_access=false 408prefetcher=Null 409response_latency=50 410sequential_access=false 411size=1024 412system=system 413tags=system.iocache.tags 414tgts_per_mshr=12 415write_buffers=8 416writeback_clean=false 417cpu_side=system.iobus.master[27] 418mem_side=system.membus.slave[2] 419 420[system.iocache.tags] 421type=LRU 422assoc=8 423block_size=64 424clk_domain=system.clk_domain |
| 425default_p_state=UNDEFINED |
|
| 365eventq_index=0 366hit_latency=50 | 426eventq_index=0 427hit_latency=50 |
| 428p_state_clk_gate_bins=20 429p_state_clk_gate_max=1000000000000 430p_state_clk_gate_min=1000 431power_model=Null |
|
| 367sequential_access=false 368size=1024 369 370[system.membus] 371type=CoherentXBar 372children=badaddr_responder 373clk_domain=system.clk_domain | 432sequential_access=false 433size=1024 434 435[system.membus] 436type=CoherentXBar 437children=badaddr_responder 438clk_domain=system.clk_domain |
| 439default_p_state=UNDEFINED |
|
| 374eventq_index=0 375forward_latency=4 376frontend_latency=3 | 440eventq_index=0 441forward_latency=4 442frontend_latency=3 |
| 443p_state_clk_gate_bins=20 444p_state_clk_gate_max=1000000000000 445p_state_clk_gate_min=1000 |
|
| 377point_of_coherency=true | 446point_of_coherency=true |
| 447power_model=Null |
|
| 378response_latency=2 379snoop_filter=Null 380snoop_response_latency=4 381system=system 382use_default_range=false 383width=16 384default=system.membus.badaddr_responder.pio 385master=system.bridge.slave system.physmem.port 386slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 387 388[system.membus.badaddr_responder] 389type=IsaFake 390clk_domain=system.clk_domain | 448response_latency=2 449snoop_filter=Null 450snoop_response_latency=4 451system=system 452use_default_range=false 453width=16 454default=system.membus.badaddr_responder.pio 455master=system.bridge.slave system.physmem.port 456slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 457 458[system.membus.badaddr_responder] 459type=IsaFake 460clk_domain=system.clk_domain |
| 461default_p_state=UNDEFINED |
|
| 391eventq_index=0 392fake_mem=false | 462eventq_index=0 463fake_mem=false |
| 464p_state_clk_gate_bins=20 465p_state_clk_gate_max=1000000000000 466p_state_clk_gate_min=1000 |
|
| 393pio_addr=0 394pio_latency=100000 395pio_size=8 | 467pio_addr=0 468pio_latency=100000 469pio_size=8 |
| 470power_model=Null |
|
| 396ret_bad_addr=true 397ret_data16=65535 398ret_data32=4294967295 399ret_data64=18446744073709551615 400ret_data8=255 401system=system 402update_data=false 403warn_access= --- 28 unchanged lines hidden (view full) --- 432activation_limit=4 433addr_mapping=RoRaBaCoCh 434bank_groups_per_rank=0 435banks_per_rank=8 436burst_length=8 437channels=1 438clk_domain=system.clk_domain 439conf_table_reported=true | 471ret_bad_addr=true 472ret_data16=65535 473ret_data32=4294967295 474ret_data64=18446744073709551615 475ret_data8=255 476system=system 477update_data=false 478warn_access= --- 28 unchanged lines hidden (view full) --- 507activation_limit=4 508addr_mapping=RoRaBaCoCh 509bank_groups_per_rank=0 510banks_per_rank=8 511burst_length=8 512channels=1 513clk_domain=system.clk_domain 514conf_table_reported=true |
| 515default_p_state=UNDEFINED |
|
| 440device_bus_width=8 441device_rowbuffer_size=1024 442device_size=536870912 443devices_per_rank=8 444dll=true 445eventq_index=0 446in_addr_map=true 447max_accesses_per_row=16 448mem_sched_policy=frfcfs 449min_writes_per_switch=16 450null=false | 516device_bus_width=8 517device_rowbuffer_size=1024 518device_size=536870912 519devices_per_rank=8 520dll=true 521eventq_index=0 522in_addr_map=true 523max_accesses_per_row=16 524mem_sched_policy=frfcfs 525min_writes_per_switch=16 526null=false |
| 527p_state_clk_gate_bins=20 528p_state_clk_gate_max=1000000000000 529p_state_clk_gate_min=1000 |
|
| 451page_policy=open_adaptive | 530page_policy=open_adaptive |
| 531power_model=Null |
|
| 452range=0:134217727 453ranks_per_channel=2 454read_buffer_size=32 455static_backend_latency=10000 456static_frontend_latency=10000 457tBURST=5000 458tCCD_L=0 459tCK=1250 --- 25 unchanged lines hidden (view full) --- 485children=disk 486disk=system.simple_disk.disk 487eventq_index=0 488system=system 489 490[system.simple_disk.disk] 491type=RawDiskImage 492eventq_index=0 | 532range=0:134217727 533ranks_per_channel=2 534read_buffer_size=32 535static_backend_latency=10000 536static_frontend_latency=10000 537tBURST=5000 538tCCD_L=0 539tCK=1250 --- 25 unchanged lines hidden (view full) --- 565children=disk 566disk=system.simple_disk.disk 567eventq_index=0 568system=system 569 570[system.simple_disk.disk] 571type=RawDiskImage 572eventq_index=0 |
| 493image_file=/dist/m5/system/disks/linux-latest.img | 573image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img |
| 494read_only=true 495 496[system.terminal] 497type=Terminal 498eventq_index=0 499intr_control=system.intrctrl 500number=0 501output=true --- 5 unchanged lines hidden (view full) --- 507eventq_index=0 508intrctrl=system.intrctrl 509system=system 510 511[system.tsunami.backdoor] 512type=AlphaBackdoor 513clk_domain=system.clk_domain 514cpu=system.cpu | 574read_only=true 575 576[system.terminal] 577type=Terminal 578eventq_index=0 579intr_control=system.intrctrl 580number=0 581output=true --- 5 unchanged lines hidden (view full) --- 587eventq_index=0 588intrctrl=system.intrctrl 589system=system 590 591[system.tsunami.backdoor] 592type=AlphaBackdoor 593clk_domain=system.clk_domain 594cpu=system.cpu |
| 595default_p_state=UNDEFINED |
|
| 515disk=system.simple_disk 516eventq_index=0 | 596disk=system.simple_disk 597eventq_index=0 |
| 598p_state_clk_gate_bins=20 599p_state_clk_gate_max=1000000000000 600p_state_clk_gate_min=1000 |
|
| 517pio_addr=8804682956800 518pio_latency=100000 519platform=system.tsunami | 601pio_addr=8804682956800 602pio_latency=100000 603platform=system.tsunami |
| 604power_model=Null |
|
| 520system=system 521terminal=system.terminal 522pio=system.iobus.master[24] 523 524[system.tsunami.cchip] 525type=TsunamiCChip 526clk_domain=system.clk_domain | 605system=system 606terminal=system.terminal 607pio=system.iobus.master[24] 608 609[system.tsunami.cchip] 610type=TsunamiCChip 611clk_domain=system.clk_domain |
| 612default_p_state=UNDEFINED |
|
| 527eventq_index=0 | 613eventq_index=0 |
| 614p_state_clk_gate_bins=20 615p_state_clk_gate_max=1000000000000 616p_state_clk_gate_min=1000 |
|
| 528pio_addr=8803072344064 529pio_latency=100000 | 617pio_addr=8803072344064 618pio_latency=100000 |
| 619power_model=Null |
|
| 530system=system 531tsunami=system.tsunami 532pio=system.iobus.master[0] 533 534[system.tsunami.ethernet] 535type=NSGigE 536BAR0=1 537BAR0LegacyIO=false --- 64 unchanged lines hidden (view full) --- 602Revision=0 603Status=656 604SubClassCode=0 605SubsystemID=0 606SubsystemVendorID=0 607VendorID=4107 608clk_domain=system.clk_domain 609config_latency=20000 | 620system=system 621tsunami=system.tsunami 622pio=system.iobus.master[0] 623 624[system.tsunami.ethernet] 625type=NSGigE 626BAR0=1 627BAR0LegacyIO=false --- 64 unchanged lines hidden (view full) --- 692Revision=0 693Status=656 694SubClassCode=0 695SubsystemID=0 696SubsystemVendorID=0 697VendorID=4107 698clk_domain=system.clk_domain 699config_latency=20000 |
| 700default_p_state=UNDEFINED |
|
| 610dma_data_free=false 611dma_desc_free=false 612dma_no_allocate=true 613dma_read_delay=0 614dma_read_factor=0 615dma_write_delay=0 616dma_write_factor=0 617eventq_index=0 618hardware_address=00:90:00:00:00:01 619host=system.tsunami.pchip 620intr_delay=10000000 | 701dma_data_free=false 702dma_desc_free=false 703dma_no_allocate=true 704dma_read_delay=0 705dma_read_factor=0 706dma_write_delay=0 707dma_write_factor=0 708eventq_index=0 709hardware_address=00:90:00:00:00:01 710host=system.tsunami.pchip 711intr_delay=10000000 |
| 712p_state_clk_gate_bins=20 713p_state_clk_gate_max=1000000000000 714p_state_clk_gate_min=1000 |
|
| 621pci_bus=0 622pci_dev=1 623pci_func=0 624pio_latency=30000 | 715pci_bus=0 716pci_dev=1 717pci_func=0 718pio_latency=30000 |
| 719power_model=Null |
|
| 625rss=false 626rx_delay=1000000 627rx_fifo_size=524288 628rx_filter=true 629rx_thread=false 630system=system 631tx_delay=1000000 632tx_fifo_size=524288 633tx_thread=false 634dma=system.iobus.slave[2] 635pio=system.iobus.master[26] 636 637[system.tsunami.fake_OROM] 638type=IsaFake 639clk_domain=system.clk_domain | 720rss=false 721rx_delay=1000000 722rx_fifo_size=524288 723rx_filter=true 724rx_thread=false 725system=system 726tx_delay=1000000 727tx_fifo_size=524288 728tx_thread=false 729dma=system.iobus.slave[2] 730pio=system.iobus.master[26] 731 732[system.tsunami.fake_OROM] 733type=IsaFake 734clk_domain=system.clk_domain |
| 735default_p_state=UNDEFINED |
|
| 640eventq_index=0 641fake_mem=false | 736eventq_index=0 737fake_mem=false |
| 738p_state_clk_gate_bins=20 739p_state_clk_gate_max=1000000000000 740p_state_clk_gate_min=1000 |
|
| 642pio_addr=8796093677568 643pio_latency=100000 644pio_size=393216 | 741pio_addr=8796093677568 742pio_latency=100000 743pio_size=393216 |
| 744power_model=Null |
|
| 645ret_bad_addr=false 646ret_data16=65535 647ret_data32=4294967295 648ret_data64=18446744073709551615 649ret_data8=255 650system=system 651update_data=false 652warn_access= 653pio=system.iobus.master[8] 654 655[system.tsunami.fake_ata0] 656type=IsaFake 657clk_domain=system.clk_domain | 745ret_bad_addr=false 746ret_data16=65535 747ret_data32=4294967295 748ret_data64=18446744073709551615 749ret_data8=255 750system=system 751update_data=false 752warn_access= 753pio=system.iobus.master[8] 754 755[system.tsunami.fake_ata0] 756type=IsaFake 757clk_domain=system.clk_domain |
| 758default_p_state=UNDEFINED |
|
| 658eventq_index=0 659fake_mem=false | 759eventq_index=0 760fake_mem=false |
| 761p_state_clk_gate_bins=20 762p_state_clk_gate_max=1000000000000 763p_state_clk_gate_min=1000 |
|
| 660pio_addr=8804615848432 661pio_latency=100000 662pio_size=8 | 764pio_addr=8804615848432 765pio_latency=100000 766pio_size=8 |
| 767power_model=Null |
|
| 663ret_bad_addr=false 664ret_data16=65535 665ret_data32=4294967295 666ret_data64=18446744073709551615 667ret_data8=255 668system=system 669update_data=false 670warn_access= 671pio=system.iobus.master[19] 672 673[system.tsunami.fake_ata1] 674type=IsaFake 675clk_domain=system.clk_domain | 768ret_bad_addr=false 769ret_data16=65535 770ret_data32=4294967295 771ret_data64=18446744073709551615 772ret_data8=255 773system=system 774update_data=false 775warn_access= 776pio=system.iobus.master[19] 777 778[system.tsunami.fake_ata1] 779type=IsaFake 780clk_domain=system.clk_domain |
| 781default_p_state=UNDEFINED |
|
| 676eventq_index=0 677fake_mem=false | 782eventq_index=0 783fake_mem=false |
| 784p_state_clk_gate_bins=20 785p_state_clk_gate_max=1000000000000 786p_state_clk_gate_min=1000 |
|
| 678pio_addr=8804615848304 679pio_latency=100000 680pio_size=8 | 787pio_addr=8804615848304 788pio_latency=100000 789pio_size=8 |
| 790power_model=Null |
|
| 681ret_bad_addr=false 682ret_data16=65535 683ret_data32=4294967295 684ret_data64=18446744073709551615 685ret_data8=255 686system=system 687update_data=false 688warn_access= 689pio=system.iobus.master[20] 690 691[system.tsunami.fake_pnp_addr] 692type=IsaFake 693clk_domain=system.clk_domain | 791ret_bad_addr=false 792ret_data16=65535 793ret_data32=4294967295 794ret_data64=18446744073709551615 795ret_data8=255 796system=system 797update_data=false 798warn_access= 799pio=system.iobus.master[20] 800 801[system.tsunami.fake_pnp_addr] 802type=IsaFake 803clk_domain=system.clk_domain |
| 804default_p_state=UNDEFINED |
|
| 694eventq_index=0 695fake_mem=false | 805eventq_index=0 806fake_mem=false |
| 807p_state_clk_gate_bins=20 808p_state_clk_gate_max=1000000000000 809p_state_clk_gate_min=1000 |
|
| 696pio_addr=8804615848569 697pio_latency=100000 698pio_size=8 | 810pio_addr=8804615848569 811pio_latency=100000 812pio_size=8 |
| 813power_model=Null |
|
| 699ret_bad_addr=false 700ret_data16=65535 701ret_data32=4294967295 702ret_data64=18446744073709551615 703ret_data8=255 704system=system 705update_data=false 706warn_access= 707pio=system.iobus.master[9] 708 709[system.tsunami.fake_pnp_read0] 710type=IsaFake 711clk_domain=system.clk_domain | 814ret_bad_addr=false 815ret_data16=65535 816ret_data32=4294967295 817ret_data64=18446744073709551615 818ret_data8=255 819system=system 820update_data=false 821warn_access= 822pio=system.iobus.master[9] 823 824[system.tsunami.fake_pnp_read0] 825type=IsaFake 826clk_domain=system.clk_domain |
| 827default_p_state=UNDEFINED |
|
| 712eventq_index=0 713fake_mem=false | 828eventq_index=0 829fake_mem=false |
| 830p_state_clk_gate_bins=20 831p_state_clk_gate_max=1000000000000 832p_state_clk_gate_min=1000 |
|
| 714pio_addr=8804615848451 715pio_latency=100000 716pio_size=8 | 833pio_addr=8804615848451 834pio_latency=100000 835pio_size=8 |
| 836power_model=Null |
|
| 717ret_bad_addr=false 718ret_data16=65535 719ret_data32=4294967295 720ret_data64=18446744073709551615 721ret_data8=255 722system=system 723update_data=false 724warn_access= 725pio=system.iobus.master[11] 726 727[system.tsunami.fake_pnp_read1] 728type=IsaFake 729clk_domain=system.clk_domain | 837ret_bad_addr=false 838ret_data16=65535 839ret_data32=4294967295 840ret_data64=18446744073709551615 841ret_data8=255 842system=system 843update_data=false 844warn_access= 845pio=system.iobus.master[11] 846 847[system.tsunami.fake_pnp_read1] 848type=IsaFake 849clk_domain=system.clk_domain |
| 850default_p_state=UNDEFINED |
|
| 730eventq_index=0 731fake_mem=false | 851eventq_index=0 852fake_mem=false |
| 853p_state_clk_gate_bins=20 854p_state_clk_gate_max=1000000000000 855p_state_clk_gate_min=1000 |
|
| 732pio_addr=8804615848515 733pio_latency=100000 734pio_size=8 | 856pio_addr=8804615848515 857pio_latency=100000 858pio_size=8 |
| 859power_model=Null |
|
| 735ret_bad_addr=false 736ret_data16=65535 737ret_data32=4294967295 738ret_data64=18446744073709551615 739ret_data8=255 740system=system 741update_data=false 742warn_access= 743pio=system.iobus.master[12] 744 745[system.tsunami.fake_pnp_read2] 746type=IsaFake 747clk_domain=system.clk_domain | 860ret_bad_addr=false 861ret_data16=65535 862ret_data32=4294967295 863ret_data64=18446744073709551615 864ret_data8=255 865system=system 866update_data=false 867warn_access= 868pio=system.iobus.master[12] 869 870[system.tsunami.fake_pnp_read2] 871type=IsaFake 872clk_domain=system.clk_domain |
| 873default_p_state=UNDEFINED |
|
| 748eventq_index=0 749fake_mem=false | 874eventq_index=0 875fake_mem=false |
| 876p_state_clk_gate_bins=20 877p_state_clk_gate_max=1000000000000 878p_state_clk_gate_min=1000 |
|
| 750pio_addr=8804615848579 751pio_latency=100000 752pio_size=8 | 879pio_addr=8804615848579 880pio_latency=100000 881pio_size=8 |
| 882power_model=Null |
|
| 753ret_bad_addr=false 754ret_data16=65535 755ret_data32=4294967295 756ret_data64=18446744073709551615 757ret_data8=255 758system=system 759update_data=false 760warn_access= 761pio=system.iobus.master[13] 762 763[system.tsunami.fake_pnp_read3] 764type=IsaFake 765clk_domain=system.clk_domain | 883ret_bad_addr=false 884ret_data16=65535 885ret_data32=4294967295 886ret_data64=18446744073709551615 887ret_data8=255 888system=system 889update_data=false 890warn_access= 891pio=system.iobus.master[13] 892 893[system.tsunami.fake_pnp_read3] 894type=IsaFake 895clk_domain=system.clk_domain |
| 896default_p_state=UNDEFINED |
|
| 766eventq_index=0 767fake_mem=false | 897eventq_index=0 898fake_mem=false |
| 899p_state_clk_gate_bins=20 900p_state_clk_gate_max=1000000000000 901p_state_clk_gate_min=1000 |
|
| 768pio_addr=8804615848643 769pio_latency=100000 770pio_size=8 | 902pio_addr=8804615848643 903pio_latency=100000 904pio_size=8 |
| 905power_model=Null |
|
| 771ret_bad_addr=false 772ret_data16=65535 773ret_data32=4294967295 774ret_data64=18446744073709551615 775ret_data8=255 776system=system 777update_data=false 778warn_access= 779pio=system.iobus.master[14] 780 781[system.tsunami.fake_pnp_read4] 782type=IsaFake 783clk_domain=system.clk_domain | 906ret_bad_addr=false 907ret_data16=65535 908ret_data32=4294967295 909ret_data64=18446744073709551615 910ret_data8=255 911system=system 912update_data=false 913warn_access= 914pio=system.iobus.master[14] 915 916[system.tsunami.fake_pnp_read4] 917type=IsaFake 918clk_domain=system.clk_domain |
| 919default_p_state=UNDEFINED |
|
| 784eventq_index=0 785fake_mem=false | 920eventq_index=0 921fake_mem=false |
| 922p_state_clk_gate_bins=20 923p_state_clk_gate_max=1000000000000 924p_state_clk_gate_min=1000 |
|
| 786pio_addr=8804615848707 787pio_latency=100000 788pio_size=8 | 925pio_addr=8804615848707 926pio_latency=100000 927pio_size=8 |
| 928power_model=Null |
|
| 789ret_bad_addr=false 790ret_data16=65535 791ret_data32=4294967295 792ret_data64=18446744073709551615 793ret_data8=255 794system=system 795update_data=false 796warn_access= 797pio=system.iobus.master[15] 798 799[system.tsunami.fake_pnp_read5] 800type=IsaFake 801clk_domain=system.clk_domain | 929ret_bad_addr=false 930ret_data16=65535 931ret_data32=4294967295 932ret_data64=18446744073709551615 933ret_data8=255 934system=system 935update_data=false 936warn_access= 937pio=system.iobus.master[15] 938 939[system.tsunami.fake_pnp_read5] 940type=IsaFake 941clk_domain=system.clk_domain |
| 942default_p_state=UNDEFINED |
|
| 802eventq_index=0 803fake_mem=false | 943eventq_index=0 944fake_mem=false |
| 945p_state_clk_gate_bins=20 946p_state_clk_gate_max=1000000000000 947p_state_clk_gate_min=1000 |
|
| 804pio_addr=8804615848771 805pio_latency=100000 806pio_size=8 | 948pio_addr=8804615848771 949pio_latency=100000 950pio_size=8 |
| 951power_model=Null |
|
| 807ret_bad_addr=false 808ret_data16=65535 809ret_data32=4294967295 810ret_data64=18446744073709551615 811ret_data8=255 812system=system 813update_data=false 814warn_access= 815pio=system.iobus.master[16] 816 817[system.tsunami.fake_pnp_read6] 818type=IsaFake 819clk_domain=system.clk_domain | 952ret_bad_addr=false 953ret_data16=65535 954ret_data32=4294967295 955ret_data64=18446744073709551615 956ret_data8=255 957system=system 958update_data=false 959warn_access= 960pio=system.iobus.master[16] 961 962[system.tsunami.fake_pnp_read6] 963type=IsaFake 964clk_domain=system.clk_domain |
| 965default_p_state=UNDEFINED |
|
| 820eventq_index=0 821fake_mem=false | 966eventq_index=0 967fake_mem=false |
| 968p_state_clk_gate_bins=20 969p_state_clk_gate_max=1000000000000 970p_state_clk_gate_min=1000 |
|
| 822pio_addr=8804615848835 823pio_latency=100000 824pio_size=8 | 971pio_addr=8804615848835 972pio_latency=100000 973pio_size=8 |
| 974power_model=Null |
|
| 825ret_bad_addr=false 826ret_data16=65535 827ret_data32=4294967295 828ret_data64=18446744073709551615 829ret_data8=255 830system=system 831update_data=false 832warn_access= 833pio=system.iobus.master[17] 834 835[system.tsunami.fake_pnp_read7] 836type=IsaFake 837clk_domain=system.clk_domain | 975ret_bad_addr=false 976ret_data16=65535 977ret_data32=4294967295 978ret_data64=18446744073709551615 979ret_data8=255 980system=system 981update_data=false 982warn_access= 983pio=system.iobus.master[17] 984 985[system.tsunami.fake_pnp_read7] 986type=IsaFake 987clk_domain=system.clk_domain |
| 988default_p_state=UNDEFINED |
|
| 838eventq_index=0 839fake_mem=false | 989eventq_index=0 990fake_mem=false |
| 991p_state_clk_gate_bins=20 992p_state_clk_gate_max=1000000000000 993p_state_clk_gate_min=1000 |
|
| 840pio_addr=8804615848899 841pio_latency=100000 842pio_size=8 | 994pio_addr=8804615848899 995pio_latency=100000 996pio_size=8 |
| 997power_model=Null |
|
| 843ret_bad_addr=false 844ret_data16=65535 845ret_data32=4294967295 846ret_data64=18446744073709551615 847ret_data8=255 848system=system 849update_data=false 850warn_access= 851pio=system.iobus.master[18] 852 853[system.tsunami.fake_pnp_write] 854type=IsaFake 855clk_domain=system.clk_domain | 998ret_bad_addr=false 999ret_data16=65535 1000ret_data32=4294967295 1001ret_data64=18446744073709551615 1002ret_data8=255 1003system=system 1004update_data=false 1005warn_access= 1006pio=system.iobus.master[18] 1007 1008[system.tsunami.fake_pnp_write] 1009type=IsaFake 1010clk_domain=system.clk_domain |
| 1011default_p_state=UNDEFINED |
|
| 856eventq_index=0 857fake_mem=false | 1012eventq_index=0 1013fake_mem=false |
| 1014p_state_clk_gate_bins=20 1015p_state_clk_gate_max=1000000000000 1016p_state_clk_gate_min=1000 |
|
| 858pio_addr=8804615850617 859pio_latency=100000 860pio_size=8 | 1017pio_addr=8804615850617 1018pio_latency=100000 1019pio_size=8 |
| 1020power_model=Null |
|
| 861ret_bad_addr=false 862ret_data16=65535 863ret_data32=4294967295 864ret_data64=18446744073709551615 865ret_data8=255 866system=system 867update_data=false 868warn_access= 869pio=system.iobus.master[10] 870 871[system.tsunami.fake_ppc] 872type=IsaFake 873clk_domain=system.clk_domain | 1021ret_bad_addr=false 1022ret_data16=65535 1023ret_data32=4294967295 1024ret_data64=18446744073709551615 1025ret_data8=255 1026system=system 1027update_data=false 1028warn_access= 1029pio=system.iobus.master[10] 1030 1031[system.tsunami.fake_ppc] 1032type=IsaFake 1033clk_domain=system.clk_domain |
| 1034default_p_state=UNDEFINED |
|
| 874eventq_index=0 875fake_mem=false | 1035eventq_index=0 1036fake_mem=false |
| 1037p_state_clk_gate_bins=20 1038p_state_clk_gate_max=1000000000000 1039p_state_clk_gate_min=1000 |
|
| 876pio_addr=8804615848891 877pio_latency=100000 878pio_size=8 | 1040pio_addr=8804615848891 1041pio_latency=100000 1042pio_size=8 |
| 1043power_model=Null |
|
| 879ret_bad_addr=false 880ret_data16=65535 881ret_data32=4294967295 882ret_data64=18446744073709551615 883ret_data8=255 884system=system 885update_data=false 886warn_access= 887pio=system.iobus.master[7] 888 889[system.tsunami.fake_sm_chip] 890type=IsaFake 891clk_domain=system.clk_domain | 1044ret_bad_addr=false 1045ret_data16=65535 1046ret_data32=4294967295 1047ret_data64=18446744073709551615 1048ret_data8=255 1049system=system 1050update_data=false 1051warn_access= 1052pio=system.iobus.master[7] 1053 1054[system.tsunami.fake_sm_chip] 1055type=IsaFake 1056clk_domain=system.clk_domain |
| 1057default_p_state=UNDEFINED |
|
| 892eventq_index=0 893fake_mem=false | 1058eventq_index=0 1059fake_mem=false |
| 1060p_state_clk_gate_bins=20 1061p_state_clk_gate_max=1000000000000 1062p_state_clk_gate_min=1000 |
|
| 894pio_addr=8804615848816 895pio_latency=100000 896pio_size=8 | 1063pio_addr=8804615848816 1064pio_latency=100000 1065pio_size=8 |
| 1066power_model=Null |
|
| 897ret_bad_addr=false 898ret_data16=65535 899ret_data32=4294967295 900ret_data64=18446744073709551615 901ret_data8=255 902system=system 903update_data=false 904warn_access= 905pio=system.iobus.master[2] 906 907[system.tsunami.fake_uart1] 908type=IsaFake 909clk_domain=system.clk_domain | 1067ret_bad_addr=false 1068ret_data16=65535 1069ret_data32=4294967295 1070ret_data64=18446744073709551615 1071ret_data8=255 1072system=system 1073update_data=false 1074warn_access= 1075pio=system.iobus.master[2] 1076 1077[system.tsunami.fake_uart1] 1078type=IsaFake 1079clk_domain=system.clk_domain |
| 1080default_p_state=UNDEFINED |
|
| 910eventq_index=0 911fake_mem=false | 1081eventq_index=0 1082fake_mem=false |
| 1083p_state_clk_gate_bins=20 1084p_state_clk_gate_max=1000000000000 1085p_state_clk_gate_min=1000 |
|
| 912pio_addr=8804615848696 913pio_latency=100000 914pio_size=8 | 1086pio_addr=8804615848696 1087pio_latency=100000 1088pio_size=8 |
| 1089power_model=Null |
|
| 915ret_bad_addr=false 916ret_data16=65535 917ret_data32=4294967295 918ret_data64=18446744073709551615 919ret_data8=255 920system=system 921update_data=false 922warn_access= 923pio=system.iobus.master[3] 924 925[system.tsunami.fake_uart2] 926type=IsaFake 927clk_domain=system.clk_domain | 1090ret_bad_addr=false 1091ret_data16=65535 1092ret_data32=4294967295 1093ret_data64=18446744073709551615 1094ret_data8=255 1095system=system 1096update_data=false 1097warn_access= 1098pio=system.iobus.master[3] 1099 1100[system.tsunami.fake_uart2] 1101type=IsaFake 1102clk_domain=system.clk_domain |
| 1103default_p_state=UNDEFINED |
|
| 928eventq_index=0 929fake_mem=false | 1104eventq_index=0 1105fake_mem=false |
| 1106p_state_clk_gate_bins=20 1107p_state_clk_gate_max=1000000000000 1108p_state_clk_gate_min=1000 |
|
| 930pio_addr=8804615848936 931pio_latency=100000 932pio_size=8 | 1109pio_addr=8804615848936 1110pio_latency=100000 1111pio_size=8 |
| 1112power_model=Null |
|
| 933ret_bad_addr=false 934ret_data16=65535 935ret_data32=4294967295 936ret_data64=18446744073709551615 937ret_data8=255 938system=system 939update_data=false 940warn_access= 941pio=system.iobus.master[4] 942 943[system.tsunami.fake_uart3] 944type=IsaFake 945clk_domain=system.clk_domain | 1113ret_bad_addr=false 1114ret_data16=65535 1115ret_data32=4294967295 1116ret_data64=18446744073709551615 1117ret_data8=255 1118system=system 1119update_data=false 1120warn_access= 1121pio=system.iobus.master[4] 1122 1123[system.tsunami.fake_uart3] 1124type=IsaFake 1125clk_domain=system.clk_domain |
| 1126default_p_state=UNDEFINED |
|
| 946eventq_index=0 947fake_mem=false | 1127eventq_index=0 1128fake_mem=false |
| 1129p_state_clk_gate_bins=20 1130p_state_clk_gate_max=1000000000000 1131p_state_clk_gate_min=1000 |
|
| 948pio_addr=8804615848680 949pio_latency=100000 950pio_size=8 | 1132pio_addr=8804615848680 1133pio_latency=100000 1134pio_size=8 |
| 1135power_model=Null |
|
| 951ret_bad_addr=false 952ret_data16=65535 953ret_data32=4294967295 954ret_data64=18446744073709551615 955ret_data8=255 956system=system 957update_data=false 958warn_access= 959pio=system.iobus.master[5] 960 961[system.tsunami.fake_uart4] 962type=IsaFake 963clk_domain=system.clk_domain | 1136ret_bad_addr=false 1137ret_data16=65535 1138ret_data32=4294967295 1139ret_data64=18446744073709551615 1140ret_data8=255 1141system=system 1142update_data=false 1143warn_access= 1144pio=system.iobus.master[5] 1145 1146[system.tsunami.fake_uart4] 1147type=IsaFake 1148clk_domain=system.clk_domain |
| 1149default_p_state=UNDEFINED |
|
| 964eventq_index=0 965fake_mem=false | 1150eventq_index=0 1151fake_mem=false |
| 1152p_state_clk_gate_bins=20 1153p_state_clk_gate_max=1000000000000 1154p_state_clk_gate_min=1000 |
|
| 966pio_addr=8804615848944 967pio_latency=100000 968pio_size=8 | 1155pio_addr=8804615848944 1156pio_latency=100000 1157pio_size=8 |
| 1158power_model=Null |
|
| 969ret_bad_addr=false 970ret_data16=65535 971ret_data32=4294967295 972ret_data64=18446744073709551615 973ret_data8=255 974system=system 975update_data=false 976warn_access= 977pio=system.iobus.master[6] 978 979[system.tsunami.fb] 980type=BadDevice 981clk_domain=system.clk_domain | 1159ret_bad_addr=false 1160ret_data16=65535 1161ret_data32=4294967295 1162ret_data64=18446744073709551615 1163ret_data8=255 1164system=system 1165update_data=false 1166warn_access= 1167pio=system.iobus.master[6] 1168 1169[system.tsunami.fb] 1170type=BadDevice 1171clk_domain=system.clk_domain |
| 1172default_p_state=UNDEFINED |
|
| 982devicename=FrameBuffer 983eventq_index=0 | 1173devicename=FrameBuffer 1174eventq_index=0 |
| 1175p_state_clk_gate_bins=20 1176p_state_clk_gate_max=1000000000000 1177p_state_clk_gate_min=1000 |
|
| 984pio_addr=8804615848912 985pio_latency=100000 | 1178pio_addr=8804615848912 1179pio_latency=100000 |
| 1180power_model=Null |
|
| 986system=system 987pio=system.iobus.master[21] 988 989[system.tsunami.ide] 990type=IdeController 991BAR0=1 992BAR0LegacyIO=false 993BAR0Size=8 --- 64 unchanged lines hidden (view full) --- 1058Status=640 1059SubClassCode=1 1060SubsystemID=0 1061SubsystemVendorID=0 1062VendorID=32902 1063clk_domain=system.clk_domain 1064config_latency=20000 1065ctrl_offset=0 | 1181system=system 1182pio=system.iobus.master[21] 1183 1184[system.tsunami.ide] 1185type=IdeController 1186BAR0=1 1187BAR0LegacyIO=false 1188BAR0Size=8 --- 64 unchanged lines hidden (view full) --- 1253Status=640 1254SubClassCode=1 1255SubsystemID=0 1256SubsystemVendorID=0 1257VendorID=32902 1258clk_domain=system.clk_domain 1259config_latency=20000 1260ctrl_offset=0 |
| 1261default_p_state=UNDEFINED |
|
| 1066disks=system.disk0 system.disk2 1067eventq_index=0 1068host=system.tsunami.pchip 1069io_shift=0 | 1262disks=system.disk0 system.disk2 1263eventq_index=0 1264host=system.tsunami.pchip 1265io_shift=0 |
| 1266p_state_clk_gate_bins=20 1267p_state_clk_gate_max=1000000000000 1268p_state_clk_gate_min=1000 |
|
| 1070pci_bus=0 1071pci_dev=0 1072pci_func=0 1073pio_latency=30000 | 1269pci_bus=0 1270pci_dev=0 1271pci_func=0 1272pio_latency=30000 |
| 1273power_model=Null |
|
| 1074system=system 1075dma=system.iobus.slave[1] 1076pio=system.iobus.master[25] 1077 1078[system.tsunami.io] 1079type=TsunamiIO 1080clk_domain=system.clk_domain | 1274system=system 1275dma=system.iobus.slave[1] 1276pio=system.iobus.master[25] 1277 1278[system.tsunami.io] 1279type=TsunamiIO 1280clk_domain=system.clk_domain |
| 1281default_p_state=UNDEFINED |
|
| 1081eventq_index=0 1082frequency=976562500 | 1282eventq_index=0 1283frequency=976562500 |
| 1284p_state_clk_gate_bins=20 1285p_state_clk_gate_max=1000000000000 1286p_state_clk_gate_min=1000 |
|
| 1083pio_addr=8804615847936 1084pio_latency=100000 | 1287pio_addr=8804615847936 1288pio_latency=100000 |
| 1289power_model=Null |
|
| 1085system=system 1086time=Thu Jan 1 00:00:00 2009 1087tsunami=system.tsunami 1088year_is_bcd=false 1089pio=system.iobus.master[22] 1090 1091[system.tsunami.pchip] 1092type=TsunamiPChip 1093clk_domain=system.clk_domain 1094conf_base=8804649402368 1095conf_device_bits=8 1096conf_size=16777216 | 1290system=system 1291time=Thu Jan 1 00:00:00 2009 1292tsunami=system.tsunami 1293year_is_bcd=false 1294pio=system.iobus.master[22] 1295 1296[system.tsunami.pchip] 1297type=TsunamiPChip 1298clk_domain=system.clk_domain 1299conf_base=8804649402368 1300conf_device_bits=8 1301conf_size=16777216 |
| 1302default_p_state=UNDEFINED |
|
| 1097eventq_index=0 | 1303eventq_index=0 |
| 1304p_state_clk_gate_bins=20 1305p_state_clk_gate_max=1000000000000 1306p_state_clk_gate_min=1000 |
|
| 1098pci_dma_base=0 1099pci_mem_base=8796093022208 1100pci_pio_base=8804615847936 1101pio_addr=8802535473152 1102pio_latency=100000 1103platform=system.tsunami | 1307pci_dma_base=0 1308pci_mem_base=8796093022208 1309pci_pio_base=8804615847936 1310pio_addr=8802535473152 1311pio_latency=100000 1312platform=system.tsunami |
| 1313power_model=Null |
|
| 1104system=system 1105tsunami=system.tsunami 1106pio=system.iobus.master[1] 1107 1108[system.tsunami.uart] 1109type=Uart8250 1110clk_domain=system.clk_domain | 1314system=system 1315tsunami=system.tsunami 1316pio=system.iobus.master[1] 1317 1318[system.tsunami.uart] 1319type=Uart8250 1320clk_domain=system.clk_domain |
| 1321default_p_state=UNDEFINED |
|
| 1111eventq_index=0 | 1322eventq_index=0 |
| 1323p_state_clk_gate_bins=20 1324p_state_clk_gate_max=1000000000000 1325p_state_clk_gate_min=1000 |
|
| 1112pio_addr=8804615848952 1113pio_latency=100000 1114platform=system.tsunami | 1326pio_addr=8804615848952 1327pio_latency=100000 1328platform=system.tsunami |
| 1329power_model=Null |
|
| 1115system=system 1116terminal=system.terminal 1117pio=system.iobus.master[23] 1118 1119[system.voltage_domain] 1120type=VoltageDomain 1121eventq_index=0 1122voltage=1.000000 1123 | 1330system=system 1331terminal=system.terminal 1332pio=system.iobus.master[23] 1333 1334[system.voltage_domain] 1335type=VoltageDomain 1336eventq_index=0 1337voltage=1.000000 1338 |