| config.ini (10636:9ac724889705) | config.ini (10736:4433fb00fa7d) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20init_param=0 21kernel=/scratch/nilay/GEM5/system/binaries/vmlinux 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20init_param=0 21kernel=/scratch/nilay/GEM5/system/binaries/vmlinux 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem |
| 28mmap_using_noreserve=false |
|
| 28num_work_ids=16 29pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal 30readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh 31symbolfile= 32system_rev=1024 33system_type=34 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 --- 182 unchanged lines hidden (view full) --- 218hit_latency=20 219sequential_access=false 220size=4194304 221 222[system.cpu.toL2Bus] 223type=CoherentXBar 224clk_domain=system.cpu_clk_domain 225eventq_index=0 | 29num_work_ids=16 30pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal 31readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh 32symbolfile= 33system_rev=1024 34system_type=34 35work_begin_ckpt_count=0 36work_begin_cpu_id_exit=-1 --- 182 unchanged lines hidden (view full) --- 219hit_latency=20 220sequential_access=false 221size=4194304 222 223[system.cpu.toL2Bus] 224type=CoherentXBar 225clk_domain=system.cpu_clk_domain 226eventq_index=0 |
| 226header_cycles=1 | 227forward_latency=0 228frontend_latency=1 229response_latency=1 |
| 227snoop_filter=Null | 230snoop_filter=Null |
| 231snoop_response_latency=1 |
|
| 228system=system 229use_default_range=false 230width=32 231master=system.cpu.l2cache.cpu_side 232slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 233 234[system.cpu.tracer] 235type=ExeTracer --- 65 unchanged lines hidden (view full) --- 301type=IntrControl 302eventq_index=0 303sys=system 304 305[system.iobus] 306type=NoncoherentXBar 307clk_domain=system.clk_domain 308eventq_index=0 | 232system=system 233use_default_range=false 234width=32 235master=system.cpu.l2cache.cpu_side 236slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 237 238[system.cpu.tracer] 239type=ExeTracer --- 65 unchanged lines hidden (view full) --- 305type=IntrControl 306eventq_index=0 307sys=system 308 309[system.iobus] 310type=NoncoherentXBar 311clk_domain=system.clk_domain 312eventq_index=0 |
| 309header_cycles=1 | 313forward_latency=1 314frontend_latency=2 315response_latency=2 |
| 310use_default_range=true | 316use_default_range=true |
| 311width=8 | 317width=16 |
| 312default=system.tsunami.pciconfig.pio 313master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 314slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 315 316[system.iocache] 317type=BaseCache 318children=tags 319addr_ranges=0:134217727 --- 29 unchanged lines hidden (view full) --- 349sequential_access=false 350size=1024 351 352[system.membus] 353type=CoherentXBar 354children=badaddr_responder 355clk_domain=system.clk_domain 356eventq_index=0 | 318default=system.tsunami.pciconfig.pio 319master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 320slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 321 322[system.iocache] 323type=BaseCache 324children=tags 325addr_ranges=0:134217727 --- 29 unchanged lines hidden (view full) --- 355sequential_access=false 356size=1024 357 358[system.membus] 359type=CoherentXBar 360children=badaddr_responder 361clk_domain=system.clk_domain 362eventq_index=0 |
| 357header_cycles=1 | 363forward_latency=4 364frontend_latency=3 365response_latency=2 |
| 358snoop_filter=Null | 366snoop_filter=Null |
| 367snoop_response_latency=4 |
|
| 359system=system 360use_default_range=false | 368system=system 369use_default_range=false |
| 361width=8 | 370width=16 |
| 362default=system.membus.badaddr_responder.pio 363master=system.bridge.slave system.physmem.port 364slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 365 366[system.membus.badaddr_responder] 367type=IsaFake 368clk_domain=system.clk_domain 369eventq_index=0 --- 33 unchanged lines hidden (view full) --- 403IDD4W2=0.000000 404IDD5=0.220000 405IDD52=0.000000 406IDD6=0.000000 407IDD62=0.000000 408VDD=1.500000 409VDD2=0.000000 410activation_limit=4 | 371default=system.membus.badaddr_responder.pio 372master=system.bridge.slave system.physmem.port 373slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 374 375[system.membus.badaddr_responder] 376type=IsaFake 377clk_domain=system.clk_domain 378eventq_index=0 --- 33 unchanged lines hidden (view full) --- 412IDD4W2=0.000000 413IDD5=0.220000 414IDD52=0.000000 415IDD6=0.000000 416IDD62=0.000000 417VDD=1.500000 418VDD2=0.000000 419activation_limit=4 |
| 411addr_mapping=RoRaBaChCo | 420addr_mapping=RoRaBaCoCh |
| 412bank_groups_per_rank=0 413banks_per_rank=8 414burst_length=8 415channels=1 416clk_domain=system.clk_domain 417conf_table_reported=true 418device_bus_width=8 419device_rowbuffer_size=1024 --- 689 unchanged lines hidden --- | 421bank_groups_per_rank=0 422banks_per_rank=8 423burst_length=8 424channels=1 425clk_domain=system.clk_domain 426conf_table_reported=true 427device_bus_width=8 428device_rowbuffer_size=1024 --- 689 unchanged lines hidden --- |