| config.ini (10315:9e02c14446bb) | config.ini (10451:3a87241adfb8) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 203 unchanged lines hidden (view full) --- 212block_size=64 213clk_domain=system.cpu_clk_domain 214eventq_index=0 215hit_latency=20 216sequential_access=false 217size=4194304 218 219[system.cpu.toL2Bus] | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 203 unchanged lines hidden (view full) --- 212block_size=64 213clk_domain=system.cpu_clk_domain 214eventq_index=0 215hit_latency=20 216sequential_access=false 217size=4194304 218 219[system.cpu.toL2Bus] |
| 220type=CoherentBus | 220type=CoherentXBar |
| 221clk_domain=system.cpu_clk_domain 222eventq_index=0 223header_cycles=1 | 221clk_domain=system.cpu_clk_domain 222eventq_index=0 223header_cycles=1 |
| 224snoop_filter=Null |
|
| 224system=system 225use_default_range=false 226width=32 227master=system.cpu.l2cache.cpu_side 228slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 229 230[system.cpu.tracer] 231type=ExeTracer --- 62 unchanged lines hidden (view full) --- 294transition_latency=100000000 295 296[system.intrctrl] 297type=IntrControl 298eventq_index=0 299sys=system 300 301[system.iobus] | 225system=system 226use_default_range=false 227width=32 228master=system.cpu.l2cache.cpu_side 229slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 230 231[system.cpu.tracer] 232type=ExeTracer --- 62 unchanged lines hidden (view full) --- 295transition_latency=100000000 296 297[system.intrctrl] 298type=IntrControl 299eventq_index=0 300sys=system 301 302[system.iobus] |
| 302type=NoncoherentBus | 303type=NoncoherentXBar |
| 303clk_domain=system.clk_domain 304eventq_index=0 305header_cycles=1 306use_default_range=true 307width=8 308default=system.tsunami.pciconfig.pio 309master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 310slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma --- 29 unchanged lines hidden (view full) --- 340block_size=64 341clk_domain=system.clk_domain 342eventq_index=0 343hit_latency=50 344sequential_access=false 345size=1024 346 347[system.membus] | 304clk_domain=system.clk_domain 305eventq_index=0 306header_cycles=1 307use_default_range=true 308width=8 309default=system.tsunami.pciconfig.pio 310master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 311slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma --- 29 unchanged lines hidden (view full) --- 341block_size=64 342clk_domain=system.clk_domain 343eventq_index=0 344hit_latency=50 345sequential_access=false 346size=1024 347 348[system.membus] |
| 348type=CoherentBus | 349type=CoherentXBar |
| 349children=badaddr_responder 350clk_domain=system.clk_domain 351eventq_index=0 352header_cycles=1 | 350children=badaddr_responder 351clk_domain=system.clk_domain 352eventq_index=0 353header_cycles=1 |
| 354snoop_filter=Null |
|
| 353system=system 354use_default_range=false 355width=8 356default=system.membus.badaddr_responder.pio 357master=system.bridge.slave system.physmem.port 358slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 359 360[system.membus.badaddr_responder] --- 11 unchanged lines hidden (view full) --- 372ret_data8=255 373system=system 374update_data=false 375warn_access= 376pio=system.membus.default 377 378[system.physmem] 379type=DRAMCtrl | 355system=system 356use_default_range=false 357width=8 358default=system.membus.badaddr_responder.pio 359master=system.bridge.slave system.physmem.port 360slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 361 362[system.membus.badaddr_responder] --- 11 unchanged lines hidden (view full) --- 374ret_data8=255 375system=system 376update_data=false 377warn_access= 378pio=system.membus.default 379 380[system.physmem] 381type=DRAMCtrl |
| 382IDD0=0.075000 383IDD02=0.000000 384IDD2N=0.050000 385IDD2N2=0.000000 386IDD2P0=0.000000 387IDD2P02=0.000000 388IDD2P1=0.000000 389IDD2P12=0.000000 390IDD3N=0.057000 391IDD3N2=0.000000 392IDD3P0=0.000000 393IDD3P02=0.000000 394IDD3P1=0.000000 395IDD3P12=0.000000 396IDD4R=0.187000 397IDD4R2=0.000000 398IDD4W=0.165000 399IDD4W2=0.000000 400IDD5=0.220000 401IDD52=0.000000 402IDD6=0.000000 403IDD62=0.000000 404VDD=1.500000 405VDD2=0.000000 |
|
| 380activation_limit=4 381addr_mapping=RoRaBaChCo | 406activation_limit=4 407addr_mapping=RoRaBaChCo |
| 408bank_groups_per_rank=0 |
|
| 382banks_per_rank=8 383burst_length=8 384channels=1 385clk_domain=system.clk_domain 386conf_table_reported=true 387device_bus_width=8 388device_rowbuffer_size=1024 389devices_per_rank=8 | 409banks_per_rank=8 410burst_length=8 411channels=1 412clk_domain=system.clk_domain 413conf_table_reported=true 414device_bus_width=8 415device_rowbuffer_size=1024 416devices_per_rank=8 |
| 417dll=true |
|
| 390eventq_index=0 391in_addr_map=true 392max_accesses_per_row=16 393mem_sched_policy=frfcfs 394min_writes_per_switch=16 395null=false 396page_policy=open_adaptive 397range=0:134217727 398ranks_per_channel=2 399read_buffer_size=32 400static_backend_latency=10000 401static_frontend_latency=10000 402tBURST=5000 | 418eventq_index=0 419in_addr_map=true 420max_accesses_per_row=16 421mem_sched_policy=frfcfs 422min_writes_per_switch=16 423null=false 424page_policy=open_adaptive 425range=0:134217727 426ranks_per_channel=2 427read_buffer_size=32 428static_backend_latency=10000 429static_frontend_latency=10000 430tBURST=5000 |
| 431tCCD_L=0 |
|
| 403tCK=1250 404tCL=13750 | 432tCK=1250 433tCL=13750 |
| 434tCS=2500 |
|
| 405tRAS=35000 406tRCD=13750 407tREFI=7800000 408tRFC=260000 409tRP=13750 410tRRD=6000 | 435tRAS=35000 436tRCD=13750 437tREFI=7800000 438tRFC=260000 439tRP=13750 440tRRD=6000 |
| 441tRRD_L=0 |
|
| 411tRTP=7500 412tRTW=2500 413tWR=15000 414tWTR=7500 415tXAW=30000 | 442tRTP=7500 443tRTW=2500 444tWR=15000 445tWTR=7500 446tXAW=30000 |
| 447tXP=0 448tXPDLL=0 449tXS=0 450tXSDLL=0 |
|
| 416write_buffer_size=64 417write_high_thresh_perc=85 418write_low_thresh_perc=50 419port=system.membus.master[1] 420 421[system.simple_disk] 422type=SimpleDisk 423children=disk --- 72 unchanged lines hidden (view full) --- 496ClassCode=2 497Command=0 498DeviceID=34 499ExpansionROM=0 500HeaderType=0 501InterruptLine=30 502InterruptPin=1 503LatencyTimer=0 | 451write_buffer_size=64 452write_high_thresh_perc=85 453write_low_thresh_perc=50 454port=system.membus.master[1] 455 456[system.simple_disk] 457type=SimpleDisk 458children=disk --- 72 unchanged lines hidden (view full) --- 531ClassCode=2 532Command=0 533DeviceID=34 534ExpansionROM=0 535HeaderType=0 536InterruptLine=30 537InterruptPin=1 538LatencyTimer=0 |
| 539LegacyIOBase=0 |
|
| 504MSICAPBaseOffset=0 505MSICAPCapId=0 506MSICAPMaskBits=0 507MSICAPMsgAddr=0 508MSICAPMsgCtrl=0 509MSICAPMsgData=0 510MSICAPMsgUpperAddr=0 511MSICAPNextCapability=0 --- 439 unchanged lines hidden (view full) --- 951ClassCode=1 952Command=0 953DeviceID=28945 954ExpansionROM=0 955HeaderType=0 956InterruptLine=31 957InterruptPin=1 958LatencyTimer=0 | 540MSICAPBaseOffset=0 541MSICAPCapId=0 542MSICAPMaskBits=0 543MSICAPMsgAddr=0 544MSICAPMsgCtrl=0 545MSICAPMsgData=0 546MSICAPMsgUpperAddr=0 547MSICAPNextCapability=0 --- 439 unchanged lines hidden (view full) --- 987ClassCode=1 988Command=0 989DeviceID=28945 990ExpansionROM=0 991HeaderType=0 992InterruptLine=31 993InterruptPin=1 994LatencyTimer=0 |
| 995LegacyIOBase=0 |
|
| 959MSICAPBaseOffset=0 960MSICAPCapId=0 961MSICAPMaskBits=0 962MSICAPMsgAddr=0 963MSICAPMsgCtrl=0 964MSICAPMsgData=0 965MSICAPMsgUpperAddr=0 966MSICAPNextCapability=0 --- 100 unchanged lines hidden --- | 996MSICAPBaseOffset=0 997MSICAPCapId=0 998MSICAPMaskBits=0 999MSICAPMsgAddr=0 1000MSICAPMsgCtrl=0 1001MSICAPMsgData=0 1002MSICAPMsgUpperAddr=0 1003MSICAPNextCapability=0 --- 100 unchanged lines hidden --- |