| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain |
| 18console=/arm/projectscratch/randd/systems/dist/binaries/console 19default_p_state=UNDEFINED |
| 20eventq_index=0 21exit_on_work_items=false 22init_param=0 |
| 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux |
| 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing 28mem_ranges=0:134217727 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 |
| 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal 37power_model=Null 38readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh |
| 39symbolfile= 40system_rev=1024 41system_type=34 42thermal_components= 43thermal_model=Null 44work_begin_ckpt_count=0 45work_begin_cpu_id_exit=-1 46work_begin_exit_count=0 47work_cpus_ckpt_count=0 48work_end_ckpt_count=0 49work_end_exit_count=0 50work_item_id=-1 51system_port=system.membus.slave[0] 52 53[system.bridge] 54type=Bridge 55clk_domain=system.clk_domain |
| 56default_p_state=UNDEFINED |
| 57delay=50000 58eventq_index=0 |
| 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null |
| 63ranges=8796093022208:18446744073709551615 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain --- 5 unchanged lines hidden (view full) --- 76 77[system.cpu] 78type=TimingSimpleCPU 79children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer 80branchPred=Null 81checker=Null 82clk_domain=system.cpu_clk_domain 83cpu_id=0 |
| 84default_p_state=UNDEFINED |
| 85do_checkpoint_insts=true 86do_quiesce=true 87do_statistics_insts=true 88dtb=system.cpu.dtb 89eventq_index=0 90function_trace=false 91function_trace_start=0 92interrupts=system.cpu.interrupts 93isa=system.cpu.isa 94itb=system.cpu.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99numThreads=1 |
| 100p_state_clk_gate_bins=20 101p_state_clk_gate_max=1000000000000 102p_state_clk_gate_min=1000 103power_model=Null |
| 104profile=0 105progress_interval=0 106simpoint_start_insts= 107socket_id=0 108switched_out=false 109system=system 110tracer=system.cpu.tracer 111workload= 112dcache_port=system.cpu.dcache.cpu_side 113icache_port=system.cpu.icache.cpu_side 114 115[system.cpu.dcache] 116type=Cache 117children=tags 118addr_ranges=0:18446744073709551615 119assoc=4 120clk_domain=system.cpu_clk_domain 121clusivity=mostly_incl |
| 122default_p_state=UNDEFINED |
| 123demand_mshr_reserve=1 124eventq_index=0 125hit_latency=2 126is_read_only=false 127max_miss_count=0 128mshrs=4 |
| 129p_state_clk_gate_bins=20 130p_state_clk_gate_max=1000000000000 131p_state_clk_gate_min=1000 132power_model=Null |
| 133prefetch_on_access=false 134prefetcher=Null 135response_latency=2 136sequential_access=false 137size=32768 138system=system 139tags=system.cpu.dcache.tags 140tgts_per_mshr=20 141write_buffers=8 142writeback_clean=false 143cpu_side=system.cpu.dcache_port 144mem_side=system.cpu.toL2Bus.slave[1] 145 146[system.cpu.dcache.tags] 147type=LRU 148assoc=4 149block_size=64 150clk_domain=system.cpu_clk_domain |
| 151default_p_state=UNDEFINED |
| 152eventq_index=0 153hit_latency=2 |
| 154p_state_clk_gate_bins=20 155p_state_clk_gate_max=1000000000000 156p_state_clk_gate_min=1000 157power_model=Null |
| 158sequential_access=false 159size=32768 160 161[system.cpu.dtb] 162type=AlphaTLB 163eventq_index=0 164size=64 165 166[system.cpu.icache] 167type=Cache 168children=tags 169addr_ranges=0:18446744073709551615 170assoc=1 171clk_domain=system.cpu_clk_domain 172clusivity=mostly_incl |
| 173default_p_state=UNDEFINED |
| 174demand_mshr_reserve=1 175eventq_index=0 176hit_latency=2 177is_read_only=true 178max_miss_count=0 179mshrs=4 |
| 180p_state_clk_gate_bins=20 181p_state_clk_gate_max=1000000000000 182p_state_clk_gate_min=1000 183power_model=Null |
| 184prefetch_on_access=false 185prefetcher=Null 186response_latency=2 187sequential_access=false 188size=32768 189system=system 190tags=system.cpu.icache.tags 191tgts_per_mshr=20 192write_buffers=8 193writeback_clean=true 194cpu_side=system.cpu.icache_port 195mem_side=system.cpu.toL2Bus.slave[0] 196 197[system.cpu.icache.tags] 198type=LRU 199assoc=1 200block_size=64 201clk_domain=system.cpu_clk_domain |
| 202default_p_state=UNDEFINED |
| 203eventq_index=0 204hit_latency=2 |
| 205p_state_clk_gate_bins=20 206p_state_clk_gate_max=1000000000000 207p_state_clk_gate_min=1000 208power_model=Null |
| 209sequential_access=false 210size=32768 211 212[system.cpu.interrupts] 213type=AlphaInterrupts 214eventq_index=0 215 216[system.cpu.isa] --- 8 unchanged lines hidden (view full) --- 225 226[system.cpu.l2cache] 227type=Cache 228children=tags 229addr_ranges=0:18446744073709551615 230assoc=8 231clk_domain=system.cpu_clk_domain 232clusivity=mostly_incl |
| 233default_p_state=UNDEFINED |
| 234demand_mshr_reserve=1 235eventq_index=0 236hit_latency=20 237is_read_only=false 238max_miss_count=0 239mshrs=20 |
| 240p_state_clk_gate_bins=20 241p_state_clk_gate_max=1000000000000 242p_state_clk_gate_min=1000 243power_model=Null |
| 244prefetch_on_access=false 245prefetcher=Null 246response_latency=20 247sequential_access=false 248size=4194304 249system=system 250tags=system.cpu.l2cache.tags 251tgts_per_mshr=12 252write_buffers=8 253writeback_clean=false 254cpu_side=system.cpu.toL2Bus.master[0] 255mem_side=system.membus.slave[1] 256 257[system.cpu.l2cache.tags] 258type=LRU 259assoc=8 260block_size=64 261clk_domain=system.cpu_clk_domain |
| 262default_p_state=UNDEFINED |
| 263eventq_index=0 264hit_latency=20 |
| 265p_state_clk_gate_bins=20 266p_state_clk_gate_max=1000000000000 267p_state_clk_gate_min=1000 268power_model=Null |
| 269sequential_access=false 270size=4194304 271 272[system.cpu.toL2Bus] 273type=CoherentXBar 274children=snoop_filter 275clk_domain=system.cpu_clk_domain |
| 276default_p_state=UNDEFINED |
| 277eventq_index=0 278forward_latency=0 279frontend_latency=1 |
| 280p_state_clk_gate_bins=20 281p_state_clk_gate_max=1000000000000 282p_state_clk_gate_min=1000 |
| 283point_of_coherency=false |
| 284power_model=Null |
| 285response_latency=1 286snoop_filter=system.cpu.toL2Bus.snoop_filter 287snoop_response_latency=1 288system=system 289use_default_range=false 290width=32 291master=system.cpu.l2cache.cpu_side 292slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 32 unchanged lines hidden (view full) --- 325eventq_index=0 326image_file= 327read_only=false 328table_size=65536 329 330[system.disk0.image.child] 331type=RawDiskImage 332eventq_index=0 |
| 333image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img |
| 334read_only=true 335 336[system.disk2] 337type=IdeDisk 338children=image 339delay=1000000 340driveID=master 341eventq_index=0 --- 6 unchanged lines hidden (view full) --- 348eventq_index=0 349image_file= 350read_only=false 351table_size=65536 352 353[system.disk2.image.child] 354type=RawDiskImage 355eventq_index=0 |
| 356image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img |
| 357read_only=true 358 359[system.dvfs_handler] 360type=DVFSHandler 361domains= 362enable=false 363eventq_index=0 364sys_clk_domain=system.clk_domain 365transition_latency=100000000 366 367[system.intrctrl] 368type=IntrControl 369eventq_index=0 370sys=system 371 372[system.iobus] 373type=NoncoherentXBar 374clk_domain=system.clk_domain |
| 375default_p_state=UNDEFINED |
| 376eventq_index=0 377forward_latency=1 378frontend_latency=2 |
| 379p_state_clk_gate_bins=20 380p_state_clk_gate_max=1000000000000 381p_state_clk_gate_min=1000 382power_model=Null |
| 383response_latency=2 384use_default_range=false 385width=16 386master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 387slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 388 389[system.iocache] 390type=Cache 391children=tags 392addr_ranges=0:134217727 393assoc=8 394clk_domain=system.clk_domain 395clusivity=mostly_incl |
| 396default_p_state=UNDEFINED |
| 397demand_mshr_reserve=1 398eventq_index=0 399hit_latency=50 400is_read_only=false 401max_miss_count=0 402mshrs=20 |
| 403p_state_clk_gate_bins=20 404p_state_clk_gate_max=1000000000000 405p_state_clk_gate_min=1000 406power_model=Null |
| 407prefetch_on_access=false 408prefetcher=Null 409response_latency=50 410sequential_access=false 411size=1024 412system=system 413tags=system.iocache.tags 414tgts_per_mshr=12 415write_buffers=8 416writeback_clean=false 417cpu_side=system.iobus.master[27] 418mem_side=system.membus.slave[2] 419 420[system.iocache.tags] 421type=LRU 422assoc=8 423block_size=64 424clk_domain=system.clk_domain |
| 425default_p_state=UNDEFINED |
| 426eventq_index=0 427hit_latency=50 |
| 428p_state_clk_gate_bins=20 429p_state_clk_gate_max=1000000000000 430p_state_clk_gate_min=1000 431power_model=Null |
| 432sequential_access=false 433size=1024 434 435[system.membus] 436type=CoherentXBar 437children=badaddr_responder 438clk_domain=system.clk_domain |
| 439default_p_state=UNDEFINED |
| 440eventq_index=0 441forward_latency=4 442frontend_latency=3 |
| 443p_state_clk_gate_bins=20 444p_state_clk_gate_max=1000000000000 445p_state_clk_gate_min=1000 |
| 446point_of_coherency=true |
| 447power_model=Null |
| 448response_latency=2 449snoop_filter=Null 450snoop_response_latency=4 451system=system 452use_default_range=false 453width=16 454default=system.membus.badaddr_responder.pio 455master=system.bridge.slave system.physmem.port 456slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 457 458[system.membus.badaddr_responder] 459type=IsaFake 460clk_domain=system.clk_domain |
| 461default_p_state=UNDEFINED |
| 462eventq_index=0 463fake_mem=false |
| 464p_state_clk_gate_bins=20 465p_state_clk_gate_max=1000000000000 466p_state_clk_gate_min=1000 |
| 467pio_addr=0 468pio_latency=100000 469pio_size=8 |
| 470power_model=Null |
| 471ret_bad_addr=true 472ret_data16=65535 473ret_data32=4294967295 474ret_data64=18446744073709551615 475ret_data8=255 476system=system 477update_data=false 478warn_access= --- 28 unchanged lines hidden (view full) --- 507activation_limit=4 508addr_mapping=RoRaBaCoCh 509bank_groups_per_rank=0 510banks_per_rank=8 511burst_length=8 512channels=1 513clk_domain=system.clk_domain 514conf_table_reported=true |
| 515default_p_state=UNDEFINED |
| 516device_bus_width=8 517device_rowbuffer_size=1024 518device_size=536870912 519devices_per_rank=8 520dll=true 521eventq_index=0 522in_addr_map=true 523max_accesses_per_row=16 524mem_sched_policy=frfcfs 525min_writes_per_switch=16 526null=false |
| 527p_state_clk_gate_bins=20 528p_state_clk_gate_max=1000000000000 529p_state_clk_gate_min=1000 |
| 530page_policy=open_adaptive |
| 531power_model=Null |
| 532range=0:134217727 533ranks_per_channel=2 534read_buffer_size=32 535static_backend_latency=10000 536static_frontend_latency=10000 537tBURST=5000 538tCCD_L=0 539tCK=1250 --- 25 unchanged lines hidden (view full) --- 565children=disk 566disk=system.simple_disk.disk 567eventq_index=0 568system=system 569 570[system.simple_disk.disk] 571type=RawDiskImage 572eventq_index=0 |
| 573image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img |
| 574read_only=true 575 576[system.terminal] 577type=Terminal 578eventq_index=0 579intr_control=system.intrctrl 580number=0 581output=true --- 5 unchanged lines hidden (view full) --- 587eventq_index=0 588intrctrl=system.intrctrl 589system=system 590 591[system.tsunami.backdoor] 592type=AlphaBackdoor 593clk_domain=system.clk_domain 594cpu=system.cpu |
| 595default_p_state=UNDEFINED |
| 596disk=system.simple_disk 597eventq_index=0 |
| 598p_state_clk_gate_bins=20 599p_state_clk_gate_max=1000000000000 600p_state_clk_gate_min=1000 |
| 601pio_addr=8804682956800 602pio_latency=100000 603platform=system.tsunami |
| 604power_model=Null |
| 605system=system 606terminal=system.terminal 607pio=system.iobus.master[24] 608 609[system.tsunami.cchip] 610type=TsunamiCChip 611clk_domain=system.clk_domain |
| 612default_p_state=UNDEFINED |
| 613eventq_index=0 |
| 614p_state_clk_gate_bins=20 615p_state_clk_gate_max=1000000000000 616p_state_clk_gate_min=1000 |
| 617pio_addr=8803072344064 618pio_latency=100000 |
| 619power_model=Null |
| 620system=system 621tsunami=system.tsunami 622pio=system.iobus.master[0] 623 624[system.tsunami.ethernet] 625type=NSGigE 626BAR0=1 627BAR0LegacyIO=false --- 64 unchanged lines hidden (view full) --- 692Revision=0 693Status=656 694SubClassCode=0 695SubsystemID=0 696SubsystemVendorID=0 697VendorID=4107 698clk_domain=system.clk_domain 699config_latency=20000 |
| 700default_p_state=UNDEFINED |
| 701dma_data_free=false 702dma_desc_free=false 703dma_no_allocate=true 704dma_read_delay=0 705dma_read_factor=0 706dma_write_delay=0 707dma_write_factor=0 708eventq_index=0 709hardware_address=00:90:00:00:00:01 710host=system.tsunami.pchip 711intr_delay=10000000 |
| 712p_state_clk_gate_bins=20 713p_state_clk_gate_max=1000000000000 714p_state_clk_gate_min=1000 |
| 715pci_bus=0 716pci_dev=1 717pci_func=0 718pio_latency=30000 |
| 719power_model=Null |
| 720rss=false 721rx_delay=1000000 722rx_fifo_size=524288 723rx_filter=true 724rx_thread=false 725system=system 726tx_delay=1000000 727tx_fifo_size=524288 728tx_thread=false 729dma=system.iobus.slave[2] 730pio=system.iobus.master[26] 731 732[system.tsunami.fake_OROM] 733type=IsaFake 734clk_domain=system.clk_domain |
| 735default_p_state=UNDEFINED |
| 736eventq_index=0 737fake_mem=false |
| 738p_state_clk_gate_bins=20 739p_state_clk_gate_max=1000000000000 740p_state_clk_gate_min=1000 |
| 741pio_addr=8796093677568 742pio_latency=100000 743pio_size=393216 |
| 744power_model=Null |
| 745ret_bad_addr=false 746ret_data16=65535 747ret_data32=4294967295 748ret_data64=18446744073709551615 749ret_data8=255 750system=system 751update_data=false 752warn_access= 753pio=system.iobus.master[8] 754 755[system.tsunami.fake_ata0] 756type=IsaFake 757clk_domain=system.clk_domain |
| 758default_p_state=UNDEFINED |
| 759eventq_index=0 760fake_mem=false |
| 761p_state_clk_gate_bins=20 762p_state_clk_gate_max=1000000000000 763p_state_clk_gate_min=1000 |
| 764pio_addr=8804615848432 765pio_latency=100000 766pio_size=8 |
| 767power_model=Null |
| 768ret_bad_addr=false 769ret_data16=65535 770ret_data32=4294967295 771ret_data64=18446744073709551615 772ret_data8=255 773system=system 774update_data=false 775warn_access= 776pio=system.iobus.master[19] 777 778[system.tsunami.fake_ata1] 779type=IsaFake 780clk_domain=system.clk_domain |
| 781default_p_state=UNDEFINED |
| 782eventq_index=0 783fake_mem=false |
| 784p_state_clk_gate_bins=20 785p_state_clk_gate_max=1000000000000 786p_state_clk_gate_min=1000 |
| 787pio_addr=8804615848304 788pio_latency=100000 789pio_size=8 |
| 790power_model=Null |
| 791ret_bad_addr=false 792ret_data16=65535 793ret_data32=4294967295 794ret_data64=18446744073709551615 795ret_data8=255 796system=system 797update_data=false 798warn_access= 799pio=system.iobus.master[20] 800 801[system.tsunami.fake_pnp_addr] 802type=IsaFake 803clk_domain=system.clk_domain |
| 804default_p_state=UNDEFINED |
| 805eventq_index=0 806fake_mem=false |
| 807p_state_clk_gate_bins=20 808p_state_clk_gate_max=1000000000000 809p_state_clk_gate_min=1000 |
| 810pio_addr=8804615848569 811pio_latency=100000 812pio_size=8 |
| 813power_model=Null |
| 814ret_bad_addr=false 815ret_data16=65535 816ret_data32=4294967295 817ret_data64=18446744073709551615 818ret_data8=255 819system=system 820update_data=false 821warn_access= 822pio=system.iobus.master[9] 823 824[system.tsunami.fake_pnp_read0] 825type=IsaFake 826clk_domain=system.clk_domain |
| 827default_p_state=UNDEFINED |
| 828eventq_index=0 829fake_mem=false |
| 830p_state_clk_gate_bins=20 831p_state_clk_gate_max=1000000000000 832p_state_clk_gate_min=1000 |
| 833pio_addr=8804615848451 834pio_latency=100000 835pio_size=8 |
| 836power_model=Null |
| 837ret_bad_addr=false 838ret_data16=65535 839ret_data32=4294967295 840ret_data64=18446744073709551615 841ret_data8=255 842system=system 843update_data=false 844warn_access= 845pio=system.iobus.master[11] 846 847[system.tsunami.fake_pnp_read1] 848type=IsaFake 849clk_domain=system.clk_domain |
| 850default_p_state=UNDEFINED |
| 851eventq_index=0 852fake_mem=false |
| 853p_state_clk_gate_bins=20 854p_state_clk_gate_max=1000000000000 855p_state_clk_gate_min=1000 |
| 856pio_addr=8804615848515 857pio_latency=100000 858pio_size=8 |
| 859power_model=Null |
| 860ret_bad_addr=false 861ret_data16=65535 862ret_data32=4294967295 863ret_data64=18446744073709551615 864ret_data8=255 865system=system 866update_data=false 867warn_access= 868pio=system.iobus.master[12] 869 870[system.tsunami.fake_pnp_read2] 871type=IsaFake 872clk_domain=system.clk_domain |
| 873default_p_state=UNDEFINED |
| 874eventq_index=0 875fake_mem=false |
| 876p_state_clk_gate_bins=20 877p_state_clk_gate_max=1000000000000 878p_state_clk_gate_min=1000 |
| 879pio_addr=8804615848579 880pio_latency=100000 881pio_size=8 |
| 882power_model=Null |
| 883ret_bad_addr=false 884ret_data16=65535 885ret_data32=4294967295 886ret_data64=18446744073709551615 887ret_data8=255 888system=system 889update_data=false 890warn_access= 891pio=system.iobus.master[13] 892 893[system.tsunami.fake_pnp_read3] 894type=IsaFake 895clk_domain=system.clk_domain |
| 896default_p_state=UNDEFINED |
| 897eventq_index=0 898fake_mem=false |
| 899p_state_clk_gate_bins=20 900p_state_clk_gate_max=1000000000000 901p_state_clk_gate_min=1000 |
| 902pio_addr=8804615848643 903pio_latency=100000 904pio_size=8 |
| 905power_model=Null |
| 906ret_bad_addr=false 907ret_data16=65535 908ret_data32=4294967295 909ret_data64=18446744073709551615 910ret_data8=255 911system=system 912update_data=false 913warn_access= 914pio=system.iobus.master[14] 915 916[system.tsunami.fake_pnp_read4] 917type=IsaFake 918clk_domain=system.clk_domain |
| 919default_p_state=UNDEFINED |
| 920eventq_index=0 921fake_mem=false |
| 922p_state_clk_gate_bins=20 923p_state_clk_gate_max=1000000000000 924p_state_clk_gate_min=1000 |
| 925pio_addr=8804615848707 926pio_latency=100000 927pio_size=8 |
| 928power_model=Null |
| 929ret_bad_addr=false 930ret_data16=65535 931ret_data32=4294967295 932ret_data64=18446744073709551615 933ret_data8=255 934system=system 935update_data=false 936warn_access= 937pio=system.iobus.master[15] 938 939[system.tsunami.fake_pnp_read5] 940type=IsaFake 941clk_domain=system.clk_domain |
| 942default_p_state=UNDEFINED |
| 943eventq_index=0 944fake_mem=false |
| 945p_state_clk_gate_bins=20 946p_state_clk_gate_max=1000000000000 947p_state_clk_gate_min=1000 |
| 948pio_addr=8804615848771 949pio_latency=100000 950pio_size=8 |
| 951power_model=Null |
| 952ret_bad_addr=false 953ret_data16=65535 954ret_data32=4294967295 955ret_data64=18446744073709551615 956ret_data8=255 957system=system 958update_data=false 959warn_access= 960pio=system.iobus.master[16] 961 962[system.tsunami.fake_pnp_read6] 963type=IsaFake 964clk_domain=system.clk_domain |
| 965default_p_state=UNDEFINED |
| 966eventq_index=0 967fake_mem=false |
| 968p_state_clk_gate_bins=20 969p_state_clk_gate_max=1000000000000 970p_state_clk_gate_min=1000 |
| 971pio_addr=8804615848835 972pio_latency=100000 973pio_size=8 |
| 974power_model=Null |
| 975ret_bad_addr=false 976ret_data16=65535 977ret_data32=4294967295 978ret_data64=18446744073709551615 979ret_data8=255 980system=system 981update_data=false 982warn_access= 983pio=system.iobus.master[17] 984 985[system.tsunami.fake_pnp_read7] 986type=IsaFake 987clk_domain=system.clk_domain |
| 988default_p_state=UNDEFINED |
| 989eventq_index=0 990fake_mem=false |
| 991p_state_clk_gate_bins=20 992p_state_clk_gate_max=1000000000000 993p_state_clk_gate_min=1000 |
| 994pio_addr=8804615848899 995pio_latency=100000 996pio_size=8 |
| 997power_model=Null |
| 998ret_bad_addr=false 999ret_data16=65535 1000ret_data32=4294967295 1001ret_data64=18446744073709551615 1002ret_data8=255 1003system=system 1004update_data=false 1005warn_access= 1006pio=system.iobus.master[18] 1007 1008[system.tsunami.fake_pnp_write] 1009type=IsaFake 1010clk_domain=system.clk_domain |
| 1011default_p_state=UNDEFINED |
| 1012eventq_index=0 1013fake_mem=false |
| 1014p_state_clk_gate_bins=20 1015p_state_clk_gate_max=1000000000000 1016p_state_clk_gate_min=1000 |
| 1017pio_addr=8804615850617 1018pio_latency=100000 1019pio_size=8 |
| 1020power_model=Null |
| 1021ret_bad_addr=false 1022ret_data16=65535 1023ret_data32=4294967295 1024ret_data64=18446744073709551615 1025ret_data8=255 1026system=system 1027update_data=false 1028warn_access= 1029pio=system.iobus.master[10] 1030 1031[system.tsunami.fake_ppc] 1032type=IsaFake 1033clk_domain=system.clk_domain |
| 1034default_p_state=UNDEFINED |
| 1035eventq_index=0 1036fake_mem=false |
| 1037p_state_clk_gate_bins=20 1038p_state_clk_gate_max=1000000000000 1039p_state_clk_gate_min=1000 |
| 1040pio_addr=8804615848891 1041pio_latency=100000 1042pio_size=8 |
| 1043power_model=Null |
| 1044ret_bad_addr=false 1045ret_data16=65535 1046ret_data32=4294967295 1047ret_data64=18446744073709551615 1048ret_data8=255 1049system=system 1050update_data=false 1051warn_access= 1052pio=system.iobus.master[7] 1053 1054[system.tsunami.fake_sm_chip] 1055type=IsaFake 1056clk_domain=system.clk_domain |
| 1057default_p_state=UNDEFINED |
| 1058eventq_index=0 1059fake_mem=false |
| 1060p_state_clk_gate_bins=20 1061p_state_clk_gate_max=1000000000000 1062p_state_clk_gate_min=1000 |
| 1063pio_addr=8804615848816 1064pio_latency=100000 1065pio_size=8 |
| 1066power_model=Null |
| 1067ret_bad_addr=false 1068ret_data16=65535 1069ret_data32=4294967295 1070ret_data64=18446744073709551615 1071ret_data8=255 1072system=system 1073update_data=false 1074warn_access= 1075pio=system.iobus.master[2] 1076 1077[system.tsunami.fake_uart1] 1078type=IsaFake 1079clk_domain=system.clk_domain |
| 1080default_p_state=UNDEFINED |
| 1081eventq_index=0 1082fake_mem=false |
| 1083p_state_clk_gate_bins=20 1084p_state_clk_gate_max=1000000000000 1085p_state_clk_gate_min=1000 |
| 1086pio_addr=8804615848696 1087pio_latency=100000 1088pio_size=8 |
| 1089power_model=Null |
| 1090ret_bad_addr=false 1091ret_data16=65535 1092ret_data32=4294967295 1093ret_data64=18446744073709551615 1094ret_data8=255 1095system=system 1096update_data=false 1097warn_access= 1098pio=system.iobus.master[3] 1099 1100[system.tsunami.fake_uart2] 1101type=IsaFake 1102clk_domain=system.clk_domain |
| 1103default_p_state=UNDEFINED |
| 1104eventq_index=0 1105fake_mem=false |
| 1106p_state_clk_gate_bins=20 1107p_state_clk_gate_max=1000000000000 1108p_state_clk_gate_min=1000 |
| 1109pio_addr=8804615848936 1110pio_latency=100000 1111pio_size=8 |
| 1112power_model=Null |
| 1113ret_bad_addr=false 1114ret_data16=65535 1115ret_data32=4294967295 1116ret_data64=18446744073709551615 1117ret_data8=255 1118system=system 1119update_data=false 1120warn_access= 1121pio=system.iobus.master[4] 1122 1123[system.tsunami.fake_uart3] 1124type=IsaFake 1125clk_domain=system.clk_domain |
| 1126default_p_state=UNDEFINED |
| 1127eventq_index=0 1128fake_mem=false |
| 1129p_state_clk_gate_bins=20 1130p_state_clk_gate_max=1000000000000 1131p_state_clk_gate_min=1000 |
| 1132pio_addr=8804615848680 1133pio_latency=100000 1134pio_size=8 |
| 1135power_model=Null |
| 1136ret_bad_addr=false 1137ret_data16=65535 1138ret_data32=4294967295 1139ret_data64=18446744073709551615 1140ret_data8=255 1141system=system 1142update_data=false 1143warn_access= 1144pio=system.iobus.master[5] 1145 1146[system.tsunami.fake_uart4] 1147type=IsaFake 1148clk_domain=system.clk_domain |
| 1149default_p_state=UNDEFINED |
| 1150eventq_index=0 1151fake_mem=false |
| 1152p_state_clk_gate_bins=20 1153p_state_clk_gate_max=1000000000000 1154p_state_clk_gate_min=1000 |
| 1155pio_addr=8804615848944 1156pio_latency=100000 1157pio_size=8 |
| 1158power_model=Null |
| 1159ret_bad_addr=false 1160ret_data16=65535 1161ret_data32=4294967295 1162ret_data64=18446744073709551615 1163ret_data8=255 1164system=system 1165update_data=false 1166warn_access= 1167pio=system.iobus.master[6] 1168 1169[system.tsunami.fb] 1170type=BadDevice 1171clk_domain=system.clk_domain |
| 1172default_p_state=UNDEFINED |
| 1173devicename=FrameBuffer 1174eventq_index=0 |
| 1175p_state_clk_gate_bins=20 1176p_state_clk_gate_max=1000000000000 1177p_state_clk_gate_min=1000 |
| 1178pio_addr=8804615848912 1179pio_latency=100000 |
| 1180power_model=Null |
| 1181system=system 1182pio=system.iobus.master[21] 1183 1184[system.tsunami.ide] 1185type=IdeController 1186BAR0=1 1187BAR0LegacyIO=false 1188BAR0Size=8 --- 64 unchanged lines hidden (view full) --- 1253Status=640 1254SubClassCode=1 1255SubsystemID=0 1256SubsystemVendorID=0 1257VendorID=32902 1258clk_domain=system.clk_domain 1259config_latency=20000 1260ctrl_offset=0 |
| 1261default_p_state=UNDEFINED |
| 1262disks=system.disk0 system.disk2 1263eventq_index=0 1264host=system.tsunami.pchip 1265io_shift=0 |
| 1266p_state_clk_gate_bins=20 1267p_state_clk_gate_max=1000000000000 1268p_state_clk_gate_min=1000 |
| 1269pci_bus=0 1270pci_dev=0 1271pci_func=0 1272pio_latency=30000 |
| 1273power_model=Null |
| 1274system=system 1275dma=system.iobus.slave[1] 1276pio=system.iobus.master[25] 1277 1278[system.tsunami.io] 1279type=TsunamiIO 1280clk_domain=system.clk_domain |
| 1281default_p_state=UNDEFINED |
| 1282eventq_index=0 1283frequency=976562500 |
| 1284p_state_clk_gate_bins=20 1285p_state_clk_gate_max=1000000000000 1286p_state_clk_gate_min=1000 |
| 1287pio_addr=8804615847936 1288pio_latency=100000 |
| 1289power_model=Null |
| 1290system=system 1291time=Thu Jan 1 00:00:00 2009 1292tsunami=system.tsunami 1293year_is_bcd=false 1294pio=system.iobus.master[22] 1295 1296[system.tsunami.pchip] 1297type=TsunamiPChip 1298clk_domain=system.clk_domain 1299conf_base=8804649402368 1300conf_device_bits=8 1301conf_size=16777216 |
| 1302default_p_state=UNDEFINED |
| 1303eventq_index=0 |
| 1304p_state_clk_gate_bins=20 1305p_state_clk_gate_max=1000000000000 1306p_state_clk_gate_min=1000 |
| 1307pci_dma_base=0 1308pci_mem_base=8796093022208 1309pci_pio_base=8804615847936 1310pio_addr=8802535473152 1311pio_latency=100000 1312platform=system.tsunami |
| 1313power_model=Null |
| 1314system=system 1315tsunami=system.tsunami 1316pio=system.iobus.master[1] 1317 1318[system.tsunami.uart] 1319type=Uart8250 1320clk_domain=system.clk_domain |
| 1321default_p_state=UNDEFINED |
| 1322eventq_index=0 |
| 1323p_state_clk_gate_bins=20 1324p_state_clk_gate_max=1000000000000 1325p_state_clk_gate_min=1000 |
| 1326pio_addr=8804615848952 1327pio_latency=100000 1328platform=system.tsunami |
| 1329power_model=Null |
| 1330system=system 1331terminal=system.terminal 1332pio=system.iobus.master[23] 1333 1334[system.voltage_domain] 1335type=VoltageDomain 1336eventq_index=0 1337voltage=1.000000 1338 |