| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.955749 # Number of seconds simulated 4sim_ticks 1955749107000 # Number of ticks simulated 5final_tick 1955749107000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.959865 # Number of seconds simulated 4sim_ticks 1959865139500 # Number of ticks simulated 5final_tick 1959865139500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 473674 # Simulator instruction rate (inst/s) 8host_op_rate 473674 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15599111797 # Simulator tick rate (ticks/s) 10host_mem_usage 350548 # Number of bytes of host memory used 11host_seconds 125.38 # Real time elapsed on the host 12sim_insts 59387196 # Number of instructions simulated 13sim_ops 59387196 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 829760 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24747584 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 34368 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 397760 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28660288 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 829760 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 34368 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 864128 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7682240 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7682240 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 12965 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 386681 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 537 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 6215 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 447817 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120035 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120035 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 424267 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12653762 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1355397 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 17573 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 203380 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14654379 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 424267 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 17573 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 441840 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 3928029 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3928029 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3928029 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 424267 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12653762 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1355397 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 17573 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 203380 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18582408 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 447817 # Total number of read requests seen 52system.physmem.writeReqs 120035 # Total number of write requests seen 53system.physmem.cpureqs 571031 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28660288 # Total number of bytes read from memory 55system.physmem.bytesWritten 7682240 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28660288 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7682240 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 3170 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28165 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 28096 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28057 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 27780 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 28035 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 27969 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 27895 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 27905 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28089 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 28219 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 28029 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 27787 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 27999 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27702 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 27735 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7483 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7551 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7343 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7579 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7442 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7393 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7470 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7849 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7658 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7804 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7534 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 7353 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7502 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7171 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7272 # Track writes on a per bank basis | 7host_inst_rate 1047911 # Simulator instruction rate (inst/s) 8host_op_rate 1047910 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33678986014 # Simulator tick rate (ticks/s) 10host_mem_usage 308256 # Number of bytes of host memory used 11host_seconds 58.19 # Real time elapsed on the host 12sim_insts 60980539 # Number of instructions simulated 13sim_ops 60980539 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 833408 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24886848 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 338688 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28741440 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 833408 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7743232 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7743232 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13022 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 388857 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 5292 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 449085 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120988 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120988 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 425237 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12698245 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1352583 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 16132 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 172812 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14665009 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 425237 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 16132 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 441369 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 3950900 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3950900 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3950900 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 425237 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12698245 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1352583 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 16132 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 172812 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18615909 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 449085 # Total number of read requests seen 52system.physmem.writeReqs 120988 # Total number of write requests seen 53system.physmem.cpureqs 577269 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28741440 # Total number of bytes read from memory 55system.physmem.bytesWritten 7743232 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28741440 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7743232 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 62 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 7195 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28163 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 28468 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28046 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 27665 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 27762 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 28266 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 27878 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28077 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 27763 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 27645 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 28133 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 28181 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 28495 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 28656 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 28031 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7895 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7532 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7157 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7275 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7314 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7754 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7257 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7316 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7137 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7066 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7523 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 7683 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 8132 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 8336 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7679 # Track writes on a per bank basis |
| 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 93system.physmem.numWrRetry 9 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1955741979500 # Total gap between requests | 93system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1959858128500 # Total gap between requests |
| 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes | 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 101system.physmem.readPktSize::6 447817 # Categorize read packet sizes | 101system.physmem.readPktSize::6 449085 # Categorize read packet sizes |
| 102system.physmem.writePktSize::0 0 # Categorize write packet sizes 103system.physmem.writePktSize::1 0 # Categorize write packet sizes 104system.physmem.writePktSize::2 0 # Categorize write packet sizes 105system.physmem.writePktSize::3 0 # Categorize write packet sizes 106system.physmem.writePktSize::4 0 # Categorize write packet sizes 107system.physmem.writePktSize::5 0 # Categorize write packet sizes | 102system.physmem.writePktSize::0 0 # Categorize write packet sizes 103system.physmem.writePktSize::1 0 # Categorize write packet sizes 104system.physmem.writePktSize::2 0 # Categorize write packet sizes 105system.physmem.writePktSize::3 0 # Categorize write packet sizes 106system.physmem.writePktSize::4 0 # Categorize write packet sizes 107system.physmem.writePktSize::5 0 # Categorize write packet sizes |
| 108system.physmem.writePktSize::6 120035 # Categorize write packet sizes 109system.physmem.rdQLenPdf::0 407051 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::1 4718 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::2 3658 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::3 2202 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::5 2939 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::6 2694 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::7 2706 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::8 2651 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::9 2603 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::10 1540 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::11 1456 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::12 1432 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::13 1384 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::15 1403 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::16 1635 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::17 1524 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::18 905 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see | 108system.physmem.writePktSize::6 120988 # Categorize write packet sizes 109system.physmem.rdQLenPdf::0 408321 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::1 7066 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::2 5331 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::3 3258 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::4 3264 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::5 3003 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::6 1531 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::7 1505 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::8 1476 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::9 1451 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::10 1408 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::11 1429 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::12 1415 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::13 2044 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::14 2352 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::15 2212 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::17 461 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::18 203 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::19 95 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see |
| 130system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 130system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 141system.physmem.wrQLenPdf::0 3699 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 4286 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 4335 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 4844 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 5204 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 5206 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 5207 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 5219 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 5219 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 5219 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 5219 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 5219 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 5219 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 5219 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 5219 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 5219 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 5219 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 5219 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 5219 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 5218 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 5218 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 1520 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 1364 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 933 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 884 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 375 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 13 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see 173system.physmem.totQLat 4786344500 # Total cycles spent in queuing delays 174system.physmem.totMemAccLat 13401468250 # Sum of mem lat for all requests 175system.physmem.totBusLat 2238740000 # Total cycles spent in databus access 176system.physmem.totBankLat 6376383750 # Total cycles spent in bank access 177system.physmem.avgQLat 10689.82 # Average queueing delay per request 178system.physmem.avgBankLat 14241.01 # Average bank access latency per request | 141system.physmem.wrQLenPdf::0 3817 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 3924 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 4968 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 5260 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 5260 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 5260 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 5260 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 5260 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 5259 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 5260 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 5260 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 5260 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 5260 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 5260 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 5260 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 5260 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 5260 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 5260 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 5260 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 5260 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 5260 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 5260 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 5260 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 1444 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 1337 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 293 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see 173system.physmem.bytesPerActivate::samples 40092 # Bytes accessed per row activation 174system.physmem.bytesPerActivate::mean 909.867305 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::gmean 223.303664 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::stdev 2368.170282 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::64-67 14180 35.37% 35.37% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::128-131 6168 15.38% 50.75% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::192-195 3902 9.73% 60.49% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::256-259 2490 6.21% 66.70% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::320-323 1693 4.22% 70.92% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::384-387 1359 3.39% 74.31% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::448-451 1096 2.73% 77.04% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::512-515 872 2.17% 79.22% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::576-579 629 1.57% 80.79% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::640-643 634 1.58% 82.37% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::704-707 494 1.23% 83.60% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::768-771 427 1.07% 84.67% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::832-835 257 0.64% 85.31% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::896-899 230 0.57% 85.88% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::960-963 171 0.43% 86.31% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1024-1027 248 0.62% 86.93% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1088-1091 146 0.36% 87.29% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1152-1155 121 0.30% 87.59% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1216-1219 95 0.24% 87.83% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1280-1283 102 0.25% 88.08% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1344-1347 86 0.21% 88.30% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1408-1411 112 0.28% 88.58% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1472-1475 1028 2.56% 91.14% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1536-1539 203 0.51% 91.65% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1600-1603 118 0.29% 91.94% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1664-1667 93 0.23% 92.17% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1728-1731 68 0.17% 92.34% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1792-1795 46 0.11% 92.46% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1856-1859 38 0.09% 92.55% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1920-1923 17 0.04% 92.59% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1984-1987 17 0.04% 92.64% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2048-2051 32 0.08% 92.72% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.76% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2176-2179 9 0.02% 92.79% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2240-2243 6 0.01% 92.80% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2304-2307 5 0.01% 92.81% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.84% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2432-2435 7 0.02% 92.85% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.86% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.87% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2624-2627 8 0.02% 92.89% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.90% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2752-2755 2 0.00% 92.91% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2816-2819 4 0.01% 92.92% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.93% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.94% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3008-3011 2 0.00% 92.94% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3072-3075 1 0.00% 92.94% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3136-3139 2 0.00% 92.95% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3200-3203 2 0.00% 92.95% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3264-3267 2 0.00% 92.96% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3328-3331 3 0.01% 92.97% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3392-3395 2 0.00% 92.97% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3456-3459 2 0.00% 92.98% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.98% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3648-3651 1 0.00% 92.99% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3776-3779 1 0.00% 92.99% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.99% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3968-3971 2 0.00% 93.00% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4032-4035 4 0.01% 93.01% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4096-4099 2 0.00% 93.01% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4160-4163 2 0.00% 93.02% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4224-4227 3 0.01% 93.02% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4352-4355 1 0.00% 93.03% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4416-4419 1 0.00% 93.03% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4480-4483 3 0.01% 93.04% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4544-4547 1 0.00% 93.04% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4672-4675 1 0.00% 93.04% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4736-4739 1 0.00% 93.04% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4800-4803 1 0.00% 93.05% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4864-4867 1 0.00% 93.05% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4928-4931 1 0.00% 93.05% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5376-5379 1 0.00% 93.05% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5568-5571 1 0.00% 93.06% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5760-5763 2 0.00% 93.06% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::6144-6147 3 0.01% 93.07% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::6400-6403 1 0.00% 93.07% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::6784-6787 1 0.00% 93.07% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::6848-6851 1 0.00% 93.08% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::7168-7171 2 0.00% 93.08% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::7232-7235 1 0.00% 93.08% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::7296-7299 2 0.00% 93.09% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.09% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.09% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::7616-7619 2 0.00% 93.10% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::7680-7683 2 0.00% 93.10% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.11% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.11% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::7936-7939 2 0.00% 93.11% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.12% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::8128-8131 6 0.01% 93.14% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::8192-8195 2435 6.07% 99.21% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.21% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.21% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.22% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.22% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.22% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.22% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.23% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.23% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.23% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.23% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.24% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.24% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.24% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.24% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.28% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.29% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.29% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.29% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.30% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.30% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::16384-16387 243 0.61% 99.91% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::16448-16451 6 0.01% 99.92% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::16512-16515 10 0.02% 99.95% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.97% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::16704-16707 2 0.00% 99.97% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.98% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::16960-16963 1 0.00% 99.99% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::17152-17155 1 0.00% 100.00% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::total 40092 # Bytes accessed per row activation 303system.physmem.totQLat 3740449750 # Total cycles spent in queuing delays 304system.physmem.totMemAccLat 12011516000 # Sum of mem lat for all requests 305system.physmem.totBusLat 2245115000 # Total cycles spent in databus access 306system.physmem.totBankLat 6025951250 # Total cycles spent in bank access 307system.physmem.avgQLat 8330.20 # Average queueing delay per request 308system.physmem.avgBankLat 13420.14 # Average bank access latency per request |
| 179system.physmem.avgBusLat 5000.00 # Average bus latency per request | 309system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 180system.physmem.avgMemAccLat 29930.83 # Average memory access latency 181system.physmem.avgRdBW 14.65 # Average achieved read bandwidth in MB/s 182system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s 183system.physmem.avgConsumedRdBW 14.65 # Average consumed read bandwidth in MB/s 184system.physmem.avgConsumedWrBW 3.93 # Average consumed write bandwidth in MB/s | 310system.physmem.avgMemAccLat 26750.34 # Average memory access latency 311system.physmem.avgRdBW 14.67 # Average achieved read bandwidth in MB/s 312system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s 313system.physmem.avgConsumedRdBW 14.67 # Average consumed read bandwidth in MB/s 314system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s |
| 185system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 186system.physmem.busUtil 0.15 # Data bus utilization in percentage 187system.physmem.avgRdQLen 0.01 # Average read queue length over time | 315system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 316system.physmem.busUtil 0.15 # Data bus utilization in percentage 317system.physmem.avgRdQLen 0.01 # Average read queue length over time |
| 188system.physmem.avgWrQLen 6.57 # Average write queue length over time 189system.physmem.readRowHits 419819 # Number of row buffer hits during reads 190system.physmem.writeRowHits 92219 # Number of row buffer hits during writes 191system.physmem.readRowHitRate 93.76 # Row buffer hit rate for reads 192system.physmem.writeRowHitRate 76.83 # Row buffer hit rate for writes 193system.physmem.avgGap 3444105.12 # Average gap between requests 194system.l2c.replacements 340805 # number of replacements 195system.l2c.tagsinuse 65304.474621 # Cycle average of tags in use 196system.l2c.total_refs 2495359 # Total number of references to valid blocks. 197system.l2c.sampled_refs 405916 # Sample count of references to valid blocks. 198system.l2c.avg_refs 6.147476 # Average number of references to valid blocks. 199system.l2c.warmup_cycle 6939667751 # Cycle when the warmup percentage was hit. 200system.l2c.occ_blocks::writebacks 55622.298055 # Average occupied blocks per requestor 201system.l2c.occ_blocks::cpu0.inst 4855.652105 # Average occupied blocks per requestor 202system.l2c.occ_blocks::cpu0.data 4698.077679 # Average occupied blocks per requestor 203system.l2c.occ_blocks::cpu1.inst 117.035866 # Average occupied blocks per requestor 204system.l2c.occ_blocks::cpu1.data 11.410916 # Average occupied blocks per requestor 205system.l2c.occ_percent::writebacks 0.848729 # Average percentage of cache occupancy 206system.l2c.occ_percent::cpu0.inst 0.074091 # Average percentage of cache occupancy 207system.l2c.occ_percent::cpu0.data 0.071687 # Average percentage of cache occupancy 208system.l2c.occ_percent::cpu1.inst 0.001786 # Average percentage of cache occupancy 209system.l2c.occ_percent::cpu1.data 0.000174 # Average percentage of cache occupancy 210system.l2c.occ_percent::total 0.996467 # Average percentage of cache occupancy 211system.l2c.ReadReq_hits::cpu0.inst 903439 # number of ReadReq hits 212system.l2c.ReadReq_hits::cpu0.data 772649 # number of ReadReq hits 213system.l2c.ReadReq_hits::cpu1.inst 86404 # number of ReadReq hits 214system.l2c.ReadReq_hits::cpu1.data 33735 # number of ReadReq hits 215system.l2c.ReadReq_hits::total 1796227 # number of ReadReq hits 216system.l2c.Writeback_hits::writebacks 821961 # number of Writeback hits 217system.l2c.Writeback_hits::total 821961 # number of Writeback hits 218system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits 219system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits 220system.l2c.UpgradeReq_hits::total 223 # number of UpgradeReq hits 221system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits 222system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits 223system.l2c.SCUpgradeReq_hits::total 42 # number of SCUpgradeReq hits 224system.l2c.ReadExReq_hits::cpu0.data 172231 # number of ReadExReq hits 225system.l2c.ReadExReq_hits::cpu1.data 12736 # number of ReadExReq hits 226system.l2c.ReadExReq_hits::total 184967 # number of ReadExReq hits 227system.l2c.demand_hits::cpu0.inst 903439 # number of demand (read+write) hits 228system.l2c.demand_hits::cpu0.data 944880 # number of demand (read+write) hits 229system.l2c.demand_hits::cpu1.inst 86404 # number of demand (read+write) hits 230system.l2c.demand_hits::cpu1.data 46471 # number of demand (read+write) hits 231system.l2c.demand_hits::total 1981194 # number of demand (read+write) hits 232system.l2c.overall_hits::cpu0.inst 903439 # number of overall hits 233system.l2c.overall_hits::cpu0.data 944880 # number of overall hits 234system.l2c.overall_hits::cpu1.inst 86404 # number of overall hits 235system.l2c.overall_hits::cpu1.data 46471 # number of overall hits 236system.l2c.overall_hits::total 1981194 # number of overall hits 237system.l2c.ReadReq_misses::cpu0.inst 12965 # number of ReadReq misses 238system.l2c.ReadReq_misses::cpu0.data 271584 # number of ReadReq misses 239system.l2c.ReadReq_misses::cpu1.inst 548 # number of ReadReq misses 240system.l2c.ReadReq_misses::cpu1.data 188 # number of ReadReq misses 241system.l2c.ReadReq_misses::total 285285 # number of ReadReq misses 242system.l2c.UpgradeReq_misses::cpu0.data 2447 # number of UpgradeReq misses 243system.l2c.UpgradeReq_misses::cpu1.data 485 # number of UpgradeReq misses 244system.l2c.UpgradeReq_misses::total 2932 # number of UpgradeReq misses 245system.l2c.SCUpgradeReq_misses::cpu0.data 28 # number of SCUpgradeReq misses 246system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses 247system.l2c.SCUpgradeReq_misses::total 101 # number of SCUpgradeReq misses 248system.l2c.ReadExReq_misses::cpu0.data 115482 # number of ReadExReq misses 249system.l2c.ReadExReq_misses::cpu1.data 6045 # number of ReadExReq misses 250system.l2c.ReadExReq_misses::total 121527 # number of ReadExReq misses 251system.l2c.demand_misses::cpu0.inst 12965 # number of demand (read+write) misses 252system.l2c.demand_misses::cpu0.data 387066 # number of demand (read+write) misses 253system.l2c.demand_misses::cpu1.inst 548 # number of demand (read+write) misses 254system.l2c.demand_misses::cpu1.data 6233 # number of demand (read+write) misses 255system.l2c.demand_misses::total 406812 # number of demand (read+write) misses 256system.l2c.overall_misses::cpu0.inst 12965 # number of overall misses 257system.l2c.overall_misses::cpu0.data 387066 # number of overall misses 258system.l2c.overall_misses::cpu1.inst 548 # number of overall misses 259system.l2c.overall_misses::cpu1.data 6233 # number of overall misses 260system.l2c.overall_misses::total 406812 # number of overall misses 261system.l2c.ReadReq_miss_latency::cpu0.inst 808064500 # number of ReadReq miss cycles 262system.l2c.ReadReq_miss_latency::cpu0.data 11672931500 # number of ReadReq miss cycles 263system.l2c.ReadReq_miss_latency::cpu1.inst 35081000 # number of ReadReq miss cycles 264system.l2c.ReadReq_miss_latency::cpu1.data 14352500 # number of ReadReq miss cycles 265system.l2c.ReadReq_miss_latency::total 12530429500 # number of ReadReq miss cycles 266system.l2c.UpgradeReq_miss_latency::cpu0.data 1060000 # number of UpgradeReq miss cycles 267system.l2c.UpgradeReq_miss_latency::cpu1.data 227000 # number of UpgradeReq miss cycles 268system.l2c.UpgradeReq_miss_latency::total 1287000 # number of UpgradeReq miss cycles 269system.l2c.SCUpgradeReq_miss_latency::cpu0.data 22500 # number of SCUpgradeReq miss cycles 270system.l2c.SCUpgradeReq_miss_latency::cpu1.data 115000 # number of SCUpgradeReq miss cycles 271system.l2c.SCUpgradeReq_miss_latency::total 137500 # number of SCUpgradeReq miss cycles 272system.l2c.ReadExReq_miss_latency::cpu0.data 5534141500 # number of ReadExReq miss cycles 273system.l2c.ReadExReq_miss_latency::cpu1.data 342947000 # number of ReadExReq miss cycles 274system.l2c.ReadExReq_miss_latency::total 5877088500 # number of ReadExReq miss cycles 275system.l2c.demand_miss_latency::cpu0.inst 808064500 # number of demand (read+write) miss cycles 276system.l2c.demand_miss_latency::cpu0.data 17207073000 # number of demand (read+write) miss cycles 277system.l2c.demand_miss_latency::cpu1.inst 35081000 # number of demand (read+write) miss cycles 278system.l2c.demand_miss_latency::cpu1.data 357299500 # number of demand (read+write) miss cycles 279system.l2c.demand_miss_latency::total 18407518000 # number of demand (read+write) miss cycles 280system.l2c.overall_miss_latency::cpu0.inst 808064500 # number of overall miss cycles 281system.l2c.overall_miss_latency::cpu0.data 17207073000 # number of overall miss cycles 282system.l2c.overall_miss_latency::cpu1.inst 35081000 # number of overall miss cycles 283system.l2c.overall_miss_latency::cpu1.data 357299500 # number of overall miss cycles 284system.l2c.overall_miss_latency::total 18407518000 # number of overall miss cycles 285system.l2c.ReadReq_accesses::cpu0.inst 916404 # number of ReadReq accesses(hits+misses) 286system.l2c.ReadReq_accesses::cpu0.data 1044233 # number of ReadReq accesses(hits+misses) 287system.l2c.ReadReq_accesses::cpu1.inst 86952 # number of ReadReq accesses(hits+misses) 288system.l2c.ReadReq_accesses::cpu1.data 33923 # number of ReadReq accesses(hits+misses) 289system.l2c.ReadReq_accesses::total 2081512 # number of ReadReq accesses(hits+misses) 290system.l2c.Writeback_accesses::writebacks 821961 # number of Writeback accesses(hits+misses) 291system.l2c.Writeback_accesses::total 821961 # number of Writeback accesses(hits+misses) 292system.l2c.UpgradeReq_accesses::cpu0.data 2616 # number of UpgradeReq accesses(hits+misses) 293system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses) 294system.l2c.UpgradeReq_accesses::total 3155 # number of UpgradeReq accesses(hits+misses) 295system.l2c.SCUpgradeReq_accesses::cpu0.data 49 # number of SCUpgradeReq accesses(hits+misses) 296system.l2c.SCUpgradeReq_accesses::cpu1.data 94 # number of SCUpgradeReq accesses(hits+misses) 297system.l2c.SCUpgradeReq_accesses::total 143 # number of SCUpgradeReq accesses(hits+misses) 298system.l2c.ReadExReq_accesses::cpu0.data 287713 # number of ReadExReq accesses(hits+misses) 299system.l2c.ReadExReq_accesses::cpu1.data 18781 # number of ReadExReq accesses(hits+misses) 300system.l2c.ReadExReq_accesses::total 306494 # number of ReadExReq accesses(hits+misses) 301system.l2c.demand_accesses::cpu0.inst 916404 # number of demand (read+write) accesses 302system.l2c.demand_accesses::cpu0.data 1331946 # number of demand (read+write) accesses 303system.l2c.demand_accesses::cpu1.inst 86952 # number of demand (read+write) accesses 304system.l2c.demand_accesses::cpu1.data 52704 # number of demand (read+write) accesses 305system.l2c.demand_accesses::total 2388006 # number of demand (read+write) accesses 306system.l2c.overall_accesses::cpu0.inst 916404 # number of overall (read+write) accesses 307system.l2c.overall_accesses::cpu0.data 1331946 # number of overall (read+write) accesses 308system.l2c.overall_accesses::cpu1.inst 86952 # number of overall (read+write) accesses 309system.l2c.overall_accesses::cpu1.data 52704 # number of overall (read+write) accesses 310system.l2c.overall_accesses::total 2388006 # number of overall (read+write) accesses 311system.l2c.ReadReq_miss_rate::cpu0.inst 0.014148 # miss rate for ReadReq accesses 312system.l2c.ReadReq_miss_rate::cpu0.data 0.260080 # miss rate for ReadReq accesses 313system.l2c.ReadReq_miss_rate::cpu1.inst 0.006302 # miss rate for ReadReq accesses 314system.l2c.ReadReq_miss_rate::cpu1.data 0.005542 # miss rate for ReadReq accesses 315system.l2c.ReadReq_miss_rate::total 0.137057 # miss rate for ReadReq accesses 316system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935398 # miss rate for UpgradeReq accesses 317system.l2c.UpgradeReq_miss_rate::cpu1.data 0.899814 # miss rate for UpgradeReq accesses 318system.l2c.UpgradeReq_miss_rate::total 0.929319 # miss rate for UpgradeReq accesses 319system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.571429 # miss rate for SCUpgradeReq accesses 320system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776596 # miss rate for SCUpgradeReq accesses 321system.l2c.SCUpgradeReq_miss_rate::total 0.706294 # miss rate for SCUpgradeReq accesses 322system.l2c.ReadExReq_miss_rate::cpu0.data 0.401379 # miss rate for ReadExReq accesses 323system.l2c.ReadExReq_miss_rate::cpu1.data 0.321868 # miss rate for ReadExReq accesses 324system.l2c.ReadExReq_miss_rate::total 0.396507 # miss rate for ReadExReq accesses 325system.l2c.demand_miss_rate::cpu0.inst 0.014148 # miss rate for demand accesses 326system.l2c.demand_miss_rate::cpu0.data 0.290602 # miss rate for demand accesses 327system.l2c.demand_miss_rate::cpu1.inst 0.006302 # miss rate for demand accesses 328system.l2c.demand_miss_rate::cpu1.data 0.118264 # miss rate for demand accesses 329system.l2c.demand_miss_rate::total 0.170356 # miss rate for demand accesses 330system.l2c.overall_miss_rate::cpu0.inst 0.014148 # miss rate for overall accesses 331system.l2c.overall_miss_rate::cpu0.data 0.290602 # miss rate for overall accesses 332system.l2c.overall_miss_rate::cpu1.inst 0.006302 # miss rate for overall accesses 333system.l2c.overall_miss_rate::cpu1.data 0.118264 # miss rate for overall accesses 334system.l2c.overall_miss_rate::total 0.170356 # miss rate for overall accesses 335system.l2c.ReadReq_avg_miss_latency::cpu0.inst 62326.610104 # average ReadReq miss latency 336system.l2c.ReadReq_avg_miss_latency::cpu0.data 42980.924870 # average ReadReq miss latency 337system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64016.423358 # average ReadReq miss latency 338system.l2c.ReadReq_avg_miss_latency::cpu1.data 76343.085106 # average ReadReq miss latency 339system.l2c.ReadReq_avg_miss_latency::total 43922.496801 # average ReadReq miss latency 340system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 433.183490 # average UpgradeReq miss latency 341system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 468.041237 # average UpgradeReq miss latency 342system.l2c.UpgradeReq_avg_miss_latency::total 438.949523 # average UpgradeReq miss latency 343system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 803.571429 # average SCUpgradeReq miss latency 344system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1575.342466 # average SCUpgradeReq miss latency 345system.l2c.SCUpgradeReq_avg_miss_latency::total 1361.386139 # average SCUpgradeReq miss latency 346system.l2c.ReadExReq_avg_miss_latency::cpu0.data 47922.113403 # average ReadExReq miss latency 347system.l2c.ReadExReq_avg_miss_latency::cpu1.data 56732.340778 # average ReadExReq miss latency 348system.l2c.ReadExReq_avg_miss_latency::total 48360.352021 # average ReadExReq miss latency 349system.l2c.demand_avg_miss_latency::cpu0.inst 62326.610104 # average overall miss latency 350system.l2c.demand_avg_miss_latency::cpu0.data 44455.139434 # average overall miss latency 351system.l2c.demand_avg_miss_latency::cpu1.inst 64016.423358 # average overall miss latency 352system.l2c.demand_avg_miss_latency::cpu1.data 57323.840847 # average overall miss latency 353system.l2c.demand_avg_miss_latency::total 45248.217850 # average overall miss latency 354system.l2c.overall_avg_miss_latency::cpu0.inst 62326.610104 # average overall miss latency 355system.l2c.overall_avg_miss_latency::cpu0.data 44455.139434 # average overall miss latency 356system.l2c.overall_avg_miss_latency::cpu1.inst 64016.423358 # average overall miss latency 357system.l2c.overall_avg_miss_latency::cpu1.data 57323.840847 # average overall miss latency 358system.l2c.overall_avg_miss_latency::total 45248.217850 # average overall miss latency | 318system.physmem.avgWrQLen 10.21 # Average write queue length over time 319system.physmem.readRowHits 433314 # Number of row buffer hits during reads 320system.physmem.writeRowHits 96597 # Number of row buffer hits during writes 321system.physmem.readRowHitRate 96.50 # Row buffer hit rate for reads 322system.physmem.writeRowHitRate 79.84 # Row buffer hit rate for writes 323system.physmem.avgGap 3437907.30 # Average gap between requests 324system.membus.throughput 18676649 # Throughput (bytes/s) 325system.membus.trans_dist::ReadReq 292796 # Transaction distribution 326system.membus.trans_dist::ReadResp 292796 # Transaction distribution 327system.membus.trans_dist::WriteReq 14151 # Transaction distribution 328system.membus.trans_dist::WriteResp 14151 # Transaction distribution 329system.membus.trans_dist::Writeback 120988 # Transaction distribution 330system.membus.trans_dist::UpgradeReq 16779 # Transaction distribution 331system.membus.trans_dist::SCUpgradeReq 11846 # Transaction distribution 332system.membus.trans_dist::UpgradeResp 7198 # Transaction distribution 333system.membus.trans_dist::ReadExReq 164928 # Transaction distribution 334system.membus.trans_dist::ReadExResp 164057 # Transaction distribution 335system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42700 # Packet count per connected master and slave (bytes) 336system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931752 # Packet count per connected master and slave (bytes) 337system.membus.pkt_count_system.l2c.mem_side::total 974452 # Packet count per connected master and slave (bytes) 338system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) 339system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) 340system.membus.pkt_count::system.bridge.slave 42700 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count::system.physmem.port 1056418 # Packet count per connected master and slave (bytes) 342system.membus.pkt_count::total 1099118 # Packet count per connected master and slave (bytes) 343system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82626 # Cumulative packet size per connected master and slave (bytes) 344system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176512 # Cumulative packet size per connected master and slave (bytes) 345system.membus.tot_pkt_size_system.l2c.mem_side::total 31259138 # Cumulative packet size per connected master and slave (bytes) 346system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) 347system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) 348system.membus.tot_pkt_size::system.bridge.slave 82626 # Cumulative packet size per connected master and slave (bytes) 349system.membus.tot_pkt_size::system.physmem.port 36484672 # Cumulative packet size per connected master and slave (bytes) 350system.membus.tot_pkt_size::total 36567298 # Cumulative packet size per connected master and slave (bytes) 351system.membus.data_through_bus 36567298 # Total data (bytes) 352system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) 353system.membus.reqLayer0.occupancy 43346000 # Layer occupancy (ticks) 354system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 355system.membus.reqLayer1.occupancy 1579141500 # Layer occupancy (ticks) 356system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 357system.membus.respLayer1.occupancy 3832845053 # Layer occupancy (ticks) 358system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 359system.membus.respLayer2.occupancy 376210250 # Layer occupancy (ticks) 360system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 361system.l2c.replacements 342163 # number of replacements 362system.l2c.tagsinuse 65224.613124 # Cycle average of tags in use 363system.l2c.total_refs 2440483 # Total number of references to valid blocks. 364system.l2c.sampled_refs 407350 # Sample count of references to valid blocks. 365system.l2c.avg_refs 5.991121 # Average number of references to valid blocks. 366system.l2c.warmup_cycle 8355445750 # Cycle when the warmup percentage was hit. 367system.l2c.occ_blocks::writebacks 55361.728852 # Average occupied blocks per requestor 368system.l2c.occ_blocks::cpu0.inst 4802.377103 # Average occupied blocks per requestor 369system.l2c.occ_blocks::cpu0.data 4855.919486 # Average occupied blocks per requestor 370system.l2c.occ_blocks::cpu1.inst 161.173506 # Average occupied blocks per requestor 371system.l2c.occ_blocks::cpu1.data 43.414178 # Average occupied blocks per requestor 372system.l2c.occ_percent::writebacks 0.844753 # Average percentage of cache occupancy 373system.l2c.occ_percent::cpu0.inst 0.073278 # Average percentage of cache occupancy 374system.l2c.occ_percent::cpu0.data 0.074095 # Average percentage of cache occupancy 375system.l2c.occ_percent::cpu1.inst 0.002459 # Average percentage of cache occupancy 376system.l2c.occ_percent::cpu1.data 0.000662 # Average percentage of cache occupancy 377system.l2c.occ_percent::total 0.995249 # Average percentage of cache occupancy 378system.l2c.ReadReq_hits::cpu0.inst 678870 # number of ReadReq hits 379system.l2c.ReadReq_hits::cpu0.data 661225 # number of ReadReq hits 380system.l2c.ReadReq_hits::cpu1.inst 323259 # number of ReadReq hits 381system.l2c.ReadReq_hits::cpu1.data 109447 # number of ReadReq hits 382system.l2c.ReadReq_hits::total 1772801 # number of ReadReq hits 383system.l2c.Writeback_hits::writebacks 790404 # number of Writeback hits 384system.l2c.Writeback_hits::total 790404 # number of Writeback hits 385system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits 386system.l2c.UpgradeReq_hits::cpu1.data 565 # number of UpgradeReq hits 387system.l2c.UpgradeReq_hits::total 747 # number of UpgradeReq hits 388system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits 389system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits 390system.l2c.SCUpgradeReq_hits::total 61 # number of SCUpgradeReq hits 391system.l2c.ReadExReq_hits::cpu0.data 127727 # number of ReadExReq hits 392system.l2c.ReadExReq_hits::cpu1.data 43997 # number of ReadExReq hits 393system.l2c.ReadExReq_hits::total 171724 # number of ReadExReq hits 394system.l2c.demand_hits::cpu0.inst 678870 # number of demand (read+write) hits 395system.l2c.demand_hits::cpu0.data 788952 # number of demand (read+write) hits 396system.l2c.demand_hits::cpu1.inst 323259 # number of demand (read+write) hits 397system.l2c.demand_hits::cpu1.data 153444 # number of demand (read+write) hits 398system.l2c.demand_hits::total 1944525 # number of demand (read+write) hits 399system.l2c.overall_hits::cpu0.inst 678870 # number of overall hits 400system.l2c.overall_hits::cpu0.data 788952 # number of overall hits 401system.l2c.overall_hits::cpu1.inst 323259 # number of overall hits 402system.l2c.overall_hits::cpu1.data 153444 # number of overall hits 403system.l2c.overall_hits::total 1944525 # number of overall hits 404system.l2c.ReadReq_misses::cpu0.inst 13022 # number of ReadReq misses 405system.l2c.ReadReq_misses::cpu0.data 271666 # number of ReadReq misses 406system.l2c.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses 407system.l2c.ReadReq_misses::cpu1.data 241 # number of ReadReq misses 408system.l2c.ReadReq_misses::total 285434 # number of ReadReq misses 409system.l2c.UpgradeReq_misses::cpu0.data 2971 # number of UpgradeReq misses 410system.l2c.UpgradeReq_misses::cpu1.data 1796 # number of UpgradeReq misses 411system.l2c.UpgradeReq_misses::total 4767 # number of UpgradeReq misses 412system.l2c.SCUpgradeReq_misses::cpu0.data 957 # number of SCUpgradeReq misses 413system.l2c.SCUpgradeReq_misses::cpu1.data 952 # number of SCUpgradeReq misses 414system.l2c.SCUpgradeReq_misses::total 1909 # number of SCUpgradeReq misses 415system.l2c.ReadExReq_misses::cpu0.data 117966 # number of ReadExReq misses 416system.l2c.ReadExReq_misses::cpu1.data 5061 # number of ReadExReq misses 417system.l2c.ReadExReq_misses::total 123027 # number of ReadExReq misses 418system.l2c.demand_misses::cpu0.inst 13022 # number of demand (read+write) misses 419system.l2c.demand_misses::cpu0.data 389632 # number of demand (read+write) misses 420system.l2c.demand_misses::cpu1.inst 505 # number of demand (read+write) misses 421system.l2c.demand_misses::cpu1.data 5302 # number of demand (read+write) misses 422system.l2c.demand_misses::total 408461 # number of demand (read+write) misses 423system.l2c.overall_misses::cpu0.inst 13022 # number of overall misses 424system.l2c.overall_misses::cpu0.data 389632 # number of overall misses 425system.l2c.overall_misses::cpu1.inst 505 # number of overall misses 426system.l2c.overall_misses::cpu1.data 5302 # number of overall misses 427system.l2c.overall_misses::total 408461 # number of overall misses 428system.l2c.ReadReq_miss_latency::cpu0.inst 1040882000 # number of ReadReq miss cycles 429system.l2c.ReadReq_miss_latency::cpu0.data 16855181499 # number of ReadReq miss cycles 430system.l2c.ReadReq_miss_latency::cpu1.inst 39850000 # number of ReadReq miss cycles 431system.l2c.ReadReq_miss_latency::cpu1.data 21000500 # number of ReadReq miss cycles 432system.l2c.ReadReq_miss_latency::total 17956913999 # number of ReadReq miss cycles 433system.l2c.UpgradeReq_miss_latency::cpu0.data 1322500 # number of UpgradeReq miss cycles 434system.l2c.UpgradeReq_miss_latency::cpu1.data 10129500 # number of UpgradeReq miss cycles 435system.l2c.UpgradeReq_miss_latency::total 11452000 # number of UpgradeReq miss cycles 436system.l2c.SCUpgradeReq_miss_latency::cpu0.data 954000 # number of SCUpgradeReq miss cycles 437system.l2c.SCUpgradeReq_miss_latency::cpu1.data 204000 # number of SCUpgradeReq miss cycles 438system.l2c.SCUpgradeReq_miss_latency::total 1158000 # number of SCUpgradeReq miss cycles 439system.l2c.ReadExReq_miss_latency::cpu0.data 7822362000 # number of ReadExReq miss cycles 440system.l2c.ReadExReq_miss_latency::cpu1.data 373828000 # number of ReadExReq miss cycles 441system.l2c.ReadExReq_miss_latency::total 8196190000 # number of ReadExReq miss cycles 442system.l2c.demand_miss_latency::cpu0.inst 1040882000 # number of demand (read+write) miss cycles 443system.l2c.demand_miss_latency::cpu0.data 24677543499 # number of demand (read+write) miss cycles 444system.l2c.demand_miss_latency::cpu1.inst 39850000 # number of demand (read+write) miss cycles 445system.l2c.demand_miss_latency::cpu1.data 394828500 # number of demand (read+write) miss cycles 446system.l2c.demand_miss_latency::total 26153103999 # number of demand (read+write) miss cycles 447system.l2c.overall_miss_latency::cpu0.inst 1040882000 # number of overall miss cycles 448system.l2c.overall_miss_latency::cpu0.data 24677543499 # number of overall miss cycles 449system.l2c.overall_miss_latency::cpu1.inst 39850000 # number of overall miss cycles 450system.l2c.overall_miss_latency::cpu1.data 394828500 # number of overall miss cycles 451system.l2c.overall_miss_latency::total 26153103999 # number of overall miss cycles 452system.l2c.ReadReq_accesses::cpu0.inst 691892 # number of ReadReq accesses(hits+misses) 453system.l2c.ReadReq_accesses::cpu0.data 932891 # number of ReadReq accesses(hits+misses) 454system.l2c.ReadReq_accesses::cpu1.inst 323764 # number of ReadReq accesses(hits+misses) 455system.l2c.ReadReq_accesses::cpu1.data 109688 # number of ReadReq accesses(hits+misses) 456system.l2c.ReadReq_accesses::total 2058235 # number of ReadReq accesses(hits+misses) 457system.l2c.Writeback_accesses::writebacks 790404 # number of Writeback accesses(hits+misses) 458system.l2c.Writeback_accesses::total 790404 # number of Writeback accesses(hits+misses) 459system.l2c.UpgradeReq_accesses::cpu0.data 3153 # number of UpgradeReq accesses(hits+misses) 460system.l2c.UpgradeReq_accesses::cpu1.data 2361 # number of UpgradeReq accesses(hits+misses) 461system.l2c.UpgradeReq_accesses::total 5514 # number of UpgradeReq accesses(hits+misses) 462system.l2c.SCUpgradeReq_accesses::cpu0.data 995 # number of SCUpgradeReq accesses(hits+misses) 463system.l2c.SCUpgradeReq_accesses::cpu1.data 975 # number of SCUpgradeReq accesses(hits+misses) 464system.l2c.SCUpgradeReq_accesses::total 1970 # number of SCUpgradeReq accesses(hits+misses) 465system.l2c.ReadExReq_accesses::cpu0.data 245693 # number of ReadExReq accesses(hits+misses) 466system.l2c.ReadExReq_accesses::cpu1.data 49058 # number of ReadExReq accesses(hits+misses) 467system.l2c.ReadExReq_accesses::total 294751 # number of ReadExReq accesses(hits+misses) 468system.l2c.demand_accesses::cpu0.inst 691892 # number of demand (read+write) accesses 469system.l2c.demand_accesses::cpu0.data 1178584 # number of demand (read+write) accesses 470system.l2c.demand_accesses::cpu1.inst 323764 # number of demand (read+write) accesses 471system.l2c.demand_accesses::cpu1.data 158746 # number of demand (read+write) accesses 472system.l2c.demand_accesses::total 2352986 # number of demand (read+write) accesses 473system.l2c.overall_accesses::cpu0.inst 691892 # number of overall (read+write) accesses 474system.l2c.overall_accesses::cpu0.data 1178584 # number of overall (read+write) accesses 475system.l2c.overall_accesses::cpu1.inst 323764 # number of overall (read+write) accesses 476system.l2c.overall_accesses::cpu1.data 158746 # number of overall (read+write) accesses 477system.l2c.overall_accesses::total 2352986 # number of overall (read+write) accesses 478system.l2c.ReadReq_miss_rate::cpu0.inst 0.018821 # miss rate for ReadReq accesses 479system.l2c.ReadReq_miss_rate::cpu0.data 0.291209 # miss rate for ReadReq accesses 480system.l2c.ReadReq_miss_rate::cpu1.inst 0.001560 # miss rate for ReadReq accesses 481system.l2c.ReadReq_miss_rate::cpu1.data 0.002197 # miss rate for ReadReq accesses 482system.l2c.ReadReq_miss_rate::total 0.138679 # miss rate for ReadReq accesses 483system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942277 # miss rate for UpgradeReq accesses 484system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760695 # miss rate for UpgradeReq accesses 485system.l2c.UpgradeReq_miss_rate::total 0.864527 # miss rate for UpgradeReq accesses 486system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961809 # miss rate for SCUpgradeReq accesses 487system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976410 # miss rate for SCUpgradeReq accesses 488system.l2c.SCUpgradeReq_miss_rate::total 0.969036 # miss rate for SCUpgradeReq accesses 489system.l2c.ReadExReq_miss_rate::cpu0.data 0.480136 # miss rate for ReadExReq accesses 490system.l2c.ReadExReq_miss_rate::cpu1.data 0.103164 # miss rate for ReadExReq accesses 491system.l2c.ReadExReq_miss_rate::total 0.417393 # miss rate for ReadExReq accesses 492system.l2c.demand_miss_rate::cpu0.inst 0.018821 # miss rate for demand accesses 493system.l2c.demand_miss_rate::cpu0.data 0.330593 # miss rate for demand accesses 494system.l2c.demand_miss_rate::cpu1.inst 0.001560 # miss rate for demand accesses 495system.l2c.demand_miss_rate::cpu1.data 0.033399 # miss rate for demand accesses 496system.l2c.demand_miss_rate::total 0.173593 # miss rate for demand accesses 497system.l2c.overall_miss_rate::cpu0.inst 0.018821 # miss rate for overall accesses 498system.l2c.overall_miss_rate::cpu0.data 0.330593 # miss rate for overall accesses 499system.l2c.overall_miss_rate::cpu1.inst 0.001560 # miss rate for overall accesses 500system.l2c.overall_miss_rate::cpu1.data 0.033399 # miss rate for overall accesses 501system.l2c.overall_miss_rate::total 0.173593 # miss rate for overall accesses 502system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79932.575641 # average ReadReq miss latency 503system.l2c.ReadReq_avg_miss_latency::cpu0.data 62043.765134 # average ReadReq miss latency 504system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78910.891089 # average ReadReq miss latency 505system.l2c.ReadReq_avg_miss_latency::cpu1.data 87139.004149 # average ReadReq miss latency 506system.l2c.ReadReq_avg_miss_latency::total 62910.914604 # average ReadReq miss latency 507system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 445.136318 # average UpgradeReq miss latency 508system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5640.033408 # average UpgradeReq miss latency 509system.l2c.UpgradeReq_avg_miss_latency::total 2402.349486 # average UpgradeReq miss latency 510system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 996.865204 # average SCUpgradeReq miss latency 511system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 214.285714 # average SCUpgradeReq miss latency 512system.l2c.SCUpgradeReq_avg_miss_latency::total 606.600314 # average SCUpgradeReq miss latency 513system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66310.309750 # average ReadExReq miss latency 514system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73864.453665 # average ReadExReq miss latency 515system.l2c.ReadExReq_avg_miss_latency::total 66621.066920 # average ReadExReq miss latency 516system.l2c.demand_avg_miss_latency::cpu0.inst 79932.575641 # average overall miss latency 517system.l2c.demand_avg_miss_latency::cpu0.data 63335.515304 # average overall miss latency 518system.l2c.demand_avg_miss_latency::cpu1.inst 78910.891089 # average overall miss latency 519system.l2c.demand_avg_miss_latency::cpu1.data 74467.842324 # average overall miss latency 520system.l2c.demand_avg_miss_latency::total 64028.399282 # average overall miss latency 521system.l2c.overall_avg_miss_latency::cpu0.inst 79932.575641 # average overall miss latency 522system.l2c.overall_avg_miss_latency::cpu0.data 63335.515304 # average overall miss latency 523system.l2c.overall_avg_miss_latency::cpu1.inst 78910.891089 # average overall miss latency 524system.l2c.overall_avg_miss_latency::cpu1.data 74467.842324 # average overall miss latency 525system.l2c.overall_avg_miss_latency::total 64028.399282 # average overall miss latency |
| 359system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 362system.l2c.blocked::no_targets 0 # number of cycles access was blocked 363system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 364system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 365system.l2c.fast_writes 0 # number of fast writes performed 366system.l2c.cache_copies 0 # number of cache copies performed | 526system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 527system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 528system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 529system.l2c.blocked::no_targets 0 # number of cycles access was blocked 530system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 531system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 532system.l2c.fast_writes 0 # number of fast writes performed 533system.l2c.cache_copies 0 # number of cache copies performed |
| 367system.l2c.writebacks::writebacks 78515 # number of writebacks 368system.l2c.writebacks::total 78515 # number of writebacks | 534system.l2c.writebacks::writebacks 79468 # number of writebacks 535system.l2c.writebacks::total 79468 # number of writebacks |
| 369system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits 370system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 371system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 372system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 373system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 374system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits | 536system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits 537system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 538system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 539system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 540system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 541system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits |
| 375system.l2c.ReadReq_mshr_misses::cpu0.inst 12965 # number of ReadReq MSHR misses 376system.l2c.ReadReq_mshr_misses::cpu0.data 271584 # number of ReadReq MSHR misses 377system.l2c.ReadReq_mshr_misses::cpu1.inst 537 # number of ReadReq MSHR misses 378system.l2c.ReadReq_mshr_misses::cpu1.data 188 # number of ReadReq MSHR misses 379system.l2c.ReadReq_mshr_misses::total 285274 # number of ReadReq MSHR misses 380system.l2c.UpgradeReq_mshr_misses::cpu0.data 2447 # number of UpgradeReq MSHR misses 381system.l2c.UpgradeReq_mshr_misses::cpu1.data 485 # number of UpgradeReq MSHR misses 382system.l2c.UpgradeReq_mshr_misses::total 2932 # number of UpgradeReq MSHR misses 383system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 28 # number of SCUpgradeReq MSHR misses 384system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses 385system.l2c.SCUpgradeReq_mshr_misses::total 101 # number of SCUpgradeReq MSHR misses 386system.l2c.ReadExReq_mshr_misses::cpu0.data 115482 # number of ReadExReq MSHR misses 387system.l2c.ReadExReq_mshr_misses::cpu1.data 6045 # number of ReadExReq MSHR misses 388system.l2c.ReadExReq_mshr_misses::total 121527 # number of ReadExReq MSHR misses 389system.l2c.demand_mshr_misses::cpu0.inst 12965 # number of demand (read+write) MSHR misses 390system.l2c.demand_mshr_misses::cpu0.data 387066 # number of demand (read+write) MSHR misses 391system.l2c.demand_mshr_misses::cpu1.inst 537 # number of demand (read+write) MSHR misses 392system.l2c.demand_mshr_misses::cpu1.data 6233 # number of demand (read+write) MSHR misses 393system.l2c.demand_mshr_misses::total 406801 # number of demand (read+write) MSHR misses 394system.l2c.overall_mshr_misses::cpu0.inst 12965 # number of overall MSHR misses 395system.l2c.overall_mshr_misses::cpu0.data 387066 # number of overall MSHR misses 396system.l2c.overall_mshr_misses::cpu1.inst 537 # number of overall MSHR misses 397system.l2c.overall_mshr_misses::cpu1.data 6233 # number of overall MSHR misses 398system.l2c.overall_mshr_misses::total 406801 # number of overall MSHR misses 399system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 644929955 # number of ReadReq MSHR miss cycles 400system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8338657576 # number of ReadReq MSHR miss cycles 401system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 27777281 # number of ReadReq MSHR miss cycles 402system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12004183 # number of ReadReq MSHR miss cycles 403system.l2c.ReadReq_mshr_miss_latency::total 9023368995 # number of ReadReq MSHR miss cycles 404system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24640443 # number of UpgradeReq MSHR miss cycles 405system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4857984 # number of UpgradeReq MSHR miss cycles 406system.l2c.UpgradeReq_mshr_miss_latency::total 29498427 # number of UpgradeReq MSHR miss cycles 407system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 280028 # number of SCUpgradeReq MSHR miss cycles 408system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 730073 # number of SCUpgradeReq MSHR miss cycles 409system.l2c.SCUpgradeReq_mshr_miss_latency::total 1010101 # number of SCUpgradeReq MSHR miss cycles 410system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4108313953 # number of ReadExReq MSHR miss cycles 411system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 267375786 # number of ReadExReq MSHR miss cycles 412system.l2c.ReadExReq_mshr_miss_latency::total 4375689739 # number of ReadExReq MSHR miss cycles 413system.l2c.demand_mshr_miss_latency::cpu0.inst 644929955 # number of demand (read+write) MSHR miss cycles 414system.l2c.demand_mshr_miss_latency::cpu0.data 12446971529 # number of demand (read+write) MSHR miss cycles 415system.l2c.demand_mshr_miss_latency::cpu1.inst 27777281 # number of demand (read+write) MSHR miss cycles 416system.l2c.demand_mshr_miss_latency::cpu1.data 279379969 # number of demand (read+write) MSHR miss cycles 417system.l2c.demand_mshr_miss_latency::total 13399058734 # number of demand (read+write) MSHR miss cycles 418system.l2c.overall_mshr_miss_latency::cpu0.inst 644929955 # number of overall MSHR miss cycles 419system.l2c.overall_mshr_miss_latency::cpu0.data 12446971529 # number of overall MSHR miss cycles 420system.l2c.overall_mshr_miss_latency::cpu1.inst 27777281 # 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number of demand (read+write) MSHR miss cycles 585system.l2c.overall_mshr_miss_latency::cpu0.inst 877008002 # number of overall MSHR miss cycles 586system.l2c.overall_mshr_miss_latency::cpu0.data 19891471761 # number of overall MSHR miss cycles 587system.l2c.overall_mshr_miss_latency::cpu1.inst 32847250 # number of overall MSHR miss cycles 588system.l2c.overall_mshr_miss_latency::cpu1.data 329030260 # number of overall MSHR miss cycles 589system.l2c.overall_mshr_miss_latency::total 21130357273 # number of overall MSHR miss cycles 590system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373163000 # number of ReadReq MSHR uncacheable cycles 591system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17611000 # number of ReadReq MSHR uncacheable cycles 592system.l2c.ReadReq_mshr_uncacheable_latency::total 1390774000 # number of ReadReq MSHR uncacheable cycles 593system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2158791500 # number of WriteReq MSHR uncacheable cycles 594system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 683644500 # number of WriteReq MSHR uncacheable cycles 595system.l2c.WriteReq_mshr_uncacheable_latency::total 2842436000 # number of WriteReq MSHR uncacheable cycles 596system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3531954500 # number of overall MSHR uncacheable cycles 597system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701255500 # number of overall MSHR uncacheable cycles 598system.l2c.overall_mshr_uncacheable_latency::total 4233210000 # number of overall MSHR uncacheable cycles 599system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for ReadReq accesses 600system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.291209 # mshr miss rate for ReadReq accesses 601system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for ReadReq accesses 602system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002197 # mshr miss rate for ReadReq accesses 603system.l2c.ReadReq_mshr_miss_rate::total 0.138674 # mshr miss rate for ReadReq accesses 604system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942277 # mshr miss rate for UpgradeReq accesses 605system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.760695 # mshr miss rate for UpgradeReq accesses 606system.l2c.UpgradeReq_mshr_miss_rate::total 0.864527 # mshr miss rate for UpgradeReq accesses 607system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961809 # mshr miss rate for SCUpgradeReq accesses 608system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976410 # mshr miss rate for SCUpgradeReq accesses 609system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969036 # mshr miss rate for SCUpgradeReq accesses 610system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480136 # mshr miss rate for ReadExReq accesses 611system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.103164 # mshr miss rate for ReadExReq accesses 612system.l2c.ReadExReq_mshr_miss_rate::total 0.417393 # mshr miss rate for ReadExReq accesses 613system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for demand accesses 614system.l2c.demand_mshr_miss_rate::cpu0.data 0.330593 # mshr miss rate for demand accesses 615system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for demand accesses 616system.l2c.demand_mshr_miss_rate::cpu1.data 0.033399 # mshr miss rate for demand accesses 617system.l2c.demand_mshr_miss_rate::total 0.173588 # mshr miss rate for demand accesses 618system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018821 # mshr miss rate for overall accesses 619system.l2c.overall_mshr_miss_rate::cpu0.data 0.330593 # mshr miss rate for overall accesses 620system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001526 # mshr miss rate for overall accesses 621system.l2c.overall_mshr_miss_rate::cpu1.data 0.033399 # mshr miss rate for overall accesses 622system.l2c.overall_mshr_miss_rate::total 0.173588 # mshr miss rate for overall accesses 623system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average ReadReq mshr miss latency 624system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49783.695785 # average ReadReq mshr miss latency 625system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average ReadReq mshr miss latency 626system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74738.589212 # average ReadReq mshr miss latency 627system.l2c.ReadReq_avg_mshr_miss_latency::total 50635.039051 # average ReadReq mshr miss latency 628system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10062.426119 # average UpgradeReq mshr miss latency 629system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.600780 # average UpgradeReq mshr miss latency 630system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10047.044892 # average UpgradeReq mshr miss latency 631system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.421108 # average SCUpgradeReq mshr miss latency |
| 465system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency | 632system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency |
| 466system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 467system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35575.361987 # average ReadExReq mshr miss latency 468system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44230.899256 # average ReadExReq mshr miss latency 469system.l2c.ReadExReq_avg_mshr_miss_latency::total 36005.906004 # average ReadExReq mshr miss latency 470system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49743.922484 # average overall mshr miss latency 471system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32157.232950 # average overall mshr miss latency 472system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51726.780261 # average overall mshr miss latency 473system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44822.712819 # average overall mshr miss latency 474system.l2c.demand_avg_mshr_miss_latency::total 32937.624868 # average overall mshr miss latency 475system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49743.922484 # average overall mshr miss latency 476system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32157.232950 # average overall mshr miss latency 477system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51726.780261 # average overall mshr miss latency 478system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44822.712819 # average overall mshr miss latency 479system.l2c.overall_avg_mshr_miss_latency::total 32937.624868 # average overall mshr miss latency | 633system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.738607 # average SCUpgradeReq mshr miss latency 634system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53972.621450 # average ReadExReq mshr miss latency 635system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61453.914246 # average ReadExReq mshr miss latency 636system.l2c.ReadExReq_avg_mshr_miss_latency::total 54280.381721 # average ReadExReq mshr miss latency 637system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average overall mshr miss latency 638system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51051.945839 # average overall mshr miss latency 639system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average overall mshr miss latency 640system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62057.763108 # average overall mshr miss latency 641system.l2c.demand_avg_mshr_miss_latency::total 51733.032863 # average overall mshr miss latency 642system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67348.180157 # average overall mshr miss latency 643system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51051.945839 # average overall mshr miss latency 644system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66492.408907 # average overall mshr miss latency 645system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62057.763108 # average overall mshr miss latency 646system.l2c.overall_avg_mshr_miss_latency::total 51733.032863 # average overall mshr miss latency |
| 480system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 481system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 482system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 483system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 484system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 485system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 486system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 487system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 488system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 489system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 490system.iocache.replacements 41694 # number of replacements | 647system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 648system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 649system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 650system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 651system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 652system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 653system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 654system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 655system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 656system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 657system.iocache.replacements 41694 # number of replacements |
| 491system.iocache.tagsinuse 0.572926 # Cycle average of tags in use | 658system.iocache.tagsinuse 0.570240 # Cycle average of tags in use |
| 492system.iocache.total_refs 0 # Total number of references to valid blocks. 493system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. 494system.iocache.avg_refs 0 # Average number of references to valid blocks. | 659system.iocache.total_refs 0 # Total number of references to valid blocks. 660system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. 661system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 495system.iocache.warmup_cycle 1747683301000 # Cycle when the warmup percentage was hit. 496system.iocache.occ_blocks::tsunami.ide 0.572926 # Average occupied blocks per requestor 497system.iocache.occ_percent::tsunami.ide 0.035808 # Average percentage of cache occupancy 498system.iocache.occ_percent::total 0.035808 # Average percentage of cache occupancy | 662system.iocache.warmup_cycle 1753558786000 # Cycle when the warmup percentage was hit. 663system.iocache.occ_blocks::tsunami.ide 0.570240 # Average occupied blocks per requestor 664system.iocache.occ_percent::tsunami.ide 0.035640 # Average percentage of cache occupancy 665system.iocache.occ_percent::total 0.035640 # Average percentage of cache occupancy |
| 499system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 500system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 501system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 502system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 503system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 504system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 505system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 506system.iocache.overall_misses::total 41726 # number of overall misses | 666system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 667system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 668system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 669system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 670system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 671system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 672system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 673system.iocache.overall_misses::total 41726 # number of overall misses |
| 507system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles 508system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles 509system.iocache.WriteReq_miss_latency::tsunami.ide 10655791911 # number of WriteReq miss cycles 510system.iocache.WriteReq_miss_latency::total 10655791911 # number of WriteReq miss cycles 511system.iocache.demand_miss_latency::tsunami.ide 10676834909 # number of demand (read+write) miss cycles 512system.iocache.demand_miss_latency::total 10676834909 # number of demand (read+write) miss cycles 513system.iocache.overall_miss_latency::tsunami.ide 10676834909 # number of overall miss cycles 514system.iocache.overall_miss_latency::total 10676834909 # number of overall miss cycles | 674system.iocache.ReadReq_miss_latency::tsunami.ide 21457883 # number of ReadReq miss cycles 675system.iocache.ReadReq_miss_latency::total 21457883 # number of ReadReq miss cycles 676system.iocache.WriteReq_miss_latency::tsunami.ide 10416109037 # number of WriteReq miss cycles 677system.iocache.WriteReq_miss_latency::total 10416109037 # number of WriteReq miss cycles 678system.iocache.demand_miss_latency::tsunami.ide 10437566920 # number of demand (read+write) miss cycles 679system.iocache.demand_miss_latency::total 10437566920 # number of demand (read+write) miss cycles 680system.iocache.overall_miss_latency::tsunami.ide 10437566920 # number of overall miss cycles 681system.iocache.overall_miss_latency::total 10437566920 # number of overall miss cycles |
| 515system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 516system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 517system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 518system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 519system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 520system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 521system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 522system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 523system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 524system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 525system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 526system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 527system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 528system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 529system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 530system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 682system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 683system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 684system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 685system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 686system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 687system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 688system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 689system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 690system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 691system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 692system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 693system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 694system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 695system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 696system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 697system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 531system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120936.770115 # average ReadReq miss latency 532system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency 533system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256444.741793 # average WriteReq miss latency 534system.iocache.WriteReq_avg_miss_latency::total 256444.741793 # average WriteReq miss latency 535system.iocache.demand_avg_miss_latency::tsunami.ide 255879.665173 # average overall miss latency 536system.iocache.demand_avg_miss_latency::total 255879.665173 # average overall miss latency 537system.iocache.overall_avg_miss_latency::tsunami.ide 255879.665173 # average overall miss latency 538system.iocache.overall_avg_miss_latency::total 255879.665173 # average overall miss latency 539system.iocache.blocked_cycles::no_mshrs 285803 # number of cycles access was blocked | 698system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123321.166667 # average ReadReq miss latency 699system.iocache.ReadReq_avg_miss_latency::total 123321.166667 # average ReadReq miss latency 700system.iocache.WriteReq_avg_miss_latency::tsunami.ide 250676.478557 # average WriteReq miss latency 701system.iocache.WriteReq_avg_miss_latency::total 250676.478557 # average WriteReq miss latency 702system.iocache.demand_avg_miss_latency::tsunami.ide 250145.399032 # average overall miss latency 703system.iocache.demand_avg_miss_latency::total 250145.399032 # average overall miss latency 704system.iocache.overall_avg_miss_latency::tsunami.ide 250145.399032 # average overall miss latency 705system.iocache.overall_avg_miss_latency::total 250145.399032 # average overall miss latency 706system.iocache.blocked_cycles::no_mshrs 272227 # number of cycles access was blocked |
| 540system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 707system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 541system.iocache.blocked::no_mshrs 27265 # number of cycles access was blocked | 708system.iocache.blocked::no_mshrs 27211 # number of cycles access was blocked |
| 542system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 709system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 543system.iocache.avg_blocked_cycles::no_mshrs 10.482413 # average number of cycles each access was blocked | 710system.iocache.avg_blocked_cycles::no_mshrs 10.004300 # average number of cycles each access was blocked |
| 544system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 545system.iocache.fast_writes 0 # number of fast writes performed 546system.iocache.cache_copies 0 # number of cache copies performed 547system.iocache.writebacks::writebacks 41520 # number of writebacks 548system.iocache.writebacks::total 41520 # number of writebacks 549system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 550system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses 551system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 552system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 553system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses 554system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses 555system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses 556system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses | 711system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 712system.iocache.fast_writes 0 # number of fast writes performed 713system.iocache.cache_copies 0 # number of cache copies performed 714system.iocache.writebacks::writebacks 41520 # number of writebacks 715system.iocache.writebacks::total 41520 # number of writebacks 716system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 717system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses 718system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 719system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 720system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses 721system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses 722system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses 723system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses |
| 557system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles 558system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles 559system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8493795674 # number of WriteReq MSHR miss cycles 560system.iocache.WriteReq_mshr_miss_latency::total 8493795674 # number of WriteReq MSHR miss cycles 561system.iocache.demand_mshr_miss_latency::tsunami.ide 8505789923 # number of demand (read+write) MSHR miss cycles 562system.iocache.demand_mshr_miss_latency::total 8505789923 # number of demand (read+write) MSHR miss cycles 563system.iocache.overall_mshr_miss_latency::tsunami.ide 8505789923 # number of overall MSHR miss cycles 564system.iocache.overall_mshr_miss_latency::total 8505789923 # number of overall MSHR miss cycles | 724system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12409133 # number of ReadReq MSHR miss cycles 725system.iocache.ReadReq_mshr_miss_latency::total 12409133 # number of ReadReq MSHR miss cycles 726system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8254729537 # number of WriteReq MSHR miss cycles 727system.iocache.WriteReq_mshr_miss_latency::total 8254729537 # number of WriteReq MSHR miss cycles 728system.iocache.demand_mshr_miss_latency::tsunami.ide 8267138670 # number of demand (read+write) MSHR miss cycles 729system.iocache.demand_mshr_miss_latency::total 8267138670 # number of demand (read+write) MSHR miss cycles 730system.iocache.overall_mshr_miss_latency::tsunami.ide 8267138670 # number of overall MSHR miss cycles 731system.iocache.overall_mshr_miss_latency::total 8267138670 # number of overall MSHR miss cycles |
| 565system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 566system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 567system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 568system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 569system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 570system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 571system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 572system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 732system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 733system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 734system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 735system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 736system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 737system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 738system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 739system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 573system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency 574system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency 575system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204413.642520 # average WriteReq mshr miss latency 576system.iocache.WriteReq_avg_mshr_miss_latency::total 204413.642520 # average WriteReq mshr miss latency 577system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203848.677635 # average overall mshr miss latency 578system.iocache.demand_avg_mshr_miss_latency::total 203848.677635 # average overall mshr miss latency 579system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203848.677635 # average overall mshr miss latency 580system.iocache.overall_avg_mshr_miss_latency::total 203848.677635 # average overall mshr miss latency | 740system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71316.856322 # average ReadReq mshr miss latency 741system.iocache.ReadReq_avg_mshr_miss_latency::total 71316.856322 # average ReadReq mshr miss latency 742system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 198660.221818 # average WriteReq mshr miss latency 743system.iocache.WriteReq_avg_mshr_miss_latency::total 198660.221818 # average WriteReq mshr miss latency 744system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198129.192110 # average overall mshr miss latency 745system.iocache.demand_avg_mshr_miss_latency::total 198129.192110 # average overall mshr miss latency 746system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198129.192110 # average overall mshr miss latency 747system.iocache.overall_avg_mshr_miss_latency::total 198129.192110 # average overall mshr miss latency |
| 581system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 582system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 583system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 584system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 585system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 586system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 587system.disk0.dma_write_txs 395 # Number of DMA write transactions. 588system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 589system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 590system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 591system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 592system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 593system.disk2.dma_write_txs 1 # Number of DMA write transactions. 594system.cpu0.dtb.fetch_hits 0 # ITB hits 595system.cpu0.dtb.fetch_misses 0 # ITB misses 596system.cpu0.dtb.fetch_acv 0 # ITB acv 597system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 748system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 749system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 750system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 751system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 752system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 753system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 754system.disk0.dma_write_txs 395 # Number of DMA write transactions. 755system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 756system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 757system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 758system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 759system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 760system.disk2.dma_write_txs 1 # Number of DMA write transactions. 761system.cpu0.dtb.fetch_hits 0 # ITB hits 762system.cpu0.dtb.fetch_misses 0 # ITB misses 763system.cpu0.dtb.fetch_acv 0 # ITB acv 764system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 598system.cpu0.dtb.read_hits 8641604 # DTB read hits 599system.cpu0.dtb.read_misses 7443 # DTB read misses | 765system.cpu0.dtb.read_hits 7504093 # DTB read hits 766system.cpu0.dtb.read_misses 7765 # DTB read misses |
| 600system.cpu0.dtb.read_acv 210 # DTB read access violations | 767system.cpu0.dtb.read_acv 210 # DTB read access violations |
| 601system.cpu0.dtb.read_accesses 490673 # DTB read accesses 602system.cpu0.dtb.write_hits 6049321 # DTB write hits 603system.cpu0.dtb.write_misses 813 # DTB write misses 604system.cpu0.dtb.write_acv 134 # DTB write access violations 605system.cpu0.dtb.write_accesses 187452 # DTB write accesses 606system.cpu0.dtb.data_hits 14690925 # DTB hits 607system.cpu0.dtb.data_misses 8256 # DTB misses 608system.cpu0.dtb.data_acv 344 # DTB access violations 609system.cpu0.dtb.data_accesses 678125 # DTB accesses 610system.cpu0.itb.fetch_hits 3853653 # ITB hits 611system.cpu0.itb.fetch_misses 3871 # ITB misses | 768system.cpu0.dtb.read_accesses 524069 # DTB read accesses 769system.cpu0.dtb.write_hits 5095666 # DTB write hits 770system.cpu0.dtb.write_misses 910 # DTB write misses 771system.cpu0.dtb.write_acv 133 # DTB write access violations 772system.cpu0.dtb.write_accesses 202595 # DTB write accesses 773system.cpu0.dtb.data_hits 12599759 # DTB hits 774system.cpu0.dtb.data_misses 8675 # DTB misses 775system.cpu0.dtb.data_acv 343 # DTB access violations 776system.cpu0.dtb.data_accesses 726664 # DTB accesses 777system.cpu0.itb.fetch_hits 3641096 # ITB hits 778system.cpu0.itb.fetch_misses 3984 # ITB misses |
| 612system.cpu0.itb.fetch_acv 184 # ITB acv | 779system.cpu0.itb.fetch_acv 184 # ITB acv |
| 613system.cpu0.itb.fetch_accesses 3857524 # ITB accesses | 780system.cpu0.itb.fetch_accesses 3645080 # ITB accesses |
| 614system.cpu0.itb.read_hits 0 # DTB read hits 615system.cpu0.itb.read_misses 0 # DTB read misses 616system.cpu0.itb.read_acv 0 # DTB read access violations 617system.cpu0.itb.read_accesses 0 # DTB read accesses 618system.cpu0.itb.write_hits 0 # DTB write hits 619system.cpu0.itb.write_misses 0 # DTB write misses 620system.cpu0.itb.write_acv 0 # DTB write access violations 621system.cpu0.itb.write_accesses 0 # DTB write accesses 622system.cpu0.itb.data_hits 0 # DTB hits 623system.cpu0.itb.data_misses 0 # DTB misses 624system.cpu0.itb.data_acv 0 # DTB access violations 625system.cpu0.itb.data_accesses 0 # DTB accesses | 781system.cpu0.itb.read_hits 0 # DTB read hits 782system.cpu0.itb.read_misses 0 # DTB read misses 783system.cpu0.itb.read_acv 0 # DTB read access violations 784system.cpu0.itb.read_accesses 0 # DTB read accesses 785system.cpu0.itb.write_hits 0 # DTB write hits 786system.cpu0.itb.write_misses 0 # DTB write misses 787system.cpu0.itb.write_acv 0 # DTB write access violations 788system.cpu0.itb.write_accesses 0 # DTB write accesses 789system.cpu0.itb.data_hits 0 # DTB hits 790system.cpu0.itb.data_misses 0 # DTB misses 791system.cpu0.itb.data_acv 0 # DTB access violations 792system.cpu0.itb.data_accesses 0 # DTB accesses |
| 626system.cpu0.numCycles 3910164768 # number of cpu cycles simulated | 793system.cpu0.numCycles 3919730279 # number of cpu cycles simulated |
| 627system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 628system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 794system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 795system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 629system.cpu0.committedInsts 54125350 # Number of instructions committed 630system.cpu0.committedOps 54125350 # Number of ops (including micro ops) committed 631system.cpu0.num_int_alu_accesses 50093853 # Number of integer alu accesses 632system.cpu0.num_fp_alu_accesses 294168 # Number of float alu accesses 633system.cpu0.num_func_calls 1428171 # number of times a function call or return occured 634system.cpu0.num_conditional_control_insts 6241814 # number of instructions that are conditional controls 635system.cpu0.num_int_insts 50093853 # number of integer instructions 636system.cpu0.num_fp_insts 294168 # number of float instructions 637system.cpu0.num_int_register_reads 68603455 # number of times the integer registers were read 638system.cpu0.num_int_register_writes 37120934 # number of times the integer registers were written 639system.cpu0.num_fp_register_reads 143452 # number of times the floating registers were read 640system.cpu0.num_fp_register_writes 146554 # number of times the floating registers were written 641system.cpu0.num_mem_refs 14736943 # number of memory refs 642system.cpu0.num_load_insts 8672910 # Number of load instructions 643system.cpu0.num_store_insts 6064033 # Number of store instructions 644system.cpu0.num_idle_cycles 3679227117.452844 # Number of idle cycles 645system.cpu0.num_busy_cycles 230937650.547156 # Number of busy cycles 646system.cpu0.not_idle_fraction 0.059061 # Percentage of non-idle cycles 647system.cpu0.idle_fraction 0.940939 # Percentage of idle cycles | 796system.cpu0.committedInsts 47851975 # Number of instructions committed 797system.cpu0.committedOps 47851975 # Number of ops (including micro ops) committed 798system.cpu0.num_int_alu_accesses 44398232 # Number of integer alu accesses 799system.cpu0.num_fp_alu_accesses 209056 # Number of float alu accesses 800system.cpu0.num_func_calls 1198231 # number of times a function call or return occured 801system.cpu0.num_conditional_control_insts 5625657 # number of instructions that are conditional controls 802system.cpu0.num_int_insts 44398232 # number of integer instructions 803system.cpu0.num_fp_insts 209056 # number of float instructions 804system.cpu0.num_int_register_reads 61087554 # number of times the integer registers were read 805system.cpu0.num_int_register_writes 33073995 # number of times the integer registers were written 806system.cpu0.num_fp_register_reads 102127 # number of times the floating registers were read 807system.cpu0.num_fp_register_writes 103890 # number of times the floating registers were written 808system.cpu0.num_mem_refs 12640550 # number of memory refs 809system.cpu0.num_load_insts 7531710 # Number of load instructions 810system.cpu0.num_store_insts 5108840 # Number of store instructions 811system.cpu0.num_idle_cycles 3699529015.998113 # Number of idle cycles 812system.cpu0.num_busy_cycles 220201263.001888 # Number of busy cycles 813system.cpu0.not_idle_fraction 0.056178 # Percentage of non-idle cycles 814system.cpu0.idle_fraction 0.943822 # Percentage of idle cycles |
| 648system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 815system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 649system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed 650system.cpu0.kern.inst.hwrei 203014 # number of hwrei instructions executed 651system.cpu0.kern.ipl_count::0 72751 40.62% 40.62% # number of times we switched to this ipl 652system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl 653system.cpu0.kern.ipl_count::22 1976 1.10% 41.80% # number of times we switched to this ipl 654system.cpu0.kern.ipl_count::30 7 0.00% 41.80% # number of times we switched to this ipl 655system.cpu0.kern.ipl_count::31 104234 58.20% 100.00% # number of times we switched to this ipl 656system.cpu0.kern.ipl_count::total 179099 # number of times we switched to this ipl 657system.cpu0.kern.ipl_good::0 71384 49.27% 49.27% # number of times we switched to this ipl from a different ipl 658system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl 659system.cpu0.kern.ipl_good::22 1976 1.36% 50.73% # number of times we switched to this ipl from a different ipl 660system.cpu0.kern.ipl_good::30 7 0.00% 50.73% # number of times we switched to this ipl from a different ipl 661system.cpu0.kern.ipl_good::31 71377 49.27% 100.00% # number of times we switched to this ipl from a different ipl 662system.cpu0.kern.ipl_good::total 144875 # number of times we switched to this ipl from a different ipl 663system.cpu0.kern.ipl_ticks::0 1898825619000 97.12% 97.12% # number of cycles we spent at this ipl 664system.cpu0.kern.ipl_ticks::21 94636000 0.00% 97.13% # number of cycles we spent at this ipl 665system.cpu0.kern.ipl_ticks::22 768885000 0.04% 97.17% # number of cycles we spent at this ipl 666system.cpu0.kern.ipl_ticks::30 5899500 0.00% 97.17% # number of cycles we spent at this ipl 667system.cpu0.kern.ipl_ticks::31 55387314500 2.83% 100.00% # number of cycles we spent at this ipl 668system.cpu0.kern.ipl_ticks::total 1955082354000 # number of cycles we spent at this ipl 669system.cpu0.kern.ipl_used::0 0.981210 # fraction of swpipl calls that actually changed the ipl | 816system.cpu0.kern.inst.quiesce 6830 # number of quiesce instructions executed 817system.cpu0.kern.inst.hwrei 164217 # number of hwrei instructions executed 818system.cpu0.kern.ipl_count::0 56358 40.22% 40.22% # number of times we switched to this ipl 819system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl 820system.cpu0.kern.ipl_count::22 1973 1.41% 41.72% # number of times we switched to this ipl 821system.cpu0.kern.ipl_count::30 445 0.32% 42.04% # number of times we switched to this ipl 822system.cpu0.kern.ipl_count::31 81223 57.96% 100.00% # number of times we switched to this ipl 823system.cpu0.kern.ipl_count::total 140130 # number of times we switched to this ipl 824system.cpu0.kern.ipl_good::0 55870 49.08% 49.08% # number of times we switched to this ipl from a different ipl 825system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl 826system.cpu0.kern.ipl_good::22 1973 1.73% 50.92% # number of times we switched to this ipl from a different ipl 827system.cpu0.kern.ipl_good::30 445 0.39% 51.31% # number of times we switched to this ipl from a different ipl 828system.cpu0.kern.ipl_good::31 55425 48.69% 100.00% # number of times we switched to this ipl from a different ipl 829system.cpu0.kern.ipl_good::total 113844 # number of times we switched to this ipl from a different ipl 830system.cpu0.kern.ipl_ticks::0 1901694919500 97.03% 97.03% # number of cycles we spent at this ipl 831system.cpu0.kern.ipl_ticks::21 94927000 0.00% 97.04% # number of cycles we spent at this ipl 832system.cpu0.kern.ipl_ticks::22 766727000 0.04% 97.08% # number of cycles we spent at this ipl 833system.cpu0.kern.ipl_ticks::30 329552000 0.02% 97.09% # number of cycles we spent at this ipl 834system.cpu0.kern.ipl_ticks::31 56978256500 2.91% 100.00% # number of cycles we spent at this ipl 835system.cpu0.kern.ipl_ticks::total 1959864382000 # number of cycles we spent at this ipl 836system.cpu0.kern.ipl_used::0 0.991341 # fraction of swpipl calls that actually changed the ipl |
| 670system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 671system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 672system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 837system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 838system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 839system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 673system.cpu0.kern.ipl_used::31 0.684777 # fraction of swpipl calls that actually changed the ipl 674system.cpu0.kern.ipl_used::total 0.808910 # fraction of swpipl calls that actually changed the ipl 675system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 676system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 677system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 678system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 679system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 680system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 681system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 682system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed 683system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed 684system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed 685system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed 686system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed 687system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed 688system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed 689system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed 690system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed 691system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed 692system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed 693system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed 694system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed 695system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed 696system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed 697system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed 698system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 699system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 700system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 701system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 702system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 703system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 704system.cpu0.kern.syscall::total 222 # number of syscalls executed | 840system.cpu0.kern.ipl_used::31 0.682381 # fraction of swpipl calls that actually changed the ipl 841system.cpu0.kern.ipl_used::total 0.812417 # fraction of swpipl calls that actually changed the ipl 842system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed 843system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed 844system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed 845system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed 846system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed 847system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed 848system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed 849system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed 850system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed 851system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed 852system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed 853system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed 854system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed 855system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed 856system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed 857system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed 858system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed 859system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed 860system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed 861system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed 862system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed 863system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed 864system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed 865system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed 866system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed 867system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed 868system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed 869system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed 870system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed 871system.cpu0.kern.syscall::total 234 # number of syscalls executed |
| 705system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 872system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 706system.cpu0.kern.callpal::wripir 89 0.05% 0.05% # number of callpals executed 707system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed 708system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed 709system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed 710system.cpu0.kern.callpal::swpctx 3897 2.07% 2.12% # number of callpals executed 711system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed 712system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed 713system.cpu0.kern.callpal::swpipl 172231 91.49% 93.64% # number of callpals executed 714system.cpu0.kern.callpal::rdps 6679 3.55% 97.19% # number of callpals executed 715system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed 716system.cpu0.kern.callpal::wrusp 3 0.00% 97.19% # number of callpals executed 717system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed 718system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed 719system.cpu0.kern.callpal::rti 4753 2.52% 99.73% # number of callpals executed 720system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed 721system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed 722system.cpu0.kern.callpal::total 188243 # number of callpals executed 723system.cpu0.kern.mode_switch::kernel 7307 # number of protection mode switches 724system.cpu0.kern.mode_switch::user 1284 # number of protection mode switches | 873system.cpu0.kern.callpal::wripir 528 0.36% 0.36% # number of callpals executed 874system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed 875system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed 876system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed 877system.cpu0.kern.callpal::swpctx 3061 2.06% 2.42% # number of callpals executed 878system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed 879system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed 880system.cpu0.kern.callpal::swpipl 133182 89.70% 92.16% # number of callpals executed 881system.cpu0.kern.callpal::rdps 6700 4.51% 96.67% # number of callpals executed 882system.cpu0.kern.callpal::wrkgp 1 0.00% 96.67% # number of callpals executed 883system.cpu0.kern.callpal::wrusp 4 0.00% 96.67% # number of callpals executed 884system.cpu0.kern.callpal::rdusp 9 0.01% 96.68% # number of callpals executed 885system.cpu0.kern.callpal::whami 2 0.00% 96.68% # number of callpals executed 886system.cpu0.kern.callpal::rti 4398 2.96% 99.64% # number of callpals executed 887system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed 888system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed 889system.cpu0.kern.callpal::total 148480 # number of callpals executed 890system.cpu0.kern.mode_switch::kernel 6996 # number of protection mode switches 891system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches |
| 725system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 892system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 726system.cpu0.kern.mode_good::kernel 1284 727system.cpu0.kern.mode_good::user 1284 | 893system.cpu0.kern.mode_good::kernel 1372 894system.cpu0.kern.mode_good::user 1373 |
| 728system.cpu0.kern.mode_good::idle 0 | 895system.cpu0.kern.mode_good::idle 0 |
| 729system.cpu0.kern.mode_switch_good::kernel 0.175722 # fraction of useful protection mode switches | 896system.cpu0.kern.mode_switch_good::kernel 0.196112 # fraction of useful protection mode switches |
| 730system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 731system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 897system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 898system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 732system.cpu0.kern.mode_switch_good::total 0.298917 # fraction of useful protection mode switches 733system.cpu0.kern.mode_ticks::kernel 1951356000500 99.82% 99.82% # number of ticks spent at the given mode 734system.cpu0.kern.mode_ticks::user 3486973000 0.18% 100.00% # number of ticks spent at the given mode | 899system.cpu0.kern.mode_switch_good::total 0.327996 # fraction of useful protection mode switches 900system.cpu0.kern.mode_ticks::kernel 1956039363000 99.80% 99.80% # number of ticks spent at the given mode 901system.cpu0.kern.mode_ticks::user 3825014500 0.20% 100.00% # number of ticks spent at the given mode |
| 735system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 902system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 736system.cpu0.kern.swap_context 3898 # number of times the context was actually changed | 903system.cpu0.kern.swap_context 3062 # number of times the context was actually changed |
| 737system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 738system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 739system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 740system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 741system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 742system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 743system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 744system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 760system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 761system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 762system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 763system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 764system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 765system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 766system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 767system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 904system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 905system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 906system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 907system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 908system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 909system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 910system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 911system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 927system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 928system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 929system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 930system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 931system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 932system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 933system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 934system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 768system.cpu0.icache.replacements 915791 # number of replacements 769system.cpu0.icache.tagsinuse 509.170825 # Cycle average of tags in use 770system.cpu0.icache.total_refs 53217526 # Total number of references to valid blocks. 771system.cpu0.icache.sampled_refs 916303 # Sample count of references to valid blocks. 772system.cpu0.icache.avg_refs 58.078524 # Average number of references to valid blocks. 773system.cpu0.icache.warmup_cycle 32591402000 # Cycle when the warmup percentage was hit. 774system.cpu0.icache.occ_blocks::cpu0.inst 509.170825 # Average occupied blocks per requestor 775system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy 776system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy 777system.cpu0.icache.ReadReq_hits::cpu0.inst 53217526 # number of ReadReq hits 778system.cpu0.icache.ReadReq_hits::total 53217526 # number of ReadReq hits 779system.cpu0.icache.demand_hits::cpu0.inst 53217526 # number of demand (read+write) hits 780system.cpu0.icache.demand_hits::total 53217526 # number of demand (read+write) hits 781system.cpu0.icache.overall_hits::cpu0.inst 53217526 # number of overall hits 782system.cpu0.icache.overall_hits::total 53217526 # number of overall hits 783system.cpu0.icache.ReadReq_misses::cpu0.inst 916424 # number of ReadReq misses 784system.cpu0.icache.ReadReq_misses::total 916424 # number of ReadReq misses 785system.cpu0.icache.demand_misses::cpu0.inst 916424 # number of demand (read+write) misses 786system.cpu0.icache.demand_misses::total 916424 # number of demand (read+write) misses 787system.cpu0.icache.overall_misses::cpu0.inst 916424 # number of overall misses 788system.cpu0.icache.overall_misses::total 916424 # number of overall misses 789system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12661489500 # number of ReadReq miss cycles 790system.cpu0.icache.ReadReq_miss_latency::total 12661489500 # number of ReadReq miss cycles 791system.cpu0.icache.demand_miss_latency::cpu0.inst 12661489500 # number of demand (read+write) miss cycles 792system.cpu0.icache.demand_miss_latency::total 12661489500 # number of demand (read+write) miss cycles 793system.cpu0.icache.overall_miss_latency::cpu0.inst 12661489500 # number of overall miss cycles 794system.cpu0.icache.overall_miss_latency::total 12661489500 # number of overall miss cycles 795system.cpu0.icache.ReadReq_accesses::cpu0.inst 54133950 # number of ReadReq accesses(hits+misses) 796system.cpu0.icache.ReadReq_accesses::total 54133950 # number of ReadReq accesses(hits+misses) 797system.cpu0.icache.demand_accesses::cpu0.inst 54133950 # number of demand (read+write) accesses 798system.cpu0.icache.demand_accesses::total 54133950 # number of demand (read+write) accesses 799system.cpu0.icache.overall_accesses::cpu0.inst 54133950 # number of overall (read+write) accesses 800system.cpu0.icache.overall_accesses::total 54133950 # number of overall (read+write) accesses 801system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016929 # miss rate for ReadReq accesses 802system.cpu0.icache.ReadReq_miss_rate::total 0.016929 # miss rate for ReadReq accesses 803system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016929 # miss rate for demand accesses 804system.cpu0.icache.demand_miss_rate::total 0.016929 # miss rate for demand accesses 805system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016929 # miss rate for overall accesses 806system.cpu0.icache.overall_miss_rate::total 0.016929 # miss rate for overall accesses 807system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13816.191523 # average ReadReq miss latency 808system.cpu0.icache.ReadReq_avg_miss_latency::total 13816.191523 # average ReadReq miss latency 809system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13816.191523 # average overall miss latency 810system.cpu0.icache.demand_avg_miss_latency::total 13816.191523 # average overall miss latency 811system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13816.191523 # average overall miss latency 812system.cpu0.icache.overall_avg_miss_latency::total 13816.191523 # average overall miss latency | 935system.toL2Bus.throughput 103923821 # Throughput (bytes/s) 936system.toL2Bus.trans_dist::ReadReq 2101274 # Transaction distribution 937system.toL2Bus.trans_dist::ReadResp 2101259 # Transaction distribution 938system.toL2Bus.trans_dist::WriteReq 14151 # Transaction distribution 939system.toL2Bus.trans_dist::WriteResp 14151 # Transaction distribution 940system.toL2Bus.trans_dist::Writeback 790404 # Transaction distribution 941system.toL2Bus.trans_dist::UpgradeReq 17004 # Transaction distribution 942system.toL2Bus.trans_dist::SCUpgradeReq 11907 # Transaction distribution 943system.toL2Bus.trans_dist::UpgradeResp 28911 # Transaction distribution 944system.toL2Bus.trans_dist::ReadExReq 338243 # Transaction distribution 945system.toL2Bus.trans_dist::ReadExResp 296693 # Transaction distribution 946system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1383805 # Packet count per connected master and slave (bytes) 947system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3109039 # Packet count per connected master and slave (bytes) 948system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 647529 # Packet count per connected master and slave (bytes) 949system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 472865 # Packet count per connected master and slave (bytes) 950system.toL2Bus.pkt_count 5613238 # Packet count per connected master and slave (bytes) 951system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 44281088 # Cumulative packet size per connected master and slave (bytes) 952system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118941040 # Cumulative packet size per connected master and slave (bytes) 953system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 20720896 # Cumulative packet size per connected master and slave (bytes) 954system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 17326866 # Cumulative packet size per connected master and slave (bytes) 955system.toL2Bus.tot_pkt_size 201269890 # Cumulative packet size per connected master and slave (bytes) 956system.toL2Bus.data_through_bus 201259586 # Total data (bytes) 957system.toL2Bus.snoop_data_through_bus 2417088 # Total snoop data (bytes) 958system.toL2Bus.reqLayer0.occupancy 4784493652 # Layer occupancy (ticks) 959system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 960system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) 961system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 962system.toL2Bus.respLayer0.occupancy 3113609997 # Layer occupancy (ticks) 963system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 964system.toL2Bus.respLayer1.occupancy 5406966495 # Layer occupancy (ticks) 965system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) 966system.toL2Bus.respLayer2.occupancy 1456953977 # Layer occupancy (ticks) 967system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) 968system.toL2Bus.respLayer3.occupancy 808879499 # Layer occupancy (ticks) 969system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 970system.iobus.throughput 1400220 # Throughput (bytes/s) 971system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 972system.iobus.trans_dist::ReadResp 7373 # Transaction distribution 973system.iobus.trans_dist::WriteReq 55703 # Transaction distribution 974system.iobus.trans_dist::WriteResp 55703 # Transaction distribution 975system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14090 # Packet count per connected master and slave (bytes) 976system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) 977system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 978system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 979system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 980system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 981system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 982system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 983system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 984system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 985system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 986system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 987system.iobus.pkt_count_system.bridge.master::total 42700 # Packet count per connected master and slave (bytes) 988system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 989system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 990system.iobus.pkt_count::system.tsunami.cchip.pio 14090 # Packet count per connected master and slave (bytes) 991system.iobus.pkt_count::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) 992system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 993system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 994system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 995system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 996system.iobus.pkt_count::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 997system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 998system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 999system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1000system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1001system.iobus.pkt_count::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 1002system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1003system.iobus.pkt_count::total 126152 # Packet count per connected master and slave (bytes) 1004system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56360 # Cumulative packet size per connected master and slave (bytes) 1005system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) 1006system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1007system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1008system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1009system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1010system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 1011system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1012system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1013system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1014system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1015system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1016system.iobus.tot_pkt_size_system.bridge.master::total 82626 # Cumulative packet size per connected master and slave (bytes) 1017system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 1018system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 1019system.iobus.tot_pkt_size::system.tsunami.cchip.pio 56360 # Cumulative packet size per connected master and slave (bytes) 1020system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) 1021system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1022system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1023system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1024system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1025system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 1026system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1027system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1028system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1029system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1030system.iobus.tot_pkt_size::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 1031system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1032system.iobus.tot_pkt_size::total 2744242 # Cumulative packet size per connected master and slave (bytes) 1033system.iobus.data_through_bus 2744242 # Total data (bytes) 1034system.iobus.reqLayer0.occupancy 13445000 # Layer occupancy (ticks) 1035system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1036system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) 1037system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1038system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1039system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1040system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1041system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1042system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 1043system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1044system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 1045system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1046system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) 1047system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1048system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1049system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1050system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1051system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1052system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1053system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1054system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1055system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1056system.iobus.reqLayer29.occupancy 378246920 # Layer occupancy (ticks) 1057system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1058system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1059system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1060system.iobus.respLayer0.occupancy 28549000 # Layer occupancy (ticks) 1061system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1062system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks) 1063system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1064system.cpu0.icache.replacements 691283 # number of replacements 1065system.cpu0.icache.tagsinuse 508.523038 # Cycle average of tags in use 1066system.cpu0.icache.total_refs 47169081 # Total number of references to valid blocks. 1067system.cpu0.icache.sampled_refs 691795 # Sample count of references to valid blocks. 1068system.cpu0.icache.avg_refs 68.183611 # Average number of references to valid blocks. 1069system.cpu0.icache.warmup_cycle 38900732000 # Cycle when the warmup percentage was hit. 1070system.cpu0.icache.occ_blocks::cpu0.inst 508.523038 # Average occupied blocks per requestor 1071system.cpu0.icache.occ_percent::cpu0.inst 0.993209 # Average percentage of cache occupancy 1072system.cpu0.icache.occ_percent::total 0.993209 # Average percentage of cache occupancy 1073system.cpu0.icache.ReadReq_hits::cpu0.inst 47169081 # number of ReadReq hits 1074system.cpu0.icache.ReadReq_hits::total 47169081 # number of ReadReq hits 1075system.cpu0.icache.demand_hits::cpu0.inst 47169081 # number of demand (read+write) hits 1076system.cpu0.icache.demand_hits::total 47169081 # number of demand (read+write) hits 1077system.cpu0.icache.overall_hits::cpu0.inst 47169081 # number of overall hits 1078system.cpu0.icache.overall_hits::total 47169081 # number of overall hits 1079system.cpu0.icache.ReadReq_misses::cpu0.inst 691913 # number of ReadReq misses 1080system.cpu0.icache.ReadReq_misses::total 691913 # number of ReadReq misses 1081system.cpu0.icache.demand_misses::cpu0.inst 691913 # number of demand (read+write) misses 1082system.cpu0.icache.demand_misses::total 691913 # number of demand (read+write) misses 1083system.cpu0.icache.overall_misses::cpu0.inst 691913 # number of overall misses 1084system.cpu0.icache.overall_misses::total 691913 # number of overall misses 1085system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9946018500 # number of ReadReq miss cycles 1086system.cpu0.icache.ReadReq_miss_latency::total 9946018500 # number of ReadReq miss cycles 1087system.cpu0.icache.demand_miss_latency::cpu0.inst 9946018500 # number of demand (read+write) miss cycles 1088system.cpu0.icache.demand_miss_latency::total 9946018500 # number of demand (read+write) miss cycles 1089system.cpu0.icache.overall_miss_latency::cpu0.inst 9946018500 # number of overall miss cycles 1090system.cpu0.icache.overall_miss_latency::total 9946018500 # number of overall miss cycles 1091system.cpu0.icache.ReadReq_accesses::cpu0.inst 47860994 # number of ReadReq accesses(hits+misses) 1092system.cpu0.icache.ReadReq_accesses::total 47860994 # number of ReadReq accesses(hits+misses) 1093system.cpu0.icache.demand_accesses::cpu0.inst 47860994 # number of demand (read+write) accesses 1094system.cpu0.icache.demand_accesses::total 47860994 # number of demand (read+write) accesses 1095system.cpu0.icache.overall_accesses::cpu0.inst 47860994 # number of overall (read+write) accesses 1096system.cpu0.icache.overall_accesses::total 47860994 # number of overall (read+write) accesses 1097system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014457 # miss rate for ReadReq accesses 1098system.cpu0.icache.ReadReq_miss_rate::total 0.014457 # miss rate for ReadReq accesses 1099system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014457 # miss rate for demand accesses 1100system.cpu0.icache.demand_miss_rate::total 0.014457 # miss rate for demand accesses 1101system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014457 # miss rate for overall accesses 1102system.cpu0.icache.overall_miss_rate::total 0.014457 # miss rate for overall accesses 1103system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14374.666324 # average ReadReq miss latency 1104system.cpu0.icache.ReadReq_avg_miss_latency::total 14374.666324 # average ReadReq miss latency 1105system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14374.666324 # average overall miss latency 1106system.cpu0.icache.demand_avg_miss_latency::total 14374.666324 # average overall miss latency 1107system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14374.666324 # average overall miss latency 1108system.cpu0.icache.overall_avg_miss_latency::total 14374.666324 # average overall miss latency |
| 813system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 814system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 815system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 816system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 817system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 818system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 819system.cpu0.icache.fast_writes 0 # number of fast writes performed 820system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1109system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1110system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1111system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1112system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1113system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1114system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1115system.cpu0.icache.fast_writes 0 # number of fast writes performed 1116system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 821system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 916424 # number of ReadReq MSHR misses 822system.cpu0.icache.ReadReq_mshr_misses::total 916424 # number of ReadReq MSHR misses 823system.cpu0.icache.demand_mshr_misses::cpu0.inst 916424 # number of demand (read+write) MSHR misses 824system.cpu0.icache.demand_mshr_misses::total 916424 # number of demand (read+write) MSHR misses 825system.cpu0.icache.overall_mshr_misses::cpu0.inst 916424 # number of overall MSHR misses 826system.cpu0.icache.overall_mshr_misses::total 916424 # number of overall MSHR misses 827system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10828641500 # number of ReadReq MSHR miss cycles 828system.cpu0.icache.ReadReq_mshr_miss_latency::total 10828641500 # number of ReadReq MSHR miss cycles 829system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10828641500 # number of demand (read+write) MSHR miss cycles 830system.cpu0.icache.demand_mshr_miss_latency::total 10828641500 # number of demand (read+write) MSHR miss cycles 831system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10828641500 # number of overall MSHR miss cycles 832system.cpu0.icache.overall_mshr_miss_latency::total 10828641500 # number of overall MSHR miss cycles 833system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for ReadReq accesses 834system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016929 # mshr miss rate for ReadReq accesses 835system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for demand accesses 836system.cpu0.icache.demand_mshr_miss_rate::total 0.016929 # mshr miss rate for demand accesses 837system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016929 # mshr miss rate for overall accesses 838system.cpu0.icache.overall_mshr_miss_rate::total 0.016929 # mshr miss rate for overall accesses 839system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average ReadReq mshr miss latency 840system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11816.191523 # average ReadReq mshr miss latency 841system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average overall mshr miss latency 842system.cpu0.icache.demand_avg_mshr_miss_latency::total 11816.191523 # average overall mshr miss latency 843system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11816.191523 # average overall mshr miss latency 844system.cpu0.icache.overall_avg_mshr_miss_latency::total 11816.191523 # average overall mshr miss latency | 1117system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 691913 # number of ReadReq MSHR misses 1118system.cpu0.icache.ReadReq_mshr_misses::total 691913 # number of ReadReq MSHR misses 1119system.cpu0.icache.demand_mshr_misses::cpu0.inst 691913 # number of demand (read+write) MSHR misses 1120system.cpu0.icache.demand_mshr_misses::total 691913 # number of demand (read+write) MSHR misses 1121system.cpu0.icache.overall_mshr_misses::cpu0.inst 691913 # number of overall MSHR misses 1122system.cpu0.icache.overall_mshr_misses::total 691913 # number of overall MSHR misses 1123system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8562191003 # number of ReadReq MSHR miss cycles 1124system.cpu0.icache.ReadReq_mshr_miss_latency::total 8562191003 # number of ReadReq MSHR miss cycles 1125system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8562191003 # number of demand (read+write) MSHR miss cycles 1126system.cpu0.icache.demand_mshr_miss_latency::total 8562191003 # number of demand (read+write) MSHR miss cycles 1127system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8562191003 # number of overall MSHR miss cycles 1128system.cpu0.icache.overall_mshr_miss_latency::total 8562191003 # number of overall MSHR miss cycles 1129system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for ReadReq accesses 1130system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014457 # mshr miss rate for ReadReq accesses 1131system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for demand accesses 1132system.cpu0.icache.demand_mshr_miss_rate::total 0.014457 # mshr miss rate for demand accesses 1133system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014457 # mshr miss rate for overall accesses 1134system.cpu0.icache.overall_mshr_miss_rate::total 0.014457 # mshr miss rate for overall accesses 1135system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average ReadReq mshr miss latency 1136system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12374.664160 # average ReadReq mshr miss latency 1137system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average overall mshr miss latency 1138system.cpu0.icache.demand_avg_mshr_miss_latency::total 12374.664160 # average overall mshr miss latency 1139system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average overall mshr miss latency 1140system.cpu0.icache.overall_avg_mshr_miss_latency::total 12374.664160 # average overall mshr miss latency |
| 845system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1141system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 846system.cpu0.dcache.replacements 1338546 # number of replacements 847system.cpu0.dcache.tagsinuse 506.515538 # Cycle average of tags in use 848system.cpu0.dcache.total_refs 13360558 # Total number of references to valid blocks. 849system.cpu0.dcache.sampled_refs 1338960 # Sample count of references to valid blocks. 850system.cpu0.dcache.avg_refs 9.978310 # Average number of references to valid blocks. 851system.cpu0.dcache.warmup_cycle 94365000 # Cycle when the warmup percentage was hit. 852system.cpu0.dcache.occ_blocks::cpu0.data 506.515538 # Average occupied blocks per requestor 853system.cpu0.dcache.occ_percent::cpu0.data 0.989288 # Average percentage of cache occupancy 854system.cpu0.dcache.occ_percent::total 0.989288 # Average percentage of cache occupancy 855system.cpu0.dcache.ReadReq_hits::cpu0.data 7428425 # number of ReadReq hits 856system.cpu0.dcache.ReadReq_hits::total 7428425 # number of ReadReq hits 857system.cpu0.dcache.WriteReq_hits::cpu0.data 5564911 # number of WriteReq hits 858system.cpu0.dcache.WriteReq_hits::total 5564911 # number of WriteReq hits 859system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176719 # number of LoadLockedReq hits 860system.cpu0.dcache.LoadLockedReq_hits::total 176719 # number of LoadLockedReq hits 861system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191683 # number of StoreCondReq hits 862system.cpu0.dcache.StoreCondReq_hits::total 191683 # number of StoreCondReq hits 863system.cpu0.dcache.demand_hits::cpu0.data 12993336 # number of demand (read+write) hits 864system.cpu0.dcache.demand_hits::total 12993336 # number of demand (read+write) hits 865system.cpu0.dcache.overall_hits::cpu0.data 12993336 # number of overall hits 866system.cpu0.dcache.overall_hits::total 12993336 # number of overall hits 867system.cpu0.dcache.ReadReq_misses::cpu0.data 1036642 # number of ReadReq misses 868system.cpu0.dcache.ReadReq_misses::total 1036642 # number of ReadReq misses 869system.cpu0.dcache.WriteReq_misses::cpu0.data 291308 # number of WriteReq misses 870system.cpu0.dcache.WriteReq_misses::total 291308 # number of WriteReq misses 871system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16366 # number of LoadLockedReq misses 872system.cpu0.dcache.LoadLockedReq_misses::total 16366 # number of LoadLockedReq misses 873system.cpu0.dcache.StoreCondReq_misses::cpu0.data 435 # number of StoreCondReq misses 874system.cpu0.dcache.StoreCondReq_misses::total 435 # number of StoreCondReq misses 875system.cpu0.dcache.demand_misses::cpu0.data 1327950 # number of demand (read+write) misses 876system.cpu0.dcache.demand_misses::total 1327950 # number of demand (read+write) misses 877system.cpu0.dcache.overall_misses::cpu0.data 1327950 # number of overall misses 878system.cpu0.dcache.overall_misses::total 1327950 # number of overall misses 879system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22380575500 # number of ReadReq miss cycles 880system.cpu0.dcache.ReadReq_miss_latency::total 22380575500 # number of ReadReq miss cycles 881system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8193151000 # number of WriteReq miss cycles 882system.cpu0.dcache.WriteReq_miss_latency::total 8193151000 # number of WriteReq miss cycles 883system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 214111000 # number of LoadLockedReq miss cycles 884system.cpu0.dcache.LoadLockedReq_miss_latency::total 214111000 # number of LoadLockedReq miss cycles 885system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2551500 # number of StoreCondReq miss cycles 886system.cpu0.dcache.StoreCondReq_miss_latency::total 2551500 # number of StoreCondReq miss cycles 887system.cpu0.dcache.demand_miss_latency::cpu0.data 30573726500 # number of demand (read+write) miss cycles 888system.cpu0.dcache.demand_miss_latency::total 30573726500 # number of demand (read+write) miss cycles 889system.cpu0.dcache.overall_miss_latency::cpu0.data 30573726500 # number of overall miss cycles 890system.cpu0.dcache.overall_miss_latency::total 30573726500 # number of overall miss cycles 891system.cpu0.dcache.ReadReq_accesses::cpu0.data 8465067 # number of ReadReq accesses(hits+misses) 892system.cpu0.dcache.ReadReq_accesses::total 8465067 # number of ReadReq accesses(hits+misses) 893system.cpu0.dcache.WriteReq_accesses::cpu0.data 5856219 # number of WriteReq accesses(hits+misses) 894system.cpu0.dcache.WriteReq_accesses::total 5856219 # number of WriteReq accesses(hits+misses) 895system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193085 # number of LoadLockedReq accesses(hits+misses) 896system.cpu0.dcache.LoadLockedReq_accesses::total 193085 # number of LoadLockedReq accesses(hits+misses) 897system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192118 # number of StoreCondReq accesses(hits+misses) 898system.cpu0.dcache.StoreCondReq_accesses::total 192118 # number of StoreCondReq accesses(hits+misses) 899system.cpu0.dcache.demand_accesses::cpu0.data 14321286 # number of demand (read+write) accesses 900system.cpu0.dcache.demand_accesses::total 14321286 # number of demand (read+write) accesses 901system.cpu0.dcache.overall_accesses::cpu0.data 14321286 # number of overall (read+write) accesses 902system.cpu0.dcache.overall_accesses::total 14321286 # number of overall (read+write) accesses 903system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122461 # miss rate for ReadReq accesses 904system.cpu0.dcache.ReadReq_miss_rate::total 0.122461 # miss rate for ReadReq accesses 905system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049743 # miss rate for WriteReq accesses 906system.cpu0.dcache.WriteReq_miss_rate::total 0.049743 # miss rate for WriteReq accesses 907system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084761 # miss rate for LoadLockedReq accesses 908system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084761 # miss rate for LoadLockedReq accesses 909system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002264 # miss rate for StoreCondReq accesses 910system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002264 # miss rate for StoreCondReq accesses 911system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092726 # miss rate for demand accesses 912system.cpu0.dcache.demand_miss_rate::total 0.092726 # miss rate for demand accesses 913system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092726 # miss rate for overall accesses 914system.cpu0.dcache.overall_miss_rate::total 0.092726 # miss rate for overall accesses 915system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21589.493287 # average ReadReq miss latency 916system.cpu0.dcache.ReadReq_avg_miss_latency::total 21589.493287 # average ReadReq miss latency 917system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28125.389622 # average WriteReq miss latency 918system.cpu0.dcache.WriteReq_avg_miss_latency::total 28125.389622 # average WriteReq miss latency 919system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13082.671392 # average LoadLockedReq miss latency 920system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13082.671392 # average LoadLockedReq miss latency 921system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5865.517241 # average StoreCondReq miss latency 922system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5865.517241 # average StoreCondReq miss latency 923system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23023.251252 # average overall miss latency 924system.cpu0.dcache.demand_avg_miss_latency::total 23023.251252 # average overall miss latency 925system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23023.251252 # average overall miss latency 926system.cpu0.dcache.overall_avg_miss_latency::total 23023.251252 # average overall miss latency | 1142system.cpu0.dcache.replacements 1181525 # number of replacements 1143system.cpu0.dcache.tagsinuse 505.231432 # Cycle average of tags in use 1144system.cpu0.dcache.total_refs 11411955 # Total number of references to valid blocks. 1145system.cpu0.dcache.sampled_refs 1182037 # Sample count of references to valid blocks. 1146system.cpu0.dcache.avg_refs 9.654482 # Average number of references to valid blocks. 1147system.cpu0.dcache.warmup_cycle 105721000 # Cycle when the warmup percentage was hit. 1148system.cpu0.dcache.occ_blocks::cpu0.data 505.231432 # Average occupied blocks per requestor 1149system.cpu0.dcache.occ_percent::cpu0.data 0.986780 # Average percentage of cache occupancy 1150system.cpu0.dcache.occ_percent::total 0.986780 # Average percentage of cache occupancy 1151system.cpu0.dcache.ReadReq_hits::cpu0.data 6427043 # number of ReadReq hits 1152system.cpu0.dcache.ReadReq_hits::total 6427043 # number of ReadReq hits 1153system.cpu0.dcache.WriteReq_hits::cpu0.data 4684362 # number of WriteReq hits 1154system.cpu0.dcache.WriteReq_hits::total 4684362 # number of WriteReq hits 1155system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139576 # number of LoadLockedReq hits 1156system.cpu0.dcache.LoadLockedReq_hits::total 139576 # number of LoadLockedReq hits 1157system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146814 # number of StoreCondReq hits 1158system.cpu0.dcache.StoreCondReq_hits::total 146814 # number of StoreCondReq hits 1159system.cpu0.dcache.demand_hits::cpu0.data 11111405 # number of demand (read+write) hits 1160system.cpu0.dcache.demand_hits::total 11111405 # number of demand (read+write) hits 1161system.cpu0.dcache.overall_hits::cpu0.data 11111405 # number of overall hits 1162system.cpu0.dcache.overall_hits::total 11111405 # number of overall hits 1163system.cpu0.dcache.ReadReq_misses::cpu0.data 936498 # number of ReadReq misses 1164system.cpu0.dcache.ReadReq_misses::total 936498 # number of ReadReq misses 1165system.cpu0.dcache.WriteReq_misses::cpu0.data 255602 # number of WriteReq misses 1166system.cpu0.dcache.WriteReq_misses::total 255602 # number of WriteReq misses 1167system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13508 # number of LoadLockedReq misses 1168system.cpu0.dcache.LoadLockedReq_misses::total 13508 # number of LoadLockedReq misses 1169system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5738 # number of StoreCondReq misses 1170system.cpu0.dcache.StoreCondReq_misses::total 5738 # number of StoreCondReq misses 1171system.cpu0.dcache.demand_misses::cpu0.data 1192100 # number of demand (read+write) misses 1172system.cpu0.dcache.demand_misses::total 1192100 # number of demand (read+write) misses 1173system.cpu0.dcache.overall_misses::cpu0.data 1192100 # number of overall misses 1174system.cpu0.dcache.overall_misses::total 1192100 # number of overall misses 1175system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26205591500 # number of ReadReq miss cycles 1176system.cpu0.dcache.ReadReq_miss_latency::total 26205591500 # number of ReadReq miss cycles 1177system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9945079500 # number of WriteReq miss cycles 1178system.cpu0.dcache.WriteReq_miss_latency::total 9945079500 # number of WriteReq miss cycles 1179system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 146904500 # number of LoadLockedReq miss cycles 1180system.cpu0.dcache.LoadLockedReq_miss_latency::total 146904500 # number of LoadLockedReq miss cycles 1181system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44028500 # number of StoreCondReq miss cycles 1182system.cpu0.dcache.StoreCondReq_miss_latency::total 44028500 # number of StoreCondReq miss cycles 1183system.cpu0.dcache.demand_miss_latency::cpu0.data 36150671000 # number of demand (read+write) miss cycles 1184system.cpu0.dcache.demand_miss_latency::total 36150671000 # number of demand (read+write) miss cycles 1185system.cpu0.dcache.overall_miss_latency::cpu0.data 36150671000 # number of overall miss cycles 1186system.cpu0.dcache.overall_miss_latency::total 36150671000 # number of overall miss cycles 1187system.cpu0.dcache.ReadReq_accesses::cpu0.data 7363541 # number of ReadReq accesses(hits+misses) 1188system.cpu0.dcache.ReadReq_accesses::total 7363541 # number of ReadReq accesses(hits+misses) 1189system.cpu0.dcache.WriteReq_accesses::cpu0.data 4939964 # number of WriteReq accesses(hits+misses) 1190system.cpu0.dcache.WriteReq_accesses::total 4939964 # number of WriteReq accesses(hits+misses) 1191system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153084 # number of LoadLockedReq accesses(hits+misses) 1192system.cpu0.dcache.LoadLockedReq_accesses::total 153084 # number of LoadLockedReq accesses(hits+misses) 1193system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152552 # number of StoreCondReq accesses(hits+misses) 1194system.cpu0.dcache.StoreCondReq_accesses::total 152552 # number of StoreCondReq accesses(hits+misses) 1195system.cpu0.dcache.demand_accesses::cpu0.data 12303505 # number of demand (read+write) accesses 1196system.cpu0.dcache.demand_accesses::total 12303505 # number of demand (read+write) accesses 1197system.cpu0.dcache.overall_accesses::cpu0.data 12303505 # number of overall (read+write) accesses 1198system.cpu0.dcache.overall_accesses::total 12303505 # number of overall (read+write) accesses 1199system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127180 # miss rate for ReadReq accesses 1200system.cpu0.dcache.ReadReq_miss_rate::total 0.127180 # miss rate for ReadReq accesses 1201system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051742 # miss rate for WriteReq accesses 1202system.cpu0.dcache.WriteReq_miss_rate::total 0.051742 # miss rate for WriteReq accesses 1203system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088239 # miss rate for LoadLockedReq accesses 1204system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088239 # miss rate for LoadLockedReq accesses 1205system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037613 # miss rate for StoreCondReq accesses 1206system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037613 # miss rate for StoreCondReq accesses 1207system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096891 # miss rate for demand accesses 1208system.cpu0.dcache.demand_miss_rate::total 0.096891 # miss rate for demand accesses 1209system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096891 # miss rate for overall accesses 1210system.cpu0.dcache.overall_miss_rate::total 0.096891 # miss rate for overall accesses 1211system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27982.538671 # average ReadReq miss latency 1212system.cpu0.dcache.ReadReq_avg_miss_latency::total 27982.538671 # average ReadReq miss latency 1213system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38908.457289 # average WriteReq miss latency 1214system.cpu0.dcache.WriteReq_avg_miss_latency::total 38908.457289 # average WriteReq miss latency 1215system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10875.370151 # average LoadLockedReq miss latency 1216system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10875.370151 # average LoadLockedReq miss latency 1217system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7673.143953 # average StoreCondReq miss latency 1218system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7673.143953 # average StoreCondReq miss latency 1219system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30325.200067 # average overall miss latency 1220system.cpu0.dcache.demand_avg_miss_latency::total 30325.200067 # average overall miss latency 1221system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30325.200067 # average overall miss latency 1222system.cpu0.dcache.overall_avg_miss_latency::total 30325.200067 # average overall miss latency |
| 927system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 928system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 929system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 930system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 931system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 932system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 933system.cpu0.dcache.fast_writes 0 # number of fast writes performed 934system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1223system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1224system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1225system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1226system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1227system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1228system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1229system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1230system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 935system.cpu0.dcache.writebacks::writebacks 791336 # number of writebacks 936system.cpu0.dcache.writebacks::total 791336 # number of writebacks 937system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036642 # number of ReadReq MSHR misses 938system.cpu0.dcache.ReadReq_mshr_misses::total 1036642 # number of ReadReq MSHR misses 939system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291308 # number of WriteReq MSHR misses 940system.cpu0.dcache.WriteReq_mshr_misses::total 291308 # number of WriteReq MSHR misses 941system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16366 # number of LoadLockedReq MSHR misses 942system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16366 # number of LoadLockedReq MSHR misses 943system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 435 # number of StoreCondReq MSHR misses 944system.cpu0.dcache.StoreCondReq_mshr_misses::total 435 # number of StoreCondReq MSHR misses 945system.cpu0.dcache.demand_mshr_misses::cpu0.data 1327950 # number of demand (read+write) MSHR misses 946system.cpu0.dcache.demand_mshr_misses::total 1327950 # number of demand (read+write) MSHR misses 947system.cpu0.dcache.overall_mshr_misses::cpu0.data 1327950 # number of overall MSHR misses 948system.cpu0.dcache.overall_mshr_misses::total 1327950 # number of overall MSHR misses 949system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20307291500 # number of ReadReq MSHR miss cycles 950system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20307291500 # number of ReadReq MSHR miss cycles 951system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7610535000 # number of WriteReq MSHR miss cycles 952system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7610535000 # number of WriteReq MSHR miss cycles 953system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181379000 # number of LoadLockedReq MSHR miss cycles 954system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181379000 # number of LoadLockedReq MSHR miss cycles 955system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1681500 # number of StoreCondReq MSHR miss cycles 956system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1681500 # number of StoreCondReq MSHR miss cycles 957system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27917826500 # number of demand (read+write) MSHR miss cycles 958system.cpu0.dcache.demand_mshr_miss_latency::total 27917826500 # number of demand (read+write) MSHR miss cycles 959system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27917826500 # number of overall MSHR miss cycles 960system.cpu0.dcache.overall_mshr_miss_latency::total 27917826500 # number of overall MSHR miss cycles 961system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465371000 # number of ReadReq MSHR uncacheable cycles 962system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465371000 # number of ReadReq MSHR uncacheable cycles 963system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092831000 # number of WriteReq MSHR uncacheable cycles 964system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092831000 # number of WriteReq MSHR uncacheable cycles 965system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3558202000 # number of overall MSHR uncacheable cycles 966system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3558202000 # number of overall MSHR uncacheable cycles 967system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122461 # mshr miss rate for ReadReq accesses 968system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122461 # mshr miss rate for ReadReq accesses 969system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049743 # mshr miss rate for WriteReq accesses 970system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049743 # mshr miss rate for WriteReq accesses 971system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084761 # mshr miss rate for LoadLockedReq accesses 972system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084761 # mshr miss rate for LoadLockedReq accesses 973system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002264 # mshr miss rate for StoreCondReq accesses 974system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002264 # mshr miss rate for StoreCondReq accesses 975system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092726 # mshr miss rate for demand accesses 976system.cpu0.dcache.demand_mshr_miss_rate::total 0.092726 # mshr miss rate for demand accesses 977system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092726 # mshr miss rate for overall accesses 978system.cpu0.dcache.overall_mshr_miss_rate::total 0.092726 # mshr miss rate for overall accesses 979system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19589.493287 # average ReadReq mshr miss latency 980system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19589.493287 # average ReadReq mshr miss latency 981system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26125.389622 # average WriteReq mshr miss latency 982system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26125.389622 # average WriteReq mshr miss latency 983system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11082.671392 # average LoadLockedReq mshr miss latency 984system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11082.671392 # average LoadLockedReq mshr miss latency 985system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3865.517241 # average StoreCondReq mshr miss latency 986system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3865.517241 # average StoreCondReq mshr miss latency 987system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21023.251252 # average overall mshr miss latency 988system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21023.251252 # average overall mshr miss latency 989system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21023.251252 # average overall mshr miss latency 990system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21023.251252 # average overall mshr miss latency | 1231system.cpu0.dcache.writebacks::writebacks 678820 # number of writebacks 1232system.cpu0.dcache.writebacks::total 678820 # number of writebacks 1233system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 936498 # number of ReadReq MSHR misses 1234system.cpu0.dcache.ReadReq_mshr_misses::total 936498 # number of ReadReq MSHR misses 1235system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255602 # number of WriteReq MSHR misses 1236system.cpu0.dcache.WriteReq_mshr_misses::total 255602 # number of WriteReq MSHR misses 1237system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13508 # number of LoadLockedReq MSHR misses 1238system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13508 # number of LoadLockedReq MSHR misses 1239system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5737 # number of StoreCondReq MSHR misses 1240system.cpu0.dcache.StoreCondReq_mshr_misses::total 5737 # number of StoreCondReq MSHR misses 1241system.cpu0.dcache.demand_mshr_misses::cpu0.data 1192100 # number of demand (read+write) MSHR misses 1242system.cpu0.dcache.demand_mshr_misses::total 1192100 # number of demand (read+write) MSHR misses 1243system.cpu0.dcache.overall_mshr_misses::cpu0.data 1192100 # number of overall MSHR misses 1244system.cpu0.dcache.overall_mshr_misses::total 1192100 # number of overall MSHR misses 1245system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24332593005 # number of ReadReq MSHR miss cycles 1246system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24332593005 # number of ReadReq MSHR miss cycles 1247system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9433875500 # number of WriteReq MSHR miss cycles 1248system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9433875500 # number of WriteReq MSHR miss cycles 1249system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 119888500 # number of LoadLockedReq MSHR miss cycles 1250system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 119888500 # number of LoadLockedReq MSHR miss cycles 1251system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32554500 # number of StoreCondReq MSHR miss cycles 1252system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32554500 # number of StoreCondReq MSHR miss cycles 1253system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 33766468505 # number of demand (read+write) MSHR miss cycles 1254system.cpu0.dcache.demand_mshr_miss_latency::total 33766468505 # number of demand (read+write) MSHR miss cycles 1255system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 33766468505 # number of overall MSHR miss cycles 1256system.cpu0.dcache.overall_mshr_miss_latency::total 33766468505 # number of overall MSHR miss cycles 1257system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465600500 # number of ReadReq MSHR uncacheable cycles 1258system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465600500 # number of ReadReq MSHR uncacheable cycles 1259system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2289389000 # number of WriteReq MSHR uncacheable cycles 1260system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2289389000 # number of WriteReq MSHR uncacheable cycles 1261system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3754989500 # number of overall MSHR uncacheable cycles 1262system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3754989500 # number of overall MSHR uncacheable cycles 1263system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127180 # mshr miss rate for ReadReq accesses 1264system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127180 # mshr miss rate for ReadReq accesses 1265system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051742 # mshr miss rate for WriteReq accesses 1266system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051742 # mshr miss rate for WriteReq accesses 1267system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088239 # mshr miss rate for LoadLockedReq accesses 1268system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088239 # mshr miss rate for LoadLockedReq accesses 1269system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037607 # mshr miss rate for StoreCondReq accesses 1270system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037607 # mshr miss rate for StoreCondReq accesses 1271system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096891 # mshr miss rate for demand accesses 1272system.cpu0.dcache.demand_mshr_miss_rate::total 0.096891 # mshr miss rate for demand accesses 1273system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096891 # mshr miss rate for overall accesses 1274system.cpu0.dcache.overall_mshr_miss_rate::total 0.096891 # mshr miss rate for overall accesses 1275system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25982.536006 # average ReadReq mshr miss latency 1276system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25982.536006 # average ReadReq mshr miss latency 1277system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36908.457289 # average WriteReq mshr miss latency 1278system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36908.457289 # average WriteReq mshr miss latency 1279system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8875.370151 # average LoadLockedReq mshr miss latency 1280system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8875.370151 # average LoadLockedReq mshr miss latency 1281system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5674.481436 # average StoreCondReq mshr miss latency 1282system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5674.481436 # average StoreCondReq mshr miss latency 1283system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency 1284system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency 1285system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency 1286system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency |
| 991system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 992system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 993system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 994system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 995system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 996system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 997system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 998system.cpu1.dtb.fetch_hits 0 # ITB hits 999system.cpu1.dtb.fetch_misses 0 # ITB misses 1000system.cpu1.dtb.fetch_acv 0 # ITB acv 1001system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 1287system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1288system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1289system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1290system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1291system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1292system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1293system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1294system.cpu1.dtb.fetch_hits 0 # ITB hits 1295system.cpu1.dtb.fetch_misses 0 # ITB misses 1296system.cpu1.dtb.fetch_acv 0 # ITB acv 1297system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 1002system.cpu1.dtb.read_hits 1047303 # DTB read hits 1003system.cpu1.dtb.read_misses 2992 # DTB read misses | 1298system.cpu1.dtb.read_hits 2417907 # DTB read hits 1299system.cpu1.dtb.read_misses 2620 # DTB read misses |
| 1004system.cpu1.dtb.read_acv 0 # DTB read access violations | 1300system.cpu1.dtb.read_acv 0 # DTB read access violations |
| 1005system.cpu1.dtb.read_accesses 239363 # DTB read accesses 1006system.cpu1.dtb.write_hits 650380 # DTB write hits 1007system.cpu1.dtb.write_misses 341 # DTB write misses 1008system.cpu1.dtb.write_acv 29 # DTB write access violations 1009system.cpu1.dtb.write_accesses 105247 # DTB write accesses 1010system.cpu1.dtb.data_hits 1697683 # DTB hits 1011system.cpu1.dtb.data_misses 3333 # DTB misses 1012system.cpu1.dtb.data_acv 29 # DTB access violations 1013system.cpu1.dtb.data_accesses 344610 # DTB accesses 1014system.cpu1.itb.fetch_hits 1487846 # ITB hits 1015system.cpu1.itb.fetch_misses 1216 # ITB misses | 1301system.cpu1.dtb.read_accesses 205337 # DTB read accesses 1302system.cpu1.dtb.write_hits 1735068 # DTB write hits 1303system.cpu1.dtb.write_misses 235 # DTB write misses 1304system.cpu1.dtb.write_acv 24 # DTB write access violations 1305system.cpu1.dtb.write_accesses 89739 # DTB write accesses 1306system.cpu1.dtb.data_hits 4152975 # DTB hits 1307system.cpu1.dtb.data_misses 2855 # DTB misses 1308system.cpu1.dtb.data_acv 24 # DTB access violations 1309system.cpu1.dtb.data_accesses 295076 # DTB accesses 1310system.cpu1.itb.fetch_hits 1826925 # ITB hits 1311system.cpu1.itb.fetch_misses 1064 # ITB misses |
| 1016system.cpu1.itb.fetch_acv 0 # ITB acv | 1312system.cpu1.itb.fetch_acv 0 # ITB acv |
| 1017system.cpu1.itb.fetch_accesses 1489062 # ITB accesses | 1313system.cpu1.itb.fetch_accesses 1827989 # ITB accesses |
| 1018system.cpu1.itb.read_hits 0 # DTB read hits 1019system.cpu1.itb.read_misses 0 # DTB read misses 1020system.cpu1.itb.read_acv 0 # DTB read access violations 1021system.cpu1.itb.read_accesses 0 # DTB read accesses 1022system.cpu1.itb.write_hits 0 # DTB write hits 1023system.cpu1.itb.write_misses 0 # DTB write misses 1024system.cpu1.itb.write_acv 0 # DTB write access violations 1025system.cpu1.itb.write_accesses 0 # DTB write accesses 1026system.cpu1.itb.data_hits 0 # DTB hits 1027system.cpu1.itb.data_misses 0 # DTB misses 1028system.cpu1.itb.data_acv 0 # DTB access violations 1029system.cpu1.itb.data_accesses 0 # DTB accesses | 1314system.cpu1.itb.read_hits 0 # DTB read hits 1315system.cpu1.itb.read_misses 0 # DTB read misses 1316system.cpu1.itb.read_acv 0 # DTB read access violations 1317system.cpu1.itb.read_accesses 0 # DTB read accesses 1318system.cpu1.itb.write_hits 0 # DTB write hits 1319system.cpu1.itb.write_misses 0 # DTB write misses 1320system.cpu1.itb.write_acv 0 # DTB write access violations 1321system.cpu1.itb.write_accesses 0 # DTB write accesses 1322system.cpu1.itb.data_hits 0 # DTB hits 1323system.cpu1.itb.data_misses 0 # DTB misses 1324system.cpu1.itb.data_acv 0 # DTB access violations 1325system.cpu1.itb.data_accesses 0 # DTB accesses |
| 1030system.cpu1.numCycles 3911498214 # number of cpu cycles simulated | 1326system.cpu1.numCycles 3917974909 # number of cpu cycles simulated |
| 1031system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1032system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1327system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1328system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1033system.cpu1.committedInsts 5261846 # Number of instructions committed 1034system.cpu1.committedOps 5261846 # Number of ops (including micro ops) committed 1035system.cpu1.num_int_alu_accesses 4930311 # Number of integer alu accesses 1036system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses 1037system.cpu1.num_func_calls 156775 # number of times a function call or return occured 1038system.cpu1.num_conditional_control_insts 508835 # number of instructions that are conditional controls 1039system.cpu1.num_int_insts 4930311 # number of integer instructions 1040system.cpu1.num_fp_insts 34031 # number of float instructions 1041system.cpu1.num_int_register_reads 6861337 # number of times the integer registers were read 1042system.cpu1.num_int_register_writes 3717514 # number of times the integer registers were written 1043system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read 1044system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written 1045system.cpu1.num_mem_refs 1707139 # number of memory refs 1046system.cpu1.num_load_insts 1053310 # Number of load instructions 1047system.cpu1.num_store_insts 653829 # Number of store instructions 1048system.cpu1.num_idle_cycles 3891938527.998010 # Number of idle cycles 1049system.cpu1.num_busy_cycles 19559686.001990 # Number of busy cycles 1050system.cpu1.not_idle_fraction 0.005001 # Percentage of non-idle cycles 1051system.cpu1.idle_fraction 0.994999 # Percentage of idle cycles | 1329system.cpu1.committedInsts 13128564 # Number of instructions committed 1330system.cpu1.committedOps 13128564 # Number of ops (including micro ops) committed 1331system.cpu1.num_int_alu_accesses 12090481 # Number of integer alu accesses 1332system.cpu1.num_fp_alu_accesses 177902 # Number of float alu accesses 1333system.cpu1.num_func_calls 416956 # number of times a function call or return occured 1334system.cpu1.num_conditional_control_insts 1297332 # number of instructions that are conditional controls 1335system.cpu1.num_int_insts 12090481 # number of integer instructions 1336system.cpu1.num_fp_insts 177902 # number of float instructions 1337system.cpu1.num_int_register_reads 16603924 # number of times the integer registers were read 1338system.cpu1.num_int_register_writes 8888139 # number of times the integer registers were written 1339system.cpu1.num_fp_register_reads 92328 # number of times the floating registers were read 1340system.cpu1.num_fp_register_writes 94344 # number of times the floating registers were written 1341system.cpu1.num_mem_refs 4176284 # number of memory refs 1342system.cpu1.num_load_insts 2431879 # Number of load instructions 1343system.cpu1.num_store_insts 1744405 # Number of store instructions 1344system.cpu1.num_idle_cycles 3867819461.141509 # Number of idle cycles 1345system.cpu1.num_busy_cycles 50155447.858491 # Number of busy cycles 1346system.cpu1.not_idle_fraction 0.012801 # Percentage of non-idle cycles 1347system.cpu1.idle_fraction 0.987199 # Percentage of idle cycles |
| 1052system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1348system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1053system.cpu1.kern.inst.quiesce 2300 # number of quiesce instructions executed 1054system.cpu1.kern.inst.hwrei 35556 # number of hwrei instructions executed 1055system.cpu1.kern.ipl_count::0 8967 31.73% 31.73% # number of times we switched to this ipl 1056system.cpu1.kern.ipl_count::22 1970 6.97% 38.70% # number of times we switched to this ipl 1057system.cpu1.kern.ipl_count::30 89 0.31% 39.02% # number of times we switched to this ipl 1058system.cpu1.kern.ipl_count::31 17234 60.98% 100.00% # number of times we switched to this ipl 1059system.cpu1.kern.ipl_count::total 28260 # number of times we switched to this ipl 1060system.cpu1.kern.ipl_good::0 8957 45.05% 45.05% # number of times we switched to this ipl from a different ipl 1061system.cpu1.kern.ipl_good::22 1970 9.91% 54.95% # number of times we switched to this ipl from a different ipl 1062system.cpu1.kern.ipl_good::30 89 0.45% 55.40% # number of times we switched to this ipl from a different ipl 1063system.cpu1.kern.ipl_good::31 8868 44.60% 100.00% # number of times we switched to this ipl from a different ipl 1064system.cpu1.kern.ipl_good::total 19884 # number of times we switched to this ipl from a different ipl 1065system.cpu1.kern.ipl_ticks::0 1918859770000 98.11% 98.11% # number of cycles we spent at this ipl 1066system.cpu1.kern.ipl_ticks::22 708002500 0.04% 98.15% # number of cycles we spent at this ipl 1067system.cpu1.kern.ipl_ticks::30 60314000 0.00% 98.15% # number of cycles we spent at this ipl 1068system.cpu1.kern.ipl_ticks::31 36120248500 1.85% 100.00% # number of cycles we spent at this ipl 1069system.cpu1.kern.ipl_ticks::total 1955748335000 # number of cycles we spent at this ipl 1070system.cpu1.kern.ipl_used::0 0.998885 # fraction of swpipl calls that actually changed the ipl | 1349system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed 1350system.cpu1.kern.inst.hwrei 79425 # number of hwrei instructions executed 1351system.cpu1.kern.ipl_count::0 27091 38.34% 38.34% # number of times we switched to this ipl 1352system.cpu1.kern.ipl_count::22 1969 2.79% 41.13% # number of times we switched to this ipl 1353system.cpu1.kern.ipl_count::30 528 0.75% 41.87% # number of times we switched to this ipl 1354system.cpu1.kern.ipl_count::31 41074 58.13% 100.00% # number of times we switched to this ipl 1355system.cpu1.kern.ipl_count::total 70662 # number of times we switched to this ipl 1356system.cpu1.kern.ipl_good::0 26202 48.19% 48.19% # number of times we switched to this ipl from a different ipl 1357system.cpu1.kern.ipl_good::22 1969 3.62% 51.81% # number of times we switched to this ipl from a different ipl 1358system.cpu1.kern.ipl_good::30 528 0.97% 52.78% # number of times we switched to this ipl from a different ipl 1359system.cpu1.kern.ipl_good::31 25675 47.22% 100.00% # number of times we switched to this ipl from a different ipl 1360system.cpu1.kern.ipl_good::total 54374 # number of times we switched to this ipl from a different ipl 1361system.cpu1.kern.ipl_ticks::0 1908747944000 97.44% 97.44% # number of cycles we spent at this ipl 1362system.cpu1.kern.ipl_ticks::22 700841000 0.04% 97.47% # number of cycles we spent at this ipl 1363system.cpu1.kern.ipl_ticks::30 369371500 0.02% 97.49% # number of cycles we spent at this ipl 1364system.cpu1.kern.ipl_ticks::31 49169268000 2.51% 100.00% # number of cycles we spent at this ipl 1365system.cpu1.kern.ipl_ticks::total 1958987424500 # number of cycles we spent at this ipl 1366system.cpu1.kern.ipl_used::0 0.967185 # fraction of swpipl calls that actually changed the ipl |
| 1071system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1072system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1367system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1368system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1073system.cpu1.kern.ipl_used::31 0.514564 # fraction of swpipl calls that actually changed the ipl 1074system.cpu1.kern.ipl_used::total 0.703609 # fraction of swpipl calls that actually changed the ipl 1075system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 1076system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 1077system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 1078system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 1079system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 1080system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 1081system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 1082system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 1083system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 1084system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 1085system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 1086system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 1087system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 1088system.cpu1.kern.syscall::total 104 # number of syscalls executed | 1369system.cpu1.kern.ipl_used::31 0.625091 # fraction of swpipl calls that actually changed the ipl 1370system.cpu1.kern.ipl_used::total 0.769494 # fraction of swpipl calls that actually changed the ipl 1371system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed 1372system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed 1373system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed 1374system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed 1375system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed 1376system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed 1377system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed 1378system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed 1379system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed 1380system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed 1381system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed 1382system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed 1383system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed 1384system.cpu1.kern.syscall::total 92 # number of syscalls executed |
| 1089system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 1385system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 1090system.cpu1.kern.callpal::wripir 7 0.02% 0.03% # number of callpals executed 1091system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 1092system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 1093system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed 1094system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed 1095system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed 1096system.cpu1.kern.callpal::swpipl 23668 81.85% 83.08% # number of callpals executed 1097system.cpu1.kern.callpal::rdps 2171 7.51% 90.59% # number of callpals executed 1098system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed 1099system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed 1100system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed 1101system.cpu1.kern.callpal::rti 2532 8.76% 99.37% # number of callpals executed 1102system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed 1103system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed | 1386system.cpu1.kern.callpal::wripir 445 0.61% 0.61% # number of callpals executed 1387system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed 1388system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed 1389system.cpu1.kern.callpal::swpctx 2045 2.80% 3.42% # number of callpals executed 1390system.cpu1.kern.callpal::tbi 3 0.00% 3.42% # number of callpals executed 1391system.cpu1.kern.callpal::wrent 7 0.01% 3.43% # number of callpals executed 1392system.cpu1.kern.callpal::swpipl 64414 88.26% 91.69% # number of callpals executed 1393system.cpu1.kern.callpal::rdps 2145 2.94% 94.63% # number of callpals executed 1394system.cpu1.kern.callpal::wrkgp 1 0.00% 94.63% # number of callpals executed 1395system.cpu1.kern.callpal::wrusp 3 0.00% 94.63% # number of callpals executed 1396system.cpu1.kern.callpal::whami 3 0.00% 94.64% # number of callpals executed 1397system.cpu1.kern.callpal::rti 3751 5.14% 99.78% # number of callpals executed 1398system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed 1399system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed |
| 1104system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 1400system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 1105system.cpu1.kern.callpal::total 28917 # number of callpals executed 1106system.cpu1.kern.mode_switch::kernel 802 # number of protection mode switches 1107system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 1108system.cpu1.kern.mode_switch::idle 2068 # number of protection mode switches 1109system.cpu1.kern.mode_good::kernel 477 1110system.cpu1.kern.mode_good::user 464 1111system.cpu1.kern.mode_good::idle 13 1112system.cpu1.kern.mode_switch_good::kernel 0.594763 # fraction of useful protection mode switches | 1401system.cpu1.kern.callpal::total 72984 # number of callpals executed 1402system.cpu1.kern.mode_switch::kernel 1994 # number of protection mode switches 1403system.cpu1.kern.mode_switch::user 369 # number of protection mode switches 1404system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches 1405system.cpu1.kern.mode_good::kernel 821 1406system.cpu1.kern.mode_good::user 369 1407system.cpu1.kern.mode_good::idle 452 1408system.cpu1.kern.mode_switch_good::kernel 0.411735 # fraction of useful protection mode switches |
| 1113system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1409system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1114system.cpu1.kern.mode_switch_good::idle 0.006286 # fraction of useful protection mode switches 1115system.cpu1.kern.mode_switch_good::total 0.286143 # fraction of useful protection mode switches 1116system.cpu1.kern.mode_ticks::kernel 3597793000 0.18% 0.18% # number of ticks spent at the given mode 1117system.cpu1.kern.mode_ticks::user 1722339500 0.09% 0.27% # number of ticks spent at the given mode 1118system.cpu1.kern.mode_ticks::idle 1950428198000 99.73% 100.00% # number of ticks spent at the given mode 1119system.cpu1.kern.swap_context 338 # number of times the context was actually changed 1120system.cpu1.icache.replacements 86405 # number of replacements 1121system.cpu1.icache.tagsinuse 422.462851 # Cycle average of tags in use 1122system.cpu1.icache.total_refs 5178256 # Total number of references to valid blocks. 1123system.cpu1.icache.sampled_refs 86917 # Sample count of references to valid blocks. 1124system.cpu1.icache.avg_refs 59.577022 # Average number of references to valid blocks. 1125system.cpu1.icache.warmup_cycle 1939963886500 # Cycle when the warmup percentage was hit. 1126system.cpu1.icache.occ_blocks::cpu1.inst 422.462851 # Average occupied blocks per requestor 1127system.cpu1.icache.occ_percent::cpu1.inst 0.825123 # Average percentage of cache occupancy 1128system.cpu1.icache.occ_percent::total 0.825123 # Average percentage of cache occupancy 1129system.cpu1.icache.ReadReq_hits::cpu1.inst 5178256 # number of ReadReq hits 1130system.cpu1.icache.ReadReq_hits::total 5178256 # number of ReadReq hits 1131system.cpu1.icache.demand_hits::cpu1.inst 5178256 # number of demand (read+write) hits 1132system.cpu1.icache.demand_hits::total 5178256 # number of demand (read+write) hits 1133system.cpu1.icache.overall_hits::cpu1.inst 5178256 # number of overall hits 1134system.cpu1.icache.overall_hits::total 5178256 # number of overall hits 1135system.cpu1.icache.ReadReq_misses::cpu1.inst 86953 # number of ReadReq misses 1136system.cpu1.icache.ReadReq_misses::total 86953 # number of ReadReq misses 1137system.cpu1.icache.demand_misses::cpu1.inst 86953 # number of demand (read+write) misses 1138system.cpu1.icache.demand_misses::total 86953 # number of demand (read+write) misses 1139system.cpu1.icache.overall_misses::cpu1.inst 86953 # number of overall misses 1140system.cpu1.icache.overall_misses::total 86953 # number of overall misses 1141system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1177160000 # number of ReadReq miss cycles 1142system.cpu1.icache.ReadReq_miss_latency::total 1177160000 # number of ReadReq miss cycles 1143system.cpu1.icache.demand_miss_latency::cpu1.inst 1177160000 # number of demand (read+write) miss cycles 1144system.cpu1.icache.demand_miss_latency::total 1177160000 # number of demand (read+write) miss cycles 1145system.cpu1.icache.overall_miss_latency::cpu1.inst 1177160000 # number of overall miss cycles 1146system.cpu1.icache.overall_miss_latency::total 1177160000 # number of overall miss cycles 1147system.cpu1.icache.ReadReq_accesses::cpu1.inst 5265209 # number of ReadReq accesses(hits+misses) 1148system.cpu1.icache.ReadReq_accesses::total 5265209 # number of ReadReq accesses(hits+misses) 1149system.cpu1.icache.demand_accesses::cpu1.inst 5265209 # number of demand (read+write) accesses 1150system.cpu1.icache.demand_accesses::total 5265209 # number of demand (read+write) accesses 1151system.cpu1.icache.overall_accesses::cpu1.inst 5265209 # number of overall (read+write) accesses 1152system.cpu1.icache.overall_accesses::total 5265209 # number of overall (read+write) accesses 1153system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016515 # miss rate for ReadReq accesses 1154system.cpu1.icache.ReadReq_miss_rate::total 0.016515 # miss rate for ReadReq accesses 1155system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016515 # miss rate for demand accesses 1156system.cpu1.icache.demand_miss_rate::total 0.016515 # miss rate for demand accesses 1157system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016515 # miss rate for overall accesses 1158system.cpu1.icache.overall_miss_rate::total 0.016515 # miss rate for overall accesses 1159system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13537.888284 # average ReadReq miss latency 1160system.cpu1.icache.ReadReq_avg_miss_latency::total 13537.888284 # average ReadReq miss latency 1161system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13537.888284 # average overall miss latency 1162system.cpu1.icache.demand_avg_miss_latency::total 13537.888284 # average overall miss latency 1163system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13537.888284 # average overall miss latency 1164system.cpu1.icache.overall_avg_miss_latency::total 13537.888284 # average overall miss latency | 1410system.cpu1.kern.mode_switch_good::idle 0.154636 # fraction of useful protection mode switches 1411system.cpu1.kern.mode_switch_good::total 0.310632 # fraction of useful protection mode switches 1412system.cpu1.kern.mode_ticks::kernel 18283551000 0.93% 0.93% # number of ticks spent at the given mode 1413system.cpu1.kern.mode_ticks::user 1485621000 0.08% 1.01% # number of ticks spent at the given mode 1414system.cpu1.kern.mode_ticks::idle 1938326244500 98.99% 100.00% # number of ticks spent at the given mode 1415system.cpu1.kern.swap_context 2046 # number of times the context was actually changed 1416system.cpu1.icache.replacements 323214 # number of replacements 1417system.cpu1.icache.tagsinuse 446.824291 # Cycle average of tags in use 1418system.cpu1.icache.total_refs 12807678 # Total number of references to valid blocks. 1419system.cpu1.icache.sampled_refs 323725 # Sample count of references to valid blocks. 1420system.cpu1.icache.avg_refs 39.563450 # Average number of references to valid blocks. 1421system.cpu1.icache.warmup_cycle 1958057375000 # Cycle when the warmup percentage was hit. 1422system.cpu1.icache.occ_blocks::cpu1.inst 446.824291 # Average occupied blocks per requestor 1423system.cpu1.icache.occ_percent::cpu1.inst 0.872704 # Average percentage of cache occupancy 1424system.cpu1.icache.occ_percent::total 0.872704 # Average percentage of cache occupancy 1425system.cpu1.icache.ReadReq_hits::cpu1.inst 12807678 # number of ReadReq hits 1426system.cpu1.icache.ReadReq_hits::total 12807678 # number of ReadReq hits 1427system.cpu1.icache.demand_hits::cpu1.inst 12807678 # number of demand (read+write) hits 1428system.cpu1.icache.demand_hits::total 12807678 # number of demand (read+write) hits 1429system.cpu1.icache.overall_hits::cpu1.inst 12807678 # number of overall hits 1430system.cpu1.icache.overall_hits::total 12807678 # number of overall hits 1431system.cpu1.icache.ReadReq_misses::cpu1.inst 323765 # number of ReadReq misses 1432system.cpu1.icache.ReadReq_misses::total 323765 # number of ReadReq misses 1433system.cpu1.icache.demand_misses::cpu1.inst 323765 # number of demand (read+write) misses 1434system.cpu1.icache.demand_misses::total 323765 # number of demand (read+write) misses 1435system.cpu1.icache.overall_misses::cpu1.inst 323765 # number of overall misses 1436system.cpu1.icache.overall_misses::total 323765 # number of overall misses 1437system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4261948000 # number of ReadReq miss cycles 1438system.cpu1.icache.ReadReq_miss_latency::total 4261948000 # number of ReadReq miss cycles 1439system.cpu1.icache.demand_miss_latency::cpu1.inst 4261948000 # number of demand (read+write) miss cycles 1440system.cpu1.icache.demand_miss_latency::total 4261948000 # number of demand (read+write) miss cycles 1441system.cpu1.icache.overall_miss_latency::cpu1.inst 4261948000 # number of overall miss cycles 1442system.cpu1.icache.overall_miss_latency::total 4261948000 # number of overall miss cycles 1443system.cpu1.icache.ReadReq_accesses::cpu1.inst 13131443 # number of ReadReq accesses(hits+misses) 1444system.cpu1.icache.ReadReq_accesses::total 13131443 # number of ReadReq accesses(hits+misses) 1445system.cpu1.icache.demand_accesses::cpu1.inst 13131443 # number of demand (read+write) accesses 1446system.cpu1.icache.demand_accesses::total 13131443 # number of demand (read+write) accesses 1447system.cpu1.icache.overall_accesses::cpu1.inst 13131443 # number of overall (read+write) accesses 1448system.cpu1.icache.overall_accesses::total 13131443 # number of overall (read+write) accesses 1449system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024656 # miss rate for ReadReq accesses 1450system.cpu1.icache.ReadReq_miss_rate::total 0.024656 # miss rate for ReadReq accesses 1451system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024656 # miss rate for demand accesses 1452system.cpu1.icache.demand_miss_rate::total 0.024656 # miss rate for demand accesses 1453system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024656 # miss rate for overall accesses 1454system.cpu1.icache.overall_miss_rate::total 0.024656 # miss rate for overall accesses 1455system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13163.708245 # average ReadReq miss latency 1456system.cpu1.icache.ReadReq_avg_miss_latency::total 13163.708245 # average ReadReq miss latency 1457system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13163.708245 # average overall miss latency 1458system.cpu1.icache.demand_avg_miss_latency::total 13163.708245 # average overall miss latency 1459system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13163.708245 # average overall miss latency 1460system.cpu1.icache.overall_avg_miss_latency::total 13163.708245 # average overall miss latency |
| 1165system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1166system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1167system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1168system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1169system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1170system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1171system.cpu1.icache.fast_writes 0 # number of fast writes performed 1172system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1461system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1462system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1463system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1464system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1465system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1466system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1467system.cpu1.icache.fast_writes 0 # number of fast writes performed 1468system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1173system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86953 # number of ReadReq MSHR misses 1174system.cpu1.icache.ReadReq_mshr_misses::total 86953 # number of ReadReq MSHR misses 1175system.cpu1.icache.demand_mshr_misses::cpu1.inst 86953 # number of demand (read+write) MSHR misses 1176system.cpu1.icache.demand_mshr_misses::total 86953 # number of demand (read+write) MSHR misses 1177system.cpu1.icache.overall_mshr_misses::cpu1.inst 86953 # number of overall MSHR misses 1178system.cpu1.icache.overall_mshr_misses::total 86953 # number of overall MSHR misses 1179system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1003254000 # number of ReadReq MSHR miss cycles 1180system.cpu1.icache.ReadReq_mshr_miss_latency::total 1003254000 # number of ReadReq MSHR miss cycles 1181system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1003254000 # number of demand (read+write) MSHR miss cycles 1182system.cpu1.icache.demand_mshr_miss_latency::total 1003254000 # number of demand (read+write) MSHR miss cycles 1183system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1003254000 # number of overall MSHR miss cycles 1184system.cpu1.icache.overall_mshr_miss_latency::total 1003254000 # number of overall MSHR miss cycles 1185system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for ReadReq accesses 1186system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016515 # mshr miss rate for ReadReq accesses 1187system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for demand accesses 1188system.cpu1.icache.demand_mshr_miss_rate::total 0.016515 # mshr miss rate for demand accesses 1189system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016515 # mshr miss rate for overall accesses 1190system.cpu1.icache.overall_mshr_miss_rate::total 0.016515 # mshr miss rate for overall accesses 1191system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average ReadReq mshr miss latency 1192system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11537.888284 # average ReadReq mshr miss latency 1193system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average overall mshr miss latency 1194system.cpu1.icache.demand_avg_mshr_miss_latency::total 11537.888284 # average overall mshr miss latency 1195system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11537.888284 # average overall mshr miss latency 1196system.cpu1.icache.overall_avg_mshr_miss_latency::total 11537.888284 # average overall mshr miss latency | 1469system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 323765 # number of ReadReq MSHR misses 1470system.cpu1.icache.ReadReq_mshr_misses::total 323765 # number of ReadReq MSHR misses 1471system.cpu1.icache.demand_mshr_misses::cpu1.inst 323765 # number of demand (read+write) MSHR misses 1472system.cpu1.icache.demand_mshr_misses::total 323765 # number of demand (read+write) MSHR misses 1473system.cpu1.icache.overall_mshr_misses::cpu1.inst 323765 # number of overall MSHR misses 1474system.cpu1.icache.overall_mshr_misses::total 323765 # number of overall MSHR misses 1475system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3614406523 # number of ReadReq MSHR miss cycles 1476system.cpu1.icache.ReadReq_mshr_miss_latency::total 3614406523 # number of ReadReq MSHR miss cycles 1477system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3614406523 # number of demand (read+write) MSHR miss cycles 1478system.cpu1.icache.demand_mshr_miss_latency::total 3614406523 # number of demand (read+write) MSHR miss cycles 1479system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3614406523 # number of overall MSHR miss cycles 1480system.cpu1.icache.overall_mshr_miss_latency::total 3614406523 # number of overall MSHR miss cycles 1481system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for ReadReq accesses 1482system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024656 # mshr miss rate for ReadReq accesses 1483system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for demand accesses 1484system.cpu1.icache.demand_mshr_miss_rate::total 0.024656 # mshr miss rate for demand accesses 1485system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024656 # mshr miss rate for overall accesses 1486system.cpu1.icache.overall_mshr_miss_rate::total 0.024656 # mshr miss rate for overall accesses 1487system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average ReadReq mshr miss latency 1488system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11163.672797 # average ReadReq mshr miss latency 1489system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average overall mshr miss latency 1490system.cpu1.icache.demand_avg_mshr_miss_latency::total 11163.672797 # average overall mshr miss latency 1491system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11163.672797 # average overall mshr miss latency 1492system.cpu1.icache.overall_avg_mshr_miss_latency::total 11163.672797 # average overall mshr miss latency |
| 1197system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1493system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1198system.cpu1.dcache.replacements 52787 # number of replacements 1199system.cpu1.dcache.tagsinuse 417.162104 # Cycle average of tags in use 1200system.cpu1.dcache.total_refs 1641435 # Total number of references to valid blocks. 1201system.cpu1.dcache.sampled_refs 53299 # Sample count of references to valid blocks. 1202system.cpu1.dcache.avg_refs 30.796732 # Average number of references to valid blocks. 1203system.cpu1.dcache.warmup_cycle 1919955450000 # Cycle when the warmup percentage was hit. 1204system.cpu1.dcache.occ_blocks::cpu1.data 417.162104 # Average occupied blocks per requestor 1205system.cpu1.dcache.occ_percent::cpu1.data 0.814770 # Average percentage of cache occupancy 1206system.cpu1.dcache.occ_percent::total 0.814770 # Average percentage of cache occupancy 1207system.cpu1.dcache.ReadReq_hits::cpu1.data 1001433 # number of ReadReq hits 1208system.cpu1.dcache.ReadReq_hits::total 1001433 # number of ReadReq hits 1209system.cpu1.dcache.WriteReq_hits::cpu1.data 616401 # number of WriteReq hits 1210system.cpu1.dcache.WriteReq_hits::total 616401 # number of WriteReq hits 1211system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10836 # number of LoadLockedReq hits 1212system.cpu1.dcache.LoadLockedReq_hits::total 10836 # number of LoadLockedReq hits 1213system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits 1214system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits 1215system.cpu1.dcache.demand_hits::cpu1.data 1617834 # number of demand (read+write) hits 1216system.cpu1.dcache.demand_hits::total 1617834 # number of demand (read+write) hits 1217system.cpu1.dcache.overall_hits::cpu1.data 1617834 # number of overall hits 1218system.cpu1.dcache.overall_hits::total 1617834 # number of overall hits 1219system.cpu1.dcache.ReadReq_misses::cpu1.data 37022 # number of ReadReq misses 1220system.cpu1.dcache.ReadReq_misses::total 37022 # number of ReadReq misses 1221system.cpu1.dcache.WriteReq_misses::cpu1.data 20409 # number of WriteReq misses 1222system.cpu1.dcache.WriteReq_misses::total 20409 # number of WriteReq misses 1223system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 934 # number of LoadLockedReq misses 1224system.cpu1.dcache.LoadLockedReq_misses::total 934 # number of LoadLockedReq misses 1225system.cpu1.dcache.StoreCondReq_misses::cpu1.data 508 # number of StoreCondReq misses 1226system.cpu1.dcache.StoreCondReq_misses::total 508 # number of StoreCondReq misses 1227system.cpu1.dcache.demand_misses::cpu1.data 57431 # number of demand (read+write) misses 1228system.cpu1.dcache.demand_misses::total 57431 # number of demand (read+write) misses 1229system.cpu1.dcache.overall_misses::cpu1.data 57431 # number of overall misses 1230system.cpu1.dcache.overall_misses::total 57431 # number of overall misses 1231system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 462724500 # number of ReadReq miss cycles 1232system.cpu1.dcache.ReadReq_miss_latency::total 462724500 # number of ReadReq miss cycles 1233system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 544418500 # number of WriteReq miss cycles 1234system.cpu1.dcache.WriteReq_miss_latency::total 544418500 # number of WriteReq miss cycles 1235system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10274000 # number of LoadLockedReq miss cycles 1236system.cpu1.dcache.LoadLockedReq_miss_latency::total 10274000 # number of LoadLockedReq miss cycles 1237system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3750500 # number of StoreCondReq miss cycles 1238system.cpu1.dcache.StoreCondReq_miss_latency::total 3750500 # number of StoreCondReq miss cycles 1239system.cpu1.dcache.demand_miss_latency::cpu1.data 1007143000 # number of demand (read+write) miss cycles 1240system.cpu1.dcache.demand_miss_latency::total 1007143000 # number of demand (read+write) miss cycles 1241system.cpu1.dcache.overall_miss_latency::cpu1.data 1007143000 # number of overall miss cycles 1242system.cpu1.dcache.overall_miss_latency::total 1007143000 # number of overall miss cycles 1243system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038455 # number of ReadReq accesses(hits+misses) 1244system.cpu1.dcache.ReadReq_accesses::total 1038455 # number of ReadReq accesses(hits+misses) 1245system.cpu1.dcache.WriteReq_accesses::cpu1.data 636810 # number of WriteReq accesses(hits+misses) 1246system.cpu1.dcache.WriteReq_accesses::total 636810 # number of WriteReq accesses(hits+misses) 1247system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 11770 # number of LoadLockedReq accesses(hits+misses) 1248system.cpu1.dcache.LoadLockedReq_accesses::total 11770 # number of LoadLockedReq accesses(hits+misses) 1249system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11711 # number of StoreCondReq accesses(hits+misses) 1250system.cpu1.dcache.StoreCondReq_accesses::total 11711 # number of StoreCondReq accesses(hits+misses) 1251system.cpu1.dcache.demand_accesses::cpu1.data 1675265 # number of demand (read+write) accesses 1252system.cpu1.dcache.demand_accesses::total 1675265 # number of demand (read+write) accesses 1253system.cpu1.dcache.overall_accesses::cpu1.data 1675265 # number of overall (read+write) accesses 1254system.cpu1.dcache.overall_accesses::total 1675265 # number of overall (read+write) accesses 1255system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035651 # miss rate for ReadReq accesses 1256system.cpu1.dcache.ReadReq_miss_rate::total 0.035651 # miss rate for ReadReq accesses 1257system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032049 # miss rate for WriteReq accesses 1258system.cpu1.dcache.WriteReq_miss_rate::total 0.032049 # miss rate for WriteReq accesses 1259system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.079354 # miss rate for LoadLockedReq accesses 1260system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.079354 # miss rate for LoadLockedReq accesses 1261system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.043378 # miss rate for StoreCondReq accesses 1262system.cpu1.dcache.StoreCondReq_miss_rate::total 0.043378 # miss rate for StoreCondReq accesses 1263system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034282 # miss rate for demand accesses 1264system.cpu1.dcache.demand_miss_rate::total 0.034282 # miss rate for demand accesses 1265system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034282 # miss rate for overall accesses 1266system.cpu1.dcache.overall_miss_rate::total 0.034282 # miss rate for overall accesses 1267system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12498.635946 # average ReadReq miss latency 1268system.cpu1.dcache.ReadReq_avg_miss_latency::total 12498.635946 # average ReadReq miss latency 1269system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26675.412808 # average WriteReq miss latency 1270system.cpu1.dcache.WriteReq_avg_miss_latency::total 26675.412808 # average WriteReq miss latency 1271system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11000 # average LoadLockedReq miss latency 1272system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11000 # average LoadLockedReq miss latency 1273system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7382.874016 # average StoreCondReq miss latency 1274system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7382.874016 # average StoreCondReq miss latency 1275system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17536.574324 # average overall miss latency 1276system.cpu1.dcache.demand_avg_miss_latency::total 17536.574324 # average overall miss latency 1277system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17536.574324 # average overall miss latency 1278system.cpu1.dcache.overall_avg_miss_latency::total 17536.574324 # average overall miss latency | 1494system.cpu1.dcache.replacements 161925 # number of replacements 1495system.cpu1.dcache.tagsinuse 486.809606 # Cycle average of tags in use 1496system.cpu1.dcache.total_refs 3976206 # Total number of references to valid blocks. 1497system.cpu1.dcache.sampled_refs 162254 # Sample count of references to valid blocks. 1498system.cpu1.dcache.avg_refs 24.506058 # Average number of references to valid blocks. 1499system.cpu1.dcache.warmup_cycle 70872567000 # Cycle when the warmup percentage was hit. 1500system.cpu1.dcache.occ_blocks::cpu1.data 486.809606 # Average occupied blocks per requestor 1501system.cpu1.dcache.occ_percent::cpu1.data 0.950800 # Average percentage of cache occupancy 1502system.cpu1.dcache.occ_percent::total 0.950800 # Average percentage of cache occupancy 1503system.cpu1.dcache.ReadReq_hits::cpu1.data 2251927 # number of ReadReq hits 1504system.cpu1.dcache.ReadReq_hits::total 2251927 # number of ReadReq hits 1505system.cpu1.dcache.WriteReq_hits::cpu1.data 1621193 # number of WriteReq hits 1506system.cpu1.dcache.WriteReq_hits::total 1621193 # number of WriteReq hits 1507system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 49026 # number of LoadLockedReq hits 1508system.cpu1.dcache.LoadLockedReq_hits::total 49026 # number of LoadLockedReq hits 1509system.cpu1.dcache.StoreCondReq_hits::cpu1.data 51669 # number of StoreCondReq hits 1510system.cpu1.dcache.StoreCondReq_hits::total 51669 # number of StoreCondReq hits 1511system.cpu1.dcache.demand_hits::cpu1.data 3873120 # number of demand (read+write) hits 1512system.cpu1.dcache.demand_hits::total 3873120 # number of demand (read+write) hits 1513system.cpu1.dcache.overall_hits::cpu1.data 3873120 # number of overall hits 1514system.cpu1.dcache.overall_hits::total 3873120 # number of overall hits 1515system.cpu1.dcache.ReadReq_misses::cpu1.data 118911 # number of ReadReq misses 1516system.cpu1.dcache.ReadReq_misses::total 118911 # number of ReadReq misses 1517system.cpu1.dcache.WriteReq_misses::cpu1.data 58093 # number of WriteReq misses 1518system.cpu1.dcache.WriteReq_misses::total 58093 # number of WriteReq misses 1519system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9306 # number of LoadLockedReq misses 1520system.cpu1.dcache.LoadLockedReq_misses::total 9306 # number of LoadLockedReq misses 1521system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6171 # number of StoreCondReq misses 1522system.cpu1.dcache.StoreCondReq_misses::total 6171 # number of StoreCondReq misses 1523system.cpu1.dcache.demand_misses::cpu1.data 177004 # number of demand (read+write) misses 1524system.cpu1.dcache.demand_misses::total 177004 # number of demand (read+write) misses 1525system.cpu1.dcache.overall_misses::cpu1.data 177004 # number of overall misses 1526system.cpu1.dcache.overall_misses::total 177004 # number of overall misses 1527system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440878500 # number of ReadReq miss cycles 1528system.cpu1.dcache.ReadReq_miss_latency::total 1440878500 # number of ReadReq miss cycles 1529system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1041850000 # number of WriteReq miss cycles 1530system.cpu1.dcache.WriteReq_miss_latency::total 1041850000 # number of WriteReq miss cycles 1531system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84410500 # number of LoadLockedReq miss cycles 1532system.cpu1.dcache.LoadLockedReq_miss_latency::total 84410500 # number of LoadLockedReq miss cycles 1533system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44897500 # number of StoreCondReq miss cycles 1534system.cpu1.dcache.StoreCondReq_miss_latency::total 44897500 # number of StoreCondReq miss cycles 1535system.cpu1.dcache.demand_miss_latency::cpu1.data 2482728500 # number of demand (read+write) miss cycles 1536system.cpu1.dcache.demand_miss_latency::total 2482728500 # number of demand (read+write) miss cycles 1537system.cpu1.dcache.overall_miss_latency::cpu1.data 2482728500 # number of overall miss cycles 1538system.cpu1.dcache.overall_miss_latency::total 2482728500 # number of overall miss cycles 1539system.cpu1.dcache.ReadReq_accesses::cpu1.data 2370838 # number of ReadReq accesses(hits+misses) 1540system.cpu1.dcache.ReadReq_accesses::total 2370838 # number of ReadReq accesses(hits+misses) 1541system.cpu1.dcache.WriteReq_accesses::cpu1.data 1679286 # number of WriteReq accesses(hits+misses) 1542system.cpu1.dcache.WriteReq_accesses::total 1679286 # number of WriteReq accesses(hits+misses) 1543system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 58332 # number of LoadLockedReq accesses(hits+misses) 1544system.cpu1.dcache.LoadLockedReq_accesses::total 58332 # number of LoadLockedReq accesses(hits+misses) 1545system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 57840 # number of StoreCondReq accesses(hits+misses) 1546system.cpu1.dcache.StoreCondReq_accesses::total 57840 # number of StoreCondReq accesses(hits+misses) 1547system.cpu1.dcache.demand_accesses::cpu1.data 4050124 # number of demand (read+write) accesses 1548system.cpu1.dcache.demand_accesses::total 4050124 # number of demand (read+write) accesses 1549system.cpu1.dcache.overall_accesses::cpu1.data 4050124 # number of overall (read+write) accesses 1550system.cpu1.dcache.overall_accesses::total 4050124 # number of overall (read+write) accesses 1551system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050156 # miss rate for ReadReq accesses 1552system.cpu1.dcache.ReadReq_miss_rate::total 0.050156 # miss rate for ReadReq accesses 1553system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034594 # miss rate for WriteReq accesses 1554system.cpu1.dcache.WriteReq_miss_rate::total 0.034594 # miss rate for WriteReq accesses 1555system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159535 # miss rate for LoadLockedReq accesses 1556system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159535 # miss rate for LoadLockedReq accesses 1557system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106691 # miss rate for StoreCondReq accesses 1558system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106691 # miss rate for StoreCondReq accesses 1559system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043703 # miss rate for demand accesses 1560system.cpu1.dcache.demand_miss_rate::total 0.043703 # miss rate for demand accesses 1561system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043703 # miss rate for overall accesses 1562system.cpu1.dcache.overall_miss_rate::total 0.043703 # miss rate for overall accesses 1563system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12117.285196 # average ReadReq miss latency 1564system.cpu1.dcache.ReadReq_avg_miss_latency::total 12117.285196 # average ReadReq miss latency 1565system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17934.174513 # average WriteReq miss latency 1566system.cpu1.dcache.WriteReq_avg_miss_latency::total 17934.174513 # average WriteReq miss latency 1567system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9070.545884 # average LoadLockedReq miss latency 1568system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9070.545884 # average LoadLockedReq miss latency 1569system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7275.563118 # average StoreCondReq miss latency 1570system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7275.563118 # average StoreCondReq miss latency 1571system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14026.397709 # average overall miss latency 1572system.cpu1.dcache.demand_avg_miss_latency::total 14026.397709 # average overall miss latency 1573system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14026.397709 # average overall miss latency 1574system.cpu1.dcache.overall_avg_miss_latency::total 14026.397709 # average overall miss latency |
| 1279system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1280system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1281system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1282system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1283system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1284system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1285system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1286system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1575system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1576system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1577system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1578system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1579system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1580system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1581system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1582system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1287system.cpu1.dcache.writebacks::writebacks 30625 # number of writebacks 1288system.cpu1.dcache.writebacks::total 30625 # number of writebacks 1289system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37022 # number of ReadReq MSHR misses 1290system.cpu1.dcache.ReadReq_mshr_misses::total 37022 # number of ReadReq MSHR misses 1291system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20409 # number of WriteReq MSHR misses 1292system.cpu1.dcache.WriteReq_mshr_misses::total 20409 # number of WriteReq MSHR misses 1293system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 934 # number of LoadLockedReq MSHR misses 1294system.cpu1.dcache.LoadLockedReq_mshr_misses::total 934 # number of LoadLockedReq MSHR misses 1295system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 508 # number of StoreCondReq MSHR misses 1296system.cpu1.dcache.StoreCondReq_mshr_misses::total 508 # number of StoreCondReq MSHR misses 1297system.cpu1.dcache.demand_mshr_misses::cpu1.data 57431 # number of demand (read+write) MSHR misses 1298system.cpu1.dcache.demand_mshr_misses::total 57431 # number of demand (read+write) MSHR misses 1299system.cpu1.dcache.overall_mshr_misses::cpu1.data 57431 # number of overall MSHR misses 1300system.cpu1.dcache.overall_mshr_misses::total 57431 # number of overall MSHR misses 1301system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 388680500 # number of ReadReq MSHR miss cycles 1302system.cpu1.dcache.ReadReq_mshr_miss_latency::total 388680500 # number of ReadReq MSHR miss cycles 1303system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 503600500 # number of WriteReq MSHR miss cycles 1304system.cpu1.dcache.WriteReq_mshr_miss_latency::total 503600500 # number of WriteReq MSHR miss cycles 1305system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8406000 # number of LoadLockedReq MSHR miss cycles 1306system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8406000 # number of LoadLockedReq MSHR miss cycles 1307system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2734500 # number of StoreCondReq MSHR miss cycles 1308system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2734500 # number of StoreCondReq MSHR miss cycles 1309system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 892281000 # number of demand (read+write) MSHR miss cycles 1310system.cpu1.dcache.demand_mshr_miss_latency::total 892281000 # number of demand (read+write) MSHR miss cycles 1311system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 892281000 # number of overall MSHR miss cycles 1312system.cpu1.dcache.overall_mshr_miss_latency::total 892281000 # number of overall MSHR miss cycles 1313system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles 1314system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles 1315system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 530266500 # number of WriteReq MSHR uncacheable cycles 1316system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 530266500 # number of WriteReq MSHR uncacheable cycles 1317system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 549654000 # number of overall MSHR uncacheable cycles 1318system.cpu1.dcache.overall_mshr_uncacheable_latency::total 549654000 # number of overall MSHR uncacheable cycles 1319system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035651 # mshr miss rate for ReadReq accesses 1320system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035651 # mshr miss rate for ReadReq accesses 1321system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032049 # mshr miss rate for WriteReq accesses 1322system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032049 # mshr miss rate for WriteReq accesses 1323system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.079354 # mshr miss rate for LoadLockedReq accesses 1324system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.079354 # mshr miss rate for LoadLockedReq accesses 1325system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043378 # mshr miss rate for StoreCondReq accesses 1326system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043378 # mshr miss rate for StoreCondReq accesses 1327system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034282 # mshr miss rate for demand accesses 1328system.cpu1.dcache.demand_mshr_miss_rate::total 0.034282 # mshr miss rate for demand accesses 1329system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034282 # mshr miss rate for overall accesses 1330system.cpu1.dcache.overall_mshr_miss_rate::total 0.034282 # mshr miss rate for overall accesses 1331system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10498.635946 # average ReadReq mshr miss latency 1332system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10498.635946 # average ReadReq mshr miss latency 1333system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24675.412808 # average WriteReq mshr miss latency 1334system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24675.412808 # average WriteReq mshr miss latency 1335system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9000 # average LoadLockedReq mshr miss latency 1336system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9000 # average LoadLockedReq mshr miss latency 1337system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5382.874016 # average StoreCondReq mshr miss latency 1338system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5382.874016 # average StoreCondReq mshr miss latency 1339system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency 1340system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency 1341system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency 1342system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency | 1583system.cpu1.dcache.writebacks::writebacks 111584 # number of writebacks 1584system.cpu1.dcache.writebacks::total 111584 # number of writebacks 1585system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118911 # number of ReadReq MSHR misses 1586system.cpu1.dcache.ReadReq_mshr_misses::total 118911 # number of ReadReq MSHR misses 1587system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58093 # number of WriteReq MSHR misses 1588system.cpu1.dcache.WriteReq_mshr_misses::total 58093 # number of WriteReq MSHR misses 1589system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9306 # number of LoadLockedReq MSHR misses 1590system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9306 # number of LoadLockedReq MSHR misses 1591system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6171 # number of StoreCondReq MSHR misses 1592system.cpu1.dcache.StoreCondReq_mshr_misses::total 6171 # number of StoreCondReq MSHR misses 1593system.cpu1.dcache.demand_mshr_misses::cpu1.data 177004 # number of demand (read+write) MSHR misses 1594system.cpu1.dcache.demand_mshr_misses::total 177004 # number of demand (read+write) MSHR misses 1595system.cpu1.dcache.overall_mshr_misses::cpu1.data 177004 # number of overall MSHR misses 1596system.cpu1.dcache.overall_mshr_misses::total 177004 # number of overall MSHR misses 1597system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203056001 # number of ReadReq MSHR miss cycles 1598system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203056001 # number of ReadReq MSHR miss cycles 1599system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 925664000 # number of WriteReq MSHR miss cycles 1600system.cpu1.dcache.WriteReq_mshr_miss_latency::total 925664000 # number of WriteReq MSHR miss cycles 1601system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65798500 # number of LoadLockedReq MSHR miss cycles 1602system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 65798500 # number of LoadLockedReq MSHR miss cycles 1603system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32557500 # number of StoreCondReq MSHR miss cycles 1604system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32557500 # number of StoreCondReq MSHR miss cycles 1605system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1606system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1607system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2128720001 # number of demand (read+write) MSHR miss cycles 1608system.cpu1.dcache.demand_mshr_miss_latency::total 2128720001 # number of demand (read+write) MSHR miss cycles 1609system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2128720001 # number of overall MSHR miss cycles 1610system.cpu1.dcache.overall_mshr_miss_latency::total 2128720001 # number of overall MSHR miss cycles 1611system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18768000 # number of ReadReq MSHR uncacheable cycles 1612system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18768000 # number of ReadReq MSHR uncacheable cycles 1613system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 722866000 # number of WriteReq MSHR uncacheable cycles 1614system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 722866000 # number of WriteReq MSHR uncacheable cycles 1615system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 741634000 # number of overall MSHR uncacheable cycles 1616system.cpu1.dcache.overall_mshr_uncacheable_latency::total 741634000 # number of overall MSHR uncacheable cycles 1617system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050156 # mshr miss rate for ReadReq accesses 1618system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050156 # mshr miss rate for ReadReq accesses 1619system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034594 # mshr miss rate for WriteReq accesses 1620system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034594 # mshr miss rate for WriteReq accesses 1621system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159535 # mshr miss rate for LoadLockedReq accesses 1622system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159535 # mshr miss rate for LoadLockedReq accesses 1623system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106691 # mshr miss rate for StoreCondReq accesses 1624system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106691 # mshr miss rate for StoreCondReq accesses 1625system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for demand accesses 1626system.cpu1.dcache.demand_mshr_miss_rate::total 0.043703 # mshr miss rate for demand accesses 1627system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for overall accesses 1628system.cpu1.dcache.overall_mshr_miss_rate::total 0.043703 # mshr miss rate for overall accesses 1629system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10117.281000 # average ReadReq mshr miss latency 1630system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10117.281000 # average ReadReq mshr miss latency 1631system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15934.174513 # average WriteReq mshr miss latency 1632system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15934.174513 # average WriteReq mshr miss latency 1633system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7070.545884 # average LoadLockedReq mshr miss latency 1634system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7070.545884 # average LoadLockedReq mshr miss latency 1635system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5275.887214 # average StoreCondReq mshr miss latency 1636system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5275.887214 # average StoreCondReq mshr miss latency 1637system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1638system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1639system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency 1640system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency 1641system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency 1642system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency |
| 1343system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1344system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1345system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1346system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1347system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1348system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1349system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1350 1351---------- End Simulation Statistics ---------- | 1643system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1644system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1645system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1646system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1647system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1648system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1649system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1650 1651---------- End Simulation Statistics ---------- |