| stats.txt (9481:b0fa6b872f40) | stats.txt (9490:e6a09d97bdc9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.950814 # Number of seconds simulated 4sim_ticks 1950813955500 # Number of ticks simulated 5final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.952724 # Number of seconds simulated 4sim_ticks 1952724269500 # Number of ticks simulated 5final_tick 1952724269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 720692 # Simulator instruction rate (inst/s) 8host_op_rate 720692 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 23054537293 # Simulator tick rate (ticks/s) 10host_mem_usage 378432 # Number of bytes of host memory used 11host_seconds 84.62 # Real time elapsed on the host 12sim_insts 60983017 # Number of instructions simulated 13sim_ops 60983017 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24727744 # Number of bytes read from this memory | 7host_inst_rate 1678586 # Simulator instruction rate (inst/s) 8host_op_rate 1678585 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53851852439 # Simulator tick rate (ticks/s) 10host_mem_usage 333452 # Number of bytes of host memory used 11host_seconds 36.26 # Real time elapsed on the host 12sim_insts 60867235 # Number of instructions simulated 13sim_ops 60867235 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 830208 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24725568 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory | 16system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 439872 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28684224 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7706496 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7706496 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 386371 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 438144 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28680000 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 830208 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 865408 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7698816 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7698816 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 12972 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 386337 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory | 27system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 6873 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 448191 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120414 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120414 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12675603 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1358858 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 225481 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14703721 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 3950400 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3950400 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3950400 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12675603 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1358858 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 225481 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18654121 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 448191 # Total number of read requests seen 52system.physmem.writeReqs 120414 # Total number of write requests seen 53system.physmem.cpureqs 599152 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28684224 # Total number of bytes read from memory 55system.physmem.bytesWritten 7706496 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28684224 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7706496 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 7175 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 27649 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7159 # Track writes on a per bank basis | 28system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 6846 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 448125 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120294 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120294 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 425154 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12662089 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1357529 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 18026 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 224376 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14687173 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 425154 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 18026 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 443180 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 3942603 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3942603 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3942603 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 425154 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12662089 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1357529 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 18026 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 224376 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18629776 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 448125 # Total number of read requests seen 52system.physmem.writeReqs 120294 # Total number of write requests seen 53system.physmem.cpureqs 598443 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28680000 # Total number of bytes read from memory 55system.physmem.bytesWritten 7698816 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28680000 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7698816 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 6945 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28344 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 28173 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28017 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 27785 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 27951 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 27964 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 28022 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 27886 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28437 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28288 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 28341 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 28051 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 27575 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 27797 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27570 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 27856 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7610 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7567 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7380 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7470 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7435 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7506 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7992 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7835 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7874 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7588 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 7131 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7029 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7371 # Track writes on a per bank basis |
| 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 93system.physmem.numWrRetry 530 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1950760240000 # Total gap between requests | 93system.physmem.numWrRetry 1406 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1952670553500 # Total gap between requests |
| 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes | 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 101system.physmem.readPktSize::6 448191 # Categorize read packet sizes | 101system.physmem.readPktSize::6 448125 # Categorize read packet sizes |
| 102system.physmem.readPktSize::7 0 # Categorize read packet sizes 103system.physmem.readPktSize::8 0 # Categorize read packet sizes 104system.physmem.writePktSize::0 0 # categorize write packet sizes 105system.physmem.writePktSize::1 0 # categorize write packet sizes 106system.physmem.writePktSize::2 0 # categorize write packet sizes 107system.physmem.writePktSize::3 0 # categorize write packet sizes 108system.physmem.writePktSize::4 0 # categorize write packet sizes 109system.physmem.writePktSize::5 0 # categorize write packet sizes | 102system.physmem.readPktSize::7 0 # Categorize read packet sizes 103system.physmem.readPktSize::8 0 # Categorize read packet sizes 104system.physmem.writePktSize::0 0 # categorize write packet sizes 105system.physmem.writePktSize::1 0 # categorize write packet sizes 106system.physmem.writePktSize::2 0 # categorize write packet sizes 107system.physmem.writePktSize::3 0 # categorize write packet sizes 108system.physmem.writePktSize::4 0 # categorize write packet sizes 109system.physmem.writePktSize::5 0 # categorize write packet sizes |
| 110system.physmem.writePktSize::6 120944 # categorize write packet sizes | 110system.physmem.writePktSize::6 121700 # categorize write packet sizes |
| 111system.physmem.writePktSize::7 0 # categorize write packet sizes 112system.physmem.writePktSize::8 0 # categorize write packet sizes 113system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::5 0 # categorize neither packet sizes | 111system.physmem.writePktSize::7 0 # categorize write packet sizes 112system.physmem.writePktSize::8 0 # categorize write packet sizes 113system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::5 0 # categorize neither packet sizes |
| 119system.physmem.neitherpktsize::6 7175 # categorize neither packet sizes | 119system.physmem.neitherpktsize::6 6945 # categorize neither packet sizes |
| 120system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 121system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 120system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 121system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| 122system.physmem.rdQLenPdf::0 409750 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::1 7530 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::2 5264 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::3 2349 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::4 2844 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::5 2407 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::6 1780 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::7 2013 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::8 1657 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::11 1572 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::12 1655 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::13 1735 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::14 1232 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::15 1426 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see | 122system.physmem.rdQLenPdf::0 407346 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::1 4785 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::3 2222 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::7 2681 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::8 2639 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::10 1535 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::11 1459 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::14 1370 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::15 1401 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::17 1508 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::18 906 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::19 771 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see |
| 143system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see | 143system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see |
| 155system.physmem.wrQLenPdf::0 4348 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 4960 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 5066 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 5108 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 5181 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 5228 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 5235 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 5235 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 5235 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 5235 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 5235 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 5235 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 5235 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 5235 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 5235 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 5235 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::23 888 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 276 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 55 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 39 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see | 155system.physmem.wrQLenPdf::0 3696 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 3880 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 4344 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 4866 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 5206 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 5215 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::7 5216 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 5218 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 5230 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 5230 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 5230 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 5230 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 5230 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 5230 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 5230 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 5230 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 5230 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 5230 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 5230 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 5230 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 5230 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 5230 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::23 1535 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 1351 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 887 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 364 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see |
| 187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 188system.physmem.totQLat 2917085023 # Total cycles spent in queuing delays 189system.physmem.totMemAccLat 10998617023 # Sum of mem lat for all requests 190system.physmem.totBusLat 1792536000 # Total cycles spent in databus access 191system.physmem.totBankLat 6288996000 # Total cycles spent in bank access 192system.physmem.avgQLat 6509.40 # Average queueing delay per request 193system.physmem.avgBankLat 14033.74 # Average bank access latency per request 194system.physmem.avgBusLat 4000.00 # Average bus latency per request 195system.physmem.avgMemAccLat 24543.14 # Average memory access latency 196system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s 197system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s 198system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s 199system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s 200system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 201system.physmem.busUtil 0.12 # Data bus utilization in percentage | 188system.physmem.totQLat 4798545467 # Total cycles spent in queuing delays 189system.physmem.totMemAccLat 13448530467 # Sum of mem lat for all requests 190system.physmem.totBusLat 2240285000 # Total cycles spent in databus access 191system.physmem.totBankLat 6409700000 # Total cycles spent in bank access 192system.physmem.avgQLat 10709.68 # Average queueing delay per request 193system.physmem.avgBankLat 14305.55 # Average bank access latency per request 194system.physmem.avgBusLat 5000.00 # Average bus latency per request 195system.physmem.avgMemAccLat 30015.22 # Average memory access latency 196system.physmem.avgRdBW 14.69 # Average achieved read bandwidth in MB/s 197system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MB/s 198system.physmem.avgConsumedRdBW 14.69 # Average consumed read bandwidth in MB/s 199system.physmem.avgConsumedWrBW 3.94 # Average consumed write bandwidth in MB/s 200system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 201system.physmem.busUtil 0.15 # Data bus utilization in percentage |
| 202system.physmem.avgRdQLen 0.01 # Average read queue length over time | 202system.physmem.avgRdQLen 0.01 # Average read queue length over time |
| 203system.physmem.avgWrQLen 10.51 # Average write queue length over time 204system.physmem.readRowHits 428061 # Number of row buffer hits during reads 205system.physmem.writeRowHits 76773 # Number of row buffer hits during writes 206system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads 207system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes 208system.physmem.avgGap 3430782.78 # Average gap between requests 209system.l2c.replacements 341335 # number of replacements 210system.l2c.tagsinuse 65247.035905 # Cycle average of tags in use 211system.l2c.total_refs 2438054 # Total number of references to valid blocks. 212system.l2c.sampled_refs 406311 # Sample count of references to valid blocks. 213system.l2c.avg_refs 6.000463 # Average number of references to valid blocks. 214system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. 215system.l2c.occ_blocks::writebacks 55545.332470 # Average occupied blocks per requestor 216system.l2c.occ_blocks::cpu0.inst 4807.217204 # Average occupied blocks per requestor 217system.l2c.occ_blocks::cpu0.data 4686.652945 # Average occupied blocks per requestor 218system.l2c.occ_blocks::cpu1.inst 164.376424 # Average occupied blocks per requestor 219system.l2c.occ_blocks::cpu1.data 43.456861 # Average occupied blocks per requestor 220system.l2c.occ_percent::writebacks 0.847555 # Average percentage of cache occupancy 221system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy 222system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy 223system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy 224system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy 225system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy 226system.l2c.ReadReq_hits::cpu0.inst 674205 # number of ReadReq hits 227system.l2c.ReadReq_hits::cpu0.data 658217 # number of ReadReq hits 228system.l2c.ReadReq_hits::cpu1.inst 328581 # number of ReadReq hits 229system.l2c.ReadReq_hits::cpu1.data 113535 # number of ReadReq hits 230system.l2c.ReadReq_hits::total 1774538 # number of ReadReq hits 231system.l2c.Writeback_hits::writebacks 791470 # number of Writeback hits 232system.l2c.Writeback_hits::total 791470 # number of Writeback hits 233system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits 234system.l2c.UpgradeReq_hits::cpu1.data 564 # number of UpgradeReq hits 235system.l2c.UpgradeReq_hits::total 738 # number of UpgradeReq hits 236system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits 237system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 238system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits 239system.l2c.ReadExReq_hits::cpu0.data 123887 # number of ReadExReq hits 240system.l2c.ReadExReq_hits::cpu1.data 48972 # number of ReadExReq hits 241system.l2c.ReadExReq_hits::total 172859 # number of ReadExReq hits 242system.l2c.demand_hits::cpu0.inst 674205 # number of demand (read+write) hits 243system.l2c.demand_hits::cpu0.data 782104 # number of demand (read+write) hits 244system.l2c.demand_hits::cpu1.inst 328581 # number of demand (read+write) hits 245system.l2c.demand_hits::cpu1.data 162507 # number of demand (read+write) hits 246system.l2c.demand_hits::total 1947397 # number of demand (read+write) hits 247system.l2c.overall_hits::cpu0.inst 674205 # number of overall hits 248system.l2c.overall_hits::cpu0.data 782104 # number of overall hits 249system.l2c.overall_hits::cpu1.inst 328581 # number of overall hits 250system.l2c.overall_hits::cpu1.data 162507 # number of overall hits 251system.l2c.overall_hits::total 1947397 # number of overall hits 252system.l2c.ReadReq_misses::cpu0.inst 12926 # number of ReadReq misses 253system.l2c.ReadReq_misses::cpu0.data 271631 # number of ReadReq misses 254system.l2c.ReadReq_misses::cpu1.inst 612 # number of ReadReq misses 255system.l2c.ReadReq_misses::cpu1.data 247 # number of ReadReq misses 256system.l2c.ReadReq_misses::total 285416 # number of ReadReq misses 257system.l2c.UpgradeReq_misses::cpu0.data 2969 # number of UpgradeReq misses 258system.l2c.UpgradeReq_misses::cpu1.data 1806 # number of UpgradeReq misses 259system.l2c.UpgradeReq_misses::total 4775 # number of UpgradeReq misses 260system.l2c.SCUpgradeReq_misses::cpu0.data 939 # number of SCUpgradeReq misses 261system.l2c.SCUpgradeReq_misses::cpu1.data 944 # number of SCUpgradeReq misses 262system.l2c.SCUpgradeReq_misses::total 1883 # number of SCUpgradeReq misses 263system.l2c.ReadExReq_misses::cpu0.data 115505 # number of ReadExReq misses 264system.l2c.ReadExReq_misses::cpu1.data 6644 # number of ReadExReq misses 265system.l2c.ReadExReq_misses::total 122149 # number of ReadExReq misses 266system.l2c.demand_misses::cpu0.inst 12926 # number of demand (read+write) misses 267system.l2c.demand_misses::cpu0.data 387136 # number of demand (read+write) misses 268system.l2c.demand_misses::cpu1.inst 612 # number of demand (read+write) misses 269system.l2c.demand_misses::cpu1.data 6891 # number of demand (read+write) misses 270system.l2c.demand_misses::total 407565 # number of demand (read+write) misses 271system.l2c.overall_misses::cpu0.inst 12926 # number of overall misses 272system.l2c.overall_misses::cpu0.data 387136 # number of overall misses 273system.l2c.overall_misses::cpu1.inst 612 # number of overall misses 274system.l2c.overall_misses::cpu1.data 6891 # number of overall misses 275system.l2c.overall_misses::total 407565 # number of overall misses 276system.l2c.ReadReq_miss_latency::cpu0.inst 706675500 # number of ReadReq miss cycles 277system.l2c.ReadReq_miss_latency::cpu0.data 11506519500 # number of ReadReq miss cycles 278system.l2c.ReadReq_miss_latency::cpu1.inst 33342000 # number of ReadReq miss cycles 279system.l2c.ReadReq_miss_latency::cpu1.data 15821000 # number of ReadReq miss cycles 280system.l2c.ReadReq_miss_latency::total 12262358000 # number of ReadReq miss cycles 281system.l2c.UpgradeReq_miss_latency::cpu0.data 1244500 # number of UpgradeReq miss cycles 282system.l2c.UpgradeReq_miss_latency::cpu1.data 10405997 # number of UpgradeReq miss cycles 283system.l2c.UpgradeReq_miss_latency::total 11650497 # number of UpgradeReq miss cycles 284system.l2c.SCUpgradeReq_miss_latency::cpu0.data 840000 # number of SCUpgradeReq miss cycles 285system.l2c.SCUpgradeReq_miss_latency::cpu1.data 182000 # number of SCUpgradeReq miss cycles 286system.l2c.SCUpgradeReq_miss_latency::total 1022000 # number of SCUpgradeReq miss cycles 287system.l2c.ReadExReq_miss_latency::cpu0.data 5700012000 # number of ReadExReq miss cycles 288system.l2c.ReadExReq_miss_latency::cpu1.data 427427500 # number of ReadExReq miss cycles 289system.l2c.ReadExReq_miss_latency::total 6127439500 # number of ReadExReq miss cycles 290system.l2c.demand_miss_latency::cpu0.inst 706675500 # number of demand (read+write) miss cycles 291system.l2c.demand_miss_latency::cpu0.data 17206531500 # number of demand (read+write) miss cycles 292system.l2c.demand_miss_latency::cpu1.inst 33342000 # number of demand (read+write) miss cycles 293system.l2c.demand_miss_latency::cpu1.data 443248500 # number of demand (read+write) miss cycles 294system.l2c.demand_miss_latency::total 18389797500 # number of demand (read+write) miss cycles 295system.l2c.overall_miss_latency::cpu0.inst 706675500 # number of overall miss cycles 296system.l2c.overall_miss_latency::cpu0.data 17206531500 # number of overall miss cycles 297system.l2c.overall_miss_latency::cpu1.inst 33342000 # number of overall miss cycles 298system.l2c.overall_miss_latency::cpu1.data 443248500 # number of overall miss cycles 299system.l2c.overall_miss_latency::total 18389797500 # number of overall miss cycles 300system.l2c.ReadReq_accesses::cpu0.inst 687131 # number of ReadReq accesses(hits+misses) 301system.l2c.ReadReq_accesses::cpu0.data 929848 # number of ReadReq accesses(hits+misses) 302system.l2c.ReadReq_accesses::cpu1.inst 329193 # number of ReadReq accesses(hits+misses) 303system.l2c.ReadReq_accesses::cpu1.data 113782 # number of ReadReq accesses(hits+misses) 304system.l2c.ReadReq_accesses::total 2059954 # number of ReadReq accesses(hits+misses) 305system.l2c.Writeback_accesses::writebacks 791470 # number of Writeback accesses(hits+misses) 306system.l2c.Writeback_accesses::total 791470 # number of Writeback accesses(hits+misses) 307system.l2c.UpgradeReq_accesses::cpu0.data 3143 # number of UpgradeReq accesses(hits+misses) 308system.l2c.UpgradeReq_accesses::cpu1.data 2370 # number of UpgradeReq accesses(hits+misses) 309system.l2c.UpgradeReq_accesses::total 5513 # number of UpgradeReq accesses(hits+misses) 310system.l2c.SCUpgradeReq_accesses::cpu0.data 975 # number of SCUpgradeReq accesses(hits+misses) 311system.l2c.SCUpgradeReq_accesses::cpu1.data 968 # number of SCUpgradeReq accesses(hits+misses) 312system.l2c.SCUpgradeReq_accesses::total 1943 # number of SCUpgradeReq accesses(hits+misses) 313system.l2c.ReadExReq_accesses::cpu0.data 239392 # number of ReadExReq accesses(hits+misses) 314system.l2c.ReadExReq_accesses::cpu1.data 55616 # number of ReadExReq accesses(hits+misses) 315system.l2c.ReadExReq_accesses::total 295008 # number of ReadExReq accesses(hits+misses) 316system.l2c.demand_accesses::cpu0.inst 687131 # number of demand (read+write) accesses 317system.l2c.demand_accesses::cpu0.data 1169240 # number of demand (read+write) accesses 318system.l2c.demand_accesses::cpu1.inst 329193 # number of demand (read+write) accesses 319system.l2c.demand_accesses::cpu1.data 169398 # number of demand (read+write) accesses 320system.l2c.demand_accesses::total 2354962 # number of demand (read+write) accesses 321system.l2c.overall_accesses::cpu0.inst 687131 # number of overall (read+write) accesses 322system.l2c.overall_accesses::cpu0.data 1169240 # number of overall (read+write) accesses 323system.l2c.overall_accesses::cpu1.inst 329193 # number of overall (read+write) accesses 324system.l2c.overall_accesses::cpu1.data 169398 # number of overall (read+write) accesses 325system.l2c.overall_accesses::total 2354962 # number of overall (read+write) accesses 326system.l2c.ReadReq_miss_rate::cpu0.inst 0.018812 # miss rate for ReadReq accesses 327system.l2c.ReadReq_miss_rate::cpu0.data 0.292124 # miss rate for ReadReq accesses 328system.l2c.ReadReq_miss_rate::cpu1.inst 0.001859 # miss rate for ReadReq accesses 329system.l2c.ReadReq_miss_rate::cpu1.data 0.002171 # miss rate for ReadReq accesses 330system.l2c.ReadReq_miss_rate::total 0.138555 # miss rate for ReadReq accesses 331system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944639 # miss rate for UpgradeReq accesses 332system.l2c.UpgradeReq_miss_rate::cpu1.data 0.762025 # miss rate for UpgradeReq accesses 333system.l2c.UpgradeReq_miss_rate::total 0.866135 # miss rate for UpgradeReq accesses 334system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963077 # miss rate for SCUpgradeReq accesses 335system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975207 # miss rate for SCUpgradeReq accesses 336system.l2c.SCUpgradeReq_miss_rate::total 0.969120 # miss rate for SCUpgradeReq accesses 337system.l2c.ReadExReq_miss_rate::cpu0.data 0.482493 # miss rate for ReadExReq accesses 338system.l2c.ReadExReq_miss_rate::cpu1.data 0.119462 # miss rate for ReadExReq accesses 339system.l2c.ReadExReq_miss_rate::total 0.414053 # miss rate for ReadExReq accesses 340system.l2c.demand_miss_rate::cpu0.inst 0.018812 # miss rate for demand accesses 341system.l2c.demand_miss_rate::cpu0.data 0.331101 # miss rate for demand accesses 342system.l2c.demand_miss_rate::cpu1.inst 0.001859 # miss rate for demand accesses 343system.l2c.demand_miss_rate::cpu1.data 0.040679 # miss rate for demand accesses 344system.l2c.demand_miss_rate::total 0.173066 # miss rate for demand accesses 345system.l2c.overall_miss_rate::cpu0.inst 0.018812 # miss rate for overall accesses 346system.l2c.overall_miss_rate::cpu0.data 0.331101 # miss rate for overall accesses 347system.l2c.overall_miss_rate::cpu1.inst 0.001859 # miss rate for overall accesses 348system.l2c.overall_miss_rate::cpu1.data 0.040679 # miss rate for overall accesses 349system.l2c.overall_miss_rate::total 0.173066 # miss rate for overall accesses 350system.l2c.ReadReq_avg_miss_latency::cpu0.inst 54670.857187 # average ReadReq miss latency 351system.l2c.ReadReq_avg_miss_latency::cpu0.data 42360.847989 # average ReadReq miss latency 352system.l2c.ReadReq_avg_miss_latency::cpu1.inst 54480.392157 # average ReadReq miss latency 353system.l2c.ReadReq_avg_miss_latency::cpu1.data 64052.631579 # average ReadReq miss latency 354system.l2c.ReadReq_avg_miss_latency::total 42963.106483 # average ReadReq miss latency 355system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 419.164702 # average UpgradeReq miss latency 356system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5761.903101 # average UpgradeReq miss latency 357system.l2c.UpgradeReq_avg_miss_latency::total 2439.894660 # average UpgradeReq miss latency 358system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 894.568690 # average SCUpgradeReq miss latency 359system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 192.796610 # average SCUpgradeReq miss latency 360system.l2c.SCUpgradeReq_avg_miss_latency::total 542.750929 # average SCUpgradeReq miss latency 361system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49348.616943 # average ReadExReq miss latency 362system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64332.856713 # average ReadExReq miss latency 363system.l2c.ReadExReq_avg_miss_latency::total 50163.648495 # average ReadExReq miss latency 364system.l2c.demand_avg_miss_latency::cpu0.inst 54670.857187 # average overall miss latency 365system.l2c.demand_avg_miss_latency::cpu0.data 44445.702544 # average overall miss latency 366system.l2c.demand_avg_miss_latency::cpu1.inst 54480.392157 # average overall miss latency 367system.l2c.demand_avg_miss_latency::cpu1.data 64322.812364 # average overall miss latency 368system.l2c.demand_avg_miss_latency::total 45121.140186 # average overall miss latency 369system.l2c.overall_avg_miss_latency::cpu0.inst 54670.857187 # average overall miss latency 370system.l2c.overall_avg_miss_latency::cpu0.data 44445.702544 # average overall miss latency 371system.l2c.overall_avg_miss_latency::cpu1.inst 54480.392157 # average overall miss latency 372system.l2c.overall_avg_miss_latency::cpu1.data 64322.812364 # average overall miss latency 373system.l2c.overall_avg_miss_latency::total 45121.140186 # average overall miss latency | 203system.physmem.avgWrQLen 10.11 # Average write queue length over time 204system.physmem.readRowHits 419119 # Number of row buffer hits during reads 205system.physmem.writeRowHits 92373 # Number of row buffer hits during writes 206system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads 207system.physmem.writeRowHitRate 76.79 # Row buffer hit rate for writes 208system.physmem.avgGap 3435266.16 # Average gap between requests 209system.l2c.replacements 341268 # number of replacements 210system.l2c.tagsinuse 65240.270273 # Cycle average of tags in use 211system.l2c.total_refs 2443367 # Total number of references to valid blocks. 212system.l2c.sampled_refs 406244 # Sample count of references to valid blocks. 213system.l2c.avg_refs 6.014531 # Average number of references to valid blocks. 214system.l2c.warmup_cycle 6941595752 # Cycle when the warmup percentage was hit. 215system.l2c.occ_blocks::writebacks 55425.253207 # Average occupied blocks per requestor 216system.l2c.occ_blocks::cpu0.inst 4870.495631 # Average occupied blocks per requestor 217system.l2c.occ_blocks::cpu0.data 4790.652765 # Average occupied blocks per requestor 218system.l2c.occ_blocks::cpu1.inst 116.277662 # Average occupied blocks per requestor 219system.l2c.occ_blocks::cpu1.data 37.591009 # Average occupied blocks per requestor 220system.l2c.occ_percent::writebacks 0.845722 # Average percentage of cache occupancy 221system.l2c.occ_percent::cpu0.inst 0.074318 # Average percentage of cache occupancy 222system.l2c.occ_percent::cpu0.data 0.073100 # Average percentage of cache occupancy 223system.l2c.occ_percent::cpu1.inst 0.001774 # Average percentage of cache occupancy 224system.l2c.occ_percent::cpu1.data 0.000574 # Average percentage of cache occupancy 225system.l2c.occ_percent::total 0.995488 # Average percentage of cache occupancy 226system.l2c.ReadReq_hits::cpu0.inst 687318 # number of ReadReq hits 227system.l2c.ReadReq_hits::cpu0.data 665852 # number of ReadReq hits 228system.l2c.ReadReq_hits::cpu1.inst 314877 # number of ReadReq hits 229system.l2c.ReadReq_hits::cpu1.data 108330 # number of ReadReq hits 230system.l2c.ReadReq_hits::total 1776377 # number of ReadReq hits 231system.l2c.Writeback_hits::writebacks 794206 # number of Writeback hits 232system.l2c.Writeback_hits::total 794206 # number of Writeback hits 233system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits 234system.l2c.UpgradeReq_hits::cpu1.data 530 # number of UpgradeReq hits 235system.l2c.UpgradeReq_hits::total 702 # number of UpgradeReq hits 236system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits 237system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits 238system.l2c.SCUpgradeReq_hits::total 62 # number of SCUpgradeReq hits 239system.l2c.ReadExReq_hits::cpu0.data 126888 # number of ReadExReq hits 240system.l2c.ReadExReq_hits::cpu1.data 47007 # number of ReadExReq hits 241system.l2c.ReadExReq_hits::total 173895 # number of ReadExReq hits 242system.l2c.demand_hits::cpu0.inst 687318 # number of demand (read+write) hits 243system.l2c.demand_hits::cpu0.data 792740 # number of demand (read+write) hits 244system.l2c.demand_hits::cpu1.inst 314877 # number of demand (read+write) hits 245system.l2c.demand_hits::cpu1.data 155337 # number of demand (read+write) hits 246system.l2c.demand_hits::total 1950272 # number of demand (read+write) hits 247system.l2c.overall_hits::cpu0.inst 687318 # number of overall hits 248system.l2c.overall_hits::cpu0.data 792740 # number of overall hits 249system.l2c.overall_hits::cpu1.inst 314877 # number of overall hits 250system.l2c.overall_hits::cpu1.data 155337 # number of overall hits 251system.l2c.overall_hits::total 1950272 # number of overall hits 252system.l2c.ReadReq_misses::cpu0.inst 12972 # number of ReadReq misses 253system.l2c.ReadReq_misses::cpu0.data 271609 # number of ReadReq misses 254system.l2c.ReadReq_misses::cpu1.inst 561 # number of ReadReq misses 255system.l2c.ReadReq_misses::cpu1.data 240 # number of ReadReq misses 256system.l2c.ReadReq_misses::total 285382 # number of ReadReq misses 257system.l2c.UpgradeReq_misses::cpu0.data 2946 # number of UpgradeReq misses 258system.l2c.UpgradeReq_misses::cpu1.data 1731 # number of UpgradeReq misses 259system.l2c.UpgradeReq_misses::total 4677 # number of UpgradeReq misses 260system.l2c.SCUpgradeReq_misses::cpu0.data 877 # number of SCUpgradeReq misses 261system.l2c.SCUpgradeReq_misses::cpu1.data 894 # number of SCUpgradeReq misses 262system.l2c.SCUpgradeReq_misses::total 1771 # number of SCUpgradeReq misses 263system.l2c.ReadExReq_misses::cpu0.data 115472 # number of ReadExReq misses 264system.l2c.ReadExReq_misses::cpu1.data 6625 # number of ReadExReq misses 265system.l2c.ReadExReq_misses::total 122097 # number of ReadExReq misses 266system.l2c.demand_misses::cpu0.inst 12972 # number of demand (read+write) misses 267system.l2c.demand_misses::cpu0.data 387081 # number of demand (read+write) misses 268system.l2c.demand_misses::cpu1.inst 561 # number of demand (read+write) misses 269system.l2c.demand_misses::cpu1.data 6865 # number of demand (read+write) misses 270system.l2c.demand_misses::total 407479 # number of demand (read+write) misses 271system.l2c.overall_misses::cpu0.inst 12972 # number of overall misses 272system.l2c.overall_misses::cpu0.data 387081 # number of overall misses 273system.l2c.overall_misses::cpu1.inst 561 # number of overall misses 274system.l2c.overall_misses::cpu1.data 6865 # number of overall misses 275system.l2c.overall_misses::total 407479 # number of overall misses 276system.l2c.ReadReq_miss_latency::cpu0.inst 816098500 # number of ReadReq miss cycles 277system.l2c.ReadReq_miss_latency::cpu0.data 11712193000 # number of ReadReq miss cycles 278system.l2c.ReadReq_miss_latency::cpu1.inst 36330000 # number of ReadReq miss cycles 279system.l2c.ReadReq_miss_latency::cpu1.data 18796500 # number of ReadReq miss cycles 280system.l2c.ReadReq_miss_latency::total 12583418000 # number of ReadReq miss cycles 281system.l2c.UpgradeReq_miss_latency::cpu0.data 1197000 # number of UpgradeReq miss cycles 282system.l2c.UpgradeReq_miss_latency::cpu1.data 9651997 # number of UpgradeReq miss cycles 283system.l2c.UpgradeReq_miss_latency::total 10848997 # number of UpgradeReq miss cycles 284system.l2c.SCUpgradeReq_miss_latency::cpu0.data 863000 # number of SCUpgradeReq miss cycles 285system.l2c.SCUpgradeReq_miss_latency::cpu1.data 182500 # number of SCUpgradeReq miss cycles 286system.l2c.SCUpgradeReq_miss_latency::total 1045500 # number of SCUpgradeReq miss cycles 287system.l2c.ReadExReq_miss_latency::cpu0.data 5538652000 # number of ReadExReq miss cycles 288system.l2c.ReadExReq_miss_latency::cpu1.data 375096499 # number of ReadExReq miss cycles 289system.l2c.ReadExReq_miss_latency::total 5913748499 # number of ReadExReq miss cycles 290system.l2c.demand_miss_latency::cpu0.inst 816098500 # number of demand (read+write) miss cycles 291system.l2c.demand_miss_latency::cpu0.data 17250845000 # number of demand (read+write) miss cycles 292system.l2c.demand_miss_latency::cpu1.inst 36330000 # number of demand (read+write) miss cycles 293system.l2c.demand_miss_latency::cpu1.data 393892999 # number of demand (read+write) miss cycles 294system.l2c.demand_miss_latency::total 18497166499 # number of demand (read+write) miss cycles 295system.l2c.overall_miss_latency::cpu0.inst 816098500 # number of overall miss cycles 296system.l2c.overall_miss_latency::cpu0.data 17250845000 # number of overall miss cycles 297system.l2c.overall_miss_latency::cpu1.inst 36330000 # number of overall miss cycles 298system.l2c.overall_miss_latency::cpu1.data 393892999 # number of overall miss cycles 299system.l2c.overall_miss_latency::total 18497166499 # number of overall miss cycles 300system.l2c.ReadReq_accesses::cpu0.inst 700290 # number of ReadReq accesses(hits+misses) 301system.l2c.ReadReq_accesses::cpu0.data 937461 # number of ReadReq accesses(hits+misses) 302system.l2c.ReadReq_accesses::cpu1.inst 315438 # number of ReadReq accesses(hits+misses) 303system.l2c.ReadReq_accesses::cpu1.data 108570 # number of ReadReq accesses(hits+misses) 304system.l2c.ReadReq_accesses::total 2061759 # number of ReadReq accesses(hits+misses) 305system.l2c.Writeback_accesses::writebacks 794206 # number of Writeback accesses(hits+misses) 306system.l2c.Writeback_accesses::total 794206 # number of Writeback accesses(hits+misses) 307system.l2c.UpgradeReq_accesses::cpu0.data 3118 # number of UpgradeReq accesses(hits+misses) 308system.l2c.UpgradeReq_accesses::cpu1.data 2261 # number of UpgradeReq accesses(hits+misses) 309system.l2c.UpgradeReq_accesses::total 5379 # number of UpgradeReq accesses(hits+misses) 310system.l2c.SCUpgradeReq_accesses::cpu0.data 917 # number of SCUpgradeReq accesses(hits+misses) 311system.l2c.SCUpgradeReq_accesses::cpu1.data 916 # number of SCUpgradeReq accesses(hits+misses) 312system.l2c.SCUpgradeReq_accesses::total 1833 # number of SCUpgradeReq accesses(hits+misses) 313system.l2c.ReadExReq_accesses::cpu0.data 242360 # number of ReadExReq accesses(hits+misses) 314system.l2c.ReadExReq_accesses::cpu1.data 53632 # number of ReadExReq accesses(hits+misses) 315system.l2c.ReadExReq_accesses::total 295992 # number of ReadExReq accesses(hits+misses) 316system.l2c.demand_accesses::cpu0.inst 700290 # number of demand (read+write) accesses 317system.l2c.demand_accesses::cpu0.data 1179821 # number of demand (read+write) accesses 318system.l2c.demand_accesses::cpu1.inst 315438 # number of demand (read+write) accesses 319system.l2c.demand_accesses::cpu1.data 162202 # number of demand (read+write) accesses 320system.l2c.demand_accesses::total 2357751 # number of demand (read+write) accesses 321system.l2c.overall_accesses::cpu0.inst 700290 # number of overall (read+write) accesses 322system.l2c.overall_accesses::cpu0.data 1179821 # number of overall (read+write) accesses 323system.l2c.overall_accesses::cpu1.inst 315438 # number of overall (read+write) accesses 324system.l2c.overall_accesses::cpu1.data 162202 # number of overall (read+write) accesses 325system.l2c.overall_accesses::total 2357751 # number of overall (read+write) accesses 326system.l2c.ReadReq_miss_rate::cpu0.inst 0.018524 # miss rate for ReadReq accesses 327system.l2c.ReadReq_miss_rate::cpu0.data 0.289728 # miss rate for ReadReq accesses 328system.l2c.ReadReq_miss_rate::cpu1.inst 0.001778 # miss rate for ReadReq accesses 329system.l2c.ReadReq_miss_rate::cpu1.data 0.002211 # miss rate for ReadReq accesses 330system.l2c.ReadReq_miss_rate::total 0.138417 # miss rate for ReadReq accesses 331system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944836 # miss rate for UpgradeReq accesses 332system.l2c.UpgradeReq_miss_rate::cpu1.data 0.765590 # miss rate for UpgradeReq accesses 333system.l2c.UpgradeReq_miss_rate::total 0.869492 # miss rate for UpgradeReq accesses 334system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.956379 # miss rate for SCUpgradeReq accesses 335system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975983 # miss rate for SCUpgradeReq accesses 336system.l2c.SCUpgradeReq_miss_rate::total 0.966176 # miss rate for SCUpgradeReq accesses 337system.l2c.ReadExReq_miss_rate::cpu0.data 0.476448 # miss rate for ReadExReq accesses 338system.l2c.ReadExReq_miss_rate::cpu1.data 0.123527 # miss rate for ReadExReq accesses 339system.l2c.ReadExReq_miss_rate::total 0.412501 # miss rate for ReadExReq accesses 340system.l2c.demand_miss_rate::cpu0.inst 0.018524 # miss rate for demand accesses 341system.l2c.demand_miss_rate::cpu0.data 0.328085 # miss rate for demand accesses 342system.l2c.demand_miss_rate::cpu1.inst 0.001778 # miss rate for demand accesses 343system.l2c.demand_miss_rate::cpu1.data 0.042324 # miss rate for demand accesses 344system.l2c.demand_miss_rate::total 0.172825 # miss rate for demand accesses 345system.l2c.overall_miss_rate::cpu0.inst 0.018524 # miss rate for overall accesses 346system.l2c.overall_miss_rate::cpu0.data 0.328085 # miss rate for overall accesses 347system.l2c.overall_miss_rate::cpu1.inst 0.001778 # miss rate for overall accesses 348system.l2c.overall_miss_rate::cpu1.data 0.042324 # miss rate for overall accesses 349system.l2c.overall_miss_rate::total 0.172825 # miss rate for overall accesses 350system.l2c.ReadReq_avg_miss_latency::cpu0.inst 62912.311132 # average ReadReq miss latency 351system.l2c.ReadReq_avg_miss_latency::cpu0.data 43121.520274 # average ReadReq miss latency 352system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64759.358289 # average ReadReq miss latency 353system.l2c.ReadReq_avg_miss_latency::cpu1.data 78318.750000 # average ReadReq miss latency 354system.l2c.ReadReq_avg_miss_latency::total 44093.243442 # average ReadReq miss latency 355system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 406.313646 # average UpgradeReq miss latency 356system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5575.965916 # average UpgradeReq miss latency 357system.l2c.UpgradeReq_avg_miss_latency::total 2319.648706 # average UpgradeReq miss latency 358system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 984.036488 # average SCUpgradeReq miss latency 359system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 204.138702 # average SCUpgradeReq miss latency 360system.l2c.SCUpgradeReq_avg_miss_latency::total 590.344438 # average SCUpgradeReq miss latency 361system.l2c.ReadExReq_avg_miss_latency::cpu0.data 47965.324927 # average ReadExReq miss latency 362system.l2c.ReadExReq_avg_miss_latency::cpu1.data 56618.339472 # average ReadExReq miss latency 363system.l2c.ReadExReq_avg_miss_latency::total 48434.838686 # average ReadExReq miss latency 364system.l2c.demand_avg_miss_latency::cpu0.inst 62912.311132 # average overall miss latency 365system.l2c.demand_avg_miss_latency::cpu0.data 44566.499002 # average overall miss latency 366system.l2c.demand_avg_miss_latency::cpu1.inst 64759.358289 # average overall miss latency 367system.l2c.demand_avg_miss_latency::cpu1.data 57376.984559 # average overall miss latency 368system.l2c.demand_avg_miss_latency::total 45394.158960 # average overall miss latency 369system.l2c.overall_avg_miss_latency::cpu0.inst 62912.311132 # average overall miss latency 370system.l2c.overall_avg_miss_latency::cpu0.data 44566.499002 # average overall miss latency 371system.l2c.overall_avg_miss_latency::cpu1.inst 64759.358289 # average overall miss latency 372system.l2c.overall_avg_miss_latency::cpu1.data 57376.984559 # average overall miss latency 373system.l2c.overall_avg_miss_latency::total 45394.158960 # average overall miss latency |
| 374system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 375system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 376system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 377system.l2c.blocked::no_targets 0 # number of cycles access was blocked 378system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 379system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 380system.l2c.fast_writes 0 # number of fast writes performed 381system.l2c.cache_copies 0 # number of cache copies performed | 374system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 375system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 376system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 377system.l2c.blocked::no_targets 0 # number of cycles access was blocked 378system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 379system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 380system.l2c.fast_writes 0 # number of fast writes performed 381system.l2c.cache_copies 0 # number of cache copies performed |
| 382system.l2c.writebacks::writebacks 78894 # number of writebacks 383system.l2c.writebacks::total 78894 # number of writebacks | 382system.l2c.writebacks::writebacks 78774 # number of writebacks 383system.l2c.writebacks::total 78774 # number of writebacks |
| 384system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits 385system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 386system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 387system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 388system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 389system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits | 384system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits 385system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 386system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 387system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 388system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 389system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits |
| 390system.l2c.ReadReq_mshr_misses::cpu0.inst 12926 # number of ReadReq MSHR misses 391system.l2c.ReadReq_mshr_misses::cpu0.data 271631 # number of ReadReq MSHR misses 392system.l2c.ReadReq_mshr_misses::cpu1.inst 601 # number of ReadReq MSHR misses 393system.l2c.ReadReq_mshr_misses::cpu1.data 247 # number of ReadReq MSHR misses 394system.l2c.ReadReq_mshr_misses::total 285405 # number of ReadReq MSHR misses 395system.l2c.UpgradeReq_mshr_misses::cpu0.data 2969 # number of UpgradeReq MSHR misses 396system.l2c.UpgradeReq_mshr_misses::cpu1.data 1806 # number of UpgradeReq MSHR misses 397system.l2c.UpgradeReq_mshr_misses::total 4775 # number of UpgradeReq MSHR misses 398system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 939 # number of SCUpgradeReq MSHR misses 399system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 944 # number of SCUpgradeReq MSHR misses 400system.l2c.SCUpgradeReq_mshr_misses::total 1883 # number of SCUpgradeReq MSHR misses 401system.l2c.ReadExReq_mshr_misses::cpu0.data 115505 # number of ReadExReq MSHR misses 402system.l2c.ReadExReq_mshr_misses::cpu1.data 6644 # number of ReadExReq MSHR misses 403system.l2c.ReadExReq_mshr_misses::total 122149 # number of ReadExReq MSHR misses 404system.l2c.demand_mshr_misses::cpu0.inst 12926 # number of demand (read+write) MSHR misses 405system.l2c.demand_mshr_misses::cpu0.data 387136 # number of demand (read+write) MSHR misses 406system.l2c.demand_mshr_misses::cpu1.inst 601 # number of demand (read+write) MSHR misses 407system.l2c.demand_mshr_misses::cpu1.data 6891 # number of demand (read+write) MSHR misses 408system.l2c.demand_mshr_misses::total 407554 # number of demand (read+write) MSHR misses 409system.l2c.overall_mshr_misses::cpu0.inst 12926 # number of overall MSHR misses 410system.l2c.overall_mshr_misses::cpu0.data 387136 # number of overall MSHR misses 411system.l2c.overall_mshr_misses::cpu1.inst 601 # number of overall MSHR misses 412system.l2c.overall_mshr_misses::cpu1.data 6891 # number of overall MSHR misses 413system.l2c.overall_mshr_misses::total 407554 # number of overall MSHR misses 414system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 543164896 # number of ReadReq MSHR miss cycles 415system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7977851486 # number of ReadReq MSHR miss cycles 416system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 25213167 # number of ReadReq MSHR miss cycles 417system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12672975 # number of ReadReq MSHR miss cycles 418system.l2c.ReadReq_mshr_miss_latency::total 8558902524 # number of ReadReq MSHR miss cycles 419system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29845964 # number of UpgradeReq MSHR miss cycles 420system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18081803 # number of UpgradeReq MSHR miss cycles 421system.l2c.UpgradeReq_mshr_miss_latency::total 47927767 # number of UpgradeReq MSHR miss cycles 422system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9405923 # number of SCUpgradeReq MSHR miss cycles 423system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9440944 # number of SCUpgradeReq MSHR miss cycles 424system.l2c.SCUpgradeReq_mshr_miss_latency::total 18846867 # number of SCUpgradeReq MSHR miss cycles 425system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4207932893 # number of ReadExReq MSHR miss cycles 426system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 343549452 # number of ReadExReq MSHR miss cycles 427system.l2c.ReadExReq_mshr_miss_latency::total 4551482345 # number of ReadExReq MSHR miss cycles 428system.l2c.demand_mshr_miss_latency::cpu0.inst 543164896 # number of demand (read+write) MSHR miss cycles 429system.l2c.demand_mshr_miss_latency::cpu0.data 12185784379 # number of demand (read+write) MSHR miss cycles 430system.l2c.demand_mshr_miss_latency::cpu1.inst 25213167 # number of demand (read+write) MSHR miss cycles 431system.l2c.demand_mshr_miss_latency::cpu1.data 356222427 # number of demand (read+write) MSHR miss cycles 432system.l2c.demand_mshr_miss_latency::total 13110384869 # number of demand (read+write) MSHR miss cycles 433system.l2c.overall_mshr_miss_latency::cpu0.inst 543164896 # number of overall MSHR miss cycles 434system.l2c.overall_mshr_miss_latency::cpu0.data 12185784379 # number of overall MSHR miss cycles 435system.l2c.overall_mshr_miss_latency::cpu1.inst 25213167 # number of overall MSHR miss cycles 436system.l2c.overall_mshr_miss_latency::cpu1.data 356222427 # number of overall MSHR miss cycles 437system.l2c.overall_mshr_miss_latency::total 13110384869 # number of overall MSHR miss cycles 438system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373080000 # number of ReadReq MSHR uncacheable cycles 439system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18172000 # number of ReadReq MSHR uncacheable cycles 440system.l2c.ReadReq_mshr_uncacheable_latency::total 1391252000 # number of ReadReq MSHR uncacheable cycles 441system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2155311500 # number of WriteReq MSHR uncacheable cycles 442system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 683999000 # number of WriteReq MSHR uncacheable cycles 443system.l2c.WriteReq_mshr_uncacheable_latency::total 2839310500 # number of WriteReq MSHR uncacheable cycles 444system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3528391500 # number of overall MSHR uncacheable cycles 445system.l2c.overall_mshr_uncacheable_latency::cpu1.data 702171000 # number of overall MSHR uncacheable cycles 446system.l2c.overall_mshr_uncacheable_latency::total 4230562500 # number of overall MSHR uncacheable cycles 447system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for ReadReq accesses 448system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.292124 # mshr miss rate for ReadReq accesses 449system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for ReadReq accesses 450system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002171 # mshr miss rate for ReadReq accesses 451system.l2c.ReadReq_mshr_miss_rate::total 0.138549 # mshr miss rate for ReadReq accesses 452system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944639 # mshr miss rate for UpgradeReq accesses 453system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.762025 # mshr miss rate for UpgradeReq accesses 454system.l2c.UpgradeReq_mshr_miss_rate::total 0.866135 # mshr miss rate for UpgradeReq accesses 455system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.963077 # mshr miss rate for SCUpgradeReq accesses 456system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975207 # mshr miss rate for SCUpgradeReq accesses 457system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969120 # mshr miss rate for SCUpgradeReq accesses 458system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482493 # mshr miss rate for ReadExReq accesses 459system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119462 # mshr miss rate for ReadExReq accesses 460system.l2c.ReadExReq_mshr_miss_rate::total 0.414053 # mshr miss rate for ReadExReq accesses 461system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for demand accesses 462system.l2c.demand_mshr_miss_rate::cpu0.data 0.331101 # mshr miss rate for demand accesses 463system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for demand accesses 464system.l2c.demand_mshr_miss_rate::cpu1.data 0.040679 # mshr miss rate for demand accesses 465system.l2c.demand_mshr_miss_rate::total 0.173062 # mshr miss rate for demand accesses 466system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for overall accesses 467system.l2c.overall_mshr_miss_rate::cpu0.data 0.331101 # mshr miss rate for overall accesses 468system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for overall accesses 469system.l2c.overall_mshr_miss_rate::cpu1.data 0.040679 # mshr miss rate for overall accesses 470system.l2c.overall_mshr_miss_rate::total 0.173062 # mshr miss rate for overall accesses 471system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average ReadReq mshr miss latency 472system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29370.180451 # average ReadReq mshr miss latency 473system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average ReadReq mshr miss latency 474system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 51307.591093 # average ReadReq mshr miss latency 475system.l2c.ReadReq_avg_mshr_miss_latency::total 29988.621517 # average ReadReq mshr miss latency 476system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10052.530818 # average UpgradeReq mshr miss latency 477system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.072536 # average UpgradeReq mshr miss latency 478system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.228691 # average UpgradeReq mshr miss latency 479system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.957401 # average SCUpgradeReq mshr miss latency | 390system.l2c.ReadReq_mshr_misses::cpu0.inst 12972 # number of ReadReq MSHR misses 391system.l2c.ReadReq_mshr_misses::cpu0.data 271609 # number of ReadReq MSHR misses 392system.l2c.ReadReq_mshr_misses::cpu1.inst 550 # number of ReadReq MSHR misses 393system.l2c.ReadReq_mshr_misses::cpu1.data 240 # number of ReadReq MSHR misses 394system.l2c.ReadReq_mshr_misses::total 285371 # number of ReadReq MSHR misses 395system.l2c.UpgradeReq_mshr_misses::cpu0.data 2946 # number of UpgradeReq MSHR misses 396system.l2c.UpgradeReq_mshr_misses::cpu1.data 1731 # number of UpgradeReq MSHR misses 397system.l2c.UpgradeReq_mshr_misses::total 4677 # number of UpgradeReq MSHR misses 398system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 877 # number of SCUpgradeReq MSHR misses 399system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 894 # number of SCUpgradeReq MSHR misses 400system.l2c.SCUpgradeReq_mshr_misses::total 1771 # number of SCUpgradeReq MSHR misses 401system.l2c.ReadExReq_mshr_misses::cpu0.data 115472 # number of ReadExReq MSHR misses 402system.l2c.ReadExReq_mshr_misses::cpu1.data 6625 # number of ReadExReq MSHR misses 403system.l2c.ReadExReq_mshr_misses::total 122097 # number of ReadExReq MSHR misses 404system.l2c.demand_mshr_misses::cpu0.inst 12972 # number of demand (read+write) MSHR misses 405system.l2c.demand_mshr_misses::cpu0.data 387081 # number of demand (read+write) MSHR misses 406system.l2c.demand_mshr_misses::cpu1.inst 550 # number of demand (read+write) MSHR misses 407system.l2c.demand_mshr_misses::cpu1.data 6865 # number of demand (read+write) MSHR misses 408system.l2c.demand_mshr_misses::total 407468 # number of demand (read+write) MSHR misses 409system.l2c.overall_mshr_misses::cpu0.inst 12972 # number of overall MSHR misses 410system.l2c.overall_mshr_misses::cpu0.data 387081 # number of overall MSHR misses 411system.l2c.overall_mshr_misses::cpu1.inst 550 # number of overall MSHR misses 412system.l2c.overall_mshr_misses::cpu1.data 6865 # number of overall MSHR misses 413system.l2c.overall_mshr_misses::total 407468 # number of overall MSHR misses 414system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 652870719 # number of ReadReq MSHR miss cycles 415system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8377504856 # number of ReadReq MSHR miss cycles 416system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 28860821 # number of ReadReq MSHR miss cycles 417system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15792455 # number of ReadReq MSHR miss cycles 418system.l2c.ReadReq_mshr_miss_latency::total 9075028851 # number of ReadReq MSHR miss cycles 419system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29675441 # number of UpgradeReq MSHR miss cycles 420system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17410227 # number of UpgradeReq MSHR miss cycles 421system.l2c.UpgradeReq_mshr_miss_latency::total 47085668 # number of UpgradeReq MSHR miss cycles 422system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8897310 # number of SCUpgradeReq MSHR miss cycles 423system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 8940894 # number of SCUpgradeReq MSHR miss cycles 424system.l2c.SCUpgradeReq_mshr_miss_latency::total 17838204 # number of SCUpgradeReq MSHR miss cycles 425system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4112913546 # number of ReadExReq MSHR miss cycles 426system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 291507382 # number of ReadExReq MSHR miss cycles 427system.l2c.ReadExReq_mshr_miss_latency::total 4404420928 # number of ReadExReq MSHR miss cycles 428system.l2c.demand_mshr_miss_latency::cpu0.inst 652870719 # number of demand (read+write) MSHR miss cycles 429system.l2c.demand_mshr_miss_latency::cpu0.data 12490418402 # number of demand (read+write) MSHR miss cycles 430system.l2c.demand_mshr_miss_latency::cpu1.inst 28860821 # number of demand (read+write) MSHR miss cycles 431system.l2c.demand_mshr_miss_latency::cpu1.data 307299837 # number of demand (read+write) MSHR miss cycles 432system.l2c.demand_mshr_miss_latency::total 13479449779 # number of demand (read+write) MSHR miss cycles 433system.l2c.overall_mshr_miss_latency::cpu0.inst 652870719 # number of overall MSHR miss cycles 434system.l2c.overall_mshr_miss_latency::cpu0.data 12490418402 # number of overall MSHR miss cycles 435system.l2c.overall_mshr_miss_latency::cpu1.inst 28860821 # number of overall MSHR miss cycles 436system.l2c.overall_mshr_miss_latency::cpu1.data 307299837 # number of overall MSHR miss cycles 437system.l2c.overall_mshr_miss_latency::total 13479449779 # number of overall MSHR miss cycles 438system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1372964000 # number of ReadReq MSHR uncacheable cycles 439system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18171500 # number of ReadReq MSHR uncacheable cycles 440system.l2c.ReadReq_mshr_uncacheable_latency::total 1391135500 # number of ReadReq MSHR uncacheable cycles 441system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2145152500 # number of WriteReq MSHR uncacheable cycles 442system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 673668500 # number of WriteReq MSHR uncacheable cycles 443system.l2c.WriteReq_mshr_uncacheable_latency::total 2818821000 # number of WriteReq MSHR uncacheable cycles 444system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3518116500 # number of overall MSHR uncacheable cycles 445system.l2c.overall_mshr_uncacheable_latency::cpu1.data 691840000 # number of overall MSHR uncacheable cycles 446system.l2c.overall_mshr_uncacheable_latency::total 4209956500 # number of overall MSHR uncacheable cycles 447system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for ReadReq accesses 448system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.289728 # mshr miss rate for ReadReq accesses 449system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for ReadReq accesses 450system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002211 # mshr miss rate for ReadReq accesses 451system.l2c.ReadReq_mshr_miss_rate::total 0.138411 # mshr miss rate for ReadReq accesses 452system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944836 # mshr miss rate for UpgradeReq accesses 453system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.765590 # mshr miss rate for UpgradeReq accesses 454system.l2c.UpgradeReq_mshr_miss_rate::total 0.869492 # mshr miss rate for UpgradeReq accesses 455system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.956379 # mshr miss rate for SCUpgradeReq accesses 456system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975983 # mshr miss rate for SCUpgradeReq accesses 457system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.966176 # mshr miss rate for SCUpgradeReq accesses 458system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476448 # mshr miss rate for ReadExReq accesses 459system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.123527 # mshr miss rate for ReadExReq accesses 460system.l2c.ReadExReq_mshr_miss_rate::total 0.412501 # mshr miss rate for ReadExReq accesses 461system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for demand accesses 462system.l2c.demand_mshr_miss_rate::cpu0.data 0.328085 # mshr miss rate for demand accesses 463system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for demand accesses 464system.l2c.demand_mshr_miss_rate::cpu1.data 0.042324 # mshr miss rate for demand accesses 465system.l2c.demand_mshr_miss_rate::total 0.172821 # mshr miss rate for demand accesses 466system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for overall accesses 467system.l2c.overall_mshr_miss_rate::cpu0.data 0.328085 # mshr miss rate for overall accesses 468system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for overall accesses 469system.l2c.overall_mshr_miss_rate::cpu1.data 0.042324 # mshr miss rate for overall accesses 470system.l2c.overall_mshr_miss_rate::total 0.172821 # mshr miss rate for overall accesses 471system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average ReadReq mshr miss latency 472system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30843.988439 # average ReadReq mshr miss latency 473system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average ReadReq mshr miss latency 474system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65801.895833 # average ReadReq mshr miss latency 475system.l2c.ReadReq_avg_mshr_miss_latency::total 31800.809651 # average ReadReq mshr miss latency 476system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.130007 # average UpgradeReq mshr miss latency 477system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.901213 # average UpgradeReq mshr miss latency 478system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10067.493693 # average UpgradeReq mshr miss latency 479system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10145.165336 # average SCUpgradeReq mshr miss latency |
| 480system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency | 480system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency |
| 481system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.957515 # average SCUpgradeReq mshr miss latency 482system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36430.742332 # average ReadExReq mshr miss latency 483system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51708.225768 # average ReadExReq mshr miss latency 484system.l2c.ReadExReq_avg_mshr_miss_latency::total 37261.724165 # average ReadExReq mshr miss latency 485system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency 486system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency 487system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency 488system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency 489system.l2c.demand_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency 490system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency 491system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency 492system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency 493system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency 494system.l2c.overall_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency | 481system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10072.390740 # average SCUpgradeReq mshr miss latency 482system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35618.275824 # average ReadExReq mshr miss latency 483system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44001.114264 # average ReadExReq mshr miss latency 484system.l2c.ReadExReq_avg_mshr_miss_latency::total 36073.129790 # average ReadExReq mshr miss latency 485system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency 486system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency 487system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency 488system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency 489system.l2c.demand_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency 490system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency 491system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency 492system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency 493system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency 494system.l2c.overall_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency |
| 495system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 496system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 497system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 498system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 499system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 500system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 501system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 502system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 503system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 504system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 505system.iocache.replacements 41696 # number of replacements | 495system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 496system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 497system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 498system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 499system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 500system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 501system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 502system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 503system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 504system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 505system.iocache.replacements 41696 # number of replacements |
| 506system.iocache.tagsinuse 0.562950 # Cycle average of tags in use | 506system.iocache.tagsinuse 0.569993 # Cycle average of tags in use |
| 507system.iocache.total_refs 0 # Total number of references to valid blocks. 508system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. 509system.iocache.avg_refs 0 # Average number of references to valid blocks. | 507system.iocache.total_refs 0 # Total number of references to valid blocks. 508system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. 509system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 510system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. 511system.iocache.occ_blocks::tsunami.ide 0.562950 # Average occupied blocks per requestor 512system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy 513system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy | 510system.iocache.warmup_cycle 1746698431000 # Cycle when the warmup percentage was hit. 511system.iocache.occ_blocks::tsunami.ide 0.569993 # Average occupied blocks per requestor 512system.iocache.occ_percent::tsunami.ide 0.035625 # Average percentage of cache occupancy 513system.iocache.occ_percent::total 0.035625 # Average percentage of cache occupancy |
| 514system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 515system.iocache.ReadReq_misses::total 176 # number of ReadReq misses 516system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 517system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 518system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 519system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 520system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 521system.iocache.overall_misses::total 41728 # number of overall misses 522system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles 523system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles | 514system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 515system.iocache.ReadReq_misses::total 176 # number of ReadReq misses 516system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 517system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 518system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 519system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 520system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 521system.iocache.overall_misses::total 41728 # number of overall misses 522system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles 523system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles |
| 524system.iocache.WriteReq_miss_latency::tsunami.ide 9497531806 # number of WriteReq miss cycles 525system.iocache.WriteReq_miss_latency::total 9497531806 # number of WriteReq miss cycles 526system.iocache.demand_miss_latency::tsunami.ide 9518800804 # number of demand (read+write) miss cycles 527system.iocache.demand_miss_latency::total 9518800804 # number of demand (read+write) miss cycles 528system.iocache.overall_miss_latency::tsunami.ide 9518800804 # number of overall miss cycles 529system.iocache.overall_miss_latency::total 9518800804 # number of overall miss cycles | 524system.iocache.WriteReq_miss_latency::tsunami.ide 10634917806 # number of WriteReq miss cycles 525system.iocache.WriteReq_miss_latency::total 10634917806 # number of WriteReq miss cycles 526system.iocache.demand_miss_latency::tsunami.ide 10656186804 # number of demand (read+write) miss cycles 527system.iocache.demand_miss_latency::total 10656186804 # number of demand (read+write) miss cycles 528system.iocache.overall_miss_latency::tsunami.ide 10656186804 # number of overall miss cycles 529system.iocache.overall_miss_latency::total 10656186804 # number of overall miss cycles |
| 530system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 531system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) 532system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 533system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 534system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 535system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 536system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 537system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses 538system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 539system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 540system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 541system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 542system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 543system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 544system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 545system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 546system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency 547system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency | 530system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 531system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) 532system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 533system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 534system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 535system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 536system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 537system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses 538system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 539system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 540system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 541system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 542system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 543system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 544system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 545system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 546system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency 547system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency |
| 548system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228569.787399 # average WriteReq miss latency 549system.iocache.WriteReq_avg_miss_latency::total 228569.787399 # average WriteReq miss latency 550system.iocache.demand_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency 551system.iocache.demand_avg_miss_latency::total 228115.433378 # average overall miss latency 552system.iocache.overall_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency 553system.iocache.overall_avg_miss_latency::total 228115.433378 # average overall miss latency 554system.iocache.blocked_cycles::no_mshrs 188605 # number of cycles access was blocked | 548system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255942.380776 # average WriteReq miss latency 549system.iocache.WriteReq_avg_miss_latency::total 255942.380776 # average WriteReq miss latency 550system.iocache.demand_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency 551system.iocache.demand_avg_miss_latency::total 255372.574866 # average overall miss latency 552system.iocache.overall_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency 553system.iocache.overall_avg_miss_latency::total 255372.574866 # average overall miss latency 554system.iocache.blocked_cycles::no_mshrs 284837 # number of cycles access was blocked |
| 555system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 555system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 556system.iocache.blocked::no_mshrs 22594 # number of cycles access was blocked | 556system.iocache.blocked::no_mshrs 27190 # number of cycles access was blocked |
| 557system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 557system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 558system.iocache.avg_blocked_cycles::no_mshrs 8.347570 # average number of cycles each access was blocked | 558system.iocache.avg_blocked_cycles::no_mshrs 10.475800 # average number of cycles each access was blocked |
| 559system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 560system.iocache.fast_writes 0 # number of fast writes performed 561system.iocache.cache_copies 0 # number of cache copies performed 562system.iocache.writebacks::writebacks 41520 # number of writebacks 563system.iocache.writebacks::total 41520 # number of writebacks 564system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 565system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses 566system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 567system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 568system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 569system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 570system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 571system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses | 559system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 560system.iocache.fast_writes 0 # number of fast writes performed 561system.iocache.cache_copies 0 # number of cache copies performed 562system.iocache.writebacks::writebacks 41520 # number of writebacks 563system.iocache.writebacks::total 41520 # number of writebacks 564system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 565system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses 566system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 567system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 568system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 569system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 570system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 571system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses |
| 572system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles 573system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles 574system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7334778982 # number of WriteReq MSHR miss cycles 575system.iocache.WriteReq_mshr_miss_latency::total 7334778982 # number of WriteReq MSHR miss cycles 576system.iocache.demand_mshr_miss_latency::tsunami.ide 7346894982 # number of demand (read+write) MSHR miss cycles 577system.iocache.demand_mshr_miss_latency::total 7346894982 # number of demand (read+write) MSHR miss cycles 578system.iocache.overall_mshr_miss_latency::tsunami.ide 7346894982 # number of overall MSHR miss cycles 579system.iocache.overall_mshr_miss_latency::total 7346894982 # number of overall MSHR miss cycles | 572system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116250 # number of ReadReq MSHR miss cycles 573system.iocache.ReadReq_mshr_miss_latency::total 12116250 # number of ReadReq MSHR miss cycles 574system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472911060 # number of WriteReq MSHR miss cycles 575system.iocache.WriteReq_mshr_miss_latency::total 8472911060 # number of WriteReq MSHR miss cycles 576system.iocache.demand_mshr_miss_latency::tsunami.ide 8485027310 # number of demand (read+write) MSHR miss cycles 577system.iocache.demand_mshr_miss_latency::total 8485027310 # number of demand (read+write) MSHR miss cycles 578system.iocache.overall_mshr_miss_latency::tsunami.ide 8485027310 # number of overall MSHR miss cycles 579system.iocache.overall_mshr_miss_latency::total 8485027310 # number of overall MSHR miss cycles |
| 580system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 581system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 582system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 583system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 584system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 585system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 586system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 587system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 580system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 581system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 582system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 583system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 584system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 585system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 586system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 587system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 588system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency 589system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency 590system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176520.479929 # average WriteReq mshr miss latency 591system.iocache.WriteReq_avg_mshr_miss_latency::total 176520.479929 # average WriteReq mshr miss latency 592system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency 593system.iocache.demand_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency 594system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency 595system.iocache.overall_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency | 588system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68842.329545 # average ReadReq mshr miss latency 589system.iocache.ReadReq_avg_mshr_miss_latency::total 68842.329545 # average ReadReq mshr miss latency 590system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203911.028591 # average WriteReq mshr miss latency 591system.iocache.WriteReq_avg_mshr_miss_latency::total 203911.028591 # average WriteReq mshr miss latency 592system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency 593system.iocache.demand_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency 594system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency 595system.iocache.overall_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency |
| 596system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 597system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 598system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 599system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 600system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 601system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 602system.disk0.dma_write_txs 395 # Number of DMA write transactions. 603system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 604system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 605system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 606system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 607system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 608system.disk2.dma_write_txs 1 # Number of DMA write transactions. 609system.cpu0.dtb.fetch_hits 0 # ITB hits 610system.cpu0.dtb.fetch_misses 0 # ITB misses 611system.cpu0.dtb.fetch_acv 0 # ITB acv 612system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 596system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 597system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 598system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 599system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 600system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 601system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 602system.disk0.dma_write_txs 395 # Number of DMA write transactions. 603system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 604system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 605system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 606system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 607system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 608system.disk2.dma_write_txs 1 # Number of DMA write transactions. 609system.cpu0.dtb.fetch_hits 0 # ITB hits 610system.cpu0.dtb.fetch_misses 0 # ITB misses 611system.cpu0.dtb.fetch_acv 0 # ITB acv 612system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 613system.cpu0.dtb.read_hits 7424685 # DTB read hits | 613system.cpu0.dtb.read_hits 7490982 # DTB read hits |
| 614system.cpu0.dtb.read_misses 7443 # DTB read misses 615system.cpu0.dtb.read_acv 210 # DTB read access violations 616system.cpu0.dtb.read_accesses 490673 # DTB read accesses | 614system.cpu0.dtb.read_misses 7443 # DTB read misses 615system.cpu0.dtb.read_acv 210 # DTB read access violations 616system.cpu0.dtb.read_accesses 490673 # DTB read accesses |
| 617system.cpu0.dtb.write_hits 5011105 # DTB write hits | 617system.cpu0.dtb.write_hits 5068153 # DTB write hits |
| 618system.cpu0.dtb.write_misses 813 # DTB write misses 619system.cpu0.dtb.write_acv 134 # DTB write access violations 620system.cpu0.dtb.write_accesses 187452 # DTB write accesses | 618system.cpu0.dtb.write_misses 813 # DTB write misses 619system.cpu0.dtb.write_acv 134 # DTB write access violations 620system.cpu0.dtb.write_accesses 187452 # DTB write accesses |
| 621system.cpu0.dtb.data_hits 12435790 # DTB hits | 621system.cpu0.dtb.data_hits 12559135 # DTB hits |
| 622system.cpu0.dtb.data_misses 8256 # DTB misses 623system.cpu0.dtb.data_acv 344 # DTB access violations 624system.cpu0.dtb.data_accesses 678125 # DTB accesses | 622system.cpu0.dtb.data_misses 8256 # DTB misses 623system.cpu0.dtb.data_acv 344 # DTB access violations 624system.cpu0.dtb.data_accesses 678125 # DTB accesses |
| 625system.cpu0.itb.fetch_hits 3481701 # ITB hits | 625system.cpu0.itb.fetch_hits 3503456 # ITB hits |
| 626system.cpu0.itb.fetch_misses 3871 # ITB misses 627system.cpu0.itb.fetch_acv 184 # ITB acv | 626system.cpu0.itb.fetch_misses 3871 # ITB misses 627system.cpu0.itb.fetch_acv 184 # ITB acv |
| 628system.cpu0.itb.fetch_accesses 3485572 # ITB accesses | 628system.cpu0.itb.fetch_accesses 3507327 # ITB accesses |
| 629system.cpu0.itb.read_hits 0 # DTB read hits 630system.cpu0.itb.read_misses 0 # DTB read misses 631system.cpu0.itb.read_acv 0 # DTB read access violations 632system.cpu0.itb.read_accesses 0 # DTB read accesses 633system.cpu0.itb.write_hits 0 # DTB write hits 634system.cpu0.itb.write_misses 0 # DTB write misses 635system.cpu0.itb.write_acv 0 # DTB write access violations 636system.cpu0.itb.write_accesses 0 # DTB write accesses 637system.cpu0.itb.data_hits 0 # DTB hits 638system.cpu0.itb.data_misses 0 # DTB misses 639system.cpu0.itb.data_acv 0 # DTB access violations 640system.cpu0.itb.data_accesses 0 # DTB accesses | 629system.cpu0.itb.read_hits 0 # DTB read hits 630system.cpu0.itb.read_misses 0 # DTB read misses 631system.cpu0.itb.read_acv 0 # DTB read access violations 632system.cpu0.itb.read_accesses 0 # DTB read accesses 633system.cpu0.itb.write_hits 0 # DTB write hits 634system.cpu0.itb.write_misses 0 # DTB write misses 635system.cpu0.itb.write_acv 0 # DTB write access violations 636system.cpu0.itb.write_accesses 0 # DTB write accesses 637system.cpu0.itb.data_hits 0 # DTB hits 638system.cpu0.itb.data_misses 0 # DTB misses 639system.cpu0.itb.data_acv 0 # DTB access violations 640system.cpu0.itb.data_accesses 0 # DTB accesses |
| 641system.cpu0.numCycles 3900399041 # number of cpu cycles simulated | 641system.cpu0.numCycles 3904305293 # number of cpu cycles simulated |
| 642system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 643system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 642system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 643system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 644system.cpu0.committedInsts 47350784 # Number of instructions committed 645system.cpu0.committedOps 47350784 # Number of ops (including micro ops) committed 646system.cpu0.num_int_alu_accesses 43919786 # Number of integer alu accesses 647system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses 648system.cpu0.num_func_calls 1188579 # number of times a function call or return occured 649system.cpu0.num_conditional_control_insts 5567614 # number of instructions that are conditional controls 650system.cpu0.num_int_insts 43919786 # number of integer instructions 651system.cpu0.num_fp_insts 206365 # number of float instructions 652system.cpu0.num_int_register_reads 60378491 # number of times the integer registers were read 653system.cpu0.num_int_register_writes 32741801 # number of times the integer registers were written 654system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read 655system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written 656system.cpu0.num_mem_refs 12475691 # number of memory refs 657system.cpu0.num_load_insts 7451626 # Number of load instructions 658system.cpu0.num_store_insts 5024065 # Number of store instructions 659system.cpu0.num_idle_cycles 3698902228.116945 # Number of idle cycles 660system.cpu0.num_busy_cycles 201496812.883055 # Number of busy cycles 661system.cpu0.not_idle_fraction 0.051661 # Percentage of non-idle cycles 662system.cpu0.idle_fraction 0.948339 # Percentage of idle cycles | 644system.cpu0.committedInsts 47706703 # Number of instructions committed 645system.cpu0.committedOps 47706703 # Number of ops (including micro ops) committed 646system.cpu0.num_int_alu_accesses 44241786 # Number of integer alu accesses 647system.cpu0.num_fp_alu_accesses 211423 # Number of float alu accesses 648system.cpu0.num_func_calls 1201591 # number of times a function call or return occured 649system.cpu0.num_conditional_control_insts 5601417 # number of instructions that are conditional controls 650system.cpu0.num_int_insts 44241786 # number of integer instructions 651system.cpu0.num_fp_insts 211423 # number of float instructions 652system.cpu0.num_int_register_reads 60797943 # number of times the integer registers were read 653system.cpu0.num_int_register_writes 32968604 # number of times the integer registers were written 654system.cpu0.num_fp_register_reads 102697 # number of times the floating registers were read 655system.cpu0.num_fp_register_writes 104564 # number of times the floating registers were written 656system.cpu0.num_mem_refs 12599388 # number of memory refs 657system.cpu0.num_load_insts 7518173 # Number of load instructions 658system.cpu0.num_store_insts 5081215 # Number of store instructions 659system.cpu0.num_idle_cycles 3700976170.173713 # Number of idle cycles 660system.cpu0.num_busy_cycles 203329122.826288 # Number of busy cycles 661system.cpu0.not_idle_fraction 0.052078 # Percentage of non-idle cycles 662system.cpu0.idle_fraction 0.947922 # Percentage of idle cycles |
| 663system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 663system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 664system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed 665system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed 666system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl 667system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl 668system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl 669system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl 670system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl 671system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl 672system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl 673system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl 674system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl 675system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl 676system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl 677system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl 678system.cpu0.kern.ipl_ticks::0 1898623862000 97.36% 97.36% # number of cycles we spent at this ipl 679system.cpu0.kern.ipl_ticks::21 92984000 0.00% 97.36% # number of cycles we spent at this ipl 680system.cpu0.kern.ipl_ticks::22 759861500 0.04% 97.40% # number of cycles we spent at this ipl 681system.cpu0.kern.ipl_ticks::30 328899000 0.02% 97.42% # number of cycles we spent at this ipl 682system.cpu0.kern.ipl_ticks::31 50393884000 2.58% 100.00% # number of cycles we spent at this ipl 683system.cpu0.kern.ipl_ticks::total 1950199490500 # number of cycles we spent at this ipl 684system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl | 664system.cpu0.kern.inst.quiesce 6787 # number of quiesce instructions executed 665system.cpu0.kern.inst.hwrei 165132 # number of hwrei instructions executed 666system.cpu0.kern.ipl_count::0 56916 40.19% 40.19% # number of times we switched to this ipl 667system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl 668system.cpu0.kern.ipl_count::22 1973 1.39% 41.67% # number of times we switched to this ipl 669system.cpu0.kern.ipl_count::30 418 0.30% 41.97% # number of times we switched to this ipl 670system.cpu0.kern.ipl_count::31 82194 58.03% 100.00% # number of times we switched to this ipl 671system.cpu0.kern.ipl_count::total 141632 # number of times we switched to this ipl 672system.cpu0.kern.ipl_good::0 56372 49.08% 49.08% # number of times we switched to this ipl from a different ipl 673system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl 674system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl 675system.cpu0.kern.ipl_good::30 418 0.36% 51.28% # number of times we switched to this ipl from a different ipl 676system.cpu0.kern.ipl_good::31 55954 48.72% 100.00% # number of times we switched to this ipl from a different ipl 677system.cpu0.kern.ipl_good::total 114848 # number of times we switched to this ipl from a different ipl 678system.cpu0.kern.ipl_ticks::0 1900150859000 97.34% 97.34% # number of cycles we spent at this ipl 679system.cpu0.kern.ipl_ticks::21 92973000 0.00% 97.34% # number of cycles we spent at this ipl 680system.cpu0.kern.ipl_ticks::22 760723500 0.04% 97.38% # number of cycles we spent at this ipl 681system.cpu0.kern.ipl_ticks::30 310562000 0.02% 97.40% # number of cycles we spent at this ipl 682system.cpu0.kern.ipl_ticks::31 50837499000 2.60% 100.00% # number of cycles we spent at this ipl 683system.cpu0.kern.ipl_ticks::total 1952152616500 # number of cycles we spent at this ipl 684system.cpu0.kern.ipl_used::0 0.990442 # fraction of swpipl calls that actually changed the ipl |
| 685system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 686system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 687system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 685system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 686system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 687system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 688system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl 689system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl | 688system.cpu0.kern.ipl_used::31 0.680755 # fraction of swpipl calls that actually changed the ipl 689system.cpu0.kern.ipl_used::total 0.810890 # fraction of swpipl calls that actually changed the ipl |
| 690system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 691system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 692system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 693system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 694system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 695system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 696system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 697system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 713system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 714system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 715system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 716system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 717system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 718system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 719system.cpu0.kern.syscall::total 222 # number of syscalls executed 720system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 690system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 691system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 692system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 693system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 694system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 695system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 696system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 697system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 713system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 714system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 715system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 716system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 717system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 718system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 719system.cpu0.kern.syscall::total 222 # number of syscalls executed 720system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 721system.cpu0.kern.callpal::wripir 525 0.36% 0.36% # number of callpals executed 722system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed 723system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed 724system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed 725system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed 726system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed 727system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed 728system.cpu0.kern.callpal::swpipl 132461 89.75% 92.20% # number of callpals executed 729system.cpu0.kern.callpal::rdps 6674 4.52% 96.72% # number of callpals executed 730system.cpu0.kern.callpal::wrkgp 1 0.00% 96.72% # number of callpals executed 731system.cpu0.kern.callpal::wrusp 3 0.00% 96.72% # number of callpals executed 732system.cpu0.kern.callpal::rdusp 9 0.01% 96.73% # number of callpals executed 733system.cpu0.kern.callpal::whami 2 0.00% 96.73% # number of callpals executed 734system.cpu0.kern.callpal::rti 4310 2.92% 99.65% # number of callpals executed 735system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed | 721system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed 722system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed 723system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 724system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed 725system.cpu0.kern.callpal::swpctx 3074 2.05% 2.39% # number of callpals executed 726system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed 727system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed 728system.cpu0.kern.callpal::swpipl 134771 89.88% 92.30% # number of callpals executed 729system.cpu0.kern.callpal::rdps 6676 4.45% 96.75% # number of callpals executed 730system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed 731system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed 732system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed 733system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed 734system.cpu0.kern.callpal::rti 4338 2.89% 99.66% # number of callpals executed 735system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed |
| 736system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed | 736system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed |
| 737system.cpu0.kern.callpal::total 147588 # number of callpals executed 738system.cpu0.kern.mode_switch::kernel 6865 # number of protection mode switches | 737system.cpu0.kern.callpal::total 149953 # number of callpals executed 738system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches |
| 739system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches 740system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 741system.cpu0.kern.mode_good::kernel 1283 742system.cpu0.kern.mode_good::user 1283 743system.cpu0.kern.mode_good::idle 0 | 739system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches 740system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 741system.cpu0.kern.mode_good::kernel 1283 742system.cpu0.kern.mode_good::user 1283 743system.cpu0.kern.mode_good::idle 0 |
| 744system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches | 744system.cpu0.kern.mode_switch_good::kernel 0.186158 # fraction of useful protection mode switches |
| 745system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 746system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 745system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 746system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 747system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches 748system.cpu0.kern.mode_ticks::kernel 1946502716500 99.83% 99.83% # number of ticks spent at the given mode 749system.cpu0.kern.mode_ticks::user 3403122000 0.17% 100.00% # number of ticks spent at the given mode | 747system.cpu0.kern.mode_switch_good::total 0.313884 # fraction of useful protection mode switches 748system.cpu0.kern.mode_ticks::kernel 1948377502000 99.82% 99.82% # number of ticks spent at the given mode 749system.cpu0.kern.mode_ticks::user 3456174500 0.18% 100.00% # number of ticks spent at the given mode |
| 750system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 750system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 751system.cpu0.kern.swap_context 3025 # number of times the context was actually changed | 751system.cpu0.kern.swap_context 3075 # number of times the context was actually changed |
| 752system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 753system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 754system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 755system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 756system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 757system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 758system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 759system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 775system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 776system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 777system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 778system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 779system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 780system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 781system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 782system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 752system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 753system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 754system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 755system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 756system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 757system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 758system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 759system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 775system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 776system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 777system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 778system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 779system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 780system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 781system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 782system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 783system.cpu0.icache.replacements 686544 # number of replacements 784system.cpu0.icache.tagsinuse 509.179305 # Cycle average of tags in use 785system.cpu0.icache.total_refs 46672235 # Total number of references to valid blocks. 786system.cpu0.icache.sampled_refs 687056 # Sample count of references to valid blocks. 787system.cpu0.icache.avg_refs 67.930758 # Average number of references to valid blocks. 788system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. 789system.cpu0.icache.occ_blocks::cpu0.inst 509.179305 # Average occupied blocks per requestor 790system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy 791system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy 792system.cpu0.icache.ReadReq_hits::cpu0.inst 46672235 # number of ReadReq hits 793system.cpu0.icache.ReadReq_hits::total 46672235 # number of ReadReq hits 794system.cpu0.icache.demand_hits::cpu0.inst 46672235 # number of demand (read+write) hits 795system.cpu0.icache.demand_hits::total 46672235 # number of demand (read+write) hits 796system.cpu0.icache.overall_hits::cpu0.inst 46672235 # number of overall hits 797system.cpu0.icache.overall_hits::total 46672235 # number of overall hits 798system.cpu0.icache.ReadReq_misses::cpu0.inst 687149 # number of ReadReq misses 799system.cpu0.icache.ReadReq_misses::total 687149 # number of ReadReq misses 800system.cpu0.icache.demand_misses::cpu0.inst 687149 # number of demand (read+write) misses 801system.cpu0.icache.demand_misses::total 687149 # number of demand (read+write) misses 802system.cpu0.icache.overall_misses::cpu0.inst 687149 # number of overall misses 803system.cpu0.icache.overall_misses::total 687149 # number of overall misses 804system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9571696500 # number of ReadReq miss cycles 805system.cpu0.icache.ReadReq_miss_latency::total 9571696500 # number of ReadReq miss cycles 806system.cpu0.icache.demand_miss_latency::cpu0.inst 9571696500 # number of demand (read+write) miss cycles 807system.cpu0.icache.demand_miss_latency::total 9571696500 # number of demand (read+write) miss cycles 808system.cpu0.icache.overall_miss_latency::cpu0.inst 9571696500 # number of overall miss cycles 809system.cpu0.icache.overall_miss_latency::total 9571696500 # number of overall miss cycles 810system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359384 # number of ReadReq accesses(hits+misses) 811system.cpu0.icache.ReadReq_accesses::total 47359384 # number of ReadReq accesses(hits+misses) 812system.cpu0.icache.demand_accesses::cpu0.inst 47359384 # number of demand (read+write) accesses 813system.cpu0.icache.demand_accesses::total 47359384 # number of demand (read+write) accesses 814system.cpu0.icache.overall_accesses::cpu0.inst 47359384 # number of overall (read+write) accesses 815system.cpu0.icache.overall_accesses::total 47359384 # number of overall (read+write) accesses 816system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014509 # miss rate for ReadReq accesses 817system.cpu0.icache.ReadReq_miss_rate::total 0.014509 # miss rate for ReadReq accesses 818system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014509 # miss rate for demand accesses 819system.cpu0.icache.demand_miss_rate::total 0.014509 # miss rate for demand accesses 820system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014509 # miss rate for overall accesses 821system.cpu0.icache.overall_miss_rate::total 0.014509 # miss rate for overall accesses 822system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13929.579320 # average ReadReq miss latency 823system.cpu0.icache.ReadReq_avg_miss_latency::total 13929.579320 # average ReadReq miss latency 824system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency 825system.cpu0.icache.demand_avg_miss_latency::total 13929.579320 # average overall miss latency 826system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency 827system.cpu0.icache.overall_avg_miss_latency::total 13929.579320 # average overall miss latency | 783system.cpu0.icache.replacements 699703 # number of replacements 784system.cpu0.icache.tagsinuse 509.161264 # Cycle average of tags in use 785system.cpu0.icache.total_refs 47014995 # Total number of references to valid blocks. 786system.cpu0.icache.sampled_refs 700215 # Sample count of references to valid blocks. 787system.cpu0.icache.avg_refs 67.143656 # Average number of references to valid blocks. 788system.cpu0.icache.warmup_cycle 32599184000 # Cycle when the warmup percentage was hit. 789system.cpu0.icache.occ_blocks::cpu0.inst 509.161264 # Average occupied blocks per requestor 790system.cpu0.icache.occ_percent::cpu0.inst 0.994456 # Average percentage of cache occupancy 791system.cpu0.icache.occ_percent::total 0.994456 # Average percentage of cache occupancy 792system.cpu0.icache.ReadReq_hits::cpu0.inst 47014995 # number of ReadReq hits 793system.cpu0.icache.ReadReq_hits::total 47014995 # number of ReadReq hits 794system.cpu0.icache.demand_hits::cpu0.inst 47014995 # number of demand (read+write) hits 795system.cpu0.icache.demand_hits::total 47014995 # number of demand (read+write) hits 796system.cpu0.icache.overall_hits::cpu0.inst 47014995 # number of overall hits 797system.cpu0.icache.overall_hits::total 47014995 # number of overall hits 798system.cpu0.icache.ReadReq_misses::cpu0.inst 700308 # number of ReadReq misses 799system.cpu0.icache.ReadReq_misses::total 700308 # number of ReadReq misses 800system.cpu0.icache.demand_misses::cpu0.inst 700308 # number of demand (read+write) misses 801system.cpu0.icache.demand_misses::total 700308 # number of demand (read+write) misses 802system.cpu0.icache.overall_misses::cpu0.inst 700308 # number of overall misses 803system.cpu0.icache.overall_misses::total 700308 # number of overall misses 804system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9851397000 # number of ReadReq miss cycles 805system.cpu0.icache.ReadReq_miss_latency::total 9851397000 # number of ReadReq miss cycles 806system.cpu0.icache.demand_miss_latency::cpu0.inst 9851397000 # number of demand (read+write) miss cycles 807system.cpu0.icache.demand_miss_latency::total 9851397000 # number of demand (read+write) miss cycles 808system.cpu0.icache.overall_miss_latency::cpu0.inst 9851397000 # number of overall miss cycles 809system.cpu0.icache.overall_miss_latency::total 9851397000 # number of overall miss cycles 810system.cpu0.icache.ReadReq_accesses::cpu0.inst 47715303 # number of ReadReq accesses(hits+misses) 811system.cpu0.icache.ReadReq_accesses::total 47715303 # number of ReadReq accesses(hits+misses) 812system.cpu0.icache.demand_accesses::cpu0.inst 47715303 # number of demand (read+write) accesses 813system.cpu0.icache.demand_accesses::total 47715303 # number of demand (read+write) accesses 814system.cpu0.icache.overall_accesses::cpu0.inst 47715303 # number of overall (read+write) accesses 815system.cpu0.icache.overall_accesses::total 47715303 # number of overall (read+write) accesses 816system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014677 # miss rate for ReadReq accesses 817system.cpu0.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses 818system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014677 # miss rate for demand accesses 819system.cpu0.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses 820system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014677 # miss rate for overall accesses 821system.cpu0.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses 822system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14067.234702 # average ReadReq miss latency 823system.cpu0.icache.ReadReq_avg_miss_latency::total 14067.234702 # average ReadReq miss latency 824system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency 825system.cpu0.icache.demand_avg_miss_latency::total 14067.234702 # average overall miss latency 826system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency 827system.cpu0.icache.overall_avg_miss_latency::total 14067.234702 # average overall miss latency |
| 828system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 829system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 830system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 831system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 832system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 833system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 834system.cpu0.icache.fast_writes 0 # number of fast writes performed 835system.cpu0.icache.cache_copies 0 # number of cache copies performed | 828system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 829system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 830system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 831system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 832system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 833system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 834system.cpu0.icache.fast_writes 0 # number of fast writes performed 835system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 836system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687149 # number of ReadReq MSHR misses 837system.cpu0.icache.ReadReq_mshr_misses::total 687149 # number of ReadReq MSHR misses 838system.cpu0.icache.demand_mshr_misses::cpu0.inst 687149 # number of demand (read+write) MSHR misses 839system.cpu0.icache.demand_mshr_misses::total 687149 # number of demand (read+write) MSHR misses 840system.cpu0.icache.overall_mshr_misses::cpu0.inst 687149 # number of overall MSHR misses 841system.cpu0.icache.overall_mshr_misses::total 687149 # number of overall MSHR misses 842system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8197398500 # number of ReadReq MSHR miss cycles 843system.cpu0.icache.ReadReq_mshr_miss_latency::total 8197398500 # number of ReadReq MSHR miss cycles 844system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8197398500 # number of demand (read+write) MSHR miss cycles 845system.cpu0.icache.demand_mshr_miss_latency::total 8197398500 # number of demand (read+write) MSHR miss cycles 846system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8197398500 # number of overall MSHR miss cycles 847system.cpu0.icache.overall_mshr_miss_latency::total 8197398500 # number of overall MSHR miss cycles 848system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for ReadReq accesses 849system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014509 # mshr miss rate for ReadReq accesses 850system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for demand accesses 851system.cpu0.icache.demand_mshr_miss_rate::total 0.014509 # mshr miss rate for demand accesses 852system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for overall accesses 853system.cpu0.icache.overall_mshr_miss_rate::total 0.014509 # mshr miss rate for overall accesses 854system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average ReadReq mshr miss latency 855system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11929.579320 # average ReadReq mshr miss latency 856system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency 857system.cpu0.icache.demand_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency 858system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency 859system.cpu0.icache.overall_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency | 836system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700308 # number of ReadReq MSHR misses 837system.cpu0.icache.ReadReq_mshr_misses::total 700308 # number of ReadReq MSHR misses 838system.cpu0.icache.demand_mshr_misses::cpu0.inst 700308 # number of demand (read+write) MSHR misses 839system.cpu0.icache.demand_mshr_misses::total 700308 # number of demand (read+write) MSHR misses 840system.cpu0.icache.overall_mshr_misses::cpu0.inst 700308 # number of overall MSHR misses 841system.cpu0.icache.overall_mshr_misses::total 700308 # number of overall MSHR misses 842system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8450781000 # number of ReadReq MSHR miss cycles 843system.cpu0.icache.ReadReq_mshr_miss_latency::total 8450781000 # number of ReadReq MSHR miss cycles 844system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8450781000 # number of demand (read+write) MSHR miss cycles 845system.cpu0.icache.demand_mshr_miss_latency::total 8450781000 # number of demand (read+write) MSHR miss cycles 846system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8450781000 # number of overall MSHR miss cycles 847system.cpu0.icache.overall_mshr_miss_latency::total 8450781000 # number of overall MSHR miss cycles 848system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for ReadReq accesses 849system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014677 # mshr miss rate for ReadReq accesses 850system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for demand accesses 851system.cpu0.icache.demand_mshr_miss_rate::total 0.014677 # mshr miss rate for demand accesses 852system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for overall accesses 853system.cpu0.icache.overall_mshr_miss_rate::total 0.014677 # mshr miss rate for overall accesses 854system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average ReadReq mshr miss latency 855system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.234702 # average ReadReq mshr miss latency 856system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency 857system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency 858system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency 859system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency |
| 860system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 860system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 861system.cpu0.dcache.replacements 1171731 # number of replacements 862system.cpu0.dcache.tagsinuse 505.264467 # Cycle average of tags in use 863system.cpu0.dcache.total_refs 11253773 # Total number of references to valid blocks. 864system.cpu0.dcache.sampled_refs 1172148 # Sample count of references to valid blocks. 865system.cpu0.dcache.avg_refs 9.600983 # Average number of references to valid blocks. 866system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit. 867system.cpu0.dcache.occ_blocks::cpu0.data 505.264467 # Average occupied blocks per requestor 868system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy 869system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy 870system.cpu0.dcache.ReadReq_hits::cpu0.data 6351999 # number of ReadReq hits 871system.cpu0.dcache.ReadReq_hits::total 6351999 # number of ReadReq hits 872system.cpu0.dcache.WriteReq_hits::cpu0.data 4607371 # number of WriteReq hits 873system.cpu0.dcache.WriteReq_hits::total 4607371 # number of WriteReq hits 874system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138396 # number of LoadLockedReq hits 875system.cpu0.dcache.LoadLockedReq_hits::total 138396 # number of LoadLockedReq hits 876system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145569 # number of StoreCondReq hits 877system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits 878system.cpu0.dcache.demand_hits::cpu0.data 10959370 # number of demand (read+write) hits 879system.cpu0.dcache.demand_hits::total 10959370 # number of demand (read+write) hits 880system.cpu0.dcache.overall_hits::cpu0.data 10959370 # number of overall hits 881system.cpu0.dcache.overall_hits::total 10959370 # number of overall hits 882system.cpu0.dcache.ReadReq_misses::cpu0.data 933038 # number of ReadReq misses 883system.cpu0.dcache.ReadReq_misses::total 933038 # number of ReadReq misses 884system.cpu0.dcache.WriteReq_misses::cpu0.data 249274 # number of WriteReq misses 885system.cpu0.dcache.WriteReq_misses::total 249274 # number of WriteReq misses 886system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13435 # number of LoadLockedReq misses 887system.cpu0.dcache.LoadLockedReq_misses::total 13435 # number of LoadLockedReq misses 888system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5731 # number of StoreCondReq misses 889system.cpu0.dcache.StoreCondReq_misses::total 5731 # number of StoreCondReq misses 890system.cpu0.dcache.demand_misses::cpu0.data 1182312 # number of demand (read+write) misses 891system.cpu0.dcache.demand_misses::total 1182312 # number of demand (read+write) misses 892system.cpu0.dcache.overall_misses::cpu0.data 1182312 # number of overall misses 893system.cpu0.dcache.overall_misses::total 1182312 # number of overall misses 894system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20824713000 # number of ReadReq miss cycles 895system.cpu0.dcache.ReadReq_miss_latency::total 20824713000 # number of ReadReq miss cycles 896system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7766651000 # number of WriteReq miss cycles 897system.cpu0.dcache.WriteReq_miss_latency::total 7766651000 # number of WriteReq miss cycles 898system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144248500 # number of LoadLockedReq miss cycles 899system.cpu0.dcache.LoadLockedReq_miss_latency::total 144248500 # number of LoadLockedReq miss cycles 900system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43490500 # number of StoreCondReq miss cycles 901system.cpu0.dcache.StoreCondReq_miss_latency::total 43490500 # number of StoreCondReq miss cycles 902system.cpu0.dcache.demand_miss_latency::cpu0.data 28591364000 # number of demand (read+write) miss cycles 903system.cpu0.dcache.demand_miss_latency::total 28591364000 # number of demand (read+write) miss cycles 904system.cpu0.dcache.overall_miss_latency::cpu0.data 28591364000 # number of overall miss cycles 905system.cpu0.dcache.overall_miss_latency::total 28591364000 # number of overall miss cycles 906system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285037 # number of ReadReq accesses(hits+misses) 907system.cpu0.dcache.ReadReq_accesses::total 7285037 # number of ReadReq accesses(hits+misses) 908system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856645 # number of WriteReq accesses(hits+misses) 909system.cpu0.dcache.WriteReq_accesses::total 4856645 # number of WriteReq accesses(hits+misses) 910system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151831 # number of LoadLockedReq accesses(hits+misses) 911system.cpu0.dcache.LoadLockedReq_accesses::total 151831 # number of LoadLockedReq accesses(hits+misses) 912system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151300 # number of StoreCondReq accesses(hits+misses) 913system.cpu0.dcache.StoreCondReq_accesses::total 151300 # number of StoreCondReq accesses(hits+misses) 914system.cpu0.dcache.demand_accesses::cpu0.data 12141682 # number of demand (read+write) accesses 915system.cpu0.dcache.demand_accesses::total 12141682 # number of demand (read+write) accesses 916system.cpu0.dcache.overall_accesses::cpu0.data 12141682 # number of overall (read+write) accesses 917system.cpu0.dcache.overall_accesses::total 12141682 # number of overall (read+write) accesses 918system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128076 # miss rate for ReadReq accesses 919system.cpu0.dcache.ReadReq_miss_rate::total 0.128076 # miss rate for ReadReq accesses 920system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051326 # miss rate for WriteReq accesses 921system.cpu0.dcache.WriteReq_miss_rate::total 0.051326 # miss rate for WriteReq accesses 922system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088487 # miss rate for LoadLockedReq accesses 923system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088487 # miss rate for LoadLockedReq accesses 924system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses 925system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses 926system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097376 # miss rate for demand accesses 927system.cpu0.dcache.demand_miss_rate::total 0.097376 # miss rate for demand accesses 928system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097376 # miss rate for overall accesses 929system.cpu0.dcache.overall_miss_rate::total 0.097376 # miss rate for overall accesses 930system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22319.254950 # average ReadReq miss latency 931system.cpu0.dcache.ReadReq_avg_miss_latency::total 22319.254950 # average ReadReq miss latency 932system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31157.084172 # average WriteReq miss latency 933system.cpu0.dcache.WriteReq_avg_miss_latency::total 31157.084172 # average WriteReq miss latency 934system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10736.769632 # average LoadLockedReq miss latency 935system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10736.769632 # average LoadLockedReq miss latency 936system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7588.640726 # average StoreCondReq miss latency 937system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7588.640726 # average StoreCondReq miss latency 938system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency 939system.cpu0.dcache.demand_avg_miss_latency::total 24182.588014 # average overall miss latency 940system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency 941system.cpu0.dcache.overall_avg_miss_latency::total 24182.588014 # average overall miss latency | 861system.cpu0.dcache.replacements 1182211 # number of replacements 862system.cpu0.dcache.tagsinuse 505.184188 # Cycle average of tags in use 863system.cpu0.dcache.total_refs 11367781 # Total number of references to valid blocks. 864system.cpu0.dcache.sampled_refs 1182629 # Sample count of references to valid blocks. 865system.cpu0.dcache.avg_refs 9.612297 # Average number of references to valid blocks. 866system.cpu0.dcache.warmup_cycle 93616000 # Cycle when the warmup percentage was hit. 867system.cpu0.dcache.occ_blocks::cpu0.data 505.184188 # Average occupied blocks per requestor 868system.cpu0.dcache.occ_percent::cpu0.data 0.986688 # Average percentage of cache occupancy 869system.cpu0.dcache.occ_percent::total 0.986688 # Average percentage of cache occupancy 870system.cpu0.dcache.ReadReq_hits::cpu0.data 6409561 # number of ReadReq hits 871system.cpu0.dcache.ReadReq_hits::total 6409561 # number of ReadReq hits 872system.cpu0.dcache.WriteReq_hits::cpu0.data 4659572 # number of WriteReq hits 873system.cpu0.dcache.WriteReq_hits::total 4659572 # number of WriteReq hits 874system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140562 # number of LoadLockedReq hits 875system.cpu0.dcache.LoadLockedReq_hits::total 140562 # number of LoadLockedReq hits 876system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148239 # number of StoreCondReq hits 877system.cpu0.dcache.StoreCondReq_hits::total 148239 # number of StoreCondReq hits 878system.cpu0.dcache.demand_hits::cpu0.data 11069133 # number of demand (read+write) hits 879system.cpu0.dcache.demand_hits::total 11069133 # number of demand (read+write) hits 880system.cpu0.dcache.overall_hits::cpu0.data 11069133 # number of overall hits 881system.cpu0.dcache.overall_hits::total 11069133 # number of overall hits 882system.cpu0.dcache.ReadReq_misses::cpu0.data 939643 # number of ReadReq misses 883system.cpu0.dcache.ReadReq_misses::total 939643 # number of ReadReq misses 884system.cpu0.dcache.WriteReq_misses::cpu0.data 251886 # number of WriteReq misses 885system.cpu0.dcache.WriteReq_misses::total 251886 # number of WriteReq misses 886system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13649 # number of LoadLockedReq misses 887system.cpu0.dcache.LoadLockedReq_misses::total 13649 # number of LoadLockedReq misses 888system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5418 # number of StoreCondReq misses 889system.cpu0.dcache.StoreCondReq_misses::total 5418 # number of StoreCondReq misses 890system.cpu0.dcache.demand_misses::cpu0.data 1191529 # number of demand (read+write) misses 891system.cpu0.dcache.demand_misses::total 1191529 # number of demand (read+write) misses 892system.cpu0.dcache.overall_misses::cpu0.data 1191529 # number of overall misses 893system.cpu0.dcache.overall_misses::total 1191529 # number of overall misses 894system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 21121102500 # number of ReadReq miss cycles 895system.cpu0.dcache.ReadReq_miss_latency::total 21121102500 # number of ReadReq miss cycles 896system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7642676000 # number of WriteReq miss cycles 897system.cpu0.dcache.WriteReq_miss_latency::total 7642676000 # number of WriteReq miss cycles 898system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149168500 # number of LoadLockedReq miss cycles 899system.cpu0.dcache.LoadLockedReq_miss_latency::total 149168500 # number of LoadLockedReq miss cycles 900system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 41236000 # number of StoreCondReq miss cycles 901system.cpu0.dcache.StoreCondReq_miss_latency::total 41236000 # number of StoreCondReq miss cycles 902system.cpu0.dcache.demand_miss_latency::cpu0.data 28763778500 # number of demand (read+write) miss cycles 903system.cpu0.dcache.demand_miss_latency::total 28763778500 # number of demand (read+write) miss cycles 904system.cpu0.dcache.overall_miss_latency::cpu0.data 28763778500 # number of overall miss cycles 905system.cpu0.dcache.overall_miss_latency::total 28763778500 # number of overall miss cycles 906system.cpu0.dcache.ReadReq_accesses::cpu0.data 7349204 # number of ReadReq accesses(hits+misses) 907system.cpu0.dcache.ReadReq_accesses::total 7349204 # number of ReadReq accesses(hits+misses) 908system.cpu0.dcache.WriteReq_accesses::cpu0.data 4911458 # number of WriteReq accesses(hits+misses) 909system.cpu0.dcache.WriteReq_accesses::total 4911458 # number of WriteReq accesses(hits+misses) 910system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154211 # number of LoadLockedReq accesses(hits+misses) 911system.cpu0.dcache.LoadLockedReq_accesses::total 154211 # number of LoadLockedReq accesses(hits+misses) 912system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153657 # number of StoreCondReq accesses(hits+misses) 913system.cpu0.dcache.StoreCondReq_accesses::total 153657 # number of StoreCondReq accesses(hits+misses) 914system.cpu0.dcache.demand_accesses::cpu0.data 12260662 # number of demand (read+write) accesses 915system.cpu0.dcache.demand_accesses::total 12260662 # number of demand (read+write) accesses 916system.cpu0.dcache.overall_accesses::cpu0.data 12260662 # number of overall (read+write) accesses 917system.cpu0.dcache.overall_accesses::total 12260662 # number of overall (read+write) accesses 918system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127856 # miss rate for ReadReq accesses 919system.cpu0.dcache.ReadReq_miss_rate::total 0.127856 # miss rate for ReadReq accesses 920system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051285 # miss rate for WriteReq accesses 921system.cpu0.dcache.WriteReq_miss_rate::total 0.051285 # miss rate for WriteReq accesses 922system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088509 # miss rate for LoadLockedReq accesses 923system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088509 # miss rate for LoadLockedReq accesses 924system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035260 # miss rate for StoreCondReq accesses 925system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035260 # miss rate for StoreCondReq accesses 926system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097183 # miss rate for demand accesses 927system.cpu0.dcache.demand_miss_rate::total 0.097183 # miss rate for demand accesses 928system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097183 # miss rate for overall accesses 929system.cpu0.dcache.overall_miss_rate::total 0.097183 # miss rate for overall accesses 930system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22477.794758 # average ReadReq miss latency 931system.cpu0.dcache.ReadReq_avg_miss_latency::total 22477.794758 # average ReadReq miss latency 932system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30341.805420 # average WriteReq miss latency 933system.cpu0.dcache.WriteReq_avg_miss_latency::total 30341.805420 # average WriteReq miss latency 934system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10928.895890 # average LoadLockedReq miss latency 935system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10928.895890 # average LoadLockedReq miss latency 936system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7610.926541 # average StoreCondReq miss latency 937system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7610.926541 # average StoreCondReq miss latency 938system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency 939system.cpu0.dcache.demand_avg_miss_latency::total 24140.225290 # average overall miss latency 940system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency 941system.cpu0.dcache.overall_avg_miss_latency::total 24140.225290 # average overall miss latency |
| 942system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 943system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 944system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 945system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 946system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 947system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 948system.cpu0.dcache.fast_writes 0 # number of fast writes performed 949system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 942system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 943system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 944system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 945system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 946system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 947system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 948system.cpu0.dcache.fast_writes 0 # number of fast writes performed 949system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 950system.cpu0.dcache.writebacks::writebacks 672345 # number of writebacks 951system.cpu0.dcache.writebacks::total 672345 # number of writebacks 952system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933038 # number of ReadReq MSHR misses 953system.cpu0.dcache.ReadReq_mshr_misses::total 933038 # number of ReadReq MSHR misses 954system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249274 # number of WriteReq MSHR misses 955system.cpu0.dcache.WriteReq_mshr_misses::total 249274 # number of WriteReq MSHR misses 956system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13435 # number of LoadLockedReq MSHR misses 957system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13435 # number of LoadLockedReq MSHR misses 958system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses 959system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses 960system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182312 # number of demand (read+write) MSHR misses 961system.cpu0.dcache.demand_mshr_misses::total 1182312 # number of demand (read+write) MSHR misses 962system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182312 # number of overall MSHR misses 963system.cpu0.dcache.overall_mshr_misses::total 1182312 # number of overall MSHR misses 964system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18958637000 # number of ReadReq MSHR miss cycles 965system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18958637000 # number of ReadReq MSHR miss cycles 966system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7268103000 # number of WriteReq MSHR miss cycles 967system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7268103000 # number of WriteReq MSHR miss cycles 968system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117378500 # number of LoadLockedReq MSHR miss cycles 969system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117378500 # number of LoadLockedReq MSHR miss cycles 970system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32028500 # number of StoreCondReq MSHR miss cycles 971system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32028500 # number of StoreCondReq MSHR miss cycles 972system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26226740000 # number of demand (read+write) MSHR miss cycles 973system.cpu0.dcache.demand_mshr_miss_latency::total 26226740000 # number of demand (read+write) MSHR miss cycles 974system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26226740000 # number of overall MSHR miss cycles 975system.cpu0.dcache.overall_mshr_miss_latency::total 26226740000 # number of overall MSHR miss cycles 976system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465462500 # number of ReadReq MSHR uncacheable cycles 977system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465462500 # number of ReadReq MSHR uncacheable cycles 978system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285670500 # number of WriteReq MSHR uncacheable cycles 979system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285670500 # number of WriteReq MSHR uncacheable cycles 980system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3751133000 # number of overall MSHR uncacheable cycles 981system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3751133000 # number of overall MSHR uncacheable cycles 982system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses 983system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses 984system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051326 # mshr miss rate for WriteReq accesses 985system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051326 # mshr miss rate for WriteReq accesses 986system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088487 # mshr miss rate for LoadLockedReq accesses 987system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088487 # mshr miss rate for LoadLockedReq accesses 988system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses 989system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses 990system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for demand accesses 991system.cpu0.dcache.demand_mshr_miss_rate::total 0.097376 # mshr miss rate for demand accesses 992system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for overall accesses 993system.cpu0.dcache.overall_mshr_miss_rate::total 0.097376 # mshr miss rate for overall accesses 994system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20319.254950 # average ReadReq mshr miss latency 995system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20319.254950 # average ReadReq mshr miss latency 996system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29157.084172 # average WriteReq mshr miss latency 997system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29157.084172 # average WriteReq mshr miss latency 998system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8736.769632 # average LoadLockedReq mshr miss latency 999system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8736.769632 # average LoadLockedReq mshr miss latency 1000system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5588.640726 # average StoreCondReq mshr miss latency 1001system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5588.640726 # average StoreCondReq mshr miss latency 1002system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency 1003system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency 1004system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency 1005system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency | 950system.cpu0.dcache.writebacks::writebacks 680601 # number of writebacks 951system.cpu0.dcache.writebacks::total 680601 # number of writebacks 952system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939643 # number of ReadReq MSHR misses 953system.cpu0.dcache.ReadReq_mshr_misses::total 939643 # number of ReadReq MSHR misses 954system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251886 # number of WriteReq MSHR misses 955system.cpu0.dcache.WriteReq_mshr_misses::total 251886 # number of WriteReq MSHR misses 956system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13649 # number of LoadLockedReq MSHR misses 957system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13649 # number of LoadLockedReq MSHR misses 958system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5418 # number of StoreCondReq MSHR misses 959system.cpu0.dcache.StoreCondReq_mshr_misses::total 5418 # number of StoreCondReq MSHR misses 960system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191529 # number of demand (read+write) MSHR misses 961system.cpu0.dcache.demand_mshr_misses::total 1191529 # number of demand (read+write) MSHR misses 962system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191529 # number of overall MSHR misses 963system.cpu0.dcache.overall_mshr_misses::total 1191529 # number of overall MSHR misses 964system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19241816500 # number of ReadReq MSHR miss cycles 965system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19241816500 # number of ReadReq MSHR miss cycles 966system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7138904000 # number of WriteReq MSHR miss cycles 967system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7138904000 # number of WriteReq MSHR miss cycles 968system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121870500 # number of LoadLockedReq MSHR miss cycles 969system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121870500 # number of LoadLockedReq MSHR miss cycles 970system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30400000 # number of StoreCondReq MSHR miss cycles 971system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30400000 # number of StoreCondReq MSHR miss cycles 972system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26380720500 # number of demand (read+write) MSHR miss cycles 973system.cpu0.dcache.demand_mshr_miss_latency::total 26380720500 # number of demand (read+write) MSHR miss cycles 974system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26380720500 # number of overall MSHR miss cycles 975system.cpu0.dcache.overall_mshr_miss_latency::total 26380720500 # number of overall MSHR miss cycles 976system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465344500 # number of ReadReq MSHR uncacheable cycles 977system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465344500 # number of ReadReq MSHR uncacheable cycles 978system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2274931000 # number of WriteReq MSHR uncacheable cycles 979system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2274931000 # number of WriteReq MSHR uncacheable cycles 980system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3740275500 # number of overall MSHR uncacheable cycles 981system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3740275500 # number of overall MSHR uncacheable cycles 982system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127856 # mshr miss rate for ReadReq accesses 983system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127856 # mshr miss rate for ReadReq accesses 984system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051285 # mshr miss rate for WriteReq accesses 985system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051285 # mshr miss rate for WriteReq accesses 986system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088509 # mshr miss rate for LoadLockedReq accesses 987system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088509 # mshr miss rate for LoadLockedReq accesses 988system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035260 # mshr miss rate for StoreCondReq accesses 989system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035260 # mshr miss rate for StoreCondReq accesses 990system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for demand accesses 991system.cpu0.dcache.demand_mshr_miss_rate::total 0.097183 # mshr miss rate for demand accesses 992system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for overall accesses 993system.cpu0.dcache.overall_mshr_miss_rate::total 0.097183 # mshr miss rate for overall accesses 994system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20477.794758 # average ReadReq mshr miss latency 995system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20477.794758 # average ReadReq mshr miss latency 996system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28341.805420 # average WriteReq mshr miss latency 997system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28341.805420 # average WriteReq mshr miss latency 998system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8928.895890 # average LoadLockedReq mshr miss latency 999system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8928.895890 # average LoadLockedReq mshr miss latency 1000system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5610.926541 # average StoreCondReq mshr miss latency 1001system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5610.926541 # average StoreCondReq mshr miss latency 1002system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency 1003system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency 1004system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency 1005system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency |
| 1006system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1007system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1008system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1009system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1010system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1011system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1012system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1013system.cpu1.dtb.fetch_hits 0 # ITB hits 1014system.cpu1.dtb.fetch_misses 0 # ITB misses 1015system.cpu1.dtb.fetch_acv 0 # ITB acv 1016system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 1006system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1007system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1008system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1009system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1010system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1011system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1012system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1013system.cpu1.dtb.fetch_hits 0 # ITB hits 1014system.cpu1.dtb.fetch_misses 0 # ITB misses 1015system.cpu1.dtb.fetch_acv 0 # ITB acv 1016system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 1017system.cpu1.dtb.read_hits 2500361 # DTB read hits | 1017system.cpu1.dtb.read_hits 2417694 # DTB read hits |
| 1018system.cpu1.dtb.read_misses 2992 # DTB read misses 1019system.cpu1.dtb.read_acv 0 # DTB read access violations 1020system.cpu1.dtb.read_accesses 239363 # DTB read accesses | 1018system.cpu1.dtb.read_misses 2992 # DTB read misses 1019system.cpu1.dtb.read_acv 0 # DTB read access violations 1020system.cpu1.dtb.read_accesses 239363 # DTB read accesses |
| 1021system.cpu1.dtb.write_hits 1820984 # DTB write hits | 1021system.cpu1.dtb.write_hits 1754404 # DTB write hits |
| 1022system.cpu1.dtb.write_misses 341 # DTB write misses 1023system.cpu1.dtb.write_acv 29 # DTB write access violations 1024system.cpu1.dtb.write_accesses 105247 # DTB write accesses | 1022system.cpu1.dtb.write_misses 341 # DTB write misses 1023system.cpu1.dtb.write_acv 29 # DTB write access violations 1024system.cpu1.dtb.write_accesses 105247 # DTB write accesses |
| 1025system.cpu1.dtb.data_hits 4321345 # DTB hits | 1025system.cpu1.dtb.data_hits 4172098 # DTB hits |
| 1026system.cpu1.dtb.data_misses 3333 # DTB misses 1027system.cpu1.dtb.data_acv 29 # DTB access violations 1028system.cpu1.dtb.data_accesses 344610 # DTB accesses | 1026system.cpu1.dtb.data_misses 3333 # DTB misses 1027system.cpu1.dtb.data_acv 29 # DTB access violations 1028system.cpu1.dtb.data_accesses 344610 # DTB accesses |
| 1029system.cpu1.itb.fetch_hits 1990033 # ITB hits | 1029system.cpu1.itb.fetch_hits 1961503 # ITB hits |
| 1030system.cpu1.itb.fetch_misses 1216 # ITB misses 1031system.cpu1.itb.fetch_acv 0 # ITB acv | 1030system.cpu1.itb.fetch_misses 1216 # ITB misses 1031system.cpu1.itb.fetch_acv 0 # ITB acv |
| 1032system.cpu1.itb.fetch_accesses 1991249 # ITB accesses | 1032system.cpu1.itb.fetch_accesses 1962719 # ITB accesses |
| 1033system.cpu1.itb.read_hits 0 # DTB read hits 1034system.cpu1.itb.read_misses 0 # DTB read misses 1035system.cpu1.itb.read_acv 0 # DTB read access violations 1036system.cpu1.itb.read_accesses 0 # DTB read accesses 1037system.cpu1.itb.write_hits 0 # DTB write hits 1038system.cpu1.itb.write_misses 0 # DTB write misses 1039system.cpu1.itb.write_acv 0 # DTB write access violations 1040system.cpu1.itb.write_accesses 0 # DTB write accesses 1041system.cpu1.itb.data_hits 0 # DTB hits 1042system.cpu1.itb.data_misses 0 # DTB misses 1043system.cpu1.itb.data_acv 0 # DTB access violations 1044system.cpu1.itb.data_accesses 0 # DTB accesses | 1033system.cpu1.itb.read_hits 0 # DTB read hits 1034system.cpu1.itb.read_misses 0 # DTB read misses 1035system.cpu1.itb.read_acv 0 # DTB read access violations 1036system.cpu1.itb.read_accesses 0 # DTB read accesses 1037system.cpu1.itb.write_hits 0 # DTB write hits 1038system.cpu1.itb.write_misses 0 # DTB write misses 1039system.cpu1.itb.write_acv 0 # DTB write access violations 1040system.cpu1.itb.write_accesses 0 # DTB write accesses 1041system.cpu1.itb.data_hits 0 # DTB hits 1042system.cpu1.itb.data_misses 0 # DTB misses 1043system.cpu1.itb.data_acv 0 # DTB access violations 1044system.cpu1.itb.data_accesses 0 # DTB accesses |
| 1045system.cpu1.numCycles 3901627911 # number of cpu cycles simulated | 1045system.cpu1.numCycles 3905448539 # number of cpu cycles simulated |
| 1046system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1047system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1046system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1047system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1048system.cpu1.committedInsts 13632233 # Number of instructions committed 1049system.cpu1.committedOps 13632233 # Number of ops (including micro ops) committed 1050system.cpu1.num_int_alu_accesses 12571690 # Number of integer alu accesses 1051system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses 1052system.cpu1.num_func_calls 426713 # number of times a function call or return occured 1053system.cpu1.num_conditional_control_insts 1355142 # number of instructions that are conditional controls 1054system.cpu1.num_int_insts 12571690 # number of integer instructions 1055system.cpu1.num_fp_insts 180459 # number of float instructions 1056system.cpu1.num_int_register_reads 17311762 # number of times the integer registers were read 1057system.cpu1.num_int_register_writes 9221860 # number of times the integer registers were written 1058system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read 1059system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written 1060system.cpu1.num_mem_refs 4345653 # number of memory refs 1061system.cpu1.num_load_insts 2515108 # Number of load instructions 1062system.cpu1.num_store_insts 1830545 # Number of store instructions 1063system.cpu1.num_idle_cycles 3850258537.998026 # Number of idle cycles 1064system.cpu1.num_busy_cycles 51369373.001974 # Number of busy cycles 1065system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles 1066system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles | 1048system.cpu1.committedInsts 13160532 # Number of instructions committed 1049system.cpu1.committedOps 13160532 # Number of ops (including micro ops) committed 1050system.cpu1.num_int_alu_accesses 12141335 # Number of integer alu accesses 1051system.cpu1.num_fp_alu_accesses 171917 # Number of float alu accesses 1052system.cpu1.num_func_calls 411397 # number of times a function call or return occured 1053system.cpu1.num_conditional_control_insts 1307333 # number of instructions that are conditional controls 1054system.cpu1.num_int_insts 12141335 # number of integer instructions 1055system.cpu1.num_fp_insts 171917 # number of float instructions 1056system.cpu1.num_int_register_reads 16724790 # number of times the integer registers were read 1057system.cpu1.num_int_register_writes 8912820 # number of times the integer registers were written 1058system.cpu1.num_fp_register_reads 89976 # number of times the floating registers were read 1059system.cpu1.num_fp_register_writes 91834 # number of times the floating registers were written 1060system.cpu1.num_mem_refs 4195541 # number of memory refs 1061system.cpu1.num_load_insts 2431931 # Number of load instructions 1062system.cpu1.num_store_insts 1763610 # Number of store instructions 1063system.cpu1.num_idle_cycles 3855992964.998025 # Number of idle cycles 1064system.cpu1.num_busy_cycles 49455574.001975 # Number of busy cycles 1065system.cpu1.not_idle_fraction 0.012663 # Percentage of non-idle cycles 1066system.cpu1.idle_fraction 0.987337 # Percentage of idle cycles |
| 1067system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1067system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1068system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed 1069system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed 1070system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl 1071system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl 1072system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl 1073system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl 1074system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl 1075system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl 1076system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl 1077system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl 1078system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl 1079system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl 1080system.cpu1.kern.ipl_ticks::0 1907137344500 97.76% 97.76% # number of cycles we spent at this ipl 1081system.cpu1.kern.ipl_ticks::22 705261000 0.04% 97.80% # number of cycles we spent at this ipl 1082system.cpu1.kern.ipl_ticks::30 364072500 0.02% 97.82% # number of cycles we spent at this ipl 1083system.cpu1.kern.ipl_ticks::31 42606519500 2.18% 100.00% # number of cycles we spent at this ipl 1084system.cpu1.kern.ipl_ticks::total 1950813197500 # number of cycles we spent at this ipl 1085system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl | 1068system.cpu1.kern.inst.quiesce 2696 # number of quiesce instructions executed 1069system.cpu1.kern.inst.hwrei 78331 # number of hwrei instructions executed 1070system.cpu1.kern.ipl_count::0 26451 38.35% 38.35% # number of times we switched to this ipl 1071system.cpu1.kern.ipl_count::22 1967 2.85% 41.20% # number of times we switched to this ipl 1072system.cpu1.kern.ipl_count::30 500 0.72% 41.92% # number of times we switched to this ipl 1073system.cpu1.kern.ipl_count::31 40063 58.08% 100.00% # number of times we switched to this ipl 1074system.cpu1.kern.ipl_count::total 68981 # number of times we switched to this ipl 1075system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl 1076system.cpu1.kern.ipl_good::22 1967 3.70% 51.85% # number of times we switched to this ipl from a different ipl 1077system.cpu1.kern.ipl_good::30 500 0.94% 52.79% # number of times we switched to this ipl from a different ipl 1078system.cpu1.kern.ipl_good::31 25118 47.21% 100.00% # number of times we switched to this ipl from a different ipl 1079system.cpu1.kern.ipl_good::total 53203 # number of times we switched to this ipl from a different ipl 1080system.cpu1.kern.ipl_ticks::0 1909244973500 97.77% 97.77% # number of cycles we spent at this ipl 1081system.cpu1.kern.ipl_ticks::22 705660500 0.04% 97.81% # number of cycles we spent at this ipl 1082system.cpu1.kern.ipl_ticks::30 346600000 0.02% 97.83% # number of cycles we spent at this ipl 1083system.cpu1.kern.ipl_ticks::31 42426277500 2.17% 100.00% # number of cycles we spent at this ipl 1084system.cpu1.kern.ipl_ticks::total 1952723511500 # number of cycles we spent at this ipl 1085system.cpu1.kern.ipl_used::0 0.968508 # fraction of swpipl calls that actually changed the ipl |
| 1086system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1087system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1086system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1087system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1088system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl 1089system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl | 1088system.cpu1.kern.ipl_used::31 0.626963 # fraction of swpipl calls that actually changed the ipl 1089system.cpu1.kern.ipl_used::total 0.771270 # fraction of swpipl calls that actually changed the ipl |
| 1090system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 1091system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 1092system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 1093system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 1094system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 1095system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 1096system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 1097system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 1098system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 1099system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 1100system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 1101system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 1102system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 1103system.cpu1.kern.syscall::total 104 # number of syscalls executed 1104system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 1090system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 1091system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 1092system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 1093system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 1094system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 1095system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 1096system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 1097system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 1098system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 1099system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 1100system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 1101system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 1102system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 1103system.cpu1.kern.syscall::total 104 # number of syscalls executed 1104system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 1105system.cpu1.kern.callpal::wripir 443 0.60% 0.60% # number of callpals executed 1106system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed 1107system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed 1108system.cpu1.kern.callpal::swpctx 2085 2.82% 3.43% # number of callpals executed 1109system.cpu1.kern.callpal::tbi 3 0.00% 3.43% # number of callpals executed 1110system.cpu1.kern.callpal::wrent 7 0.01% 3.44% # number of callpals executed 1111system.cpu1.kern.callpal::swpipl 65093 88.17% 91.61% # number of callpals executed 1112system.cpu1.kern.callpal::rdps 2167 2.94% 94.55% # number of callpals executed 1113system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed 1114system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed 1115system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed 1116system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed 1117system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed | 1105system.cpu1.kern.callpal::wripir 418 0.59% 0.59% # number of callpals executed 1106system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 1107system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed 1108system.cpu1.kern.callpal::swpctx 1983 2.78% 3.37% # number of callpals executed 1109system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed 1110system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed 1111system.cpu1.kern.callpal::swpipl 62750 88.03% 91.41% # number of callpals executed 1112system.cpu1.kern.callpal::rdps 2168 3.04% 94.46% # number of callpals executed 1113system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed 1114system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed 1115system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed 1116system.cpu1.kern.callpal::rti 3763 5.28% 99.75% # number of callpals executed 1117system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed |
| 1118system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 1119system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 1118system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 1119system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 1120system.cpu1.kern.callpal::total 73828 # number of callpals executed 1121system.cpu1.kern.mode_switch::kernel 2125 # number of protection mode switches | 1120system.cpu1.kern.callpal::total 71284 # number of callpals executed 1121system.cpu1.kern.mode_switch::kernel 2048 # number of protection mode switches |
| 1122system.cpu1.kern.mode_switch::user 465 # number of protection mode switches | 1122system.cpu1.kern.mode_switch::user 465 # number of protection mode switches |
| 1123system.cpu1.kern.mode_switch::idle 2925 # number of protection mode switches 1124system.cpu1.kern.mode_good::kernel 915 | 1123system.cpu1.kern.mode_switch::idle 2876 # number of protection mode switches 1124system.cpu1.kern.mode_good::kernel 889 |
| 1125system.cpu1.kern.mode_good::user 465 | 1125system.cpu1.kern.mode_good::user 465 |
| 1126system.cpu1.kern.mode_good::idle 450 1127system.cpu1.kern.mode_switch_good::kernel 0.430588 # fraction of useful protection mode switches | 1126system.cpu1.kern.mode_good::idle 424 1127system.cpu1.kern.mode_switch_good::kernel 0.434082 # fraction of useful protection mode switches |
| 1128system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1128system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1129system.cpu1.kern.mode_switch_good::idle 0.153846 # fraction of useful protection mode switches 1130system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches 1131system.cpu1.kern.mode_ticks::kernel 18664257000 0.96% 0.96% # number of ticks spent at the given mode 1132system.cpu1.kern.mode_ticks::user 1710579000 0.09% 1.04% # number of ticks spent at the given mode 1133system.cpu1.kern.mode_ticks::idle 1930438358000 98.96% 100.00% # number of ticks spent at the given mode 1134system.cpu1.kern.swap_context 2086 # number of times the context was actually changed 1135system.cpu1.icache.replacements 328646 # number of replacements 1136system.cpu1.icache.tagsinuse 446.257851 # Cycle average of tags in use 1137system.cpu1.icache.total_refs 13306402 # Total number of references to valid blocks. 1138system.cpu1.icache.sampled_refs 329158 # Sample count of references to valid blocks. 1139system.cpu1.icache.avg_refs 40.425577 # Average number of references to valid blocks. 1140system.cpu1.icache.warmup_cycle 1948915489000 # Cycle when the warmup percentage was hit. 1141system.cpu1.icache.occ_blocks::cpu1.inst 446.257851 # Average occupied blocks per requestor 1142system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy 1143system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy 1144system.cpu1.icache.ReadReq_hits::cpu1.inst 13306402 # number of ReadReq hits 1145system.cpu1.icache.ReadReq_hits::total 13306402 # number of ReadReq hits 1146system.cpu1.icache.demand_hits::cpu1.inst 13306402 # number of demand (read+write) hits 1147system.cpu1.icache.demand_hits::total 13306402 # number of demand (read+write) hits 1148system.cpu1.icache.overall_hits::cpu1.inst 13306402 # number of overall hits 1149system.cpu1.icache.overall_hits::total 13306402 # number of overall hits 1150system.cpu1.icache.ReadReq_misses::cpu1.inst 329194 # number of ReadReq misses 1151system.cpu1.icache.ReadReq_misses::total 329194 # number of ReadReq misses 1152system.cpu1.icache.demand_misses::cpu1.inst 329194 # number of demand (read+write) misses 1153system.cpu1.icache.demand_misses::total 329194 # number of demand (read+write) misses 1154system.cpu1.icache.overall_misses::cpu1.inst 329194 # number of overall misses 1155system.cpu1.icache.overall_misses::total 329194 # number of overall misses 1156system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4346536000 # number of ReadReq miss cycles 1157system.cpu1.icache.ReadReq_miss_latency::total 4346536000 # number of ReadReq miss cycles 1158system.cpu1.icache.demand_miss_latency::cpu1.inst 4346536000 # number of demand (read+write) miss cycles 1159system.cpu1.icache.demand_miss_latency::total 4346536000 # number of demand (read+write) miss cycles 1160system.cpu1.icache.overall_miss_latency::cpu1.inst 4346536000 # number of overall miss cycles 1161system.cpu1.icache.overall_miss_latency::total 4346536000 # number of overall miss cycles 1162system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635596 # number of ReadReq accesses(hits+misses) 1163system.cpu1.icache.ReadReq_accesses::total 13635596 # number of ReadReq accesses(hits+misses) 1164system.cpu1.icache.demand_accesses::cpu1.inst 13635596 # number of demand (read+write) accesses 1165system.cpu1.icache.demand_accesses::total 13635596 # number of demand (read+write) accesses 1166system.cpu1.icache.overall_accesses::cpu1.inst 13635596 # number of overall (read+write) accesses 1167system.cpu1.icache.overall_accesses::total 13635596 # number of overall (read+write) accesses 1168system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024142 # miss rate for ReadReq accesses 1169system.cpu1.icache.ReadReq_miss_rate::total 0.024142 # miss rate for ReadReq accesses 1170system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024142 # miss rate for demand accesses 1171system.cpu1.icache.demand_miss_rate::total 0.024142 # miss rate for demand accesses 1172system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024142 # miss rate for overall accesses 1173system.cpu1.icache.overall_miss_rate::total 0.024142 # miss rate for overall accesses 1174system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13203.569931 # average ReadReq miss latency 1175system.cpu1.icache.ReadReq_avg_miss_latency::total 13203.569931 # average ReadReq miss latency 1176system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency 1177system.cpu1.icache.demand_avg_miss_latency::total 13203.569931 # average overall miss latency 1178system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency 1179system.cpu1.icache.overall_avg_miss_latency::total 13203.569931 # average overall miss latency | 1129system.cpu1.kern.mode_switch_good::idle 0.147427 # fraction of useful protection mode switches 1130system.cpu1.kern.mode_switch_good::total 0.329931 # fraction of useful protection mode switches 1131system.cpu1.kern.mode_ticks::kernel 17784732000 0.91% 0.91% # number of ticks spent at the given mode 1132system.cpu1.kern.mode_ticks::user 1713538500 0.09% 1.00% # number of ticks spent at the given mode 1133system.cpu1.kern.mode_ticks::idle 1933225237500 99.00% 100.00% # number of ticks spent at the given mode 1134system.cpu1.kern.swap_context 1984 # number of times the context was actually changed 1135system.cpu1.icache.replacements 314891 # number of replacements 1136system.cpu1.icache.tagsinuse 448.025093 # Cycle average of tags in use 1137system.cpu1.icache.total_refs 12848456 # Total number of references to valid blocks. 1138system.cpu1.icache.sampled_refs 315403 # Sample count of references to valid blocks. 1139system.cpu1.icache.avg_refs 40.736632 # Average number of references to valid blocks. 1140system.cpu1.icache.warmup_cycle 1950842738500 # Cycle when the warmup percentage was hit. 1141system.cpu1.icache.occ_blocks::cpu1.inst 448.025093 # Average occupied blocks per requestor 1142system.cpu1.icache.occ_percent::cpu1.inst 0.875049 # Average percentage of cache occupancy 1143system.cpu1.icache.occ_percent::total 0.875049 # Average percentage of cache occupancy 1144system.cpu1.icache.ReadReq_hits::cpu1.inst 12848456 # number of ReadReq hits 1145system.cpu1.icache.ReadReq_hits::total 12848456 # number of ReadReq hits 1146system.cpu1.icache.demand_hits::cpu1.inst 12848456 # number of demand (read+write) hits 1147system.cpu1.icache.demand_hits::total 12848456 # number of demand (read+write) hits 1148system.cpu1.icache.overall_hits::cpu1.inst 12848456 # number of overall hits 1149system.cpu1.icache.overall_hits::total 12848456 # number of overall hits 1150system.cpu1.icache.ReadReq_misses::cpu1.inst 315439 # number of ReadReq misses 1151system.cpu1.icache.ReadReq_misses::total 315439 # number of ReadReq misses 1152system.cpu1.icache.demand_misses::cpu1.inst 315439 # number of demand (read+write) misses 1153system.cpu1.icache.demand_misses::total 315439 # number of demand (read+write) misses 1154system.cpu1.icache.overall_misses::cpu1.inst 315439 # number of overall misses 1155system.cpu1.icache.overall_misses::total 315439 # number of overall misses 1156system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4168917000 # number of ReadReq miss cycles 1157system.cpu1.icache.ReadReq_miss_latency::total 4168917000 # number of ReadReq miss cycles 1158system.cpu1.icache.demand_miss_latency::cpu1.inst 4168917000 # number of demand (read+write) miss cycles 1159system.cpu1.icache.demand_miss_latency::total 4168917000 # number of demand (read+write) miss cycles 1160system.cpu1.icache.overall_miss_latency::cpu1.inst 4168917000 # number of overall miss cycles 1161system.cpu1.icache.overall_miss_latency::total 4168917000 # number of overall miss cycles 1162system.cpu1.icache.ReadReq_accesses::cpu1.inst 13163895 # number of ReadReq accesses(hits+misses) 1163system.cpu1.icache.ReadReq_accesses::total 13163895 # number of ReadReq accesses(hits+misses) 1164system.cpu1.icache.demand_accesses::cpu1.inst 13163895 # number of demand (read+write) accesses 1165system.cpu1.icache.demand_accesses::total 13163895 # number of demand (read+write) accesses 1166system.cpu1.icache.overall_accesses::cpu1.inst 13163895 # number of overall (read+write) accesses 1167system.cpu1.icache.overall_accesses::total 13163895 # number of overall (read+write) accesses 1168system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023962 # miss rate for ReadReq accesses 1169system.cpu1.icache.ReadReq_miss_rate::total 0.023962 # miss rate for ReadReq accesses 1170system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023962 # miss rate for demand accesses 1171system.cpu1.icache.demand_miss_rate::total 0.023962 # miss rate for demand accesses 1172system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023962 # miss rate for overall accesses 1173system.cpu1.icache.overall_miss_rate::total 0.023962 # miss rate for overall accesses 1174system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13216.238322 # average ReadReq miss latency 1175system.cpu1.icache.ReadReq_avg_miss_latency::total 13216.238322 # average ReadReq miss latency 1176system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency 1177system.cpu1.icache.demand_avg_miss_latency::total 13216.238322 # average overall miss latency 1178system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency 1179system.cpu1.icache.overall_avg_miss_latency::total 13216.238322 # average overall miss latency |
| 1180system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1181system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1182system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1183system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1184system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1185system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1186system.cpu1.icache.fast_writes 0 # number of fast writes performed 1187system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1180system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1181system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1182system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1183system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1184system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1185system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1186system.cpu1.icache.fast_writes 0 # number of fast writes performed 1187system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1188system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329194 # number of ReadReq MSHR misses 1189system.cpu1.icache.ReadReq_mshr_misses::total 329194 # number of ReadReq MSHR misses 1190system.cpu1.icache.demand_mshr_misses::cpu1.inst 329194 # number of demand (read+write) MSHR misses 1191system.cpu1.icache.demand_mshr_misses::total 329194 # number of demand (read+write) MSHR misses 1192system.cpu1.icache.overall_mshr_misses::cpu1.inst 329194 # number of overall MSHR misses 1193system.cpu1.icache.overall_mshr_misses::total 329194 # number of overall MSHR misses 1194system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688148000 # number of ReadReq MSHR miss cycles 1195system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688148000 # number of ReadReq MSHR miss cycles 1196system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688148000 # number of demand (read+write) MSHR miss cycles 1197system.cpu1.icache.demand_mshr_miss_latency::total 3688148000 # number of demand (read+write) MSHR miss cycles 1198system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688148000 # number of overall MSHR miss cycles 1199system.cpu1.icache.overall_mshr_miss_latency::total 3688148000 # number of overall MSHR miss cycles 1200system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for ReadReq accesses 1201system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024142 # mshr miss rate for ReadReq accesses 1202system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for demand accesses 1203system.cpu1.icache.demand_mshr_miss_rate::total 0.024142 # mshr miss rate for demand accesses 1204system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for overall accesses 1205system.cpu1.icache.overall_mshr_miss_rate::total 0.024142 # mshr miss rate for overall accesses 1206system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average ReadReq mshr miss latency 1207system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11203.569931 # average ReadReq mshr miss latency 1208system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency 1209system.cpu1.icache.demand_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency 1210system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency 1211system.cpu1.icache.overall_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency | 1188system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315439 # number of ReadReq MSHR misses 1189system.cpu1.icache.ReadReq_mshr_misses::total 315439 # number of ReadReq MSHR misses 1190system.cpu1.icache.demand_mshr_misses::cpu1.inst 315439 # number of demand (read+write) MSHR misses 1191system.cpu1.icache.demand_mshr_misses::total 315439 # number of demand (read+write) MSHR misses 1192system.cpu1.icache.overall_mshr_misses::cpu1.inst 315439 # number of overall MSHR misses 1193system.cpu1.icache.overall_mshr_misses::total 315439 # number of overall MSHR misses 1194system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3538039000 # number of ReadReq MSHR miss cycles 1195system.cpu1.icache.ReadReq_mshr_miss_latency::total 3538039000 # number of ReadReq MSHR miss cycles 1196system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3538039000 # number of demand (read+write) MSHR miss cycles 1197system.cpu1.icache.demand_mshr_miss_latency::total 3538039000 # number of demand (read+write) MSHR miss cycles 1198system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3538039000 # number of overall MSHR miss cycles 1199system.cpu1.icache.overall_mshr_miss_latency::total 3538039000 # number of overall MSHR miss cycles 1200system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for ReadReq accesses 1201system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023962 # mshr miss rate for ReadReq accesses 1202system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for demand accesses 1203system.cpu1.icache.demand_mshr_miss_rate::total 0.023962 # mshr miss rate for demand accesses 1204system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for overall accesses 1205system.cpu1.icache.overall_mshr_miss_rate::total 0.023962 # mshr miss rate for overall accesses 1206system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average ReadReq mshr miss latency 1207system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11216.238322 # average ReadReq mshr miss latency 1208system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency 1209system.cpu1.icache.demand_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency 1210system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency 1211system.cpu1.icache.overall_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency |
| 1212system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1212system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1213system.cpu1.dcache.replacements 172801 # number of replacements 1214system.cpu1.dcache.tagsinuse 487.450819 # Cycle average of tags in use 1215system.cpu1.dcache.total_refs 4146327 # Total number of references to valid blocks. 1216system.cpu1.dcache.sampled_refs 173313 # Sample count of references to valid blocks. 1217system.cpu1.dcache.avg_refs 23.923924 # Average number of references to valid blocks. 1218system.cpu1.dcache.warmup_cycle 62292445000 # Cycle when the warmup percentage was hit. 1219system.cpu1.dcache.occ_blocks::cpu1.data 487.450819 # Average occupied blocks per requestor 1220system.cpu1.dcache.occ_percent::cpu1.data 0.952052 # Average percentage of cache occupancy 1221system.cpu1.dcache.occ_percent::total 0.952052 # Average percentage of cache occupancy 1222system.cpu1.dcache.ReadReq_hits::cpu1.data 2329216 # number of ReadReq hits 1223system.cpu1.dcache.ReadReq_hits::total 2329216 # number of ReadReq hits 1224system.cpu1.dcache.WriteReq_hits::cpu1.data 1699225 # number of WriteReq hits 1225system.cpu1.dcache.WriteReq_hits::total 1699225 # number of WriteReq hits 1226system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50220 # number of LoadLockedReq hits 1227system.cpu1.dcache.LoadLockedReq_hits::total 50220 # number of LoadLockedReq hits 1228system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52927 # number of StoreCondReq hits 1229system.cpu1.dcache.StoreCondReq_hits::total 52927 # number of StoreCondReq hits 1230system.cpu1.dcache.demand_hits::cpu1.data 4028441 # number of demand (read+write) hits 1231system.cpu1.dcache.demand_hits::total 4028441 # number of demand (read+write) hits 1232system.cpu1.dcache.overall_hits::cpu1.data 4028441 # number of overall hits 1233system.cpu1.dcache.overall_hits::total 4028441 # number of overall hits 1234system.cpu1.dcache.ReadReq_misses::cpu1.data 123241 # number of ReadReq misses 1235system.cpu1.dcache.ReadReq_misses::total 123241 # number of ReadReq misses 1236system.cpu1.dcache.WriteReq_misses::cpu1.data 64769 # number of WriteReq misses 1237system.cpu1.dcache.WriteReq_misses::total 64769 # number of WriteReq misses 1238system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9346 # number of LoadLockedReq misses 1239system.cpu1.dcache.LoadLockedReq_misses::total 9346 # number of LoadLockedReq misses 1240system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6142 # number of StoreCondReq misses 1241system.cpu1.dcache.StoreCondReq_misses::total 6142 # number of StoreCondReq misses 1242system.cpu1.dcache.demand_misses::cpu1.data 188010 # number of demand (read+write) misses 1243system.cpu1.dcache.demand_misses::total 188010 # number of demand (read+write) misses 1244system.cpu1.dcache.overall_misses::cpu1.data 188010 # number of overall misses 1245system.cpu1.dcache.overall_misses::total 188010 # number of overall misses 1246system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1494406500 # number of ReadReq miss cycles 1247system.cpu1.dcache.ReadReq_miss_latency::total 1494406500 # number of ReadReq miss cycles 1248system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1166606000 # number of WriteReq miss cycles 1249system.cpu1.dcache.WriteReq_miss_latency::total 1166606000 # number of WriteReq miss cycles 1250system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85391000 # number of LoadLockedReq miss cycles 1251system.cpu1.dcache.LoadLockedReq_miss_latency::total 85391000 # number of LoadLockedReq miss cycles 1252system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44592000 # number of StoreCondReq miss cycles 1253system.cpu1.dcache.StoreCondReq_miss_latency::total 44592000 # number of StoreCondReq miss cycles 1254system.cpu1.dcache.demand_miss_latency::cpu1.data 2661012500 # number of demand (read+write) miss cycles 1255system.cpu1.dcache.demand_miss_latency::total 2661012500 # number of demand (read+write) miss cycles 1256system.cpu1.dcache.overall_miss_latency::cpu1.data 2661012500 # number of overall miss cycles 1257system.cpu1.dcache.overall_miss_latency::total 2661012500 # number of overall miss cycles 1258system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452457 # number of ReadReq accesses(hits+misses) 1259system.cpu1.dcache.ReadReq_accesses::total 2452457 # number of ReadReq accesses(hits+misses) 1260system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763994 # number of WriteReq accesses(hits+misses) 1261system.cpu1.dcache.WriteReq_accesses::total 1763994 # number of WriteReq accesses(hits+misses) 1262system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59566 # number of LoadLockedReq accesses(hits+misses) 1263system.cpu1.dcache.LoadLockedReq_accesses::total 59566 # number of LoadLockedReq accesses(hits+misses) 1264system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59069 # number of StoreCondReq accesses(hits+misses) 1265system.cpu1.dcache.StoreCondReq_accesses::total 59069 # number of StoreCondReq accesses(hits+misses) 1266system.cpu1.dcache.demand_accesses::cpu1.data 4216451 # number of demand (read+write) accesses 1267system.cpu1.dcache.demand_accesses::total 4216451 # number of demand (read+write) accesses 1268system.cpu1.dcache.overall_accesses::cpu1.data 4216451 # number of overall (read+write) accesses 1269system.cpu1.dcache.overall_accesses::total 4216451 # number of overall (read+write) accesses 1270system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050252 # miss rate for ReadReq accesses 1271system.cpu1.dcache.ReadReq_miss_rate::total 0.050252 # miss rate for ReadReq accesses 1272system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036717 # miss rate for WriteReq accesses 1273system.cpu1.dcache.WriteReq_miss_rate::total 0.036717 # miss rate for WriteReq accesses 1274system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156902 # miss rate for LoadLockedReq accesses 1275system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156902 # miss rate for LoadLockedReq accesses 1276system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103980 # miss rate for StoreCondReq accesses 1277system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103980 # miss rate for StoreCondReq accesses 1278system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044590 # miss rate for demand accesses 1279system.cpu1.dcache.demand_miss_rate::total 0.044590 # miss rate for demand accesses 1280system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044590 # miss rate for overall accesses 1281system.cpu1.dcache.overall_miss_rate::total 0.044590 # miss rate for overall accesses 1282system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12125.887489 # average ReadReq miss latency 1283system.cpu1.dcache.ReadReq_avg_miss_latency::total 12125.887489 # average ReadReq miss latency 1284system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18011.795766 # average WriteReq miss latency 1285system.cpu1.dcache.WriteReq_avg_miss_latency::total 18011.795766 # average WriteReq miss latency 1286system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9136.635994 # average LoadLockedReq miss latency 1287system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9136.635994 # average LoadLockedReq miss latency 1288system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7260.175838 # average StoreCondReq miss latency 1289system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7260.175838 # average StoreCondReq miss latency 1290system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency 1291system.cpu1.dcache.demand_avg_miss_latency::total 14153.568959 # average overall miss latency 1292system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency 1293system.cpu1.dcache.overall_avg_miss_latency::total 14153.568959 # average overall miss latency | 1213system.cpu1.dcache.replacements 165415 # number of replacements 1214system.cpu1.dcache.tagsinuse 486.567196 # Cycle average of tags in use 1215system.cpu1.dcache.total_refs 4004380 # Total number of references to valid blocks. 1216system.cpu1.dcache.sampled_refs 165927 # Sample count of references to valid blocks. 1217system.cpu1.dcache.avg_refs 24.133384 # Average number of references to valid blocks. 1218system.cpu1.dcache.warmup_cycle 60834829000 # Cycle when the warmup percentage was hit. 1219system.cpu1.dcache.occ_blocks::cpu1.data 486.567196 # Average occupied blocks per requestor 1220system.cpu1.dcache.occ_percent::cpu1.data 0.950327 # Average percentage of cache occupancy 1221system.cpu1.dcache.occ_percent::total 0.950327 # Average percentage of cache occupancy 1222system.cpu1.dcache.ReadReq_hits::cpu1.data 2254351 # number of ReadReq hits 1223system.cpu1.dcache.ReadReq_hits::total 2254351 # number of ReadReq hits 1224system.cpu1.dcache.WriteReq_hits::cpu1.data 1637565 # number of WriteReq hits 1225system.cpu1.dcache.WriteReq_hits::total 1637565 # number of WriteReq hits 1226system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47962 # number of LoadLockedReq hits 1227system.cpu1.dcache.LoadLockedReq_hits::total 47962 # number of LoadLockedReq hits 1228system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50536 # number of StoreCondReq hits 1229system.cpu1.dcache.StoreCondReq_hits::total 50536 # number of StoreCondReq hits 1230system.cpu1.dcache.demand_hits::cpu1.data 3891916 # number of demand (read+write) hits 1231system.cpu1.dcache.demand_hits::total 3891916 # number of demand (read+write) hits 1232system.cpu1.dcache.overall_hits::cpu1.data 3891916 # number of overall hits 1233system.cpu1.dcache.overall_hits::total 3891916 # number of overall hits 1234system.cpu1.dcache.ReadReq_misses::cpu1.data 117672 # number of ReadReq misses 1235system.cpu1.dcache.ReadReq_misses::total 117672 # number of ReadReq misses 1236system.cpu1.dcache.WriteReq_misses::cpu1.data 62334 # number of WriteReq misses 1237system.cpu1.dcache.WriteReq_misses::total 62334 # number of WriteReq misses 1238system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8861 # number of LoadLockedReq misses 1239system.cpu1.dcache.LoadLockedReq_misses::total 8861 # number of LoadLockedReq misses 1240system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5817 # number of StoreCondReq misses 1241system.cpu1.dcache.StoreCondReq_misses::total 5817 # number of StoreCondReq misses 1242system.cpu1.dcache.demand_misses::cpu1.data 180006 # number of demand (read+write) misses 1243system.cpu1.dcache.demand_misses::total 180006 # number of demand (read+write) misses 1244system.cpu1.dcache.overall_misses::cpu1.data 180006 # number of overall misses 1245system.cpu1.dcache.overall_misses::total 180006 # number of overall misses 1246system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427906500 # number of ReadReq miss cycles 1247system.cpu1.dcache.ReadReq_miss_latency::total 1427906500 # number of ReadReq miss cycles 1248system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1084822000 # number of WriteReq miss cycles 1249system.cpu1.dcache.WriteReq_miss_latency::total 1084822000 # number of WriteReq miss cycles 1250system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81394000 # number of LoadLockedReq miss cycles 1251system.cpu1.dcache.LoadLockedReq_miss_latency::total 81394000 # number of LoadLockedReq miss cycles 1252system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 42192000 # number of StoreCondReq miss cycles 1253system.cpu1.dcache.StoreCondReq_miss_latency::total 42192000 # number of StoreCondReq miss cycles 1254system.cpu1.dcache.demand_miss_latency::cpu1.data 2512728500 # number of demand (read+write) miss cycles 1255system.cpu1.dcache.demand_miss_latency::total 2512728500 # number of demand (read+write) miss cycles 1256system.cpu1.dcache.overall_miss_latency::cpu1.data 2512728500 # number of overall miss cycles 1257system.cpu1.dcache.overall_miss_latency::total 2512728500 # number of overall miss cycles 1258system.cpu1.dcache.ReadReq_accesses::cpu1.data 2372023 # number of ReadReq accesses(hits+misses) 1259system.cpu1.dcache.ReadReq_accesses::total 2372023 # number of ReadReq accesses(hits+misses) 1260system.cpu1.dcache.WriteReq_accesses::cpu1.data 1699899 # number of WriteReq accesses(hits+misses) 1261system.cpu1.dcache.WriteReq_accesses::total 1699899 # number of WriteReq accesses(hits+misses) 1262system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56823 # number of LoadLockedReq accesses(hits+misses) 1263system.cpu1.dcache.LoadLockedReq_accesses::total 56823 # number of LoadLockedReq accesses(hits+misses) 1264system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56353 # number of StoreCondReq accesses(hits+misses) 1265system.cpu1.dcache.StoreCondReq_accesses::total 56353 # number of StoreCondReq accesses(hits+misses) 1266system.cpu1.dcache.demand_accesses::cpu1.data 4071922 # number of demand (read+write) accesses 1267system.cpu1.dcache.demand_accesses::total 4071922 # number of demand (read+write) accesses 1268system.cpu1.dcache.overall_accesses::cpu1.data 4071922 # number of overall (read+write) accesses 1269system.cpu1.dcache.overall_accesses::total 4071922 # number of overall (read+write) accesses 1270system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049608 # miss rate for ReadReq accesses 1271system.cpu1.dcache.ReadReq_miss_rate::total 0.049608 # miss rate for ReadReq accesses 1272system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036669 # miss rate for WriteReq accesses 1273system.cpu1.dcache.WriteReq_miss_rate::total 0.036669 # miss rate for WriteReq accesses 1274system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155940 # miss rate for LoadLockedReq accesses 1275system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155940 # miss rate for LoadLockedReq accesses 1276system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103224 # miss rate for StoreCondReq accesses 1277system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103224 # miss rate for StoreCondReq accesses 1278system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044207 # miss rate for demand accesses 1279system.cpu1.dcache.demand_miss_rate::total 0.044207 # miss rate for demand accesses 1280system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044207 # miss rate for overall accesses 1281system.cpu1.dcache.overall_miss_rate::total 0.044207 # miss rate for overall accesses 1282system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12134.632708 # average ReadReq miss latency 1283system.cpu1.dcache.ReadReq_avg_miss_latency::total 12134.632708 # average ReadReq miss latency 1284system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17403.375365 # average WriteReq miss latency 1285system.cpu1.dcache.WriteReq_avg_miss_latency::total 17403.375365 # average WriteReq miss latency 1286system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.644961 # average LoadLockedReq miss latency 1287system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.644961 # average LoadLockedReq miss latency 1288system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7253.223311 # average StoreCondReq miss latency 1289system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7253.223311 # average StoreCondReq miss latency 1290system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency 1291system.cpu1.dcache.demand_avg_miss_latency::total 13959.137473 # average overall miss latency 1292system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency 1293system.cpu1.dcache.overall_avg_miss_latency::total 13959.137473 # average overall miss latency |
| 1294system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1295system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1296system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1297system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1298system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1299system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1300system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1301system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1294system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1295system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1296system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1297system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1298system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1299system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1300system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1301system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1302system.cpu1.dcache.writebacks::writebacks 119125 # number of writebacks 1303system.cpu1.dcache.writebacks::total 119125 # number of writebacks 1304system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123241 # number of ReadReq MSHR misses 1305system.cpu1.dcache.ReadReq_mshr_misses::total 123241 # number of ReadReq MSHR misses 1306system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64769 # number of WriteReq MSHR misses 1307system.cpu1.dcache.WriteReq_mshr_misses::total 64769 # number of WriteReq MSHR misses 1308system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9346 # number of LoadLockedReq MSHR misses 1309system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9346 # number of LoadLockedReq MSHR misses 1310system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6142 # number of StoreCondReq MSHR misses 1311system.cpu1.dcache.StoreCondReq_mshr_misses::total 6142 # number of StoreCondReq MSHR misses 1312system.cpu1.dcache.demand_mshr_misses::cpu1.data 188010 # number of demand (read+write) MSHR misses 1313system.cpu1.dcache.demand_mshr_misses::total 188010 # number of demand (read+write) MSHR misses 1314system.cpu1.dcache.overall_mshr_misses::cpu1.data 188010 # number of overall MSHR misses 1315system.cpu1.dcache.overall_mshr_misses::total 188010 # number of overall MSHR misses 1316system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247924500 # number of ReadReq MSHR miss cycles 1317system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247924500 # number of ReadReq MSHR miss cycles 1318system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1037068000 # number of WriteReq MSHR miss cycles 1319system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1037068000 # number of WriteReq MSHR miss cycles 1320system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66699000 # number of LoadLockedReq MSHR miss cycles 1321system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66699000 # number of LoadLockedReq MSHR miss cycles 1322system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32308000 # number of StoreCondReq MSHR miss cycles 1323system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32308000 # number of StoreCondReq MSHR miss cycles 1324system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284992500 # number of demand (read+write) MSHR miss cycles 1325system.cpu1.dcache.demand_mshr_miss_latency::total 2284992500 # number of demand (read+write) MSHR miss cycles 1326system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284992500 # number of overall MSHR miss cycles 1327system.cpu1.dcache.overall_mshr_miss_latency::total 2284992500 # number of overall MSHR miss cycles 1328system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles 1329system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles 1330system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723292500 # number of WriteReq MSHR uncacheable cycles 1331system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723292500 # number of WriteReq MSHR uncacheable cycles 1332system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742673500 # number of overall MSHR uncacheable cycles 1333system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742673500 # number of overall MSHR uncacheable cycles 1334system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050252 # mshr miss rate for ReadReq accesses 1335system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050252 # mshr miss rate for ReadReq accesses 1336system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses 1337system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses 1338system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156902 # mshr miss rate for LoadLockedReq accesses 1339system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156902 # mshr miss rate for LoadLockedReq accesses 1340system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103980 # mshr miss rate for StoreCondReq accesses 1341system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103980 # mshr miss rate for StoreCondReq accesses 1342system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for demand accesses 1343system.cpu1.dcache.demand_mshr_miss_rate::total 0.044590 # mshr miss rate for demand accesses 1344system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for overall accesses 1345system.cpu1.dcache.overall_mshr_miss_rate::total 0.044590 # mshr miss rate for overall accesses 1346system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10125.887489 # average ReadReq mshr miss latency 1347system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10125.887489 # average ReadReq mshr miss latency 1348system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.795766 # average WriteReq mshr miss latency 1349system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.795766 # average WriteReq mshr miss latency 1350system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7136.635994 # average LoadLockedReq mshr miss latency 1351system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7136.635994 # average LoadLockedReq mshr miss latency 1352system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5260.175838 # average StoreCondReq mshr miss latency 1353system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5260.175838 # average StoreCondReq mshr miss latency 1354system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency 1355system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency 1356system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency 1357system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency | 1302system.cpu1.dcache.writebacks::writebacks 113605 # number of writebacks 1303system.cpu1.dcache.writebacks::total 113605 # number of writebacks 1304system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117672 # number of ReadReq MSHR misses 1305system.cpu1.dcache.ReadReq_mshr_misses::total 117672 # number of ReadReq MSHR misses 1306system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62334 # number of WriteReq MSHR misses 1307system.cpu1.dcache.WriteReq_mshr_misses::total 62334 # number of WriteReq MSHR misses 1308system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8861 # number of LoadLockedReq MSHR misses 1309system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8861 # number of LoadLockedReq MSHR misses 1310system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5817 # number of StoreCondReq MSHR misses 1311system.cpu1.dcache.StoreCondReq_mshr_misses::total 5817 # number of StoreCondReq MSHR misses 1312system.cpu1.dcache.demand_mshr_misses::cpu1.data 180006 # number of demand (read+write) MSHR misses 1313system.cpu1.dcache.demand_mshr_misses::total 180006 # number of demand (read+write) MSHR misses 1314system.cpu1.dcache.overall_mshr_misses::cpu1.data 180006 # number of overall MSHR misses 1315system.cpu1.dcache.overall_mshr_misses::total 180006 # number of overall MSHR misses 1316system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1192562500 # number of ReadReq MSHR miss cycles 1317system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1192562500 # number of ReadReq MSHR miss cycles 1318system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 960154000 # number of WriteReq MSHR miss cycles 1319system.cpu1.dcache.WriteReq_mshr_miss_latency::total 960154000 # number of WriteReq MSHR miss cycles 1320system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63672000 # number of LoadLockedReq MSHR miss cycles 1321system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63672000 # number of LoadLockedReq MSHR miss cycles 1322system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30558000 # number of StoreCondReq MSHR miss cycles 1323system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30558000 # number of StoreCondReq MSHR miss cycles 1324system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2152716500 # number of demand (read+write) MSHR miss cycles 1325system.cpu1.dcache.demand_mshr_miss_latency::total 2152716500 # number of demand (read+write) MSHR miss cycles 1326system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2152716500 # number of overall MSHR miss cycles 1327system.cpu1.dcache.overall_mshr_miss_latency::total 2152716500 # number of overall MSHR miss cycles 1328system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380500 # number of ReadReq MSHR uncacheable cycles 1329system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380500 # number of ReadReq MSHR uncacheable cycles 1330system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 712390500 # number of WriteReq MSHR uncacheable cycles 1331system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 712390500 # number of WriteReq MSHR uncacheable cycles 1332system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 731771000 # number of overall MSHR uncacheable cycles 1333system.cpu1.dcache.overall_mshr_uncacheable_latency::total 731771000 # number of overall MSHR uncacheable cycles 1334system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049608 # mshr miss rate for ReadReq accesses 1335system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049608 # mshr miss rate for ReadReq accesses 1336system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036669 # mshr miss rate for WriteReq accesses 1337system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036669 # mshr miss rate for WriteReq accesses 1338system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155940 # mshr miss rate for LoadLockedReq accesses 1339system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155940 # mshr miss rate for LoadLockedReq accesses 1340system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103224 # mshr miss rate for StoreCondReq accesses 1341system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103224 # mshr miss rate for StoreCondReq accesses 1342system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for demand accesses 1343system.cpu1.dcache.demand_mshr_miss_rate::total 0.044207 # mshr miss rate for demand accesses 1344system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for overall accesses 1345system.cpu1.dcache.overall_mshr_miss_rate::total 0.044207 # mshr miss rate for overall accesses 1346system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10134.632708 # average ReadReq mshr miss latency 1347system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10134.632708 # average ReadReq mshr miss latency 1348system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15403.375365 # average WriteReq mshr miss latency 1349system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15403.375365 # average WriteReq mshr miss latency 1350system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7185.644961 # average LoadLockedReq mshr miss latency 1351system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7185.644961 # average LoadLockedReq mshr miss latency 1352system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5253.223311 # average StoreCondReq mshr miss latency 1353system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5253.223311 # average StoreCondReq mshr miss latency 1354system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency 1355system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency 1356system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency 1357system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency |
| 1358system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1359system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1360system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1361system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1362system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1363system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1364system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1365 1366---------- End Simulation Statistics ---------- | 1358system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1359system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1360system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1361system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1362system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1363system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1364system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1365 1366---------- End Simulation Statistics ---------- |